s6ddrphy: fix read latency

diff --git a/top.py b/top.py
index 910b90ed24d40d361a567d442820d653606bea2b..1a0c1b52baa85a4dc67f68966175463c0a96016c 100644 (file)
--- a/top.py
+++ b/top.py
@@ -44,7 +44,7 @@ sdram_timing = lasmicon.TimingSettings(
        tRFC=ns(70),
        
        CL=3,
-       read_latency=4,
+       read_latency=5,
        write_latency=0,
 
        read_time=32,

diff --git a/verilog/s6ddrphy/s6ddrphy.v b/verilog/s6ddrphy/s6ddrphy.v
index dc4a49b6ee3e9d0316ddd45cf5a14553f675dfa9..9fb5cdc76466507fbd3dac15cdae4139155daa4c 100644 (file)
--- a/verilog/s6ddrphy/s6ddrphy.v
+++ b/verilog/s6ddrphy/s6ddrphy.v
@@ -7,7 +7,7 @@
  *
  * Assert dfi_rddata_en in the same cycle as the read
  * command. The data will come back on dfi_rddata
- * 4 cycles later, along with the assertion of
+ * 5 cycles later, along with the assertion of
  * dfi_rddata_valid.
  *
  * This PHY only supports CAS Latency 3.