r600g/llvm:translate ARL opcode to a simple cast

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 258e796595ad8562cef43fcbb4d24eacf75f1aee..4eb860307dfdafa11d79660ae674e37255814343 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -800,6 +800,17 @@ static void emit_not(
        emit_data->output[emit_data->chan] = LLVMBuildNot(builder, v, "");
 }
 
+static void emit_arl(
+               const struct lp_build_tgsi_action * action,
+               struct lp_build_tgsi_context * bld_base,
+               struct lp_build_emit_data * emit_data)
+{
+       LLVMBuilderRef builder = bld_base->base.gallivm->builder;
+       LLVMValueRef floor_index =  lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_FLR, emit_data->args[0]);
+       emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
+                       floor_index, bld_base->base.int_elem_type , "");
+}
+
 static void emit_and(
                const struct lp_build_tgsi_action * action,
                struct lp_build_tgsi_context * bld_base,
@@ -1119,8 +1130,7 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
 
        bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_readonly;
        bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "fabs";
-       bld_base->op_actions[TGSI_OPCODE_ARL].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_ARL].intr_name = "llvm.AMDGPU.arl";
+       bld_base->op_actions[TGSI_OPCODE_ARL].emit = emit_arl;
        bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
        bld_base->op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit;
        bld_base->op_actions[TGSI_OPCODE_BRK].emit = brk_emit;