stats: update EIO stats for recent changes
authorSteve Reinhardt <stever@gmail.com>
Sat, 6 Feb 2016 06:35:03 +0000 (01:35 -0500)
committerSteve Reinhardt <stever@gmail.com>
Sat, 6 Feb 2016 06:35:03 +0000 (01:35 -0500)
12 files changed:
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt

index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..8af5388f958ee1421c269a98792132d9e5363dc5 100755 (executable)
@@ -0,0 +1,5 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+
+gzip: stdout: Broken pipe
index 03581733bb7036824469f335641ca1a7a0440b1e..11b21f546b226681a5bbaa3e1016102b2e2014e6 100755 (executable)
@@ -1,9 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:02
-gem5 executing on zizzer, pid 33994
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
+gem5 compiled Feb  1 2016 02:06:47
+gem5 started Feb  1 2016 02:07:02
+gem5 executing on zizzer, pid 44725
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
 
-Skipping test: Test requires the 'EioProcess' SimObject.
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+main dictionary has 1245 entries
+49508 bytes wasted
+>Exiting @ tick 250015500 because a thread reached the max instruction count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..8d68a74bcc85e5c1939b5438f7c2623c26f29938 100644 (file)
@@ -0,0 +1,152 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.000250                       # Number of seconds simulated
+sim_ticks                                   250015500                       # Number of ticks simulated
+final_tick                                  250015500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1689656                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1689524                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              844754706                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219516                       # Number of bytes of host memory used
+host_seconds                                     0.30                       # Real time elapsed on the host
+sim_insts                                      500001                       # Number of instructions simulated
+sim_ops                                        500001                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.bytes_read::cpu.inst           2000076                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            872600                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              2872676                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      2000076                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         2000076                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data         417562                       # Number of bytes written to this memory
+system.physmem.bytes_written::total            417562                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst             500019                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             124435                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                624454                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data             56340                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                56340                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst           7999808012                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           3490183609                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total             11489991621                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      7999808012                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         7999808012                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1670144451                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1670144451                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          7999808012                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          5160328060                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            13160136072                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                       124435                       # DTB read hits
+system.cpu.dtb.read_misses                          8                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                   124443                       # DTB read accesses
+system.cpu.dtb.write_hits                       56340                       # DTB write hits
+system.cpu.dtb.write_misses                        10                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                   56350                       # DTB write accesses
+system.cpu.dtb.data_hits                       180775                       # DTB hits
+system.cpu.dtb.data_misses                         18                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                   180793                       # DTB accesses
+system.cpu.itb.fetch_hits                      500019                       # ITB hits
+system.cpu.itb.fetch_misses                        13                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                  500032                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   18                       # Number of system calls
+system.cpu.numCycles                           500032                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                      500001                       # Number of instructions committed
+system.cpu.committedOps                        500001                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                474689                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     32                       # Number of float alu accesses
+system.cpu.num_func_calls                       14357                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                       474689                       # number of integer instructions
+system.cpu.num_fp_insts                            32                       # number of float instructions
+system.cpu.num_int_register_reads              654286                       # number of times the integer registers were read
+system.cpu.num_int_register_writes             371542                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   32                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
+system.cpu.num_mem_refs                        180793                       # number of memory refs
+system.cpu.num_load_insts                      124443                       # Number of load instructions
+system.cpu.num_store_insts                      56350                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                     500032                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.Branches                             59023                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                 18814      3.76%      3.76% # Class of executed instruction
+system.cpu.op_class::IntAlu                    300388     60.08%     63.84% # Class of executed instruction
+system.cpu.op_class::IntMult                       10      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatAdd                      10      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       2      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatMult                      2      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::MemRead                   124443     24.89%     88.73% # Class of executed instruction
+system.cpu.op_class::MemWrite                   56350     11.27%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                     500019                       # Class of executed instruction
+system.membus.trans_dist::ReadReq              624454                       # Transaction distribution
+system.membus.trans_dist::ReadResp             624454                       # Transaction distribution
+system.membus.trans_dist::WriteReq              56340                       # Transaction distribution
+system.membus.trans_dist::WriteResp             56340                       # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port      1000038                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port       361550                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1361588                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port      2000076                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port      1290162                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 3290238                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples            680794                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.734464                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.441618                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  180775     26.55%     26.55% # Request fanout histogram
+system.membus.snoop_fanout::1                  500019     73.45%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::total              680794                       # Request fanout histogram
+
+---------- End Simulation Statistics   ----------
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..8af5388f958ee1421c269a98792132d9e5363dc5 100755 (executable)
@@ -0,0 +1,5 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+
+gzip: stdout: Broken pipe
index 7a11e4e17aa6b586e520ee8fcfd6c735d8f31d6a..9b0bce3536dbd229531f78193f0e132a0041ae55 100755 (executable)
@@ -1,9 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:26
-gem5 executing on zizzer, pid 34075
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
+gem5 compiled Feb  1 2016 02:06:47
+gem5 started Feb  1 2016 02:07:02
+gem5 executing on zizzer, pid 44728
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
 
-Skipping test: Test requires the 'EioProcess' SimObject.
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+main dictionary has 1245 entries
+49508 bytes wasted
+>Exiting @ tick 733071500 because a thread reached the max instruction count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..4b844e2e563174099eafd6a97ce0daf788970a4e 100644 (file)
@@ -0,0 +1,506 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.000733                       # Number of seconds simulated
+sim_ticks                                   733071500                       # Number of ticks simulated
+final_tick                                  733071500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 728390                       # Simulator instruction rate (inst/s)
+host_op_rate                                   728363                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1067851383                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229580                       # Number of bytes of host memory used
+host_seconds                                     0.69                       # Real time elapsed on the host
+sim_insts                                      500001                       # Number of instructions simulated
+sim_ops                                        500001                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.bytes_read::cpu.inst             25792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             29056                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                54848                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        25792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           25792                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                403                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                454                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   857                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst             35183471                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             39635970                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                74819441                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        35183471                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           35183471                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            35183471                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            39635970                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               74819441                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                       124435                       # DTB read hits
+system.cpu.dtb.read_misses                          8                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                   124443                       # DTB read accesses
+system.cpu.dtb.write_hits                       56340                       # DTB write hits
+system.cpu.dtb.write_misses                        10                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                   56350                       # DTB write accesses
+system.cpu.dtb.data_hits                       180775                       # DTB hits
+system.cpu.dtb.data_misses                         18                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                   180793                       # DTB accesses
+system.cpu.itb.fetch_hits                      500020                       # ITB hits
+system.cpu.itb.fetch_misses                        13                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                  500033                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   18                       # Number of system calls
+system.cpu.numCycles                          1466143                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                      500001                       # Number of instructions committed
+system.cpu.committedOps                        500001                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                474689                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     32                       # Number of float alu accesses
+system.cpu.num_func_calls                       14357                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                       474689                       # number of integer instructions
+system.cpu.num_fp_insts                            32                       # number of float instructions
+system.cpu.num_int_register_reads              654286                       # number of times the integer registers were read
+system.cpu.num_int_register_writes             371542                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   32                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
+system.cpu.num_mem_refs                        180793                       # number of memory refs
+system.cpu.num_load_insts                      124443                       # Number of load instructions
+system.cpu.num_store_insts                      56350                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                    1466143                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.Branches                             59023                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                 18814      3.76%      3.76% # Class of executed instruction
+system.cpu.op_class::IntAlu                    300388     60.08%     63.84% # Class of executed instruction
+system.cpu.op_class::IntMult                       10      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatAdd                      10      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       2      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatMult                      2      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     63.84% # Class of executed instruction
+system.cpu.op_class::MemRead                   124443     24.89%     88.73% # Class of executed instruction
+system.cpu.op_class::MemWrite                   56350     11.27%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                     500019                       # Class of executed instruction
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           286.668758                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs              180321                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               454                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            397.182819                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   286.668758                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.069987                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.069987                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          454                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          426                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.110840                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses            362004                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses           362004                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data       124120                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total          124120                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data        56201                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total          56201                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data        180321                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total           180321                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data       180321                       # number of overall hits
+system.cpu.dcache.overall_hits::total          180321                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          315                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           315                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          139                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          454                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            454                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          454                       # number of overall misses
+system.cpu.dcache.overall_misses::total           454                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     19530000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     19530000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      8618000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      8618000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     28148000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     28148000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     28148000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     28148000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data       124435                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data        56340                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data       180775                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data       180775                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002531                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002531                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002467                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002511                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.002511                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.002511                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.002511                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        62000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total        62000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        62000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        62000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data        62000                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total        62000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data        62000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total        62000                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          315                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          315                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data          139                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          454                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          454                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          454                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          454                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     19215000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     19215000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      8479000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      8479000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     27694000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     27694000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     27694000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     27694000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002531                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002531                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002467                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002467                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002511                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002511                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002511                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002511                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        61000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        61000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        61000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        61000                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        61000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements                 0                       # number of replacements
+system.cpu.icache.tags.tagsinuse           264.585152                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs              499617                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               403                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1239.744417                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   264.585152                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.129192                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.129192                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          403                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          403                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.196777                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses           1000443                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses          1000443                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst       499617                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total          499617                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst        499617                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total           499617                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst       499617                       # number of overall hits
+system.cpu.icache.overall_hits::total          499617                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          403                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           403                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          403                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            403                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          403                       # number of overall misses
+system.cpu.icache.overall_misses::total           403                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     24986500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     24986500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     24986500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     24986500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     24986500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     24986500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst       500020                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total       500020                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst       500020                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total       500020                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst       500020                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total       500020                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000806                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000806                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000806                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000806                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000806                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000806                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62001.240695                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 62001.240695                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 62001.240695                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 62001.240695                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 62001.240695                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 62001.240695                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          403                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          403                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          403                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          403                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          403                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          403                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24583500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     24583500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24583500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     24583500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24583500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     24583500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000806                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000806                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000806                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000806                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000806                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000806                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61001.240695                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61001.240695                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61001.240695                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 61001.240695                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61001.240695                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 61001.240695                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          480.680597                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              718                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   264.590924                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   216.089673                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.008075                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.006595                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.014669                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          718                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          714                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.021912                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             7713                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            7713                       # Number of data accesses
+system.cpu.l2cache.ReadExReq_misses::cpu.data          139                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total          139                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          403                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          403                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          315                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          315                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          403                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          454                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           857                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          403                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          454                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          857                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      8270500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      8270500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     23979000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     23979000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     18742500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     18742500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     23979000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     27013000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     50992000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     23979000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     27013000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     50992000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_accesses::cpu.data          139                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total          139                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          403                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          403                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          315                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total          315                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          403                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          454                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          857                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          403                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          454                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          857                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total            1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        59500                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        59500                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.240695                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.240695                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        59500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        59500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.240695                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        59500                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 59500.583431                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.240695                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        59500                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 59500.583431                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          139                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total          139                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          403                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          403                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          315                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          315                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          403                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          454                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          857                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          403                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          454                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          857                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      6880500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      6880500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     19949000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     19949000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     15592500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     15592500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19949000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     22473000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     42422000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19949000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     22473000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     42422000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        49500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        49500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.240695                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.240695                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        49500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        49500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.240695                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.583431                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.240695                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.583431                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.snoop_filter.tot_requests          857                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp           718                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq          139                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp          139                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          403                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          315                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          806                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          908                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total              1714                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        25792                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        29056                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              54848                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples          857                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                857    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total            857                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         428500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        604500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        681000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp                718                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               139                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              139                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           718                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1714                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1714                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        54848                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   54848                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples               857                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     857    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                 857                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              857500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4285000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.6                       # Layer utilization (%)
+
+---------- End Simulation Statistics   ----------
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..8be63e41646c5b18571fd88fcb1492303ce2d949 100755 (executable)
@@ -0,0 +1,7 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+
+gzip: stdout: Broken pipe
+stdout: Broken pipe
+stdout: Broken pipe
index 20b7b421fbe0f45cadb1a8d57e1a7b92eec2d081..77a39329a1639c35bd63c60636640b47be9b83c7 100755 (executable)
@@ -1,9 +1,19 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:00
-gem5 executing on zizzer, pid 33976
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
+gem5 compiled Feb  1 2016 02:06:47
+gem5 started Feb  1 2016 02:07:02
+gem5 executing on zizzer, pid 44731
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
 
-Skipping test: Test requires the 'EioProcess' SimObject.
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+49508 bytes wasted
+49508 bytes wasted
+49508 bytes wasted
+49508 bytes wasted
+>>>>Exiting @ tick 250015500 because a thread reached the max instruction count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..c98459e0ccd16dc7a20eb5ce72b42d12724206f2 100644 (file)
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.000250                       # Number of seconds simulated
+sim_ticks                                   250015500                       # Number of ticks simulated
+final_tick                                  250015500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1345479                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1345456                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              168189773                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 243396                       # Number of bytes of host memory used
+host_seconds                                     1.49                       # Real time elapsed on the host
+sim_insts                                     2000004                       # Number of instructions simulated
+sim_ops                                       2000004                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.bytes_read::cpu0.inst            25792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data            29056                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            25792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data            29056                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst            25792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data            29056                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst            25792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data            29056                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               219392                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst        25792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        25792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst        25792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst        25792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          103168                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu0.inst               403                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data               454                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst               403                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data               454                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst               403                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data               454                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst               403                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data               454                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  3428                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu0.inst           103161604                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data           116216795                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst           103161604                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data           116216795                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst           103161604                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data           116216795                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst           103161604                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data           116216795                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               877513594                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst      103161604                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst      103161604                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst      103161604                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst      103161604                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          412646416                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst          103161604                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data          116216795                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst          103161604                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data          116216795                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst          103161604                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data          116216795                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst          103161604                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data          116216795                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              877513594                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu0.dtb.fetch_hits                          0                       # ITB hits
+system.cpu0.dtb.fetch_misses                        0                       # ITB misses
+system.cpu0.dtb.fetch_acv                           0                       # ITB acv
+system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu0.dtb.read_hits                      124435                       # DTB read hits
+system.cpu0.dtb.read_misses                         8                       # DTB read misses
+system.cpu0.dtb.read_acv                            0                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  124443                       # DTB read accesses
+system.cpu0.dtb.write_hits                      56340                       # DTB write hits
+system.cpu0.dtb.write_misses                       10                       # DTB write misses
+system.cpu0.dtb.write_acv                           0                       # DTB write access violations
+system.cpu0.dtb.write_accesses                  56350                       # DTB write accesses
+system.cpu0.dtb.data_hits                      180775                       # DTB hits
+system.cpu0.dtb.data_misses                        18                       # DTB misses
+system.cpu0.dtb.data_acv                            0                       # DTB access violations
+system.cpu0.dtb.data_accesses                  180793                       # DTB accesses
+system.cpu0.itb.fetch_hits                     500019                       # ITB hits
+system.cpu0.itb.fetch_misses                       13                       # ITB misses
+system.cpu0.itb.fetch_acv                           0                       # ITB acv
+system.cpu0.itb.fetch_accesses                 500032                       # ITB accesses
+system.cpu0.itb.read_hits                           0                       # DTB read hits
+system.cpu0.itb.read_misses                         0                       # DTB read misses
+system.cpu0.itb.read_acv                            0                       # DTB read access violations
+system.cpu0.itb.read_accesses                       0                       # DTB read accesses
+system.cpu0.itb.write_hits                          0                       # DTB write hits
+system.cpu0.itb.write_misses                        0                       # DTB write misses
+system.cpu0.itb.write_acv                           0                       # DTB write access violations
+system.cpu0.itb.write_accesses                      0                       # DTB write accesses
+system.cpu0.itb.data_hits                           0                       # DTB hits
+system.cpu0.itb.data_misses                         0                       # DTB misses
+system.cpu0.itb.data_acv                            0                       # DTB access violations
+system.cpu0.itb.data_accesses                       0                       # DTB accesses
+system.cpu0.workload.num_syscalls                  18                       # Number of system calls
+system.cpu0.numCycles                          500032                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.committedInsts                     500001                       # Number of instructions committed
+system.cpu0.committedOps                       500001                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses               474689                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu0.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                      474689                       # number of integer instructions
+system.cpu0.num_fp_insts                           32                       # number of float instructions
+system.cpu0.num_int_register_reads             654286                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes            371542                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                       180793                       # number of memory refs
+system.cpu0.num_load_insts                     124443                       # Number of load instructions
+system.cpu0.num_store_insts                     56350                       # Number of store instructions
+system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
+system.cpu0.num_busy_cycles                    500032                       # Number of busy cycles
+system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu0.Branches                            59023                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                18814      3.76%      3.76% # Class of executed instruction
+system.cpu0.op_class::IntAlu                   300388     60.08%     63.84% # Class of executed instruction
+system.cpu0.op_class::IntMult                      10      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                     10      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      2      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     2      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::MemRead                  124443     24.89%     88.73% # Class of executed instruction
+system.cpu0.op_class::MemWrite                  56350     11.27%    100.00% # Class of executed instruction
+system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::total                    500019                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements               61                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          276.872320                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs             180312                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs           389.442765                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   276.872320                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.540766                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.540766                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          138                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          248                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses           723563                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses          723563                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data       124111                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data        56201                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
+system.cpu0.dcache.demand_hits::cpu0.data       180312                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data       180312                       # number of overall hits
+system.cpu0.dcache.overall_hits::total         180312                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data          324                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data          139                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
+system.cpu0.dcache.demand_misses::cpu0.data          463                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total           463                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data          463                       # number of overall misses
+system.cpu0.dcache.overall_misses::total          463                       # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data       124435                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data        56340                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data       180775                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data       180775                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.002604                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.002467                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.002561                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.002561                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
+system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks           29                       # number of writebacks
+system.cpu0.dcache.writebacks::total               29                       # number of writebacks
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.icache.tags.replacements              152                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          218.086151                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs             499556                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs          1078.954644                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   218.086151                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.425950                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.425950                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          190                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          121                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses           500482                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses          500482                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst       499556                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst       499556                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total          499556                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst       499556                       # number of overall hits
+system.cpu0.icache.overall_hits::total         499556                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst          463                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total          463                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst          463                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total           463                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst          463                       # number of overall misses
+system.cpu0.icache.overall_misses::total          463                       # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst       500019                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total       500019                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst       500019                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total       500019                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst       500019                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total       500019                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.000926                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.000926                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.000926                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
+system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.writebacks::writebacks          152                       # number of writebacks
+system.cpu0.icache.writebacks::total              152                       # number of writebacks
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dtb.fetch_hits                          0                       # ITB hits
+system.cpu1.dtb.fetch_misses                        0                       # ITB misses
+system.cpu1.dtb.fetch_acv                           0                       # ITB acv
+system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu1.dtb.read_hits                      124435                       # DTB read hits
+system.cpu1.dtb.read_misses                         8                       # DTB read misses
+system.cpu1.dtb.read_acv                            0                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  124443                       # DTB read accesses
+system.cpu1.dtb.write_hits                      56340                       # DTB write hits
+system.cpu1.dtb.write_misses                       10                       # DTB write misses
+system.cpu1.dtb.write_acv                           0                       # DTB write access violations
+system.cpu1.dtb.write_accesses                  56350                       # DTB write accesses
+system.cpu1.dtb.data_hits                      180775                       # DTB hits
+system.cpu1.dtb.data_misses                        18                       # DTB misses
+system.cpu1.dtb.data_acv                            0                       # DTB access violations
+system.cpu1.dtb.data_accesses                  180793                       # DTB accesses
+system.cpu1.itb.fetch_hits                     500019                       # ITB hits
+system.cpu1.itb.fetch_misses                       13                       # ITB misses
+system.cpu1.itb.fetch_acv                           0                       # ITB acv
+system.cpu1.itb.fetch_accesses                 500032                       # ITB accesses
+system.cpu1.itb.read_hits                           0                       # DTB read hits
+system.cpu1.itb.read_misses                         0                       # DTB read misses
+system.cpu1.itb.read_acv                            0                       # DTB read access violations
+system.cpu1.itb.read_accesses                       0                       # DTB read accesses
+system.cpu1.itb.write_hits                          0                       # DTB write hits
+system.cpu1.itb.write_misses                        0                       # DTB write misses
+system.cpu1.itb.write_acv                           0                       # DTB write access violations
+system.cpu1.itb.write_accesses                      0                       # DTB write accesses
+system.cpu1.itb.data_hits                           0                       # DTB hits
+system.cpu1.itb.data_misses                         0                       # DTB misses
+system.cpu1.itb.data_acv                            0                       # DTB access violations
+system.cpu1.itb.data_accesses                       0                       # DTB accesses
+system.cpu1.workload.num_syscalls                  18                       # Number of system calls
+system.cpu1.numCycles                          500032                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.committedInsts                     500001                       # Number of instructions committed
+system.cpu1.committedOps                       500001                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses               474689                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu1.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                      474689                       # number of integer instructions
+system.cpu1.num_fp_insts                           32                       # number of float instructions
+system.cpu1.num_int_register_reads             654286                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes            371542                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                       180793                       # number of memory refs
+system.cpu1.num_load_insts                     124443                       # Number of load instructions
+system.cpu1.num_store_insts                     56350                       # Number of store instructions
+system.cpu1.num_idle_cycles                         0                       # Number of idle cycles
+system.cpu1.num_busy_cycles                    500032                       # Number of busy cycles
+system.cpu1.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu1.Branches                            59023                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                18814      3.76%      3.76% # Class of executed instruction
+system.cpu1.op_class::IntAlu                   300388     60.08%     63.84% # Class of executed instruction
+system.cpu1.op_class::IntMult                      10      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                     10      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      2      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     2      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::MemRead                  124443     24.89%     88.73% # Class of executed instruction
+system.cpu1.op_class::MemWrite                  56350     11.27%    100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::total                    500019                       # Class of executed instruction
+system.cpu1.dcache.tags.replacements               61                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          276.872320                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs             180312                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs           389.442765                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   276.872320                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.540766                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.540766                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          138                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          248                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses           723563                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses          723563                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data       124111                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data        56201                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
+system.cpu1.dcache.demand_hits::cpu1.data       180312                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data       180312                       # number of overall hits
+system.cpu1.dcache.overall_hits::total         180312                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data          324                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data          139                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
+system.cpu1.dcache.demand_misses::cpu1.data          463                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total           463                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data          463                       # number of overall misses
+system.cpu1.dcache.overall_misses::total          463                       # number of overall misses
+system.cpu1.dcache.ReadReq_accesses::cpu1.data       124435                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data        56340                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data       180775                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data       180775                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.002604                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.002467                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.002561                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.002561                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
+system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.dcache.writebacks::writebacks           29                       # number of writebacks
+system.cpu1.dcache.writebacks::total               29                       # number of writebacks
+system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.icache.tags.replacements              152                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          218.086151                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs             499556                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs          1078.954644                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   218.086151                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.425950                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.425950                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          190                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          121                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses           500482                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses          500482                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst       499556                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst       499556                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total          499556                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst       499556                       # number of overall hits
+system.cpu1.icache.overall_hits::total         499556                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst          463                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total          463                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst          463                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total           463                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst          463                       # number of overall misses
+system.cpu1.icache.overall_misses::total          463                       # number of overall misses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst       500019                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total       500019                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst       500019                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total       500019                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst       500019                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total       500019                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.000926                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.000926                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.000926                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
+system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.icache.writebacks::writebacks          152                       # number of writebacks
+system.cpu1.icache.writebacks::total              152                       # number of writebacks
+system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu2.dtb.fetch_hits                          0                       # ITB hits
+system.cpu2.dtb.fetch_misses                        0                       # ITB misses
+system.cpu2.dtb.fetch_acv                           0                       # ITB acv
+system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu2.dtb.read_hits                      124435                       # DTB read hits
+system.cpu2.dtb.read_misses                         8                       # DTB read misses
+system.cpu2.dtb.read_acv                            0                       # DTB read access violations
+system.cpu2.dtb.read_accesses                  124443                       # DTB read accesses
+system.cpu2.dtb.write_hits                      56340                       # DTB write hits
+system.cpu2.dtb.write_misses                       10                       # DTB write misses
+system.cpu2.dtb.write_acv                           0                       # DTB write access violations
+system.cpu2.dtb.write_accesses                  56350                       # DTB write accesses
+system.cpu2.dtb.data_hits                      180775                       # DTB hits
+system.cpu2.dtb.data_misses                        18                       # DTB misses
+system.cpu2.dtb.data_acv                            0                       # DTB access violations
+system.cpu2.dtb.data_accesses                  180793                       # DTB accesses
+system.cpu2.itb.fetch_hits                     500019                       # ITB hits
+system.cpu2.itb.fetch_misses                       13                       # ITB misses
+system.cpu2.itb.fetch_acv                           0                       # ITB acv
+system.cpu2.itb.fetch_accesses                 500032                       # ITB accesses
+system.cpu2.itb.read_hits                           0                       # DTB read hits
+system.cpu2.itb.read_misses                         0                       # DTB read misses
+system.cpu2.itb.read_acv                            0                       # DTB read access violations
+system.cpu2.itb.read_accesses                       0                       # DTB read accesses
+system.cpu2.itb.write_hits                          0                       # DTB write hits
+system.cpu2.itb.write_misses                        0                       # DTB write misses
+system.cpu2.itb.write_acv                           0                       # DTB write access violations
+system.cpu2.itb.write_accesses                      0                       # DTB write accesses
+system.cpu2.itb.data_hits                           0                       # DTB hits
+system.cpu2.itb.data_misses                         0                       # DTB misses
+system.cpu2.itb.data_acv                            0                       # DTB access violations
+system.cpu2.itb.data_accesses                       0                       # DTB accesses
+system.cpu2.workload.num_syscalls                  18                       # Number of system calls
+system.cpu2.numCycles                          500032                       # number of cpu cycles simulated
+system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu2.committedInsts                     500001                       # Number of instructions committed
+system.cpu2.committedOps                       500001                       # Number of ops (including micro ops) committed
+system.cpu2.num_int_alu_accesses               474689                       # Number of integer alu accesses
+system.cpu2.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu2.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu2.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
+system.cpu2.num_int_insts                      474689                       # number of integer instructions
+system.cpu2.num_fp_insts                           32                       # number of float instructions
+system.cpu2.num_int_register_reads             654286                       # number of times the integer registers were read
+system.cpu2.num_int_register_writes            371542                       # number of times the integer registers were written
+system.cpu2.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu2.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu2.num_mem_refs                       180793                       # number of memory refs
+system.cpu2.num_load_insts                     124443                       # Number of load instructions
+system.cpu2.num_store_insts                     56350                       # Number of store instructions
+system.cpu2.num_idle_cycles                         0                       # Number of idle cycles
+system.cpu2.num_busy_cycles                    500032                       # Number of busy cycles
+system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu2.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu2.Branches                            59023                       # Number of branches fetched
+system.cpu2.op_class::No_OpClass                18814      3.76%      3.76% # Class of executed instruction
+system.cpu2.op_class::IntAlu                   300388     60.08%     63.84% # Class of executed instruction
+system.cpu2.op_class::IntMult                      10      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::IntDiv                        0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::FloatAdd                     10      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::FloatCmp                      2      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::FloatCvt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::FloatMult                     2      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::FloatDiv                      0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::FloatSqrt                     0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdAdd                       0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdAddAcc                    0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdAlu                       0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdCmp                       0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdCvt                       0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdMisc                      0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdMult                      0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdMultAcc                   0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdShift                     0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdShiftAcc                  0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdSqrt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdFloatAdd                  0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdFloatAlu                  0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdFloatCmp                  0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdFloatCvt                  0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdFloatDiv                  0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMisc                 0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMult                 0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMultAcc              0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdFloatSqrt                 0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::MemRead                  124443     24.89%     88.73% # Class of executed instruction
+system.cpu2.op_class::MemWrite                  56350     11.27%    100.00% # Class of executed instruction
+system.cpu2.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu2.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu2.op_class::total                    500019                       # Class of executed instruction
+system.cpu2.dcache.tags.replacements               61                       # number of replacements
+system.cpu2.dcache.tags.tagsinuse          276.872320                       # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs             180312                       # Total number of references to valid blocks.
+system.cpu2.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs           389.442765                       # Average number of references to valid blocks.
+system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu2.dcache.tags.occ_blocks::cpu2.data   276.872320                       # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data     0.540766                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total     0.540766                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
+system.cpu2.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
+system.cpu2.dcache.tags.age_task_id_blocks_1024::1          138                       # Occupied blocks per task id
+system.cpu2.dcache.tags.age_task_id_blocks_1024::2          248                       # Occupied blocks per task id
+system.cpu2.dcache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
+system.cpu2.dcache.tags.tag_accesses           723563                       # Number of tag accesses
+system.cpu2.dcache.tags.data_accesses          723563                       # Number of data accesses
+system.cpu2.dcache.ReadReq_hits::cpu2.data       124111                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data        56201                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
+system.cpu2.dcache.demand_hits::cpu2.data       180312                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data       180312                       # number of overall hits
+system.cpu2.dcache.overall_hits::total         180312                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data          324                       # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data          139                       # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
+system.cpu2.dcache.demand_misses::cpu2.data          463                       # number of demand (read+write) misses
+system.cpu2.dcache.demand_misses::total           463                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses::cpu2.data          463                       # number of overall misses
+system.cpu2.dcache.overall_misses::total          463                       # number of overall misses
+system.cpu2.dcache.ReadReq_accesses::cpu2.data       124435                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data        56340                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data       180775                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data       180775                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.002604                       # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.002467                       # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data     0.002561                       # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data     0.002561                       # miss rate for overall accesses
+system.cpu2.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
+system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu2.dcache.writebacks::writebacks           29                       # number of writebacks
+system.cpu2.dcache.writebacks::total               29                       # number of writebacks
+system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu2.icache.tags.replacements              152                       # number of replacements
+system.cpu2.icache.tags.tagsinuse          218.086151                       # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs             499556                       # Total number of references to valid blocks.
+system.cpu2.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu2.icache.tags.avg_refs          1078.954644                       # Average number of references to valid blocks.
+system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu2.icache.tags.occ_blocks::cpu2.inst   218.086151                       # Average occupied blocks per requestor
+system.cpu2.icache.tags.occ_percent::cpu2.inst     0.425950                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total     0.425950                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
+system.cpu2.icache.tags.age_task_id_blocks_1024::1          190                       # Occupied blocks per task id
+system.cpu2.icache.tags.age_task_id_blocks_1024::2          121                       # Occupied blocks per task id
+system.cpu2.icache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
+system.cpu2.icache.tags.tag_accesses           500482                       # Number of tag accesses
+system.cpu2.icache.tags.data_accesses          500482                       # Number of data accesses
+system.cpu2.icache.ReadReq_hits::cpu2.inst       499556                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst       499556                       # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total          499556                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst       499556                       # number of overall hits
+system.cpu2.icache.overall_hits::total         499556                       # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst          463                       # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total          463                       # number of ReadReq misses
+system.cpu2.icache.demand_misses::cpu2.inst          463                       # number of demand (read+write) misses
+system.cpu2.icache.demand_misses::total           463                       # number of demand (read+write) misses
+system.cpu2.icache.overall_misses::cpu2.inst          463                       # number of overall misses
+system.cpu2.icache.overall_misses::total          463                       # number of overall misses
+system.cpu2.icache.ReadReq_accesses::cpu2.inst       500019                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total       500019                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst       500019                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total       500019                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst       500019                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total       500019                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.000926                       # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst     0.000926                       # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst     0.000926                       # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
+system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu2.icache.writebacks::writebacks          152                       # number of writebacks
+system.cpu2.icache.writebacks::total              152                       # number of writebacks
+system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu3.dtb.fetch_hits                          0                       # ITB hits
+system.cpu3.dtb.fetch_misses                        0                       # ITB misses
+system.cpu3.dtb.fetch_acv                           0                       # ITB acv
+system.cpu3.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu3.dtb.read_hits                      124435                       # DTB read hits
+system.cpu3.dtb.read_misses                         8                       # DTB read misses
+system.cpu3.dtb.read_acv                            0                       # DTB read access violations
+system.cpu3.dtb.read_accesses                  124443                       # DTB read accesses
+system.cpu3.dtb.write_hits                      56340                       # DTB write hits
+system.cpu3.dtb.write_misses                       10                       # DTB write misses
+system.cpu3.dtb.write_acv                           0                       # DTB write access violations
+system.cpu3.dtb.write_accesses                  56350                       # DTB write accesses
+system.cpu3.dtb.data_hits                      180775                       # DTB hits
+system.cpu3.dtb.data_misses                        18                       # DTB misses
+system.cpu3.dtb.data_acv                            0                       # DTB access violations
+system.cpu3.dtb.data_accesses                  180793                       # DTB accesses
+system.cpu3.itb.fetch_hits                     500019                       # ITB hits
+system.cpu3.itb.fetch_misses                       13                       # ITB misses
+system.cpu3.itb.fetch_acv                           0                       # ITB acv
+system.cpu3.itb.fetch_accesses                 500032                       # ITB accesses
+system.cpu3.itb.read_hits                           0                       # DTB read hits
+system.cpu3.itb.read_misses                         0                       # DTB read misses
+system.cpu3.itb.read_acv                            0                       # DTB read access violations
+system.cpu3.itb.read_accesses                       0                       # DTB read accesses
+system.cpu3.itb.write_hits                          0                       # DTB write hits
+system.cpu3.itb.write_misses                        0                       # DTB write misses
+system.cpu3.itb.write_acv                           0                       # DTB write access violations
+system.cpu3.itb.write_accesses                      0                       # DTB write accesses
+system.cpu3.itb.data_hits                           0                       # DTB hits
+system.cpu3.itb.data_misses                         0                       # DTB misses
+system.cpu3.itb.data_acv                            0                       # DTB access violations
+system.cpu3.itb.data_accesses                       0                       # DTB accesses
+system.cpu3.workload.num_syscalls                  18                       # Number of system calls
+system.cpu3.numCycles                          500032                       # number of cpu cycles simulated
+system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu3.committedInsts                     500001                       # Number of instructions committed
+system.cpu3.committedOps                       500001                       # Number of ops (including micro ops) committed
+system.cpu3.num_int_alu_accesses               474689                       # Number of integer alu accesses
+system.cpu3.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu3.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu3.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
+system.cpu3.num_int_insts                      474689                       # number of integer instructions
+system.cpu3.num_fp_insts                           32                       # number of float instructions
+system.cpu3.num_int_register_reads             654286                       # number of times the integer registers were read
+system.cpu3.num_int_register_writes            371542                       # number of times the integer registers were written
+system.cpu3.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu3.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu3.num_mem_refs                       180793                       # number of memory refs
+system.cpu3.num_load_insts                     124443                       # Number of load instructions
+system.cpu3.num_store_insts                     56350                       # Number of store instructions
+system.cpu3.num_idle_cycles                         0                       # Number of idle cycles
+system.cpu3.num_busy_cycles                    500032                       # Number of busy cycles
+system.cpu3.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu3.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu3.Branches                            59023                       # Number of branches fetched
+system.cpu3.op_class::No_OpClass                18814      3.76%      3.76% # Class of executed instruction
+system.cpu3.op_class::IntAlu                   300388     60.08%     63.84% # Class of executed instruction
+system.cpu3.op_class::IntMult                      10      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::IntDiv                        0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::FloatAdd                     10      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::FloatCmp                      2      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::FloatCvt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::FloatMult                     2      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::FloatDiv                      0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::FloatSqrt                     0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdAdd                       0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdAddAcc                    0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdAlu                       0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdCmp                       0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdCvt                       0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdMisc                      0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdMult                      0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdMultAcc                   0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdShift                     0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdShiftAcc                  0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdSqrt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdFloatAdd                  0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdFloatAlu                  0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdFloatCmp                  0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdFloatCvt                  0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdFloatDiv                  0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMisc                 0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMult                 0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMultAcc              0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdFloatSqrt                 0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::MemRead                  124443     24.89%     88.73% # Class of executed instruction
+system.cpu3.op_class::MemWrite                  56350     11.27%    100.00% # Class of executed instruction
+system.cpu3.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu3.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu3.op_class::total                    500019                       # Class of executed instruction
+system.cpu3.dcache.tags.replacements               61                       # number of replacements
+system.cpu3.dcache.tags.tagsinuse          276.872320                       # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs             180312                       # Total number of references to valid blocks.
+system.cpu3.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs           389.442765                       # Average number of references to valid blocks.
+system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu3.dcache.tags.occ_blocks::cpu3.data   276.872320                       # Average occupied blocks per requestor
+system.cpu3.dcache.tags.occ_percent::cpu3.data     0.540766                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_percent::total     0.540766                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
+system.cpu3.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
+system.cpu3.dcache.tags.age_task_id_blocks_1024::1          138                       # Occupied blocks per task id
+system.cpu3.dcache.tags.age_task_id_blocks_1024::2          248                       # Occupied blocks per task id
+system.cpu3.dcache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
+system.cpu3.dcache.tags.tag_accesses           723563                       # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses          723563                       # Number of data accesses
+system.cpu3.dcache.ReadReq_hits::cpu3.data       124111                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data        56201                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
+system.cpu3.dcache.demand_hits::cpu3.data       180312                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data       180312                       # number of overall hits
+system.cpu3.dcache.overall_hits::total         180312                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data          324                       # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data          139                       # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
+system.cpu3.dcache.demand_misses::cpu3.data          463                       # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total           463                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data          463                       # number of overall misses
+system.cpu3.dcache.overall_misses::total          463                       # number of overall misses
+system.cpu3.dcache.ReadReq_accesses::cpu3.data       124435                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data        56340                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data       180775                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data       180775                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.002604                       # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.002467                       # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data     0.002561                       # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data     0.002561                       # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
+system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu3.dcache.writebacks::writebacks           29                       # number of writebacks
+system.cpu3.dcache.writebacks::total               29                       # number of writebacks
+system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu3.icache.tags.replacements              152                       # number of replacements
+system.cpu3.icache.tags.tagsinuse          218.086151                       # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs             499556                       # Total number of references to valid blocks.
+system.cpu3.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu3.icache.tags.avg_refs          1078.954644                       # Average number of references to valid blocks.
+system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu3.icache.tags.occ_blocks::cpu3.inst   218.086151                       # Average occupied blocks per requestor
+system.cpu3.icache.tags.occ_percent::cpu3.inst     0.425950                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total     0.425950                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::1          190                       # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::2          121                       # Occupied blocks per task id
+system.cpu3.icache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
+system.cpu3.icache.tags.tag_accesses           500482                       # Number of tag accesses
+system.cpu3.icache.tags.data_accesses          500482                       # Number of data accesses
+system.cpu3.icache.ReadReq_hits::cpu3.inst       499556                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst       499556                       # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total          499556                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst       499556                       # number of overall hits
+system.cpu3.icache.overall_hits::total         499556                       # number of overall hits
+system.cpu3.icache.ReadReq_misses::cpu3.inst          463                       # number of ReadReq misses
+system.cpu3.icache.ReadReq_misses::total          463                       # number of ReadReq misses
+system.cpu3.icache.demand_misses::cpu3.inst          463                       # number of demand (read+write) misses
+system.cpu3.icache.demand_misses::total           463                       # number of demand (read+write) misses
+system.cpu3.icache.overall_misses::cpu3.inst          463                       # number of overall misses
+system.cpu3.icache.overall_misses::total          463                       # number of overall misses
+system.cpu3.icache.ReadReq_accesses::cpu3.inst       500019                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total       500019                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst       500019                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total       500019                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst       500019                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total       500019                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.000926                       # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst     0.000926                       # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst     0.000926                       # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
+system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu3.icache.writebacks::writebacks          152                       # number of writebacks
+system.cpu3.icache.writebacks::total              152                       # number of writebacks
+system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.l2c.tags.replacements                        0                       # number of replacements
+system.l2c.tags.tagsinuse                 1962.780232                       # Cycle average of tags in use
+system.l2c.tags.total_refs                       1068                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                     2932                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     0.364256                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks      17.466765                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst      267.152061                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data      219.176305                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      267.152061                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      219.176305                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst      267.152061                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data      219.176305                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst      267.152061                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data      219.176305                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.000267                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.004076                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.003344                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.004076                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.003344                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.004076                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.003344                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst       0.004076                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.data       0.003344                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.029950                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024         2932                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1         1088                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1836                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.044739                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                    39936                       # Number of tag accesses
+system.l2c.tags.data_accesses                   39936                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks          116                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total             116                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks          608                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total             608                       # number of WritebackClean hits
+system.l2c.ReadCleanReq_hits::cpu0.inst            60                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst            60                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu2.inst            60                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu3.inst            60                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total               240                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu2.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu3.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total               36                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.inst                  60                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data                   9                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst                  60                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data                   9                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst                  60                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst                  60                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                     276                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst                 60                       # number of overall hits
+system.l2c.overall_hits::cpu0.data                  9                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst                 60                       # number of overall hits
+system.l2c.overall_hits::cpu1.data                  9                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst                 60                       # number of overall hits
+system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
+system.l2c.overall_hits::cpu3.inst                 60                       # number of overall hits
+system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
+system.l2c.overall_hits::total                    276                       # number of overall hits
+system.l2c.ReadExReq_misses::cpu0.data            139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data            139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data            139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3.data            139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total                556                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst          403                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst          403                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu2.inst          403                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu3.inst          403                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total            1612                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data          315                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data          315                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu2.data          315                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu3.data          315                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total           1260                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.inst               403                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data               454                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst               403                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data               454                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst               403                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data               454                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst               403                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.data               454                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                  3428                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst              403                       # number of overall misses
+system.l2c.overall_misses::cpu0.data              454                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst              403                       # number of overall misses
+system.l2c.overall_misses::cpu1.data              454                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst              403                       # number of overall misses
+system.l2c.overall_misses::cpu2.data              454                       # number of overall misses
+system.l2c.overall_misses::cpu3.inst              403                       # number of overall misses
+system.l2c.overall_misses::cpu3.data              454                       # number of overall misses
+system.l2c.overall_misses::total                 3428                       # number of overall misses
+system.l2c.WritebackDirty_accesses::writebacks          116                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total          116                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackClean_accesses::writebacks          608                       # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::total          608                       # number of WritebackClean accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data          139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data          139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data          139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data          139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total              556                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst          463                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst          463                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst          463                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu3.inst          463                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total          1852                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data          324                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data          324                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2.data          324                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3.data          324                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total         1296                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total                3704                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total               3704                       # number of overall (read+write) accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.972222                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.972222                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.972222                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.972222                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.972222                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.870410                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.980562                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.870410                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.980562                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.870410                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.980562                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.870410                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data       0.980562                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.925486                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.870410                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.980562                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.870410                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.980562                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.870410                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.980562                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.870410                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data      0.980562                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.925486                       # miss rate for overall accesses
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadResp               2872                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               556                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              556                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          2872                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         6856                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   6856                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port       219392                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  219392                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples              3428                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    3428    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                3428                       # Request fanout histogram
+system.toL2Bus.snoop_filter.tot_requests         4556                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests          852                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadResp              3148                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty          116                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean          608                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict             128                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq              556                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp             556                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq          1852                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq         1296                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                  8260                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        39360                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        39360                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        39360                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        39360                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total                 283392                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                               0                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples             4556                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean                   0                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev                  0                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                   4556    100.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value              0                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total               4556                       # Request fanout histogram
+
+---------- End Simulation Statistics   ----------
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..90c68ad5bf9f673ec974e6540537af7c6e63c1c0 100755 (executable)
@@ -0,0 +1,8 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+
+gzip: 
+gzip: stdout: Broken pipe
+stdout: Broken pipe
+stdout: Broken pipe
index 918548b7c6d99c9761af097551050b3f5f1a5ca1..42592b7b744fba7a2343c174651cf9a870feeb29 100755 (executable)
@@ -1,9 +1,19 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:01
-gem5 executing on zizzer, pid 33988
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
+gem5 compiled Feb  1 2016 02:06:47
+gem5 started Feb  1 2016 02:07:02
+gem5 executing on zizzer, pid 44723
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
 
-Skipping test: Test requires the 'EioProcess' SimObject.
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+49508 bytes wasted
+49508 bytes wasted
+49508 bytes wasted
+49508 bytes wasted
+>>>>Exiting @ tick 733914500 because a thread reached the max instruction count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..35a5b4177a5fed0bc44eda656503740888871d3d 100644 (file)
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.000734                       # Number of seconds simulated
+sim_ticks                                   733914500                       # Number of ticks simulated
+final_tick                                  733914500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 608165                       # Simulator instruction rate (inst/s)
+host_op_rate                                   608160                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              223170099                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 243400                       # Number of bytes of host memory used
+host_seconds                                     3.29                       # Real time elapsed on the host
+sim_insts                                     1999973                       # Number of instructions simulated
+sim_ops                                       1999973                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.bytes_read::cpu0.inst            25792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data            29056                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            25792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data            29056                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst            25792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data            29056                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst            25792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data            29056                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               219392                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst        25792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        25792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst        25792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst        25792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          103168                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu0.inst               403                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data               454                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst               403                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data               454                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst               403                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data               454                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst               403                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data               454                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  3428                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu0.inst            35143058                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            39590443                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst            35143058                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data            39590443                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst            35143058                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data            39590443                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst            35143058                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data            39590443                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               298934004                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst       35143058                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst       35143058                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst       35143058                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst       35143058                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          140572233                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst           35143058                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           39590443                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst           35143058                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data           39590443                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst           35143058                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data           39590443                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst           35143058                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data           39590443                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              298934004                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu0.dtb.fetch_hits                          0                       # ITB hits
+system.cpu0.dtb.fetch_misses                        0                       # ITB misses
+system.cpu0.dtb.fetch_acv                           0                       # ITB acv
+system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu0.dtb.read_hits                      124435                       # DTB read hits
+system.cpu0.dtb.read_misses                         8                       # DTB read misses
+system.cpu0.dtb.read_acv                            0                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  124443                       # DTB read accesses
+system.cpu0.dtb.write_hits                      56340                       # DTB write hits
+system.cpu0.dtb.write_misses                       10                       # DTB write misses
+system.cpu0.dtb.write_acv                           0                       # DTB write access violations
+system.cpu0.dtb.write_accesses                  56350                       # DTB write accesses
+system.cpu0.dtb.data_hits                      180775                       # DTB hits
+system.cpu0.dtb.data_misses                        18                       # DTB misses
+system.cpu0.dtb.data_acv                            0                       # DTB access violations
+system.cpu0.dtb.data_accesses                  180793                       # DTB accesses
+system.cpu0.itb.fetch_hits                     500020                       # ITB hits
+system.cpu0.itb.fetch_misses                       13                       # ITB misses
+system.cpu0.itb.fetch_acv                           0                       # ITB acv
+system.cpu0.itb.fetch_accesses                 500033                       # ITB accesses
+system.cpu0.itb.read_hits                           0                       # DTB read hits
+system.cpu0.itb.read_misses                         0                       # DTB read misses
+system.cpu0.itb.read_acv                            0                       # DTB read access violations
+system.cpu0.itb.read_accesses                       0                       # DTB read accesses
+system.cpu0.itb.write_hits                          0                       # DTB write hits
+system.cpu0.itb.write_misses                        0                       # DTB write misses
+system.cpu0.itb.write_acv                           0                       # DTB write access violations
+system.cpu0.itb.write_accesses                      0                       # DTB write accesses
+system.cpu0.itb.data_hits                           0                       # DTB hits
+system.cpu0.itb.data_misses                         0                       # DTB misses
+system.cpu0.itb.data_acv                            0                       # DTB access violations
+system.cpu0.itb.data_accesses                       0                       # DTB accesses
+system.cpu0.workload.num_syscalls                  18                       # Number of system calls
+system.cpu0.numCycles                         1467829                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.committedInsts                     500001                       # Number of instructions committed
+system.cpu0.committedOps                       500001                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses               474689                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu0.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                      474689                       # number of integer instructions
+system.cpu0.num_fp_insts                           32                       # number of float instructions
+system.cpu0.num_int_register_reads             654286                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes            371542                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                       180793                       # number of memory refs
+system.cpu0.num_load_insts                     124443                       # Number of load instructions
+system.cpu0.num_store_insts                     56350                       # Number of store instructions
+system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
+system.cpu0.num_busy_cycles                   1467829                       # Number of busy cycles
+system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu0.Branches                            59023                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                18814      3.76%      3.76% # Class of executed instruction
+system.cpu0.op_class::IntAlu                   300388     60.08%     63.84% # Class of executed instruction
+system.cpu0.op_class::IntMult                      10      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                     10      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      2      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     2      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     63.84% # Class of executed instruction
+system.cpu0.op_class::MemRead                  124443     24.89%     88.73% # Class of executed instruction
+system.cpu0.op_class::MemWrite                  56350     11.27%    100.00% # Class of executed instruction
+system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::total                    500019                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements               61                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          273.068294                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs             180312                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs           389.442765                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   273.068294                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.533337                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.533337                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          367                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses           723563                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses          723563                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data       124111                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data        56201                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
+system.cpu0.dcache.demand_hits::cpu0.data       180312                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data       180312                       # number of overall hits
+system.cpu0.dcache.overall_hits::total         180312                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data          324                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data          139                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
+system.cpu0.dcache.demand_misses::cpu0.data          463                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total           463                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data          463                       # number of overall misses
+system.cpu0.dcache.overall_misses::total          463                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     19649000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total     19649000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      8621000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total      8621000                       # number of WriteReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data     28270000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total     28270000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data     28270000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total     28270000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data       124435                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data        56340                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data       180775                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data       180775                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.002604                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.002467                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.002561                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.002561                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 60645.061728                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 60645.061728                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62021.582734                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 62021.582734                       # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 61058.315335                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 61058.315335                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 61058.315335                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 61058.315335                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks           29                       # number of writebacks
+system.cpu0.dcache.writebacks::total               29                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          324                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          139                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data          463                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data          463                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data     19325000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total     19325000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      8482000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total      8482000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     27807000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total     27807000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     27807000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total     27807000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002604                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002604                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002467                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002467                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002561                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.002561                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002561                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.002561                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 59645.061728                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 59645.061728                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 61021.582734                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 61021.582734                       # average WriteReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 60058.315335                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 60058.315335                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 60058.315335                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 60058.315335                       # average overall mshr miss latency
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.icache.tags.replacements              152                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          216.116668                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs             499557                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs          1078.956803                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   216.116668                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.422103                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.422103                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          311                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses           500483                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses          500483                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst       499557                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total         499557                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst       499557                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total          499557                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst       499557                       # number of overall hits
+system.cpu0.icache.overall_hits::total         499557                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst          463                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total          463                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst          463                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total           463                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst          463                       # number of overall misses
+system.cpu0.icache.overall_misses::total          463                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     25776500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total     25776500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst     25776500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total     25776500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst     25776500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total     25776500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst       500020                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total       500020                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst       500020                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total       500020                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst       500020                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total       500020                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.000926                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.000926                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.000926                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 55672.786177                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 55672.786177                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 55672.786177                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 55672.786177                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 55672.786177                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 55672.786177                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.writebacks::writebacks          152                       # number of writebacks
+system.cpu0.icache.writebacks::total              152                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          463                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst          463                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst          463                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     25313500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total     25313500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     25313500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total     25313500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     25313500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total     25313500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.000926                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.000926                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.000926                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.000926                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.000926                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.000926                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 54672.786177                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 54672.786177                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 54672.786177                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 54672.786177                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 54672.786177                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 54672.786177                       # average overall mshr miss latency
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dtb.fetch_hits                          0                       # ITB hits
+system.cpu1.dtb.fetch_misses                        0                       # ITB misses
+system.cpu1.dtb.fetch_acv                           0                       # ITB acv
+system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu1.dtb.read_hits                      124435                       # DTB read hits
+system.cpu1.dtb.read_misses                         8                       # DTB read misses
+system.cpu1.dtb.read_acv                            0                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  124443                       # DTB read accesses
+system.cpu1.dtb.write_hits                      56339                       # DTB write hits
+system.cpu1.dtb.write_misses                       10                       # DTB write misses
+system.cpu1.dtb.write_acv                           0                       # DTB write access violations
+system.cpu1.dtb.write_accesses                  56349                       # DTB write accesses
+system.cpu1.dtb.data_hits                      180774                       # DTB hits
+system.cpu1.dtb.data_misses                        18                       # DTB misses
+system.cpu1.dtb.data_acv                            0                       # DTB access violations
+system.cpu1.dtb.data_accesses                  180792                       # DTB accesses
+system.cpu1.itb.fetch_hits                     500014                       # ITB hits
+system.cpu1.itb.fetch_misses                       13                       # ITB misses
+system.cpu1.itb.fetch_acv                           0                       # ITB acv
+system.cpu1.itb.fetch_accesses                 500027                       # ITB accesses
+system.cpu1.itb.read_hits                           0                       # DTB read hits
+system.cpu1.itb.read_misses                         0                       # DTB read misses
+system.cpu1.itb.read_acv                            0                       # DTB read access violations
+system.cpu1.itb.read_accesses                       0                       # DTB read accesses
+system.cpu1.itb.write_hits                          0                       # DTB write hits
+system.cpu1.itb.write_misses                        0                       # DTB write misses
+system.cpu1.itb.write_acv                           0                       # DTB write access violations
+system.cpu1.itb.write_accesses                      0                       # DTB write accesses
+system.cpu1.itb.data_hits                           0                       # DTB hits
+system.cpu1.itb.data_misses                         0                       # DTB misses
+system.cpu1.itb.data_acv                            0                       # DTB access violations
+system.cpu1.itb.data_accesses                       0                       # DTB accesses
+system.cpu1.workload.num_syscalls                  18                       # Number of system calls
+system.cpu1.numCycles                         1467829                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.committedInsts                     499995                       # Number of instructions committed
+system.cpu1.committedOps                       499995                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses               474683                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu1.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts        38179                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                      474683                       # number of integer instructions
+system.cpu1.num_fp_insts                           32                       # number of float instructions
+system.cpu1.num_int_register_reads             654276                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes            371538                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                       180792                       # number of memory refs
+system.cpu1.num_load_insts                     124443                       # Number of load instructions
+system.cpu1.num_store_insts                     56349                       # Number of store instructions
+system.cpu1.num_idle_cycles                         0                       # Number of idle cycles
+system.cpu1.num_busy_cycles                   1467829                       # Number of busy cycles
+system.cpu1.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu1.Branches                            59022                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                18814      3.76%      3.76% # Class of executed instruction
+system.cpu1.op_class::IntAlu                   300383     60.08%     63.84% # Class of executed instruction
+system.cpu1.op_class::IntMult                      10      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                     10      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      2      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     2      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     63.84% # Class of executed instruction
+system.cpu1.op_class::MemRead                  124443     24.89%     88.73% # Class of executed instruction
+system.cpu1.op_class::MemWrite                  56349     11.27%    100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::total                    500013                       # Class of executed instruction
+system.cpu1.dcache.tags.replacements               61                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          273.065457                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs             180311                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs           389.440605                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   273.065457                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.533331                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.533331                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          367                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses           723559                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses          723559                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data       124111                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data        56200                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total         56200                       # number of WriteReq hits
+system.cpu1.dcache.demand_hits::cpu1.data       180311                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total          180311                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data       180311                       # number of overall hits
+system.cpu1.dcache.overall_hits::total         180311                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data          324                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data          139                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
+system.cpu1.dcache.demand_misses::cpu1.data          463                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total           463                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data          463                       # number of overall misses
+system.cpu1.dcache.overall_misses::total          463                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data     19649000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total     19649000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      8621500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total      8621500                       # number of WriteReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data     28270500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total     28270500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data     28270500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total     28270500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data       124435                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data        56339                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total        56339                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data       180774                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total       180774                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data       180774                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total       180774                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.002604                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.002467                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.002561                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.002561                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 60645.061728                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 60645.061728                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 62025.179856                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 62025.179856                       # average WriteReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 61059.395248                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 61059.395248                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 61059.395248                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 61059.395248                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.dcache.writebacks::writebacks           29                       # number of writebacks
+system.cpu1.dcache.writebacks::total               29                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          324                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          139                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data          463                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data          463                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data     19325000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total     19325000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      8482500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total      8482500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data     27807500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total     27807500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data     27807500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total     27807500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.002604                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.002604                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002467                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002467                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.002561                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.002561                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.002561                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.002561                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 59645.061728                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 59645.061728                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 61025.179856                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 61025.179856                       # average WriteReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 60059.395248                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 60059.395248                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 60059.395248                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 60059.395248                       # average overall mshr miss latency
+system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.icache.tags.replacements              152                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          216.114546                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs             499551                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs          1078.943844                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   216.114546                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.422099                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.422099                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          311                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses           500477                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses          500477                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst       499551                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total         499551                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst       499551                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total          499551                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst       499551                       # number of overall hits
+system.cpu1.icache.overall_hits::total         499551                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst          463                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total          463                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst          463                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total           463                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst          463                       # number of overall misses
+system.cpu1.icache.overall_misses::total          463                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     25783000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total     25783000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst     25783000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total     25783000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst     25783000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total     25783000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst       500014                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total       500014                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst       500014                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total       500014                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst       500014                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total       500014                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.000926                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.000926                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.000926                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 55686.825054                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 55686.825054                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 55686.825054                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 55686.825054                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 55686.825054                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 55686.825054                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.icache.writebacks::writebacks          152                       # number of writebacks
+system.cpu1.icache.writebacks::total              152                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          463                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst          463                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst          463                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     25320000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total     25320000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     25320000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total     25320000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     25320000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total     25320000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.000926                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.000926                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.000926                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.000926                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.000926                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.000926                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 54686.825054                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 54686.825054                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 54686.825054                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 54686.825054                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 54686.825054                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 54686.825054                       # average overall mshr miss latency
+system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu2.dtb.fetch_hits                          0                       # ITB hits
+system.cpu2.dtb.fetch_misses                        0                       # ITB misses
+system.cpu2.dtb.fetch_acv                           0                       # ITB acv
+system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu2.dtb.read_hits                      124435                       # DTB read hits
+system.cpu2.dtb.read_misses                         8                       # DTB read misses
+system.cpu2.dtb.read_acv                            0                       # DTB read access violations
+system.cpu2.dtb.read_accesses                  124443                       # DTB read accesses
+system.cpu2.dtb.write_hits                      56339                       # DTB write hits
+system.cpu2.dtb.write_misses                       10                       # DTB write misses
+system.cpu2.dtb.write_acv                           0                       # DTB write access violations
+system.cpu2.dtb.write_accesses                  56349                       # DTB write accesses
+system.cpu2.dtb.data_hits                      180774                       # DTB hits
+system.cpu2.dtb.data_misses                        18                       # DTB misses
+system.cpu2.dtb.data_acv                            0                       # DTB access violations
+system.cpu2.dtb.data_accesses                  180792                       # DTB accesses
+system.cpu2.itb.fetch_hits                     500009                       # ITB hits
+system.cpu2.itb.fetch_misses                       13                       # ITB misses
+system.cpu2.itb.fetch_acv                           0                       # ITB acv
+system.cpu2.itb.fetch_accesses                 500022                       # ITB accesses
+system.cpu2.itb.read_hits                           0                       # DTB read hits
+system.cpu2.itb.read_misses                         0                       # DTB read misses
+system.cpu2.itb.read_acv                            0                       # DTB read access violations
+system.cpu2.itb.read_accesses                       0                       # DTB read accesses
+system.cpu2.itb.write_hits                          0                       # DTB write hits
+system.cpu2.itb.write_misses                        0                       # DTB write misses
+system.cpu2.itb.write_acv                           0                       # DTB write access violations
+system.cpu2.itb.write_accesses                      0                       # DTB write accesses
+system.cpu2.itb.data_hits                           0                       # DTB hits
+system.cpu2.itb.data_misses                         0                       # DTB misses
+system.cpu2.itb.data_acv                            0                       # DTB access violations
+system.cpu2.itb.data_accesses                       0                       # DTB accesses
+system.cpu2.workload.num_syscalls                  18                       # Number of system calls
+system.cpu2.numCycles                         1467829                       # number of cpu cycles simulated
+system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu2.committedInsts                     499990                       # Number of instructions committed
+system.cpu2.committedOps                       499990                       # Number of ops (including micro ops) committed
+system.cpu2.num_int_alu_accesses               474678                       # Number of integer alu accesses
+system.cpu2.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu2.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu2.num_conditional_control_insts        38179                       # number of instructions that are conditional controls
+system.cpu2.num_int_insts                      474678                       # number of integer instructions
+system.cpu2.num_fp_insts                           32                       # number of float instructions
+system.cpu2.num_int_register_reads             654270                       # number of times the integer registers were read
+system.cpu2.num_int_register_writes            371533                       # number of times the integer registers were written
+system.cpu2.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu2.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu2.num_mem_refs                       180791                       # number of memory refs
+system.cpu2.num_load_insts                     124442                       # Number of load instructions
+system.cpu2.num_store_insts                     56349                       # Number of store instructions
+system.cpu2.num_idle_cycles                         0                       # Number of idle cycles
+system.cpu2.num_busy_cycles                   1467829                       # Number of busy cycles
+system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu2.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu2.Branches                            59022                       # Number of branches fetched
+system.cpu2.op_class::No_OpClass                18814      3.76%      3.76% # Class of executed instruction
+system.cpu2.op_class::IntAlu                   300379     60.07%     63.84% # Class of executed instruction
+system.cpu2.op_class::IntMult                      10      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::IntDiv                        0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::FloatAdd                     10      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::FloatCmp                      2      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::FloatCvt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::FloatMult                     2      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::FloatDiv                      0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::FloatSqrt                     0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdAdd                       0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdAddAcc                    0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdAlu                       0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdCmp                       0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdCvt                       0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdMisc                      0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdMult                      0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdMultAcc                   0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdShift                     0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdShiftAcc                  0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdSqrt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdFloatAdd                  0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdFloatAlu                  0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdFloatCmp                  0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdFloatCvt                  0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdFloatDiv                  0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMisc                 0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMult                 0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMultAcc              0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::SimdFloatSqrt                 0      0.00%     63.84% # Class of executed instruction
+system.cpu2.op_class::MemRead                  124442     24.89%     88.73% # Class of executed instruction
+system.cpu2.op_class::MemWrite                  56349     11.27%    100.00% # Class of executed instruction
+system.cpu2.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu2.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu2.op_class::total                    500008                       # Class of executed instruction
+system.cpu2.dcache.tags.replacements               61                       # number of replacements
+system.cpu2.dcache.tags.tagsinuse          273.062707                       # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs             180311                       # Total number of references to valid blocks.
+system.cpu2.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs           389.440605                       # Average number of references to valid blocks.
+system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu2.dcache.tags.occ_blocks::cpu2.data   273.062707                       # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data     0.533326                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total     0.533326                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
+system.cpu2.dcache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
+system.cpu2.dcache.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
+system.cpu2.dcache.tags.age_task_id_blocks_1024::2          367                       # Occupied blocks per task id
+system.cpu2.dcache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
+system.cpu2.dcache.tags.tag_accesses           723559                       # Number of tag accesses
+system.cpu2.dcache.tags.data_accesses          723559                       # Number of data accesses
+system.cpu2.dcache.ReadReq_hits::cpu2.data       124111                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data        56200                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total         56200                       # number of WriteReq hits
+system.cpu2.dcache.demand_hits::cpu2.data       180311                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total          180311                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data       180311                       # number of overall hits
+system.cpu2.dcache.overall_hits::total         180311                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data          324                       # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data          139                       # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
+system.cpu2.dcache.demand_misses::cpu2.data          463                       # number of demand (read+write) misses
+system.cpu2.dcache.demand_misses::total           463                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses::cpu2.data          463                       # number of overall misses
+system.cpu2.dcache.overall_misses::total          463                       # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data     19649000                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total     19649000                       # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      8621000                       # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total      8621000                       # number of WriteReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data     28270000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total     28270000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data     28270000                       # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total     28270000                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data       124435                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data        56339                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total        56339                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data       180774                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total       180774                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data       180774                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total       180774                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.002604                       # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.002467                       # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data     0.002561                       # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data     0.002561                       # miss rate for overall accesses
+system.cpu2.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 60645.061728                       # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 60645.061728                       # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 62021.582734                       # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total 62021.582734                       # average WriteReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 61058.315335                       # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 61058.315335                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 61058.315335                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 61058.315335                       # average overall miss latency
+system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu2.dcache.writebacks::writebacks           29                       # number of writebacks
+system.cpu2.dcache.writebacks::total               29                       # number of writebacks
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          324                       # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          139                       # number of WriteReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses::cpu2.data          463                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data          463                       # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data     19325000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total     19325000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      8482000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total      8482000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data     27807000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total     27807000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data     27807000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total     27807000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.002604                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.002604                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002467                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.002467                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.002561                       # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total     0.002561                       # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.002561                       # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total     0.002561                       # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 59645.061728                       # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 59645.061728                       # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 61021.582734                       # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 61021.582734                       # average WriteReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 60058.315335                       # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 60058.315335                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 60058.315335                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 60058.315335                       # average overall mshr miss latency
+system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu2.icache.tags.replacements              152                       # number of replacements
+system.cpu2.icache.tags.tagsinuse          216.112416                       # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs             499546                       # Total number of references to valid blocks.
+system.cpu2.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu2.icache.tags.avg_refs          1078.933045                       # Average number of references to valid blocks.
+system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu2.icache.tags.occ_blocks::cpu2.inst   216.112416                       # Average occupied blocks per requestor
+system.cpu2.icache.tags.occ_percent::cpu2.inst     0.422095                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total     0.422095                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
+system.cpu2.icache.tags.age_task_id_blocks_1024::2          311                       # Occupied blocks per task id
+system.cpu2.icache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
+system.cpu2.icache.tags.tag_accesses           500472                       # Number of tag accesses
+system.cpu2.icache.tags.data_accesses          500472                       # Number of data accesses
+system.cpu2.icache.ReadReq_hits::cpu2.inst       499546                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total         499546                       # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst       499546                       # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total          499546                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst       499546                       # number of overall hits
+system.cpu2.icache.overall_hits::total         499546                       # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst          463                       # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total          463                       # number of ReadReq misses
+system.cpu2.icache.demand_misses::cpu2.inst          463                       # number of demand (read+write) misses
+system.cpu2.icache.demand_misses::total           463                       # number of demand (read+write) misses
+system.cpu2.icache.overall_misses::cpu2.inst          463                       # number of overall misses
+system.cpu2.icache.overall_misses::total          463                       # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     25788500                       # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total     25788500                       # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst     25788500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total     25788500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst     25788500                       # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total     25788500                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst       500009                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total       500009                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst       500009                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total       500009                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst       500009                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total       500009                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.000926                       # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst     0.000926                       # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst     0.000926                       # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 55698.704104                       # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 55698.704104                       # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 55698.704104                       # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 55698.704104                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 55698.704104                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 55698.704104                       # average overall miss latency
+system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu2.icache.writebacks::writebacks          152                       # number of writebacks
+system.cpu2.icache.writebacks::total              152                       # number of writebacks
+system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          463                       # number of ReadReq MSHR misses
+system.cpu2.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
+system.cpu2.icache.demand_mshr_misses::cpu2.inst          463                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.overall_mshr_misses::cpu2.inst          463                       # number of overall MSHR misses
+system.cpu2.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst     25325500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total     25325500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst     25325500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total     25325500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst     25325500                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total     25325500                       # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.000926                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.000926                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.000926                       # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_miss_rate::total     0.000926                       # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.000926                       # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_miss_rate::total     0.000926                       # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 54698.704104                       # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 54698.704104                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 54698.704104                       # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 54698.704104                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 54698.704104                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 54698.704104                       # average overall mshr miss latency
+system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu3.dtb.fetch_hits                          0                       # ITB hits
+system.cpu3.dtb.fetch_misses                        0                       # ITB misses
+system.cpu3.dtb.fetch_acv                           0                       # ITB acv
+system.cpu3.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu3.dtb.read_hits                      124433                       # DTB read hits
+system.cpu3.dtb.read_misses                         8                       # DTB read misses
+system.cpu3.dtb.read_acv                            0                       # DTB read access violations
+system.cpu3.dtb.read_accesses                  124441                       # DTB read accesses
+system.cpu3.dtb.write_hits                      56339                       # DTB write hits
+system.cpu3.dtb.write_misses                       10                       # DTB write misses
+system.cpu3.dtb.write_acv                           0                       # DTB write access violations
+system.cpu3.dtb.write_accesses                  56349                       # DTB write accesses
+system.cpu3.dtb.data_hits                      180772                       # DTB hits
+system.cpu3.dtb.data_misses                        18                       # DTB misses
+system.cpu3.dtb.data_acv                            0                       # DTB access violations
+system.cpu3.dtb.data_accesses                  180790                       # DTB accesses
+system.cpu3.itb.fetch_hits                     500006                       # ITB hits
+system.cpu3.itb.fetch_misses                       13                       # ITB misses
+system.cpu3.itb.fetch_acv                           0                       # ITB acv
+system.cpu3.itb.fetch_accesses                 500019                       # ITB accesses
+system.cpu3.itb.read_hits                           0                       # DTB read hits
+system.cpu3.itb.read_misses                         0                       # DTB read misses
+system.cpu3.itb.read_acv                            0                       # DTB read access violations
+system.cpu3.itb.read_accesses                       0                       # DTB read accesses
+system.cpu3.itb.write_hits                          0                       # DTB write hits
+system.cpu3.itb.write_misses                        0                       # DTB write misses
+system.cpu3.itb.write_acv                           0                       # DTB write access violations
+system.cpu3.itb.write_accesses                      0                       # DTB write accesses
+system.cpu3.itb.data_hits                           0                       # DTB hits
+system.cpu3.itb.data_misses                         0                       # DTB misses
+system.cpu3.itb.data_acv                            0                       # DTB access violations
+system.cpu3.itb.data_accesses                       0                       # DTB accesses
+system.cpu3.workload.num_syscalls                  18                       # Number of system calls
+system.cpu3.numCycles                         1467829                       # number of cpu cycles simulated
+system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu3.committedInsts                     499987                       # Number of instructions committed
+system.cpu3.committedOps                       499987                       # Number of ops (including micro ops) committed
+system.cpu3.num_int_alu_accesses               474675                       # Number of integer alu accesses
+system.cpu3.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu3.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu3.num_conditional_control_insts        38179                       # number of instructions that are conditional controls
+system.cpu3.num_int_insts                      474675                       # number of integer instructions
+system.cpu3.num_fp_insts                           32                       # number of float instructions
+system.cpu3.num_int_register_reads             654265                       # number of times the integer registers were read
+system.cpu3.num_int_register_writes            371530                       # number of times the integer registers were written
+system.cpu3.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu3.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu3.num_mem_refs                       180790                       # number of memory refs
+system.cpu3.num_load_insts                     124441                       # Number of load instructions
+system.cpu3.num_store_insts                     56349                       # Number of store instructions
+system.cpu3.num_idle_cycles                         0                       # Number of idle cycles
+system.cpu3.num_busy_cycles                   1467829                       # Number of busy cycles
+system.cpu3.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu3.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu3.Branches                            59022                       # Number of branches fetched
+system.cpu3.op_class::No_OpClass                18814      3.76%      3.76% # Class of executed instruction
+system.cpu3.op_class::IntAlu                   300377     60.07%     63.84% # Class of executed instruction
+system.cpu3.op_class::IntMult                      10      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::IntDiv                        0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::FloatAdd                     10      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::FloatCmp                      2      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::FloatCvt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::FloatMult                     2      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::FloatDiv                      0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::FloatSqrt                     0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdAdd                       0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdAddAcc                    0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdAlu                       0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdCmp                       0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdCvt                       0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdMisc                      0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdMult                      0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdMultAcc                   0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdShift                     0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdShiftAcc                  0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdSqrt                      0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdFloatAdd                  0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdFloatAlu                  0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdFloatCmp                  0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdFloatCvt                  0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdFloatDiv                  0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMisc                 0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMult                 0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMultAcc              0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::SimdFloatSqrt                 0      0.00%     63.84% # Class of executed instruction
+system.cpu3.op_class::MemRead                  124441     24.89%     88.73% # Class of executed instruction
+system.cpu3.op_class::MemWrite                  56349     11.27%    100.00% # Class of executed instruction
+system.cpu3.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu3.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu3.op_class::total                    500005                       # Class of executed instruction
+system.cpu3.dcache.tags.replacements               61                       # number of replacements
+system.cpu3.dcache.tags.tagsinuse          273.059955                       # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs             180309                       # Total number of references to valid blocks.
+system.cpu3.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs           389.436285                       # Average number of references to valid blocks.
+system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu3.dcache.tags.occ_blocks::cpu3.data   273.059955                       # Average occupied blocks per requestor
+system.cpu3.dcache.tags.occ_percent::cpu3.data     0.533320                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_percent::total     0.533320                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
+system.cpu3.dcache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
+system.cpu3.dcache.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
+system.cpu3.dcache.tags.age_task_id_blocks_1024::2          367                       # Occupied blocks per task id
+system.cpu3.dcache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
+system.cpu3.dcache.tags.tag_accesses           723551                       # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses          723551                       # Number of data accesses
+system.cpu3.dcache.ReadReq_hits::cpu3.data       124109                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total         124109                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data        56200                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total         56200                       # number of WriteReq hits
+system.cpu3.dcache.demand_hits::cpu3.data       180309                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total          180309                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data       180309                       # number of overall hits
+system.cpu3.dcache.overall_hits::total         180309                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data          324                       # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data          139                       # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
+system.cpu3.dcache.demand_misses::cpu3.data          463                       # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total           463                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data          463                       # number of overall misses
+system.cpu3.dcache.overall_misses::total          463                       # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data     19649500                       # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total     19649500                       # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      8621000                       # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total      8621000                       # number of WriteReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data     28270500                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total     28270500                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data     28270500                       # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total     28270500                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data       124433                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total       124433                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data        56339                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total        56339                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data       180772                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total       180772                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data       180772                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total       180772                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.002604                       # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.002467                       # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data     0.002561                       # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data     0.002561                       # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 60646.604938                       # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 60646.604938                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 62021.582734                       # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 62021.582734                       # average WriteReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 61059.395248                       # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 61059.395248                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 61059.395248                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 61059.395248                       # average overall miss latency
+system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu3.dcache.writebacks::writebacks           29                       # number of writebacks
+system.cpu3.dcache.writebacks::total               29                       # number of writebacks
+system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          324                       # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          139                       # number of WriteReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses::cpu3.data          463                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses::cpu3.data          463                       # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data     19325500                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total     19325500                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      8482000                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total      8482000                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data     27807500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total     27807500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data     27807500                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total     27807500                       # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.002604                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.002604                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002467                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002467                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.002561                       # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_miss_rate::total     0.002561                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.002561                       # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_miss_rate::total     0.002561                       # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 59646.604938                       # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 59646.604938                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 61021.582734                       # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 61021.582734                       # average WriteReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 60059.395248                       # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total 60059.395248                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 60059.395248                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total 60059.395248                       # average overall mshr miss latency
+system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu3.icache.tags.replacements              152                       # number of replacements
+system.cpu3.icache.tags.tagsinuse          216.110261                       # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs             499543                       # Total number of references to valid blocks.
+system.cpu3.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu3.icache.tags.avg_refs          1078.926566                       # Average number of references to valid blocks.
+system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu3.icache.tags.occ_blocks::cpu3.inst   216.110261                       # Average occupied blocks per requestor
+system.cpu3.icache.tags.occ_percent::cpu3.inst     0.422090                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total     0.422090                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::2          311                       # Occupied blocks per task id
+system.cpu3.icache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
+system.cpu3.icache.tags.tag_accesses           500469                       # Number of tag accesses
+system.cpu3.icache.tags.data_accesses          500469                       # Number of data accesses
+system.cpu3.icache.ReadReq_hits::cpu3.inst       499543                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total         499543                       # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst       499543                       # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total          499543                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst       499543                       # number of overall hits
+system.cpu3.icache.overall_hits::total         499543                       # number of overall hits
+system.cpu3.icache.ReadReq_misses::cpu3.inst          463                       # number of ReadReq misses
+system.cpu3.icache.ReadReq_misses::total          463                       # number of ReadReq misses
+system.cpu3.icache.demand_misses::cpu3.inst          463                       # number of demand (read+write) misses
+system.cpu3.icache.demand_misses::total           463                       # number of demand (read+write) misses
+system.cpu3.icache.overall_misses::cpu3.inst          463                       # number of overall misses
+system.cpu3.icache.overall_misses::total          463                       # number of overall misses
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst     25793000                       # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total     25793000                       # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst     25793000                       # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total     25793000                       # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst     25793000                       # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total     25793000                       # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst       500006                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total       500006                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst       500006                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total       500006                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst       500006                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total       500006                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.000926                       # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst     0.000926                       # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst     0.000926                       # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 55708.423326                       # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::total 55708.423326                       # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 55708.423326                       # average overall miss latency
+system.cpu3.icache.demand_avg_miss_latency::total 55708.423326                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 55708.423326                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::total 55708.423326                       # average overall miss latency
+system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu3.icache.writebacks::writebacks          152                       # number of writebacks
+system.cpu3.icache.writebacks::total              152                       # number of writebacks
+system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          463                       # number of ReadReq MSHR misses
+system.cpu3.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
+system.cpu3.icache.demand_mshr_misses::cpu3.inst          463                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.overall_mshr_misses::cpu3.inst          463                       # number of overall MSHR misses
+system.cpu3.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst     25330000                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total     25330000                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst     25330000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total     25330000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst     25330000                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total     25330000                       # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.000926                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.000926                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.000926                       # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_miss_rate::total     0.000926                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.000926                       # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_miss_rate::total     0.000926                       # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 54708.423326                       # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 54708.423326                       # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 54708.423326                       # average overall mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::total 54708.423326                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 54708.423326                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::total 54708.423326                       # average overall mshr miss latency
+system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.l2c.tags.replacements                        0                       # number of replacements
+system.l2c.tags.tagsinuse                 1940.317854                       # Cycle average of tags in use
+system.l2c.tags.total_refs                       1068                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                     2932                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     0.364256                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks      17.170012                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst      264.661885                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data      216.132475                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      264.659128                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      216.130297                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst      264.656363                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data      216.128138                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst      264.653570                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data      216.125986                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.000262                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.004038                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.003298                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.004038                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.003298                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.004038                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.003298                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst       0.004038                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.data       0.003298                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.029607                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024         2932                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2904                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.044739                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                    39936                       # Number of tag accesses
+system.l2c.tags.data_accesses                   39936                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks          116                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total             116                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks          608                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total             608                       # number of WritebackClean hits
+system.l2c.ReadCleanReq_hits::cpu0.inst            60                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst            60                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu2.inst            60                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu3.inst            60                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total               240                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu2.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu3.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total               36                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.inst                  60                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data                   9                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst                  60                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data                   9                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst                  60                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst                  60                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                     276                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst                 60                       # number of overall hits
+system.l2c.overall_hits::cpu0.data                  9                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst                 60                       # number of overall hits
+system.l2c.overall_hits::cpu1.data                  9                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst                 60                       # number of overall hits
+system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
+system.l2c.overall_hits::cpu3.inst                 60                       # number of overall hits
+system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
+system.l2c.overall_hits::total                    276                       # number of overall hits
+system.l2c.ReadExReq_misses::cpu0.data            139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data            139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data            139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3.data            139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total                556                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst          403                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst          403                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu2.inst          403                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu3.inst          403                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total            1612                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data          315                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data          315                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu2.data          315                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu3.data          315                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total           1260                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.inst               403                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data               454                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst               403                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data               454                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst               403                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data               454                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst               403                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.data               454                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                  3428                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst              403                       # number of overall misses
+system.l2c.overall_misses::cpu0.data              454                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst              403                       # number of overall misses
+system.l2c.overall_misses::cpu1.data              454                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst              403                       # number of overall misses
+system.l2c.overall_misses::cpu2.data              454                       # number of overall misses
+system.l2c.overall_misses::cpu3.inst              403                       # number of overall misses
+system.l2c.overall_misses::cpu3.data              454                       # number of overall misses
+system.l2c.overall_misses::total                 3428                       # number of overall misses
+system.l2c.ReadExReq_miss_latency::cpu0.data      8272000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data      8272500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data      8272000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data      8272500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total     33089000                       # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu0.inst     23984000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu1.inst     23989500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu2.inst     23995500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu3.inst     24001000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total     95970000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data     18743500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data     18743500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu2.data     18743500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu3.data     18744000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total     74974500                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst     23984000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data     27015500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst     23989500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data     27016000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst     23995500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data     27015500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst     24001000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data     27016500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total       204033500                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst     23984000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data     27015500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst     23989500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data     27016000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst     23995500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data     27015500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst     24001000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data     27016500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total      204033500                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks          116                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total          116                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackClean_accesses::writebacks          608                       # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::total          608                       # number of WritebackClean accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data          139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data          139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data          139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data          139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total              556                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst          463                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst          463                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst          463                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu3.inst          463                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total          1852                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data          324                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data          324                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2.data          324                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3.data          324                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total         1296                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total                3704                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total               3704                       # number of overall (read+write) accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.972222                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.972222                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.972222                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.972222                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.972222                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.870410                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.980562                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.870410                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.980562                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.870410                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.980562                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.870410                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data       0.980562                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.925486                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.870410                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.980562                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.870410                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.980562                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.870410                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.980562                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.870410                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data      0.980562                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.925486                       # miss rate for overall accesses
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 59510.791367                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 59514.388489                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 59510.791367                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 59514.388489                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 59512.589928                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 59513.647643                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 59527.295285                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 59542.183623                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 59555.831266                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 59534.739454                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 59503.174603                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 59503.174603                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 59503.174603                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 59504.761905                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 59503.571429                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 59513.647643                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 59505.506608                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 59527.295285                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 59506.607930                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 59542.183623                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 59505.506608                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 59555.831266                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 59507.709251                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 59519.690782                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 59513.647643                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 59505.506608                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 59527.295285                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 59506.607930                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 59542.183623                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 59505.506608                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 59555.831266                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 59507.709251                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 59519.690782                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.ReadExReq_mshr_misses::cpu0.data          139                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data          139                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data          139                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu3.data          139                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total           556                       # number of ReadExReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu0.inst          403                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst          403                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu2.inst          403                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu3.inst          403                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total         1612                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data          315                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data          315                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu2.data          315                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu3.data          315                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total         1260                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst          403                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data          454                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst          403                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data          454                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst          403                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data          454                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.inst          403                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.data          454                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total             3428                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst          403                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data          454                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst          403                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data          454                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst          403                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data          454                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.inst          403                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.data          454                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total            3428                       # number of overall MSHR misses
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      6882000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data      6882500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data      6882000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data      6882500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total     27529000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     19954000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst     19959500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst     19965500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst     19971000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total     79850000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data     15593500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     15593500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data     15593500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data     15594000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total     62374500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst     19954000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data     22475500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     19959500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data     22476000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst     19965500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data     22475500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst     19971000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data     22476500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total    169753500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst     19954000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data     22475500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst     19959500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data     22476000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst     19965500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data     22475500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst     19971000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data     22476500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total    169753500                       # number of overall MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.870410                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.870410                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.870410                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.870410                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.870410                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.972222                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.972222                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.972222                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.972222                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.972222                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.870410                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.980562                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.870410                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.980562                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.870410                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.980562                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.870410                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data     0.980562                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.925486                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.870410                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.980562                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.870410                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.980562                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.870410                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.980562                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.870410                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data     0.980562                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.925486                       # mshr miss rate for overall accesses
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 49510.791367                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 49514.388489                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 49510.791367                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 49514.388489                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 49512.589928                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49513.647643                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 49527.295285                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 49542.183623                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 49555.831266                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 49534.739454                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 49503.174603                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 49503.174603                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 49503.174603                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 49504.761905                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 49503.571429                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49513.647643                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 49505.506608                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 49527.295285                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 49506.607930                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49542.183623                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 49505.506608                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 49555.831266                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49507.709251                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 49519.690782                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49513.647643                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 49505.506608                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 49527.295285                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 49506.607930                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49542.183623                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 49505.506608                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49555.831266                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49507.709251                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 49519.690782                       # average overall mshr miss latency
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadResp               2872                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               556                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              556                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          2872                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         6856                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   6856                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port       219392                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  219392                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples              3442                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    3442    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                3442                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             3471468                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
+system.membus.respLayer1.occupancy           17140000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              2.3                       # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests         4556                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests          852                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadResp              3148                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty          116                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean          608                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict             128                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq              556                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp             556                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq          1852                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq         1296                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                  8260                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        39360                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        39360                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        39360                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        39360                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total                 283392                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                               0                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples             3704                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean                   0                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev                  0                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                   3704    100.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value              0                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total               3704                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy            3002000                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              0.4                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy            694500                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy            694500                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy            694500                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization             0.1                       # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy            694500                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization             0.1                       # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy            694500                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization             0.1                       # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy            694500                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization             0.1                       # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy            694500                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization             0.1                       # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy            694500                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization             0.1                       # Layer utilization (%)
+
+---------- End Simulation Statistics   ----------