Added support for parsing attributes on parameters in Verilog frontent. Content of...

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index d23009e60f41dd32fd5a28b39b5175a7be22d8e7..ce1eb31d887ac6a974b6fcde60d4c4f09a8c85a6 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1193,7 +1193,7 @@ param_range:
        };
 
 param_decl:
-       TOK_PARAMETER {
+       attr TOK_PARAMETER {
                astbuf1 = new AstNode(AST_PARAMETER);
                astbuf1->children.push_back(AstNode::mkconst_int(0, true));
        } param_signed param_integer param_real param_range param_decl_list ';' {
@@ -1201,7 +1201,7 @@ param_decl:
        };
 
 localparam_decl:
-       TOK_LOCALPARAM {
+       attr TOK_LOCALPARAM {
                astbuf1 = new AstNode(AST_LOCALPARAM);
                astbuf1->children.push_back(AstNode::mkconst_int(0, true));
        } param_signed param_integer param_real param_range param_decl_list ';' {