RISC-V: Correct legacy misa register number.
authorJim Wilson <jimw@sifive.com>
Tue, 17 Jul 2018 16:42:23 +0000 (09:42 -0700)
committerJim Wilson <jimw@sifive.com>
Tue, 17 Jul 2018 16:42:23 +0000 (09:42 -0700)
gdb/
* riscv-tdep.h (DECLARE_CSR): Use RISCV_FIRST_CSR_REGNUM instead of
RISCV_LAST_FP_REGNUM + 1.
(RSICV_CSR_LEGACY_MISA_REGNUM): Add RISCV_FIRST_CSR_REGNUM.

gdb/ChangeLog
gdb/riscv-tdep.h

index 6f5487c10e8b1a7f25e673db30417c730b04f911..ecf360fefe34a73258dbb384b4d16e9294c74bc1 100644 (file)
@@ -1,3 +1,9 @@
+2018-07-17  Jim Wilson  <jimw@sifive.com>
+
+       * riscv-tdep.h (DECLARE_CSR): Use RISCV_FIRST_CSR_REGNUM instead of
+       RISCV_LAST_FP_REGNUM + 1.
+       (RSICV_CSR_LEGACY_MISA_REGNUM): Add RISCV_FIRST_CSR_REGNUM.
+
 2018-07-17  Tom Tromey  <tom@tromey.com>
 
        * configure.ac: Remove --disable-gdbcli.
index ab5e278759cce3e6e871136a177eca998ff1e206..4fc05976ba81ea231285303fabb6b49441db20b8 100644 (file)
@@ -39,11 +39,11 @@ enum
   RISCV_LAST_FP_REGNUM = 64,   /* Last Floating Point Register */
 
   RISCV_FIRST_CSR_REGNUM = 65,  /* First CSR */
-#define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM = RISCV_LAST_FP_REGNUM + 1 + num,
+#define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
 #include "opcode/riscv-opc.h"
 #undef DECLARE_CSR
   RISCV_LAST_CSR_REGNUM = 4160,
-  RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10,
+  RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM,
 
   RISCV_PRIV_REGNUM = 4161,