vc4: Disable early Z with computed depth.
authorEric Anholt <eric@anholt.net>
Tue, 19 Jul 2016 18:10:36 +0000 (11:10 -0700)
committerEric Anholt <eric@anholt.net>
Tue, 26 Jul 2016 20:47:50 +0000 (13:47 -0700)
We don't tell the hardware whether we're computing depth, so we need
to manage early Z state manually.  Fixes piglit early-z.

src/gallium/drivers/vc4/vc4_context.h
src/gallium/drivers/vc4/vc4_emit.c
src/gallium/drivers/vc4/vc4_program.c

index 751f0437807e66fb86d011f49ce2ff0f4baf3858..b656539611cdfd1dc8dbfab0fcaf0d7bbdc936ea 100644 (file)
@@ -142,6 +142,8 @@ struct vc4_compiled_shader {
         /** bitmask of which inputs are color inputs, for flat shade handling. */
         uint32_t color_inputs;
 
+        bool disable_early_z;
+
         uint8_t num_inputs;
 
         /* Byte offsets for the start of the vertex attributes 0-7, and the
index 5d6479777551fc5b8c97e63cd2e3b53806379ad0..8b192da47f29c687d254c878777a548ebb49ca0c 100644 (file)
@@ -71,7 +71,9 @@ vc4_emit_state(struct pipe_context *pctx)
                 vc4->draw_max_y = MAX2(vc4->draw_max_y, maxy);
         }
 
-        if (vc4->dirty & (VC4_DIRTY_RASTERIZER | VC4_DIRTY_ZSA)) {
+        if (vc4->dirty & (VC4_DIRTY_RASTERIZER |
+                          VC4_DIRTY_ZSA |
+                          VC4_DIRTY_COMPILED_FS)) {
                 uint8_t ez_enable_mask_out = ~0;
 
                 /* HW-2905: If the RCL ends up doing a full-res load when
@@ -83,7 +85,7 @@ vc4_emit_state(struct pipe_context *pctx)
                  * was seeing bad rendering on glxgears -samples 4 even in
                  * that case.
                  */
-                if (vc4->msaa)
+                if (vc4->msaa || vc4->prog.fs->disable_early_z)
                         ez_enable_mask_out &= ~VC4_CONFIG_BITS_EARLY_Z;
 
                 cl_u8(&bcl, VC4_PACKET_CONFIGURATION_BITS);
index 4ee49a258f129bf9bb12b5fd594bfc6c876473af..9057b86068e38cebccc079a8fa9c38b004dc7f7f 100644 (file)
@@ -2253,6 +2253,11 @@ vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
                         shader->input_slots[shader->num_inputs] = *slot;
                         shader->num_inputs++;
                 }
+
+                /* Note: the temporary clone in c->s has been freed. */
+                nir_shader *orig_shader = key->shader_state->base.ir.nir;
+                if (orig_shader->info.outputs_written & (1 << FRAG_RESULT_DEPTH))
+                        shader->disable_early_z = true;
         } else {
                 shader->num_inputs = c->num_inputs;