vc4->draw_max_y = MAX2(vc4->draw_max_y, maxy);
}
- if (vc4->dirty & (VC4_DIRTY_RASTERIZER | VC4_DIRTY_ZSA)) {
+ if (vc4->dirty & (VC4_DIRTY_RASTERIZER |
+ VC4_DIRTY_ZSA |
+ VC4_DIRTY_COMPILED_FS)) {
uint8_t ez_enable_mask_out = ~0;
/* HW-2905: If the RCL ends up doing a full-res load when
* was seeing bad rendering on glxgears -samples 4 even in
* that case.
*/
- if (vc4->msaa)
+ if (vc4->msaa || vc4->prog.fs->disable_early_z)
ez_enable_mask_out &= ~VC4_CONFIG_BITS_EARLY_Z;
cl_u8(&bcl, VC4_PACKET_CONFIGURATION_BITS);
shader->input_slots[shader->num_inputs] = *slot;
shader->num_inputs++;
}
+
+ /* Note: the temporary clone in c->s has been freed. */
+ nir_shader *orig_shader = key->shader_state->base.ir.nir;
+ if (orig_shader->info.outputs_written & (1 << FRAG_RESULT_DEPTH))
+ shader->disable_early_z = true;
} else {
shader->num_inputs = c->num_inputs;