Make the GSR into a renamed control register. It should be split into a renamed part...

--HG--
extra : convert_revision : ffeb4f874bd4430255064f6e8bcb135309932ff8

diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index 110b37d1535d8a1d09f64c651086f79b2b2da715..a627a2e6f34da737c773520c36182c148c3d145e 100644 (file)
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -149,7 +149,8 @@ def operands {{
     'Fprs':            ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
     'Pcr':             ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
     'Pic':             ('ControlReg', 'udw', 'MISCREG_PIC', None, 45),
-    'Gsr':             ('ControlReg', 'udw', 'MISCREG_GSR', None, 46),
+#   'Gsr':             ('ControlReg', 'udw', 'MISCREG_GSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 46),
+    'Gsr':             ('IntReg', 'udw', 'NumIntArchRegs + 8', None, 46),
     'Softint':         ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),
     'SoftintSet':      ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),
     'SoftintClr':      ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),

diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index d0b8827f388ddda3dad85acc710f924244957b05..8b3ec36a6b801156ff1d5f6ca2f37eca41cb0d06 100644 (file)
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -58,7 +58,7 @@ namespace SparcISA
 
     // These enumerate all the registers for dependence tracking.
     enum DependenceTags {
-        FP_Base_DepTag = 32*3+8,
+        FP_Base_DepTag = 32*3+9,
         Ctrl_Base_DepTag = FP_Base_DepTag + 64
     };
 

diff --git a/src/arch/sparc/sparc_traits.hh b/src/arch/sparc/sparc_traits.hh
index d89ec11198a8f3a7ef1d481a34cd06d030f9ac3f..715c08c03bf702c4ef44e678c1b57f541d644eb2 100644 (file)
--- a/src/arch/sparc/sparc_traits.hh
+++ b/src/arch/sparc/sparc_traits.hh
@@ -42,7 +42,7 @@ namespace SparcISA
     // Number of register windows, can legally be 3 to 32
     const int NWindows = 8;
     //const int NumMicroIntRegs = 1;
-    const int NumMicroIntRegs = 8;
+    const int NumMicroIntRegs = 9;
 
 //    const int NumRegularIntRegs = MaxGL * 8 + NWindows * 16;
 //    const int NumMicroIntRegs = 1;