radeon/llvm: Cleanup makefile
authorTom Stellard <thomas.stellard@amd.com>
Wed, 29 Aug 2012 13:01:15 +0000 (13:01 +0000)
committerTom Stellard <thomas.stellard@amd.com>
Thu, 6 Sep 2012 13:30:42 +0000 (13:30 +0000)
Hopefully, this will fix all the parallel make problems people have
been having.

src/gallium/drivers/radeon/Makefile
src/gallium/drivers/radeon/Makefile.sources

index 43f668a3f04de3790ad0a4dfcd6f8ce5dd7aeff5..7f1c61352e3db9f77a30872384f38bbe6e35f721 100644 (file)
@@ -20,8 +20,6 @@ tablegen = $(TBLGEN) -I $(LLVM_INCLUDEDIR) $1 $2 -o $3
 
 HAVE_LLVM_INTRINSICS = $(shell grep IntrinsicsR600.td $(LLVM_INCLUDEDIR)/llvm/Intrinsics.td)
 
-gen: $(GENERATED_SOURCES)
-
 SIRegisterInfo.td: SIGenRegisterInfo.pl
        $(PERL) $^ > $@
 
@@ -38,37 +36,37 @@ endif
 R600RegisterInfo.td: R600GenRegisterInfo.pl
        $(PERL) $^ > $@
 
-AMDGPUGenRegisterInfo.inc: *.td
+AMDGPUGenRegisterInfo.inc: $(TD_FILES)
        $(call tablegen, -gen-register-info, AMDGPU.td, $@)
 
-AMDGPUGenInstrInfo.inc: *.td
+AMDGPUGenInstrInfo.inc: $(TD_FILES)
        $(call tablegen, -gen-instr-info, AMDGPU.td, $@)
 
-AMDGPUGenAsmWriter.inc: *.td
+AMDGPUGenAsmWriter.inc: $(TD_FILES)
        $(call tablegen, -gen-asm-writer, AMDGPU.td, $@)
 
-AMDGPUGenDAGISel.inc: *.td
+AMDGPUGenDAGISel.inc: $(TD_FILES)
        $(call tablegen, -gen-dag-isel, AMDGPU.td, $@)
 
-AMDGPUGenCallingConv.inc: *.td
+AMDGPUGenCallingConv.inc: $(TD_FILES)
        $(call tablegen, -gen-callingconv, AMDGPU.td, $@)
 
-AMDGPUGenSubtargetInfo.inc: *.td
+AMDGPUGenSubtargetInfo.inc: $(TD_FILES)
        $(call tablegen, -gen-subtarget, AMDGPU.td, $@)
 
-AMDGPUGenEDInfo.inc: *.td
+AMDGPUGenEDInfo.inc: $(TD_FILES)
        $(call tablegen, -gen-enhanced-disassembly-info, AMDGPU.td, $@)
 
-AMDGPUGenIntrinsics.inc: *.td
+AMDGPUGenIntrinsics.inc: $(TD_FILES)
        $(call tablegen, -gen-tgt-intrinsic, AMDGPU.td, $@)
 
-AMDGPUGenCodeEmitter.inc: *.td
+AMDGPUGenCodeEmitter.inc: $(TD_FILES)
        $(call tablegen, -gen-emitter, AMDGPU.td, $@)
 
-AMDGPUGenMCCodeEmitter.inc: *.td
+AMDGPUGenMCCodeEmitter.inc: $(TD_FILES)
        $(call tablegen, -mc-emitter -gen-emitter, AMDGPU.td, $@)
 
-AMDGPUGenDFAPacketizer.inc: *.td
+AMDGPUGenDFAPacketizer.inc: $(TD_FILES)
        $(call tablegen, -gen-dfa-packetizer, AMDGPU.td, $@)
 
 LOADER_LIBS=$(shell llvm-config --libs bitreader asmparser)
index 2eb1120895780328a984a253b81e0d721680089f..333dd03392d288f91216c5acf1c55dacfd93ece6 100644 (file)
@@ -1,4 +1,30 @@
 
+TD_FILES := \
+       AMDGPU.td               \
+       AMDGPUInstrInfo.td      \
+       AMDGPUInstructions.td   \
+       AMDGPUIntrinsics.td     \
+       AMDGPURegisterInfo.td   \
+       AMDILBase.td            \
+       AMDILInstrInfo.td       \
+       AMDILIntrinsics.td      \
+       AMDILRegisterInfo.td    \
+       Processors.td           \
+       R600InstrInfo.td        \
+       R600Instructions.td     \
+       R600Intrinsics.td       \
+       R600IntrinsicsNoOpenCL.td       \
+       R600IntrinsicsOpenCL.td \
+       R600RegisterInfo.td     \
+       R600Schedule.td         \
+       SIInstrFormats.td       \
+       SIInstrInfo.td          \
+       SIInstructions.td       \
+       SIIntrinsics.td         \
+       SIRegisterInfo.td       \
+       SISchedule.td
+
+
 GENERATED_SOURCES := \
        R600Intrinsics.td               \
        R600RegisterInfo.td             \