Fix clock signal for ECP5 PHY

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index 5e3398308eadda3aa34aaa0254d9feff0fe82c6f..289c001d3a6a49b151152461fce506a4602dacca 100644 (file)
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -275,7 +275,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                                      p_DQS_LO_DEL_ADJ="MINUS",
                                      p_DQS_LO_DEL_VAL=4,
                                      # Clocks / Reset
-                                     i_SCLK=ClockSignal("sys"),
+                                     i_SCLK=ClockSignal("sync"),
                                      i_ECLK=ClockSignal("sync2x"),
                                      i_RST=ResetSignal("sync2x"),
                                      i_DDRDEL=self.init.delay,