emulate callpal halt for non FULL_SYSTEM

in the process make m5_exit more generic

arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
    There's no reason that this needs to be in an arch specific file
arch/alpha/isa_desc:
    m5_exit -> SimExit
    Emulate callpal halt and cause the simulator to exit
    while we're at it, sort #includes
sim/sim_events.cc:
sim/sim_events.hh:
    move the m5_exit function here, renaming it to SimExit.
    Also Allow the caller to pass in the termination message.

--HG--
extra : convert_revision : 54b43b17a412ab387b8672c27ef0b04fce10ee15

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 7330d7ce0094254519fb1c385f26f0a306e0e698..ff1ecc4bfb1855eb02205a304210885298f3e931 100644 (file)
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -54,12 +54,6 @@ AlphaISA::initCPU(RegFile *regs)
     regs->npc = regs->pc + sizeof(MachInst);
 }
 
-void
-m5_exit()
-{
-    static SimExitEvent event("m5_exit instruction encountered");
-}
-
 ////////////////////////////////////////////////////////////////////////
 //
 // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE

diff --git a/arch/alpha/ev5.hh b/arch/alpha/ev5.hh
index 921aeb12d71ca004f51be5b88f21ae517f839718..aa3d7e226c2afa0ceff69128c1a0c203cfa1e2c3 100644 (file)
--- a/arch/alpha/ev5.hh
+++ b/arch/alpha/ev5.hh
@@ -9,8 +9,6 @@
 
 #include "targetarch/isa_traits.hh"
 
-void m5_exit();
-
 ////////////////////////////////////////////////////////////////////////
 //
 //

diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 89ec05c0e26a5c3e17e8614160128d5ffbd06903..ac6934fac47b88d673803379bcde62ebf0a22205 100644 (file)
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -18,17 +18,17 @@ let {{
 #include <fenv.h>
 #endif
 
-#include "cpu/static_inst.hh"
 #include "base/cprintf.hh"
 #include "base/misc.hh"
-#include "cpu/full_cpu/op_class.hh"
-
 #include "cpu/exec_context.hh"
-#include "cpu/simple_cpu/simple_cpu.hh"
-#include "cpu/full_cpu/spec_state.hh"
-#include "cpu/full_cpu/full_cpu.hh"
 #include "cpu/exetrace.hh"
+#include "cpu/full_cpu/full_cpu.hh"
+#include "cpu/full_cpu/op_class.hh"
+#include "cpu/full_cpu/spec_state.hh"
+#include "cpu/simple_cpu/simple_cpu.hh"
+#include "cpu/static_inst.hh"
 #include "sim/annotation.hh"
+#include "sim/sim_events.hh"
 
 #ifdef FULL_SYSTEM
 #include "targetarch/ev5.hh"
@@ -2356,6 +2356,10 @@ decode OPCODE default Unknown::unknown() {
 #else
     0x00: decode PALFUNC {
        format EmulatedCallPal {
+           0x00: halt ({{
+               if (!xc->misspeculating()) 
+                   SimExit("halt instruction encountered");
+           }});
            0x83: callsys({{ xc->syscall(); }});
            // Read uniq reg into ABI return value register (r0)
            0x9e: rduniq({{ R0 = Runiq; }});
@@ -2414,7 +2418,7 @@ decode OPCODE default Unknown::unknown() {
            }}, No_OpClass);
            0x20: m5exit({{
                if (!xc->misspeculating())
-                   m5_exit();
+                   SimExit("m5_exit instruction encountered");
            }}, No_OpClass);
             0x30: initparam({{ Ra = xc->cpu->system->init_param; }});
             0x40: resetstats({{

diff --git a/sim/sim_events.cc b/sim/sim_events.cc
index b622cb14d8e2a9647c48f984c7628da2e6e210e6..5f24de5161cb581209ca209abc1501e21f57053a 100644 (file)
--- a/sim/sim_events.cc
+++ b/sim/sim_events.cc
@@ -63,6 +63,11 @@ SimExitEvent::description()
     return "simulation termination";
 }
 
+void
+SimExit(const char *message)
+{
+    static SimExitEvent event(message);
+}
 
 //
 // constructor: automatically schedules at specified time

diff --git a/sim/sim_events.hh b/sim/sim_events.hh
index b1ae7793aa92f47212ebf502a1c3d4182f465a56..0029a8404df88f4c3544a91a68c463765b450d4a 100644 (file)
--- a/sim/sim_events.hh
+++ b/sim/sim_events.hh
@@ -66,6 +66,8 @@ class SimExitEvent : public Event
     virtual const char *description();
 };
 
+void SimExit(const char *message);
+
 //
 // Event class to terminate simulation after 'n' related events have
 // occurred using a shared counter: used to terminate when *all*