(no commit message)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 88f3626f2cafeba54f4a9267edc71834c3fd405b..8137c0070e9fed590c4f12245fc05e67bb886d74 100644 (file)
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -129,7 +129,7 @@ Brief description of fields:
 * **sz=1** if predication is enabled and `sz=1` and a predicate
   element bit is zero, `SNZ` will
   be substituted in place of the CR bit selected by `BI`.
-  the src CR Field when the predicate bit is zero. Contrast this with
+  Contrast this with
   normal SVP64 `sz=1` behaviour, where *only* a zero is put in
   place of masked-out predicate bits.
 * **sz=0** When `sz=0` skipping occurs as usual, but unlike all