*/
machine(L0Cache, "MESI Directory L0 Cache")
- : Sequencer * sequencer,
- CacheMemory * Icache,
- CacheMemory * Dcache,
- Cycles request_latency = 2,
- Cycles response_latency = 2,
- bool send_evictions,
+ : Sequencer * sequencer;
+ CacheMemory * Icache;
+ CacheMemory * Dcache;
+ Cycles request_latency := 2;
+ Cycles response_latency := 2;
+ bool send_evictions;
{
// NODE L0 CACHE
// From this node's L0 cache to the network
*/
machine(L1Cache, "MESI Directory L1 Cache CMP")
- : CacheMemory * cache,
- int l2_select_num_bits,
- Cycles l1_request_latency = 2,
- Cycles l1_response_latency = 2,
- Cycles to_l2_latency = 1,
+ : CacheMemory * cache;
+ int l2_select_num_bits;
+ Cycles l1_request_latency := 2;
+ Cycles l1_response_latency := 2;
+ Cycles to_l2_latency := 1;
{
// From this node's L1 cache TO the network
// a local L1 -> this L2 bank, currently ordered with directory forwarded requests
MessageBuffer responseToL2, network="To", virtual_network="1", ordered="false", vnet_type="response";
MessageBuffer unblockToL2, network="To", virtual_network="2", ordered="false", vnet_type="unblock";
-
// To this node's L1 cache FROM the network
// a L2 bank -> this L1
MessageBuffer requestFromL2, network="From", virtual_network="0", ordered="false", vnet_type="request";
*/
machine(L1Cache, "MESI Directory L1 Cache CMP")
- : Sequencer * sequencer,
- CacheMemory * L1Icache,
- CacheMemory * L1Dcache,
- Prefetcher * prefetcher = 'NULL',
- int l2_select_num_bits,
- Cycles l1_request_latency = 2,
- Cycles l1_response_latency = 2,
- Cycles to_l2_latency = 1,
- bool send_evictions,
- bool enable_prefetch = "False"
+ : Sequencer * sequencer;
+ CacheMemory * L1Icache;
+ CacheMemory * L1Dcache;
+ Prefetcher * prefetcher;
+ int l2_select_num_bits;
+ Cycles l1_request_latency := 2;
+ Cycles l1_response_latency := 2;
+ Cycles to_l2_latency := 1;
+ bool send_evictions;
+ bool enable_prefetch := "False";
{
// NODE L1 CACHE
// From this node's L1 cache TO the network
*/
machine(L2Cache, "MESI Directory L2 Cache CMP")
- : CacheMemory * L2cache,
- Cycles l2_request_latency = 2,
- Cycles l2_response_latency = 2,
- Cycles to_l1_latency = 1
+ : CacheMemory * L2cache;
+ Cycles l2_request_latency := 2;
+ Cycles l2_response_latency := 2;
+ Cycles to_l1_latency := 1;
{
// L2 BANK QUEUES
// From local bank of L2 cache TO the network
machine(Directory, "MESI Two Level directory protocol")
- : DirectoryMemory * directory,
- MemoryControl * memBuffer,
- Cycles to_mem_ctrl_latency = 1,
- Cycles directory_latency = 6,
+ : DirectoryMemory * directory;
+ MemoryControl * memBuffer;
+ Cycles to_mem_ctrl_latency := 1;
+ Cycles directory_latency := 6;
{
MessageBuffer requestToDir, network="From", virtual_network="0",
ordered="false", vnet_type="request";
*/
machine(DMA, "DMA Controller")
-: DMASequencer * dma_sequencer,
- Cycles request_latency = 6
+: DMASequencer * dma_sequencer;
+ Cycles request_latency := 6;
{
MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response";
*/
machine(L1Cache, "MI Example L1 Cache")
-: Sequencer * sequencer,
- CacheMemory * cacheMemory,
- Cycles cache_response_latency = 12,
- Cycles issue_latency = 2,
- bool send_evictions
+: Sequencer * sequencer;
+ CacheMemory * cacheMemory;
+ Cycles cache_response_latency := 12;
+ Cycles issue_latency := 2;
+ bool send_evictions;
{
// NETWORK BUFFERS
*/
machine(Directory, "Directory protocol")
-: DirectoryMemory * directory,
- MemoryControl * memBuffer,
- Cycles directory_latency = 12
+: DirectoryMemory * directory;
+ MemoryControl * memBuffer;
+ Cycles directory_latency := 12;
{
MessageBuffer forwardFromDir, network="To", virtual_network="3", ordered="false", vnet_type="forward";
*/
machine(DMA, "DMA Controller")
-: DMASequencer * dma_sequencer,
- Cycles request_latency = 6
+: DMASequencer * dma_sequencer;
+ Cycles request_latency := 6;
{
MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response";
*/
machine(L1Cache, "Directory protocol")
- : Sequencer * sequencer,
- CacheMemory * L1Icache,
- CacheMemory * L1Dcache,
- int l2_select_num_bits,
- Cycles request_latency = 2,
- Cycles use_timeout_latency = 50,
- bool send_evictions
+ : Sequencer * sequencer;
+ CacheMemory * L1Icache;
+ CacheMemory * L1Dcache;
+ int l2_select_num_bits;
+ Cycles request_latency := 2;
+ Cycles use_timeout_latency := 50;
+ bool send_evictions;
{
// NODE L1 CACHE
*/
machine(L2Cache, "Token protocol")
-: CacheMemory * L2cache,
- Cycles response_latency = 2,
- Cycles request_latency = 2
+: CacheMemory * L2cache;
+ Cycles response_latency := 2;
+ Cycles request_latency := 2;
{
// L2 BANK QUEUES
*/
machine(Directory, "Directory protocol")
-: DirectoryMemory * directory,
- MemoryControl * memBuffer,
- Cycles directory_latency = 6
+: DirectoryMemory * directory;
+ MemoryControl * memBuffer;
+ Cycles directory_latency := 6;
{
// ** IN QUEUES **
*/
machine(DMA, "DMA Controller")
-: DMASequencer * dma_sequencer,
- Cycles request_latency = 14,
- Cycles response_latency = 14
+: DMASequencer * dma_sequencer;
+ Cycles request_latency := 14;
+ Cycles response_latency := 14;
{
MessageBuffer responseFromDir, network="From", virtual_network="2", ordered="false", vnet_type="response";
*/
machine(L1Cache, "Token protocol")
- : Sequencer * sequencer,
- CacheMemory * L1Icache,
- CacheMemory * L1Dcache,
- int l2_select_num_bits,
- int N_tokens,
-
- Cycles l1_request_latency = 2,
- Cycles l1_response_latency = 2,
- int retry_threshold = 1,
- Cycles fixed_timeout_latency = 100,
- Cycles reissue_wakeup_latency = 10,
- Cycles use_timeout_latency = 50,
-
- bool dynamic_timeout_enabled = true,
- bool no_mig_atomic = true,
- bool send_evictions
+ : Sequencer * sequencer;
+ CacheMemory * L1Icache;
+ CacheMemory * L1Dcache;
+ int l2_select_num_bits;
+ int N_tokens;
+
+ Cycles l1_request_latency := 2;
+ Cycles l1_response_latency := 2;
+ int retry_threshold := 1;
+ Cycles fixed_timeout_latency := 100;
+ Cycles reissue_wakeup_latency := 10;
+ Cycles use_timeout_latency := 50;
+
+ bool dynamic_timeout_enabled := "True";
+ bool no_mig_atomic := "True";
+ bool send_evictions;
{
// From this node's L1 cache TO the network
Cycles averageLatencyEstimate() {
DPRINTF(RubySlicc, "%d\n",
(averageLatencyCounter >> averageLatencyHysteresis));
- //profile_average_latency_estimate( (averageLatencyCounter >> averageLatencyHysteresis) );
return averageLatencyCounter >> averageLatencyHysteresis;
}
*/
machine(L2Cache, "Token protocol")
- : CacheMemory * L2cache,
- int N_tokens,
- Cycles l2_request_latency = 5,
- Cycles l2_response_latency = 5,
- bool filtering_enabled = true
+ : CacheMemory * L2cache;
+ int N_tokens;
+ Cycles l2_request_latency := 5;
+ Cycles l2_response_latency := 5;
+ bool filtering_enabled := "True";
{
// L2 BANK QUEUES
*/
machine(Directory, "Token protocol")
- : DirectoryMemory * directory,
- MemoryControl * memBuffer,
- int l2_select_num_bits,
- Cycles directory_latency = 5,
- bool distributed_persistent = true,
- Cycles fixed_timeout_latency = 100,
- Cycles reissue_wakeup_latency = 10
+ : DirectoryMemory * directory;
+ MemoryControl * memBuffer;
+ int l2_select_num_bits;
+ Cycles directory_latency := 5;
+ bool distributed_persistent := "True";
+ Cycles fixed_timeout_latency := 100;
+ Cycles reissue_wakeup_latency := 10;
{
MessageBuffer dmaResponseFromDir, network="To", virtual_network="5", ordered="true", vnet_type="response";
machine(DMA, "DMA Controller")
-: DMASequencer * dma_sequencer,
- Cycles request_latency = 6
+: DMASequencer * dma_sequencer;
+ Cycles request_latency := 6;
{
MessageBuffer responseFromDir, network="From", virtual_network="5", ordered="true", vnet_type="response";
*/
machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
-: Sequencer * sequencer,
- CacheMemory * L1Icache,
- CacheMemory * L1Dcache,
- CacheMemory * L2cache,
- Cycles cache_response_latency = 10,
- Cycles issue_latency = 2,
- Cycles l2_cache_hit_latency = 10,
- bool no_mig_atomic = true,
- bool send_evictions
+: Sequencer * sequencer;
+ CacheMemory * L1Icache;
+ CacheMemory * L1Dcache;
+ CacheMemory * L2cache;
+ Cycles cache_response_latency := 10;
+ Cycles issue_latency := 2;
+ Cycles l2_cache_hit_latency := 10;
+ bool no_mig_atomic := "True";
+ bool send_evictions;
{
// NETWORK BUFFERS
*/
machine(Directory, "AMD Hammer-like protocol")
-: DirectoryMemory * directory,
- CacheMemory * probeFilter,
- MemoryControl * memBuffer,
- Cycles memory_controller_latency = 2,
- bool probe_filter_enabled = false,
- bool full_bit_dir_enabled = false
+: DirectoryMemory * directory;
+ CacheMemory * probeFilter;
+ MemoryControl * memBuffer;
+ Cycles memory_controller_latency := 2;
+ bool probe_filter_enabled := "False";
+ bool full_bit_dir_enabled := "False";
{
MessageBuffer forwardFromDir, network="To", virtual_network="3", ordered="false", vnet_type="forward";
machine(DMA, "DMA Controller")
-: DMASequencer * dma_sequencer,
- Cycles request_latency = 6
+: DMASequencer * dma_sequencer;
+ Cycles request_latency := 6;
{
MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response";
machine(L1Cache, "Network_test L1 Cache")
-: Sequencer * sequencer,
- Cycles issue_latency = 2
+: Sequencer * sequencer;
+ Cycles issue_latency := 2;
{
// NETWORK BUFFERS
v = Var(self.symtab, self.ident, self.location, type, param,
self.pairs)
self.symtab.newSymbol(v)
+
if self.pointer or str(type) == "TBE" or (
"interface" in type and (
type["interface"] == "AbstractCacheEntry" or
from slicc.symbols import Var
class ObjDeclAST(DeclAST):
- def __init__(self, slicc, type_ast, ident, pairs, rvalue):
+ def __init__(self, slicc, type_ast, ident, pairs, rvalue, pointer):
super(ObjDeclAST, self).__init__(slicc, pairs)
self.type_ast = type_ast
self.ident = ident
self.rvalue = rvalue
+ self.pointer = pointer
def __repr__(self):
return "[ObjDecl: %r]" % self.ident
self.address = address
def __repr__(self):
- return "[StallAndWaitStatementAst: %r]" % self.variable
+ return "[StallAndWaitStatementAst: %r]" % self.in_port
def generate(self, code, return_type):
self.in_port.assertType("InPort")
p[0] = self.parse_file(filename)
def p_decl__machine0(self, p):
- "decl : MACHINE '(' idents ')' ':' params '{' decls '}'"
+ "decl : MACHINE '(' idents ')' ':' obj_decls '{' decls '}'"
p[0] = ast.MachineAST(self, p[3], [], p[7], p[9])
def p_decl__machine1(self, p):
- "decl : MACHINE '(' idents pairs ')' ':' params '{' decls '}'"
+ "decl : MACHINE '(' idents pairs ')' ':' obj_decls '{' decls '}'"
p[0] = ast.MachineAST(self, p[3], p[4], p[7], p[9])
def p_decl__action(self, p):
p[0] = ast.StateDeclAST(self, p[3], p[4], p[7])
# Type fields
+ def p_obj_decls__list(self, p):
+ "obj_decls : obj_decl obj_decls"
+ p[0] = [ p[1] ] + p[2]
+
+ def p_obj_decls__empty(self, p):
+ "obj_decls : empty"
+ p[0] = []
+
def p_type_members__list(self, p):
"type_members : type_member type_members"
p[0] = [ p[1] ] + p[2]
def p_obj_decl__0(self, p):
"obj_decl : type ident pairs SEMI"
- p[0] = ast.ObjDeclAST(self, p[1], p[2], p[3], None)
+ p[0] = ast.ObjDeclAST(self, p[1], p[2], p[3], None, False)
def p_obj_decl__1(self, p):
"obj_decl : type STAR ident pairs SEMI"
- p[0] = ast.ObjDeclAST(self, p[1], p[3], p[4], None)
+ p[0] = ast.ObjDeclAST(self, p[1], p[3], p[4], None, True)
def p_obj_decl__2(self, p):
"obj_decl : type ident ASSIGN expr SEMI"
- p[0] = ast.ObjDeclAST(self, p[1], p[2], ast.PairListAST(self), p[4])
+ p[0] = ast.ObjDeclAST(self, p[1], p[2], ast.PairListAST(self), p[4],
+ False)
def p_obj_decl__3(self, p):
"obj_decl : type STAR ident ASSIGN expr SEMI"
- p[0] = ast.ObjDeclAST(self, p[1], p[3], ast.PairListAST(self), p[5])
+ p[0] = ast.ObjDeclAST(self, p[1], p[3], ast.PairListAST(self), p[5],
+ True)
# Function definition and declaration
def p_decl__func_decl(self, p):
p[0] = ast.FormalParamAST(self, p[1], p[3], None, True)
def p_param__pointer_default(self, p):
- "param : type STAR ident '=' STRING"
+ "param : type STAR ident ASSIGN STRING"
p[0] = ast.FormalParamAST(self, p[1], p[3], p[5], True)
def p_param__default_number(self, p):
- "param : type ident '=' NUMBER"
+ "param : type ident ASSIGN NUMBER"
p[0] = ast.FormalParamAST(self, p[1], p[2], p[4])
def p_param__default_bool(self, p):
- "param : type ident '=' LIT_BOOL"
+ "param : type ident ASSIGN LIT_BOOL"
p[0] = ast.FormalParamAST(self, p[1], p[2], p[4])
def p_param__default_string(self, p):
- "param : type ident '=' STRING"
+ "param : type ident ASSIGN STRING"
p[0] = ast.FormalParamAST(self, p[1], p[2], p[4])
# Type
for param in config_parameters:
if param.pointer:
- var = Var(symtab, param.name, location, param.type_ast.type,
- "(*m_%s_ptr)" % param.name, {}, self)
+ var = Var(symtab, param.ident, location, param.type_ast.type,
+ "(*m_%s_ptr)" % param.ident, {}, self)
else:
- var = Var(symtab, param.name, location, param.type_ast.type,
- "m_%s" % param.name, {}, self)
- self.symtab.registerSym(param.name, var)
+ var = Var(symtab, param.ident, location, param.type_ast.type,
+ "m_%s" % param.ident, {}, self)
+
+ self.symtab.registerSym(param.ident, var)
+
if str(param.type_ast.type) == "Prefetcher":
self.prefetchers.append(var)
def printControllerPython(self, path):
code = self.symtab.codeFormatter()
ident = self.ident
+
py_ident = "%s_Controller" % ident
c_ident = "%s_Controller" % self.ident
+
code('''
from m5.params import *
from m5.SimObject import SimObject
code.indent()
for param in self.config_parameters:
dflt_str = ''
- if param.default is not None:
- dflt_str = str(param.default) + ', '
+
+ if param.rvalue is not None:
+ dflt_str = str(param.rvalue.inline()) + ', '
+
if python_class_map.has_key(param.type_ast.type.c_ident):
python_type = python_class_map[param.type_ast.type.c_ident]
- code('${{param.name}} = Param.${{python_type}}(${dflt_str}"")')
+ code('${{param.ident}} = Param.${{python_type}}(${dflt_str}"")')
+
else:
self.error("Unknown c++ to python class conversion for c++ " \
"type: '%s'. Please update the python_class_map " \
#
for param in self.config_parameters:
if param.pointer:
- code('m_${{param.name}}_ptr = p->${{param.name}};')
+ code('m_${{param.ident}}_ptr = p->${{param.ident}};')
else:
- code('m_${{param.name}} = p->${{param.name}};')
- if re.compile("sequencer").search(param.name):
- code('m_${{param.name}}_ptr->setController(this);')
+ code('m_${{param.ident}} = p->${{param.ident}};')
+ if re.compile("sequencer").search(param.ident):
+ code('m_${{param.ident}}_ptr->setController(this);')
for var in self.objects:
if var.ident.find("mandatoryQueue") >= 0:
seq_ident = "NULL"
for param in self.config_parameters:
- if param.name == "sequencer":
+ if param.ident == "sequencer":
assert(param.pointer)
- seq_ident = "m_%s_ptr" % param.name
+ seq_ident = "m_%s_ptr" % param.ident
code('''
projects / gem5.git / commitdiff