i965: Set the r8stencil flag in miptree_finish_write

This seems to be the most appropriate place.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 4b0b15cf4f63331f977af2cf0df9a01571d8fb17..9922c59f6e17a01742b8835f99fba6783b6b9435 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -121,7 +121,7 @@ brw_blorp_init(struct brw_context *brw)
 static void
 blorp_surf_for_miptree(struct brw_context *brw,
                        struct blorp_surf *surf,
-                       struct intel_mipmap_tree *mt,
+                       const struct intel_mipmap_tree *mt,
                        enum isl_aux_usage aux_usage,
                        bool is_render_target,
                        unsigned *level,
@@ -156,10 +156,6 @@ blorp_surf_for_miptree(struct brw_context *brw,
       .tile_y_sa = mt->level[*level].level_y,
    };
 
-   if (mt->format == MESA_FORMAT_S_UINT8 && is_render_target &&
-       devinfo->gen <= 7)
-      mt->r8stencil_needs_update = true;
-
    if (surf->aux_usage == ISL_AUX_USAGE_HIZ &&
        !intel_miptree_level_has_hiz(mt, *level))
       surf->aux_usage = ISL_AUX_USAGE_NONE;

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index b097dfe346c9c48e748cdb6ef9e33ddd261905d0..30e09861491e90b3b66d6cf557f189d805d1c97f 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -261,14 +261,6 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
       }
    }
 
-   if (mask & BUFFER_BIT_STENCIL) {
-      struct intel_renderbuffer *stencil_irb =
-         intel_get_renderbuffer(fb, BUFFER_STENCIL);
-      struct intel_mipmap_tree *mt = stencil_irb->mt;
-      if (mt && mt->stencil_mt)
-         mt->stencil_mt->r8stencil_needs_update = true;
-   }
-
    if (mask & BUFFER_BITS_COLOR) {
       brw_blorp_clear_color(brw, fb, mask, partial_clear,
                             ctx->Color.sRGBEnabled);

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index cc51176a3e808c5891be7561a2f676a73268e613..90ebad412ea65bd21f63feac5bdd926823e57b02 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2462,11 +2462,13 @@ intel_miptree_finish_write(struct brw_context *brw,
                            uint32_t start_layer, uint32_t num_layers,
                            enum isl_aux_usage aux_usage)
 {
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    num_layers = miptree_layer_range_length(mt, level, start_layer, num_layers);
 
    switch (mt->aux_usage) {
    case ISL_AUX_USAGE_NONE:
-      /* Nothing to do */
+      if (mt->format == MESA_FORMAT_S_UINT8 && devinfo->gen <= 7)
+         mt->r8stencil_needs_update = true;
       break;
 
    case ISL_AUX_USAGE_MCS:

diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index fae179214dd3036521cfdbe2dae0c4cd3e716049..3d948381f4ab893412b618e6d2c936b799054fb6 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -325,9 +325,6 @@ intel_upload_tex(struct gl_context * ctx,
 
    bool tex_busy = mt && brw_bo_busy(mt->bo);
 
-   if (mt && mt->format == MESA_FORMAT_S_UINT8)
-      mt->r8stencil_needs_update = true;
-
    if (_mesa_is_bufferobj(packing->BufferObj) || tex_busy ||
        mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
       ok = intel_texsubimage_blorp(brw, dims, texImage,