Fix CARRY4 abc_box_id

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 94bc3ef8667997dd2163b58e3291e5c55dad411d..3937d35364fdd4df5b0dfb6920e01561b694e6eb 100644 (file)
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -181,7 +181,7 @@ module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
 
-(* abc_box_id = 3, abc_carry="CI,CO", lib_whitebox *)
+(* abc_box_id = 4, abc_carry="CI,CO", lib_whitebox *)
 module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
   assign O = S ^ {CO[2:0], CI | CYINIT};
   assign CO[0] = S[0] ? CI | CYINIT : DI[0];