r600g: move resource setting to its own structures.

resource setting could be a fair bit more lightweight,
this patch just separates the resource structs from the standard
reg tracking structs in the driver, later patches will improve
the winsys.

Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 54f5410c3246b8fcfa8c803b4cd351d03101cfea..17abdff49cd66796b82313f99c11b71e86ff3598 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -380,9 +380,8 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
                                                        struct pipe_resource *texture,
                                                        const struct pipe_sampler_view *state)
 {
-       struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
        struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
-       struct r600_pipe_state *rstate;
+       struct r600_pipe_resource_state *rstate;
        const struct util_format_description *desc;
        struct r600_resource_texture *tmp;
        struct r600_resource *rbuffer;
@@ -438,35 +437,27 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
        array_mode = tmp->array_mode[0];
        tile_type = tmp->tile_type;
 
-       r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
-                               S_030000_DIM(r600_tex_dim(texture->target)) |
-                               S_030000_PITCH((pitch / 8) - 1) |
-                               S_030000_NON_DISP_TILING_ORDER(tile_type) |
-                               S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
-                               S_030004_TEX_HEIGHT(texture->height0 - 1) |
-                               S_030004_TEX_DEPTH(texture->depth0 - 1) |
-                               S_030004_ARRAY_MODE(array_mode),
-                               0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
-                               (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
-       r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
-                               (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
-       r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
-                               word4 |
-                               S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
-                               S_030010_ENDIAN_SWAP(endian) |
-                               S_030010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
-                               S_030014_LAST_LEVEL(state->u.tex.last_level) |
-                               S_030014_BASE_ARRAY(0) |
-                               S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
-       r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6,
-                               S_030018_MAX_ANISO(4 /* max 16 samples */),
-                               0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
-                               S_03001C_DATA_FORMAT(format) |
-                               S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
+       rstate->bo[0] = bo[0];
+       rstate->bo[1] = bo[1];
+       rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
+                         S_030000_PITCH((pitch / 8) - 1) |
+                         S_030000_NON_DISP_TILING_ORDER(tile_type) |
+                         S_030000_TEX_WIDTH(texture->width0 - 1));
+       rstate->val[1] = (S_030004_TEX_HEIGHT(texture->height0 - 1) |
+                         S_030004_TEX_DEPTH(texture->depth0 - 1) |
+                         S_030004_ARRAY_MODE(array_mode));
+       rstate->val[2] = (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8;
+       rstate->val[3] = (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8;
+       rstate->val[4] = (word4 |
+                         S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
+                         S_030010_ENDIAN_SWAP(endian) |
+                         S_030010_BASE_LEVEL(state->u.tex.first_level));
+       rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
+                         S_030014_BASE_ARRAY(0) |
+                         S_030014_LAST_ARRAY(0));
+       rstate->val[6] = (S_030018_MAX_ANISO(4 /* max 16 samples */));
+       rstate->val[7] = (S_03001C_DATA_FORMAT(format) |
+                         S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE));
 
        return &resource->base;
 }
@@ -1769,45 +1760,32 @@ void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
 }
 
 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
-                                        struct r600_pipe_state *rstate,
-                                        struct r600_resource *rbuffer,
-                                        unsigned offset, unsigned stride)
+                                        struct r600_pipe_resource_state *rstate)
 {
        rstate->id = R600_PIPE_STATE_RESOURCE;
-       rstate->nregs = 0;
-       r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
-                               offset, 0xFFFFFFFF, rbuffer->bo);
-       r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
-                               rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
-                               S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
-                               S_030008_STRIDE(stride), 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
-                               S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
-                               S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
-                               S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
-                               S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W),
-                               0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
-                               0x00000000, 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
-                               0x00000000, 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6,
-                               0x00000000, 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
-                               0xC0000000, 0xFFFFFFFF, NULL);
+
+       rstate->val[0] = 0;
+       rstate->bo[0] = NULL;
+       rstate->val[1] = 0;
+       rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
+       rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
+         S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
+         S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
+         S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
+       rstate->val[4] = 0;
+       rstate->val[5] = 0;
+       rstate->val[6] = 0;
+       rstate->val[7] = 0xc0000000;
 }
 
 
-void evergreen_pipe_mod_buffer_resource(struct r600_pipe_state *rstate,
+void evergreen_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
                                        struct r600_resource *rbuffer,
                                        unsigned offset, unsigned stride)
 {
-       rstate->nregs = 0;
-       r600_pipe_state_mod_reg_bo(rstate, offset, rbuffer->bo);
-       r600_pipe_state_mod_reg(rstate, rbuffer->bo_size - offset - 1);
-       r600_pipe_state_mod_reg(rstate, S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
-                               S_030008_STRIDE(stride));
-       rstate->nregs = 8;
-
+       rstate->bo[0] = rbuffer->bo;
+       rstate->val[0] = offset;
+       rstate->val[1] = rbuffer->bo_size - offset - 1;
+       rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
+                        S_030008_STRIDE(stride);
 }

diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index 23e7181a86e21993258560a5bbe91dc072aa715c..5d6240aef243961e2434218d93f17513cce05160 100644 (file)
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -170,6 +170,12 @@ struct r600_pipe_state {
        struct r600_pipe_reg            regs[R600_BLOCK_MAX_REG];
 };
 
+struct r600_pipe_resource_state {
+       unsigned                        id;
+       u32                             val[8];
+       struct r600_bo *bo[2];
+};
+
 #define R600_BLOCK_STATUS_ENABLED      (1 << 0)
 #define R600_BLOCK_STATUS_DIRTY                (1 << 1)
 
@@ -275,9 +281,9 @@ struct r600_draw {
 int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
 void r600_context_fini(struct r600_context *ctx);
 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
-void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
-void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
-void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
+void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
+void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
+void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 void r600_context_flush(struct r600_context *ctx);
@@ -303,9 +309,9 @@ void r600_context_flush_dest_caches(struct r600_context *ctx);
 int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
 void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 void evergreen_context_flush_dest_caches(struct r600_context *ctx);
-void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
-void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
-void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
+void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
+void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
+void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 

diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 8002d943abd2c63136e39d56239d8f00a3a08d55..f40d6fd3fa2c79601e01c76c800110ff7f10f576 100644 (file)
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -82,7 +82,7 @@ struct r600_screen {
 
 struct r600_pipe_sampler_view {
        struct pipe_sampler_view        base;
-       struct r600_pipe_state          state;
+       struct r600_pipe_resource_state         state;
 };
 
 struct r600_pipe_rasterizer {
@@ -173,7 +173,7 @@ struct r600_pipe_context {
        struct r600_pipe_state          *states[R600_PIPE_NSTATES];
        struct r600_context             ctx;
        struct r600_vertex_element      *vertex_elements;
-       struct r600_pipe_state          fs_resource[PIPE_MAX_ATTRIBS];
+       struct r600_pipe_resource_state         fs_resource[PIPE_MAX_ATTRIBS];
        struct pipe_framebuffer_state   framebuffer;
        struct pipe_index_buffer        index_buffer;
        unsigned                        cb_target_mask;
@@ -185,9 +185,9 @@ struct r600_pipe_context {
        struct r600_pipe_shader         *ps_shader;
        struct r600_pipe_shader         *vs_shader;
        struct r600_pipe_state          vs_const_buffer;
-       struct r600_pipe_state          vs_const_buffer_resource[R600_MAX_CONST_BUFFERS];
+       struct r600_pipe_resource_state         vs_const_buffer_resource[R600_MAX_CONST_BUFFERS];
        struct r600_pipe_state          ps_const_buffer;
-       struct r600_pipe_state          ps_const_buffer_resource[R600_MAX_CONST_BUFFERS];
+       struct r600_pipe_resource_state         ps_const_buffer_resource[R600_MAX_CONST_BUFFERS];
        struct r600_pipe_rasterizer     *rasterizer;
        struct r600_pipe_state          vgt;
        struct r600_pipe_state          spi;
@@ -224,10 +224,8 @@ void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element
 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx);
 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx);
 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
-                                   struct r600_pipe_state *rstate,
-                                   struct r600_resource *rbuffer,
-                                   unsigned offset, unsigned stride);
-void evergreen_pipe_mod_buffer_resource(struct r600_pipe_state *rstate,
+                                        struct r600_pipe_resource_state *rstate);
+void evergreen_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
                                        struct r600_resource *rbuffer,
                                        unsigned offset, unsigned stride);
 
@@ -268,10 +266,8 @@ void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve)
 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx);
 void r600_polygon_offset_update(struct r600_pipe_context *rctx);
 void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
-                                   struct r600_pipe_state *rstate,
-                                   struct r600_resource *rbuffer,
-                                   unsigned offset, unsigned stride);
-void r600_pipe_mod_buffer_resource(struct r600_pipe_state *rstate,
+                                   struct r600_pipe_resource_state *rstate);
+void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
                                   struct r600_resource *rbuffer,
                                   unsigned offset, unsigned stride);
 

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index e9011de9fe05795125ac90f44d843eb042fcd8e2..4e62857343ea087279a8c6863df2d09dc5e3308c 100644 (file)
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -409,7 +409,7 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 {
        struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
        struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
-       struct r600_pipe_state *rstate;
+       struct r600_pipe_resource_state *rstate;
        const struct util_format_description *desc;
        struct r600_resource_texture *tmp;
        struct r600_resource *rbuffer;
@@ -472,33 +472,29 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
                depth = texture->array_size;
        }
 
-       r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
-                               S_038000_DIM(r600_tex_dim(texture->target)) |
-                               S_038000_TILE_MODE(array_mode) |
-                               S_038000_TILE_TYPE(tile_type) |
-                               S_038000_PITCH((pitch / 8) - 1) |
-                               S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
-                               S_038004_TEX_HEIGHT(height - 1) |
-                               S_038004_TEX_DEPTH(depth - 1) |
-                               S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
-                               (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
-       r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
-                               (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
-       r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
-                               word4 |
-                               S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
-                               S_038010_REQUEST_SIZE(1) |
-                               S_038010_ENDIAN_SWAP(endian) |
-                               S_038010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
-                               S_038014_LAST_LEVEL(state->u.tex.last_level) |
-                               S_038014_BASE_ARRAY(state->u.tex.first_layer) |
-                               S_038014_LAST_ARRAY(state->u.tex.last_layer), 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
-                               S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
-                               S_038018_MAX_ANISO(4 /* max 16 samples */), 0xFFFFFFFF, NULL);
+       rstate->bo[0] = bo[0];
+       rstate->bo[1] = bo[1];
+
+       rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
+                         S_038000_TILE_MODE(array_mode) |
+                         S_038000_TILE_TYPE(tile_type) |
+                         S_038000_PITCH((pitch / 8) - 1) |
+                         S_038000_TEX_WIDTH(texture->width0 - 1));
+       rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
+                         S_038004_TEX_DEPTH(depth - 1) |
+                         S_038004_DATA_FORMAT(format));
+       rstate->val[2] = (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8;
+       rstate->val[3] = (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8;
+       rstate->val[4] = (word4 |
+                         S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
+                         S_038010_REQUEST_SIZE(1) |
+                         S_038010_ENDIAN_SWAP(endian) |
+                         S_038010_BASE_LEVEL(state->u.tex.first_level));
+       rstate->val[5] = (S_038014_LAST_LEVEL(state->u.tex.last_level) |
+                         S_038014_BASE_ARRAY(state->u.tex.first_layer) |
+                         S_038014_LAST_ARRAY(state->u.tex.last_layer));
+       rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
+                         S_038018_MAX_ANISO(4 /* max 16 samples */));
 
        return &resource->base;
 }
@@ -1481,37 +1477,27 @@ void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
 }
 
 void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
-                                   struct r600_pipe_state *rstate,
-                                   struct r600_resource *rbuffer,
-                                   unsigned offset, unsigned stride)
+                                   struct r600_pipe_resource_state *rstate)
 {
        rstate->id = R600_PIPE_STATE_RESOURCE;
-       rstate->nregs = 0;
-       r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
-                               offset, 0xFFFFFFFF, rbuffer->bo);
-       r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
-                               rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
-                               S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
-                               S_038008_STRIDE(stride), 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
-                               0x00000000, 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
-                               0x00000000, 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
-                               0x00000000, 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
-                               0xC0000000, 0xFFFFFFFF, NULL);
+
+       rstate->bo[0] = NULL;
+       rstate->val[0] = 0;
+       rstate->val[1] = 0;
+       rstate->val[2] = 0;
+       rstate->val[3] = 0;
+       rstate->val[4] = 0;
+       rstate->val[5] = 0;
+       rstate->val[6] = 0xc0000000;
 }
 
-void r600_pipe_mod_buffer_resource(struct r600_pipe_state *rstate,
+void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
                                   struct r600_resource *rbuffer,
                                   unsigned offset, unsigned stride)
 {
-       rstate->nregs = 0;
-       r600_pipe_state_mod_reg_bo(rstate, offset, rbuffer->bo);
-       r600_pipe_state_mod_reg(rstate, rbuffer->bo_size - offset - 1);
-       r600_pipe_state_mod_reg(rstate, S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
-                               S_038008_STRIDE(stride));
-       rstate->nregs = 7;
+       rstate->val[0] = offset;
+       rstate->bo[0] = rbuffer->bo;
+       rstate->val[1] = rbuffer->bo_size - offset - 1;
+       rstate->val[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
+                        S_038008_STRIDE(stride);
 }

diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index 48ab15f9323164e262652e7bb801fe518f54ffbf..0928d964dc253959f4bf2504357086e4929cda1b 100644 (file)
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -388,7 +388,7 @@ void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 {
        struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
        struct r600_resource_buffer *rbuffer = r600_buffer(buffer);
-       struct r600_pipe_state *rstate;
+       struct r600_pipe_resource_state *rstate;
        uint32_t offset;
 
        /* Note that the state tracker can unbind constant buffers by
@@ -416,9 +416,9 @@ void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
                rstate = &rctx->vs_const_buffer_resource[index];
                if (!rstate->id) {
                        if (rctx->family >= CHIP_CEDAR) {
-                               evergreen_pipe_init_buffer_resource(rctx, rstate, &rbuffer->r, offset, 16);
+                               evergreen_pipe_init_buffer_resource(rctx, rstate);
                        } else {
-                               r600_pipe_init_buffer_resource(rctx, rstate, &rbuffer->r, offset, 16);
+                               r600_pipe_init_buffer_resource(rctx, rstate);
                        }
                }
 
@@ -444,9 +444,9 @@ void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
                rstate = &rctx->ps_const_buffer_resource[index];
                if (!rstate->id) {
                        if (rctx->family >= CHIP_CEDAR) {
-                               evergreen_pipe_init_buffer_resource(rctx, rstate, &rbuffer->r, offset, 16);
+                               evergreen_pipe_init_buffer_resource(rctx, rstate);
                        } else {
-                               r600_pipe_init_buffer_resource(rctx, rstate, &rbuffer->r, offset, 16);
+                               r600_pipe_init_buffer_resource(rctx, rstate);
                        }
                }
                if (rctx->family >= CHIP_CEDAR) {
@@ -468,7 +468,7 @@ void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 
 static void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
 {
-       struct r600_pipe_state *rstate;
+       struct r600_pipe_resource_state *rstate;
        struct r600_resource *rbuffer;
        struct pipe_vertex_buffer *vertex_buffer;
        unsigned i, count, offset;
@@ -503,9 +503,9 @@ static void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
 
                if (!rstate->id) {
                        if (rctx->family >= CHIP_CEDAR) {
-                               evergreen_pipe_init_buffer_resource(rctx, rstate, rbuffer, offset, vertex_buffer->stride);
+                               evergreen_pipe_init_buffer_resource(rctx, rstate);
                        } else {
-                               r600_pipe_init_buffer_resource(rctx, rstate, rbuffer, offset, vertex_buffer->stride);
+                               r600_pipe_init_buffer_resource(rctx, rstate);
                        }
                }
 

diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index aa789e69d1993b29daac9381543d8211aa260bee..701d4e9401f7cf149818339418bf98511f959d3d 100644 (file)
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -1023,21 +1023,21 @@ out_err:
        return r;
 }
 
-void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
 {
        unsigned offset = R_030000_SQ_TEX_RESOURCE_WORD0_0 + 0x20 * rid;
 
        r600_context_pipe_state_set_resource(ctx, state, offset);
 }
 
-void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
 {
        unsigned offset = R_030000_SQ_TEX_RESOURCE_WORD0_0 + 0x1600 + 0x20 * rid;
 
        r600_context_pipe_state_set_resource(ctx, state, offset);
 }
 
-void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
 {
        unsigned offset = R_030000_SQ_TEX_RESOURCE_WORD0_0 + 0x7C00 + 0x20 * rid;
 

diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c
index 1be485400fc638f834528e618610481d087b6e43..2039e8afdabed9d7b18d54186b4f519168d77bda 100644 (file)
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -976,13 +976,14 @@ void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_stat
        }
 }
 
-void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
+void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned offset)
 {
        struct r600_range *range;
        struct r600_block *block;
        int i;
        int dirty;
        int num_regs = ctx->radeon->chip_class >= EVERGREEN ? 8 : 7;
+       boolean is_vertex;
 
        range = &ctx->range[CTX_RANGE_ID(offset)];
        block = range->blocks[CTX_BLOCK_ID(offset)];
@@ -997,12 +998,13 @@ void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_
                return;
        }
 
+       is_vertex = ((state->val[num_regs-1] & 0xc0000000) == 0xc0000000);
        dirty = block->status & R600_BLOCK_STATUS_DIRTY;
 
        for (i = 0; i < num_regs; i++) {
-               if (dirty || (block->reg[i] != state->regs[i].value)) {
+               if (dirty || (block->reg[i] != state->val[i])) {
                        dirty |= R600_BLOCK_STATUS_DIRTY;
-                       block->reg[i] = state->regs[i].value;
+                       block->reg[i] = state->val[i];
                }
        }
 
@@ -1011,61 +1013,61 @@ void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_
                dirty |= R600_BLOCK_STATUS_DIRTY;
 
        if (!dirty) {
-               if (state->regs[0].bo) {
-                       if ((block->reloc[1].bo->bo->handle != state->regs[0].bo->bo->handle) ||
-                           (block->reloc[2].bo->bo->handle != state->regs[0].bo->bo->handle))
+               if (is_vertex) {
+                       if ((block->reloc[1].bo->bo->handle != state->bo[0]->bo->handle) ||
+                           (block->reloc[2].bo->bo->handle != state->bo[0]->bo->handle))
                                dirty |= R600_BLOCK_STATUS_DIRTY;
                } else {
-                       if ((block->reloc[1].bo->bo->handle != state->regs[2].bo->bo->handle) ||
-                           (block->reloc[2].bo->bo->handle != state->regs[3].bo->bo->handle))
+                       if ((block->reloc[1].bo->bo->handle != state->bo[0]->bo->handle) ||
+                           (block->reloc[2].bo->bo->handle != state->bo[1]->bo->handle))
                                dirty |= R600_BLOCK_STATUS_DIRTY;
                }
        }
        if (!dirty) {
-               if (state->regs[0].bo)
-                       state->regs[0].bo->fence = ctx->radeon->fence;
+               if (is_vertex)
+                       state->bo[0]->fence = ctx->radeon->fence;
                else {
-                       state->regs[2].bo->fence = ctx->radeon->fence;
-                       state->regs[3].bo->fence = ctx->radeon->fence;
+                       state->bo[0]->fence = ctx->radeon->fence;
+                       state->bo[1]->fence = ctx->radeon->fence;
                }
        } else {
                r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
                r600_bo_reference(ctx->radeon, &block->reloc[2].bo, NULL);
-               if (state->regs[0].bo) {
+               if (is_vertex) {
                        /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
                         * we have single case btw VERTEX & TEXTURE resource
                         */
-                       r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
-                       r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
-                       state->regs[0].bo->fence = ctx->radeon->fence;
+                       r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->bo[0]);
+                       r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->bo[0]);
+                       state->bo[0]->fence = ctx->radeon->fence;
                } else {
                        /* TEXTURE RESOURCE */
-                       r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
-                       r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
-                       state->regs[2].bo->fence = ctx->radeon->fence;
-                       state->regs[3].bo->fence = ctx->radeon->fence;
-                       state->regs[2].bo->bo->binding |= BO_BOUND_TEXTURE;
+                       r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->bo[0]);
+                       r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->bo[1]);
+                       state->bo[0]->fence = ctx->radeon->fence;
+                       state->bo[1]->fence = ctx->radeon->fence;
+                       state->bo[0]->bo->binding |= BO_BOUND_TEXTURE;
                }
        }
        if (dirty)
                r600_context_dirty_block(ctx, block, dirty, num_regs - 1);
 }
 
-void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
 {
        unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1C * rid;
 
        r600_context_pipe_state_set_resource(ctx, state, offset);
 }
 
-void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
 {
        unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1180 + 0x1C * rid;
 
        r600_context_pipe_state_set_resource(ctx, state, offset);
 }
 
-void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
 {
        unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x2300 + 0x1C * rid;
 

diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h
index 9be5c358f85a4e88cd44ba1f8889b979dae9faab..1790f770897813759246d6c23499cd560885d087 100644 (file)
--- a/src/gallium/winsys/r600/drm/r600_priv.h
+++ b/src/gallium/winsys/r600/drm/r600_priv.h
@@ -158,7 +158,7 @@ void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
 struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset);
 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
                           unsigned opcode, unsigned offset_base);
-void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset);
+void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned offset);
 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block);
 void r600_context_dirty_block(struct r600_context *ctx, struct r600_block *block,
                              int dirty, int index);