#include "arch/hsail/gpu_types.hh"
#include "base/logging.hh"
+#include "base/types.hh"
#include "gpu-compute/misc.hh"
namespace HsailISA
/** @} */
/** Records an integer register being set to a value. */
- void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
+ void setIntRegOperand(const StaticInst *si, int idx, RegVal val)
{
setScalarResult(val);
}
/** Records an fp register being set to an integer value. */
void
- setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val)
+ setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
{
setScalarResult(val);
}
{
protected:
typedef TheISA::MachInst MachInst;
- typedef TheISA::FloatReg FloatReg;
- typedef TheISA::FloatRegBits FloatRegBits;
- typedef TheISA::MiscReg MiscReg;
using VecRegContainer = TheISA::VecRegContainer;
/** id attached to all issued requests */
// storage (which is pretty hard to imagine they would have reason
// to do).
- IntReg readIntRegOperand(const StaticInst *si, int idx) override
+ RegVal
+ readIntRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isIntReg());
return thread->readIntReg(reg.index());
}
- FloatRegBits readFloatRegOperandBits(const StaticInst *si,
- int idx) override
+ RegVal
+ readFloatRegOperandBits(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isFloatReg());
/**
* Read source vector register operand.
*/
- const VecRegContainer& readVecRegOperand(const StaticInst *si,
- int idx) const override
+ const VecRegContainer &
+ readVecRegOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isVecReg());
/**
* Read destination vector register operand for modification.
*/
- VecRegContainer& getWritableVecRegOperand(const StaticInst *si,
- int idx) override
+ VecRegContainer &
+ getWritableVecRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
/** @{ */
/** Reads source vector 8bit operand. */
virtual ConstVecLane8
- readVec8BitLaneOperand(const StaticInst *si, int idx) const
- override
+ readVec8BitLaneOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
/** Reads source vector 16bit operand. */
virtual ConstVecLane16
- readVec16BitLaneOperand(const StaticInst *si, int idx) const
- override
+ readVec16BitLaneOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
/** Reads source vector 32bit operand. */
virtual ConstVecLane32
- readVec32BitLaneOperand(const StaticInst *si, int idx) const
- override
+ readVec32BitLaneOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
/** Reads source vector 64bit operand. */
virtual ConstVecLane64
- readVec64BitLaneOperand(const StaticInst *si, int idx) const
- override
+ readVec64BitLaneOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
}
/** @} */
- VecElem readVecElemOperand(const StaticInst *si, int idx) const override
+ VecElem
+ readVecElemOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
return thread->readVecElem(reg);
}
- CCReg readCCRegOperand(const StaticInst *si, int idx) override
+ CCReg
+ readCCRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isCCReg());
}
template<typename T>
- void setScalarResult(T&& t)
+ void
+ setScalarResult(T&& t)
{
result.push(InstResult(std::forward<T>(t),
- InstResult::ResultType::Scalar));
+ InstResult::ResultType::Scalar));
}
template<typename T>
- void setVecResult(T&& t)
+ void
+ setVecResult(T&& t)
{
result.push(InstResult(std::forward<T>(t),
- InstResult::ResultType::VecReg));
+ InstResult::ResultType::VecReg));
}
template<typename T>
- void setVecElemResult(T&& t)
+ void
+ setVecElemResult(T&& t)
{
result.push(InstResult(std::forward<T>(t),
- InstResult::ResultType::VecElem));
+ InstResult::ResultType::VecElem));
}
- void setIntRegOperand(const StaticInst *si, int idx,
- IntReg val) override
+ void
+ setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isIntReg());
setScalarResult(val);
}
- void setFloatRegOperandBits(const StaticInst *si, int idx,
- FloatRegBits val) override
+ void
+ setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isFloatReg());
setScalarResult(val);
}
- void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
+ void
+ setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isCCReg());
setScalarResult((uint64_t)val);
}
- void setVecRegOperand(const StaticInst *si, int idx,
- const VecRegContainer& val) override
+ void
+ setVecRegOperand(const StaticInst *si, int idx,
+ const VecRegContainer& val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
setVecResult(val);
}
- void setVecElemOperand(const StaticInst *si, int idx,
- const VecElem val) override
+ void
+ setVecElemOperand(const StaticInst *si, int idx,
+ const VecElem val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecElem());
bool readPredicate() const override { return thread->readPredicate(); }
- void setPredicate(bool val) override
+ void
+ setPredicate(bool val) override
{
thread->setPredicate(val);
}
TheISA::PCState pcState() const override { return thread->pcState(); }
- void pcState(const TheISA::PCState &val) override
+ void
+ pcState(const TheISA::PCState &val) override
{
DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
val, thread->pcState());
MicroPC microPC() { return thread->microPC(); }
//////////////////////////////////////////
- MiscReg readMiscRegNoEffect(int misc_reg) const
+ RegVal
+ readMiscRegNoEffect(int misc_reg) const
{
return thread->readMiscRegNoEffect(misc_reg);
}
- MiscReg readMiscReg(int misc_reg) override
+ RegVal
+ readMiscReg(int misc_reg) override
{
return thread->readMiscReg(misc_reg);
}
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+ void
+ setMiscRegNoEffect(int misc_reg, const RegVal &val)
{
- DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg);
+ DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n",
+ misc_reg);
miscRegIdxs.push(misc_reg);
return thread->setMiscRegNoEffect(misc_reg, val);
}
- void setMiscReg(int misc_reg, const MiscReg &val) override
+ void
+ setMiscReg(int misc_reg, const RegVal &val) override
{
- DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg);
+ DPRINTF(Checker, "Setting misc reg %d with effect to check later\n",
+ misc_reg);
miscRegIdxs.push(misc_reg);
return thread->setMiscReg(misc_reg, val);
}
- MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
+ RegVal
+ readMiscRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isMiscReg());
return thread->readMiscReg(reg.index());
}
- void setMiscRegOperand(const StaticInst *si, int idx,
- const MiscReg &val) override
+ void
+ setMiscRegOperand(const StaticInst *si, int idx,
+ const RegVal &val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());
}
#if THE_ISA == MIPS_ISA
- MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid) override
+ RegVal
+ readRegOtherThread(const RegId &misc_reg, ThreadID tid) override
{
panic("MIPS MT not defined for CheckerCPU.\n");
return 0;
}
- void setRegOtherThread(const RegId& misc_reg, MiscReg val,
- ThreadID tid) override
+ void
+ setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) override
{
panic("MIPS MT not defined for CheckerCPU.\n");
}
/////////////////////////////////////////
- void recordPCChange(const TheISA::PCState &val)
+ void
+ recordPCChange(const TheISA::PCState &val)
{
changedPC = true;
newPCState = val;
}
- void demapPage(Addr vaddr, uint64_t asn) override
+ void
+ demapPage(Addr vaddr, uint64_t asn) override
{
this->itb->demapPage(vaddr, asn);
this->dtb->demapPage(vaddr, asn);
}
// monitor/mwait funtions
- void armMonitor(Addr address) override
- { BaseCPU::armMonitor(0, address); }
+ void armMonitor(Addr address) override { BaseCPU::armMonitor(0, address); }
bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); }
void mwaitAtomic(ThreadContext *tc) override
{ return BaseCPU::mwaitAtomic(0, tc, thread->dtb); }
AddressMonitor *getAddrMonitor() override
{ return BaseCPU::getCpuAddrMonitor(0); }
- void demapInstPage(Addr vaddr, uint64_t asn)
+ void
+ demapInstPage(Addr vaddr, uint64_t asn)
{
this->itb->demapPage(vaddr, asn);
}
- void demapDataPage(Addr vaddr, uint64_t asn)
+ void
+ demapDataPage(Addr vaddr, uint64_t asn)
{
this->dtb->demapPage(vaddr, asn);
}
Fault writeMem(uint8_t *data, unsigned size, Addr addr,
Request::Flags flags, uint64_t *res) override;
- unsigned int readStCondFailures() const override {
+ unsigned int
+ readStCondFailures() const override {
return thread->readStCondFailures();
}
- void setStCondFailures(unsigned int sc_failures) override
- {}
+ void setStCondFailures(unsigned int sc_failures) override {}
/////////////////////////////////////////////////////
Fault hwrei() override { return thread->hwrei(); }
// The checker's state would have already been updated by the syscall.
void syscall(int64_t callnum, Fault *fault) override { }
- void handleError()
+ void
+ handleError()
{
if (exitOnError)
dumpAndExit();
//
// New accessors for new decoder.
//
- uint64_t readIntReg(int reg_idx)
- { return actualTC->readIntReg(reg_idx); }
+ RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); }
- FloatRegBits readFloatRegBits(int reg_idx)
- { return actualTC->readFloatRegBits(reg_idx); }
+ RegVal
+ readFloatRegBits(int reg_idx)
+ {
+ return actualTC->readFloatRegBits(reg_idx);
+ }
const VecRegContainer& readVecReg(const RegId& reg) const
{ return actualTC->readVecReg(reg); }
CCReg readCCReg(int reg_idx)
{ return actualTC->readCCReg(reg_idx); }
- void setIntReg(int reg_idx, uint64_t val)
+ void
+ setIntReg(int reg_idx, RegVal val)
{
actualTC->setIntReg(reg_idx, val);
checkerTC->setIntReg(reg_idx, val);
}
- void setFloatRegBits(int reg_idx, FloatRegBits val)
+ void
+ setFloatRegBits(int reg_idx, RegVal val)
{
actualTC->setFloatRegBits(reg_idx, val);
checkerTC->setFloatRegBits(reg_idx, val);
}
- void setVecReg(const RegId& reg, const VecRegContainer& val)
+ void
+ setVecReg(const RegId& reg, const VecRegContainer& val)
{
actualTC->setVecReg(reg, val);
checkerTC->setVecReg(reg, val);
}
- void setVecElem(const RegId& reg, const VecElem& val)
+ void
+ setVecElem(const RegId& reg, const VecElem& val)
{
actualTC->setVecElem(reg, val);
checkerTC->setVecElem(reg, val);
}
- void setCCReg(int reg_idx, CCReg val)
+ void
+ setCCReg(int reg_idx, CCReg val)
{
actualTC->setCCReg(reg_idx, val);
checkerTC->setCCReg(reg_idx, val);
{ return actualTC->pcState(); }
/** Sets this thread's PC state. */
- void pcState(const TheISA::PCState &val)
+ void
+ pcState(const TheISA::PCState &val)
{
DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
val, checkerTC->pcState());
return actualTC->pcState(val);
}
- void setNPC(Addr val)
+ void
+ setNPC(Addr val)
{
checkerTC->setNPC(val);
actualTC->setNPC(val);
}
- void pcStateNoRecord(const TheISA::PCState &val)
+ void
+ pcStateNoRecord(const TheISA::PCState &val)
{
return actualTC->pcState(val);
}
MicroPC microPC()
{ return actualTC->microPC(); }
- MiscReg readMiscRegNoEffect(int misc_reg) const
+ RegVal readMiscRegNoEffect(int misc_reg) const
{ return actualTC->readMiscRegNoEffect(misc_reg); }
- MiscReg readMiscReg(int misc_reg)
+ RegVal readMiscReg(int misc_reg)
{ return actualTC->readMiscReg(misc_reg); }
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+ void
+ setMiscRegNoEffect(int misc_reg, const RegVal &val)
{
DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
" and O3..\n", misc_reg);
actualTC->setMiscRegNoEffect(misc_reg, val);
}
- void setMiscReg(int misc_reg, const MiscReg &val)
+ void
+ setMiscReg(int misc_reg, const RegVal &val)
{
DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
" and O3..\n", misc_reg);
actualTC->setMiscReg(misc_reg, val);
}
- RegId flattenRegId(const RegId& regId) const {
+ RegId
+ flattenRegId(const RegId& regId) const
+ {
return actualTC->flattenRegId(regId);
}
unsigned readStCondFailures()
{ return actualTC->readStCondFailures(); }
- void setStCondFailures(unsigned sc_failures)
+ void
+ setStCondFailures(unsigned sc_failures)
{
actualTC->setStCondFailures(sc_failures);
}
Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
- uint64_t readIntRegFlat(int idx)
- { return actualTC->readIntRegFlat(idx); }
+ RegVal readIntRegFlat(int idx) { return actualTC->readIntRegFlat(idx); }
- void setIntRegFlat(int idx, uint64_t val)
- { actualTC->setIntRegFlat(idx, val); }
+ void
+ setIntRegFlat(int idx, RegVal val)
+ {
+ actualTC->setIntRegFlat(idx, val);
+ }
- FloatRegBits readFloatRegBitsFlat(int idx)
- { return actualTC->readFloatRegBitsFlat(idx); }
+ RegVal
+ readFloatRegBitsFlat(int idx)
+ {
+ return actualTC->readFloatRegBitsFlat(idx);
+ }
- void setFloatRegBitsFlat(int idx, FloatRegBits val)
- { actualTC->setFloatRegBitsFlat(idx, val); }
+ void
+ setFloatRegBitsFlat(int idx, RegVal val)
+ {
+ actualTC->setFloatRegBitsFlat(idx, val);
+ }
- const VecRegContainer& readVecRegFlat(int idx) const
- { return actualTC->readVecRegFlat(idx); }
+ const VecRegContainer &
+ readVecRegFlat(int idx) const
+ {
+ return actualTC->readVecRegFlat(idx);
+ }
/**
* Read vector register for modification, flat indexing.
*/
- VecRegContainer& getWritableVecRegFlat(int idx)
- { return actualTC->getWritableVecRegFlat(idx); }
+ VecRegContainer &
+ getWritableVecRegFlat(int idx)
+ {
+ return actualTC->getWritableVecRegFlat(idx);
+ }
void setVecRegFlat(int idx, const VecRegContainer& val)
{ actualTC->setVecRegFlat(idx, val); }
*/
class ExecContext {
public:
- typedef TheISA::IntReg IntReg;
typedef TheISA::PCState PCState;
- typedef TheISA::FloatReg FloatReg;
- typedef TheISA::FloatRegBits FloatRegBits;
- typedef TheISA::MiscReg MiscReg;
typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
*/
/** Reads an integer register. */
- virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0;
+ virtual RegVal readIntRegOperand(const StaticInst *si, int idx) = 0;
/** Sets an integer register to a value. */
virtual void setIntRegOperand(const StaticInst *si,
- int idx, IntReg val) = 0;
+ int idx, RegVal val) = 0;
/** @} */
/** Reads a floating point register in its binary format, instead
* of by value. */
- virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si,
- int idx) = 0;
+ virtual RegVal readFloatRegOperandBits(const StaticInst *si, int idx) = 0;
/** Sets the bits of a floating point register of single width
* to a binary value. */
virtual void setFloatRegOperandBits(const StaticInst *si,
- int idx, FloatRegBits val) = 0;
+ int idx, RegVal val) = 0;
/** @} */
* @{
* @name Misc Register Interfaces
*/
- virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0;
+ virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
virtual void setMiscRegOperand(const StaticInst *si,
- int idx, const MiscReg &val) = 0;
+ int idx, const RegVal &val) = 0;
/**
* Reads a miscellaneous register, handling any architectural
* side effects due to reading that register.
*/
- virtual MiscReg readMiscReg(int misc_reg) = 0;
+ virtual RegVal readMiscReg(int misc_reg) = 0;
/**
* Sets a miscellaneous register, handling any architectural
* side effects due to writing that register.
*/
- virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
+ virtual void setMiscReg(int misc_reg, const RegVal &val) = 0;
/** @} */
*/
#if THE_ISA == MIPS_ISA
- virtual MiscReg readRegOtherThread(const RegId& reg,
- ThreadID tid = InvalidThreadID) = 0;
- virtual void setRegOtherThread(const RegId& reg, MiscReg val,
- ThreadID tid = InvalidThreadID) = 0;
+ virtual RegVal readRegOtherThread(const RegId ®,
+ ThreadID tid=InvalidThreadID) = 0;
+ virtual void setRegOtherThread(const RegId& reg, RegVal val,
+ ThreadID tid=InvalidThreadID) = 0;
#endif
/** @} */
static void
updateKvmStateFPUCommon(ThreadContext *tc, T &fpu)
{
- static_assert(sizeof(X86ISA::FloatRegBits) == 8,
- "Unexpected size of X86ISA::FloatRegBits");
-
fpu.mxcsr = tc->readMiscRegNoEffect(MISCREG_MXCSR);
fpu.fcw = tc->readMiscRegNoEffect(MISCREG_FCW);
// No need to rebuild from MISCREG_FSW and MISCREG_TOP if we read
// TODO: We should update the MMX state
for (int i = 0; i < 16; ++i) {
- *(X86ISA::FloatRegBits *)&fpu.xmm[i][0] =
+ *(uint64_t *)&fpu.xmm[i][0] =
tc->readFloatRegBits(FLOATREG_XMM_LOW(i));
- *(X86ISA::FloatRegBits *)&fpu.xmm[i][8] =
+ *(uint64_t *)&fpu.xmm[i][8] =
tc->readFloatRegBits(FLOATREG_XMM_HIGH(i));
}
}
{
const unsigned top((fpu.fsw >> 11) & 0x7);
- static_assert(sizeof(X86ISA::FloatRegBits) == 8,
- "Unexpected size of X86ISA::FloatRegBits");
-
for (int i = 0; i < 8; ++i) {
const unsigned reg_idx((i + top) & 0x7);
const double value(X86ISA::loadFloat80(fpu.fpr[i]));
for (int i = 0; i < 16; ++i) {
tc->setFloatRegBits(FLOATREG_XMM_LOW(i),
- *(X86ISA::FloatRegBits *)&fpu.xmm[i][0]);
+ *(uint64_t *)&fpu.xmm[i][0]);
tc->setFloatRegBits(FLOATREG_XMM_HIGH(i),
- *(X86ISA::FloatRegBits *)&fpu.xmm[i][8]);
+ *(uint64_t *)&fpu.xmm[i][8]);
}
}
return NoFault;
}
- IntReg
+ RegVal
readIntRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
return thread.readIntReg(reg.index());
}
- TheISA::FloatRegBits
+ RegVal
readFloatRegOperandBits(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
return thread.readFloatRegBits(reg.index());
}
- const TheISA::VecRegContainer&
+ const TheISA::VecRegContainer &
readVecRegOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
return thread.readVecReg(reg);
}
- TheISA::VecRegContainer&
+ TheISA::VecRegContainer &
getWritableVecRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->destRegIdx(idx);
}
void
- setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
+ setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isIntReg());
}
void
- setFloatRegOperandBits(const StaticInst *si, int idx,
- TheISA::FloatRegBits val) override
+ setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isFloatReg());
/** Write a lane of the destination vector operand. */
template <typename LD>
void
- setVecLaneOperandT(const StaticInst *si, int idx,
- const LD& val)
+ setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
thread.pcState(val);
}
- TheISA::MiscReg
+ RegVal
readMiscRegNoEffect(int misc_reg) const
{
return thread.readMiscRegNoEffect(misc_reg);
}
- TheISA::MiscReg
+ RegVal
readMiscReg(int misc_reg) override
{
return thread.readMiscReg(misc_reg);
}
void
- setMiscReg(int misc_reg, const TheISA::MiscReg &val) override
+ setMiscReg(int misc_reg, const RegVal &val) override
{
thread.setMiscReg(misc_reg, val);
}
- TheISA::MiscReg
+ RegVal
readMiscRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
void
setMiscRegOperand(const StaticInst *si, int idx,
- const TheISA::MiscReg &val) override
+ const RegVal &val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());
void
syscall(int64_t callnum, Fault *fault) override
- {
+ {
if (FullSystem)
panic("Syscall emulation isn't available in FS mode.\n");
BaseCPU *getCpuPtr() { return &cpu; }
/* MIPS: other thread register reading/writing */
- uint64_t
- readRegOtherThread(const RegId& reg, ThreadID tid = InvalidThreadID)
+ RegVal
+ readRegOtherThread(const RegId ®, ThreadID tid=InvalidThreadID)
{
SimpleThread *other_thread = (tid == InvalidThreadID
? &thread : cpu.threads[tid]);
}
void
- setRegOtherThread(const RegId& reg, const TheISA::MiscReg &val,
- ThreadID tid = InvalidThreadID)
+ setRegOtherThread(const RegId ®, const RegVal &val,
+ ThreadID tid=InvalidThreadID)
{
SimpleThread *other_thread = (tid == InvalidThreadID
? &thread : cpu.threads[tid]);
}
template <class Impl>
-TheISA::MiscReg
+RegVal
FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
{
return this->isa[tid]->readMiscRegNoEffect(misc_reg);
}
template <class Impl>
-TheISA::MiscReg
+RegVal
FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
{
miscRegfileReads++;
template <class Impl>
void
FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
- const TheISA::MiscReg &val, ThreadID tid)
+ const RegVal &val, ThreadID tid)
{
this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
}
template <class Impl>
void
FullO3CPU<Impl>::setMiscReg(int misc_reg,
- const TheISA::MiscReg &val, ThreadID tid)
+ const RegVal &val, ThreadID tid)
{
miscRegfileWrites++;
this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
}
template <class Impl>
-uint64_t
+RegVal
FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
{
intRegfileReads++;
}
template <class Impl>
-FloatRegBits
+RegVal
FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
{
fpRegfileReads++;
template <class Impl>
void
-FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
+FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val)
{
intRegfileWrites++;
regFile.setIntReg(phys_reg, val);
template <class Impl>
void
-FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
+FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val)
{
fpRegfileWrites++;
regFile.setFloatRegBits(phys_reg, val);
}
template <class Impl>
-uint64_t
+RegVal
FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
{
intRegfileReads++;
}
template <class Impl>
-uint64_t
+RegVal
FullO3CPU<Impl>::readArchFloatRegBits(int reg_idx, ThreadID tid)
{
fpRegfileReads++;
template <class Impl>
void
-FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
+FullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
{
intRegfileWrites++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
template <class Impl>
void
-FullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, uint64_t val, ThreadID tid)
+FullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid)
{
fpRegfileWrites++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
/** Register accessors. Index refers to the physical register index. */
/** Reads a miscellaneous register. */
- TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
+ RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
/** Reads a misc. register, including any side effects the read
* might have as defined by the architecture.
*/
- TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
+ RegVal readMiscReg(int misc_reg, ThreadID tid);
/** Sets a miscellaneous register. */
- void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
- ThreadID tid);
+ void setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid);
/** Sets a misc. register, including any side effects the write
* might have as defined by the architecture.
*/
- void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
- ThreadID tid);
+ void setMiscReg(int misc_reg, const RegVal &val, ThreadID tid);
- uint64_t readIntReg(PhysRegIdPtr phys_reg);
+ RegVal readIntReg(PhysRegIdPtr phys_reg);
- TheISA::FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg);
+ RegVal readFloatRegBits(PhysRegIdPtr phys_reg);
const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg);
- void setIntReg(PhysRegIdPtr phys_reg, uint64_t val);
+ void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
- void setFloatRegBits(PhysRegIdPtr phys_reg, TheISA::FloatRegBits val);
+ void setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val);
void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val);
void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val);
- uint64_t readArchIntReg(int reg_idx, ThreadID tid);
+ RegVal readArchIntReg(int reg_idx, ThreadID tid);
- uint64_t readArchFloatRegBits(int reg_idx, ThreadID tid);
+ RegVal readArchFloatRegBits(int reg_idx, ThreadID tid);
const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
/** Read architectural vector register for modification. */
* architected register first, then accesses that physical
* register.
*/
- void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
+ void setArchIntReg(int reg_idx, RegVal val, ThreadID tid);
- void setArchFloatRegBits(int reg_idx, uint64_t val, ThreadID tid);
+ void setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid);
void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid);
/** Binary machine instruction type. */
typedef TheISA::MachInst MachInst;
/** Register types. */
- typedef TheISA::IntReg IntReg;
- typedef TheISA::FloatReg FloatReg;
- typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
- /** Misc register type. */
- typedef TheISA::MiscReg MiscReg;
-
enum {
MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
using BaseDynInst<Impl>::_destRegIdx;
/** Values to be written to the destination misc. registers. */
- std::array<MiscReg, TheISA::MaxMiscDestRegs> _destMiscRegVal;
+ std::array<RegVal, TheISA::MaxMiscDestRegs> _destMiscRegVal;
/** Indexes of the destination misc. registers. They are needed to defer
* the write accesses to the misc. registers until the commit stage, when
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/
- MiscReg readMiscReg(int misc_reg)
+ RegVal
+ readMiscReg(int misc_reg)
{
return this->cpu->readMiscReg(misc_reg, this->threadNumber);
}
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
- void setMiscReg(int misc_reg, const MiscReg &val)
+ void
+ setMiscReg(int misc_reg, const RegVal &val)
{
/** Writes to misc. registers are recorded and deferred until the
* commit stage, when updateMiscRegs() is called. First, check if
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/
- TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
+ RegVal
+ readMiscRegOperand(const StaticInst *si, int idx)
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isMiscReg());
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
- void setMiscRegOperand(const StaticInst *si, int idx,
- const MiscReg &val)
+ void
+ setMiscRegOperand(const StaticInst *si, int idx, const RegVal &val)
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());
}
/** Called at the commit stage to update the misc. registers. */
- void updateMiscRegs()
+ void
+ updateMiscRegs()
{
// @todo: Pretty convoluted way to avoid squashing from happening when
// using the TC during an instruction's execution (specifically for
// storage (which is pretty hard to imagine they would have reason
// to do).
- IntReg readIntRegOperand(const StaticInst *si, int idx)
+ RegVal
+ readIntRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readIntReg(this->_srcRegIdx[idx]);
}
- FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
+ RegVal
+ readFloatRegOperandBits(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
}
/** @todo: Make results into arrays so they can handle multiple dest
* registers.
*/
- void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
+ void
+ setIntRegOperand(const StaticInst *si, int idx, RegVal val)
{
this->cpu->setIntReg(this->_destRegIdx[idx], val);
BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
}
- void setFloatRegOperandBits(const StaticInst *si, int idx,
- FloatRegBits val)
+ void
+ setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
{
this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
#if THE_ISA == MIPS_ISA
- MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid)
+ RegVal
+ readRegOtherThread(const RegId& misc_reg, ThreadID tid)
{
panic("MIPS MT not defined for O3 CPU.\n");
return 0;
}
- void setRegOtherThread(const RegId& misc_reg, MiscReg val, ThreadID tid)
+ void
+ setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
{
panic("MIPS MT not defined for O3 CPU.\n");
}
{
private:
- typedef TheISA::IntReg IntReg;
- typedef TheISA::FloatReg FloatReg;
- typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::CCReg CCReg;
using VecElem = TheISA::VecElem;
using VecRegContainer = TheISA::VecRegContainer;
static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
/** Integer register file. */
- std::vector<IntReg> intRegFile;
+ std::vector<RegVal> intRegFile;
std::vector<PhysRegId> intRegIds;
/** Floating point register file. */
- std::vector<FloatRegBits> floatRegFile;
+ std::vector<RegVal> floatRegFile;
std::vector<PhysRegId> floatRegIds;
/** Vector register file. */
}
/** Reads an integer register. */
- uint64_t readIntReg(PhysRegIdPtr phys_reg) const
+ RegVal
+ readIntReg(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->isIntPhysReg());
return intRegFile[phys_reg->index()];
}
- FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg) const
+ RegVal
+ readFloatRegBits(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->isFloatPhysReg());
- FloatRegBits floatRegBits = floatRegFile[phys_reg->index()];
+ RegVal floatRegBits = floatRegFile[phys_reg->index()];
DPRINTF(IEW, "RegFile: Access to float register %i as int, "
- "has data %#x\n", phys_reg->index(),
- (uint64_t)floatRegBits);
+ "has data %#x\n", phys_reg->index(), floatRegBits);
return floatRegBits;
}
/** Reads a vector register. */
- const VecRegContainer& readVecReg(PhysRegIdPtr phys_reg) const
+ const VecRegContainer &
+ readVecReg(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->isVectorPhysReg());
}
/** Reads a vector register for modification. */
- VecRegContainer& getWritableVecReg(PhysRegIdPtr phys_reg)
+ VecRegContainer &
+ getWritableVecReg(PhysRegIdPtr phys_reg)
{
/* const_cast for not duplicating code above. */
return const_cast<VecRegContainer&>(readVecReg(phys_reg));
}
/** Reads a vector element. */
- const VecElem& readVecElem(PhysRegIdPtr phys_reg) const
+ const VecElem &
+ readVecElem(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->isVectorPhysElem());
auto ret = vectorRegFile[phys_reg->index()].as<VecElem>();
}
/** Reads a condition-code register. */
- CCReg readCCReg(PhysRegIdPtr phys_reg)
+ CCReg
+ readCCReg(PhysRegIdPtr phys_reg)
{
assert(phys_reg->isCCPhysReg());
}
/** Sets an integer register to the given value. */
- void setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
+ void
+ setIntReg(PhysRegIdPtr phys_reg, RegVal val)
{
assert(phys_reg->isIntPhysReg());
intRegFile[phys_reg->index()] = val;
}
- void setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
+ void
+ setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val)
{
assert(phys_reg->isFloatPhysReg());
}
/** Sets a vector register to the given value. */
- void setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
+ void
+ setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
{
assert(phys_reg->isVectorPhysReg());
}
/** Sets a vector register to the given value. */
- void setVecElem(PhysRegIdPtr phys_reg, const VecElem val)
+ void
+ setVecElem(PhysRegIdPtr phys_reg, const VecElem val)
{
assert(phys_reg->isVectorPhysElem());
}
/** Sets a condition-code register to the given value. */
- void setCCReg(PhysRegIdPtr phys_reg, CCReg val)
+ void
+ setCCReg(PhysRegIdPtr phys_reg, CCReg val)
{
assert(phys_reg->isCCPhysReg());
*/
IdRange getRegIds(RegClass cls);
- /**
- * Get the true physical register id.
- * As many parts work with PhysRegIdPtr, we need to be able to produce
- * the pointer out of just class and register idx.
- */
- PhysRegIdPtr getTrueId(PhysRegIdPtr reg);
+ /**
+ * Get the true physical register id.
+ * As many parts work with PhysRegIdPtr, we need to be able to produce
+ * the pointer out of just class and register idx.
+ */
+ PhysRegIdPtr getTrueId(PhysRegIdPtr reg);
};
virtual void clearArchRegs();
/** Reads an integer register. */
- virtual uint64_t readReg(int reg_idx) {
+ virtual RegVal
+ readReg(int reg_idx)
+ {
return readIntRegFlat(flattenRegId(RegId(IntRegClass,
reg_idx)).index());
}
- virtual uint64_t readIntReg(int reg_idx) {
+ virtual RegVal
+ readIntReg(int reg_idx)
+ {
return readIntRegFlat(flattenRegId(RegId(IntRegClass,
reg_idx)).index());
}
- virtual FloatRegBits readFloatRegBits(int reg_idx) {
+ virtual RegVal
+ readFloatRegBits(int reg_idx)
+ {
return readFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass,
reg_idx)).index());
}
- virtual const VecRegContainer& readVecReg(const RegId& id) const {
+ virtual const VecRegContainer &
+ readVecReg(const RegId& id) const
+ {
return readVecRegFlat(flattenRegId(id).index());
}
/**
* Read vector register operand for modification, hierarchical indexing.
*/
- virtual VecRegContainer& getWritableVecReg(const RegId& id) {
+ virtual VecRegContainer &
+ getWritableVecReg(const RegId& id)
+ {
return getWritableVecRegFlat(flattenRegId(id).index());
}
}
/** Sets an integer register to a value. */
- virtual void setIntReg(int reg_idx, uint64_t val) {
+ virtual void
+ setIntReg(int reg_idx, RegVal val)
+ {
setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val);
}
- virtual void setFloatRegBits(int reg_idx, FloatRegBits val) {
+ virtual void
+ setFloatRegBits(int reg_idx, RegVal val)
+ {
setFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass,
reg_idx)).index(), val);
}
- virtual void setVecReg(const RegId& reg, const VecRegContainer& val) {
+ virtual void
+ setVecReg(const RegId& reg, const VecRegContainer& val)
+ {
setVecRegFlat(flattenRegId(reg).index(), val);
}
- virtual void setVecElem(const RegId& reg, const VecElem& val) {
+ virtual void
+ setVecElem(const RegId& reg, const VecElem& val)
+ {
setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
}
- virtual void setCCReg(int reg_idx, CCReg val) {
+ virtual void
+ setCCReg(int reg_idx, CCReg val)
+ {
setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
}
{ return cpu->microPC(thread->threadId()); }
/** Reads a miscellaneous register. */
- virtual MiscReg readMiscRegNoEffect(int misc_reg) const
+ virtual RegVal readMiscRegNoEffect(int misc_reg) const
{ return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
/** Reads a misc. register, including any side-effects the
* read might have as defined by the architecture. */
- virtual MiscReg readMiscReg(int misc_reg)
+ virtual RegVal readMiscReg(int misc_reg)
{ return cpu->readMiscReg(misc_reg, thread->threadId()); }
/** Sets a misc. register. */
- virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
+ virtual void setMiscRegNoEffect(int misc_reg, const RegVal &val);
/** Sets a misc. register, including any side-effects the
* write might have as defined by the architecture. */
- virtual void setMiscReg(int misc_reg, const MiscReg &val);
+ virtual void setMiscReg(int misc_reg, const RegVal &val);
virtual RegId flattenRegId(const RegId& regId) const;
virtual Counter readFuncExeInst() { return thread->funcExeInst; }
/** Returns pointer to the quiesce event. */
- virtual EndQuiesceEvent *getQuiesceEvent()
+ virtual EndQuiesceEvent *
+ getQuiesceEvent()
{
return this->thread->quiesceEvent;
}
* similar is currently writing to the thread context and doesn't want
* reset all the state (see noSquashFromTC).
*/
- inline void conditionalSquash()
+ inline void
+ conditionalSquash()
{
if (!thread->trapPending && !thread->noSquashFromTC)
cpu->squashFromTC(thread->threadId());
}
- virtual uint64_t readIntRegFlat(int idx);
- virtual void setIntRegFlat(int idx, uint64_t val);
+ virtual RegVal readIntRegFlat(int idx);
+ virtual void setIntRegFlat(int idx, RegVal val);
- virtual FloatRegBits readFloatRegBitsFlat(int idx);
- virtual void setFloatRegBitsFlat(int idx, FloatRegBits val);
+ virtual RegVal readFloatRegBitsFlat(int idx);
+ virtual void setFloatRegBitsFlat(int idx, RegVal val);
virtual const VecRegContainer& readVecRegFlat(int idx) const;
/** Read vector register operand for modification, flat indexing. */
virtual void setVecRegFlat(int idx, const VecRegContainer& val);
template <typename VecElem>
- VecLaneT<VecElem, true> readVecLaneFlat(int idx, int lId) const
+ VecLaneT<VecElem, true>
+ readVecLaneFlat(int idx, int lId) const
{
return cpu->template readArchVecLane<VecElem>(idx, lId,
thread->threadId());
}
template <class Impl>
-uint64_t
+RegVal
O3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
{
return cpu->readArchIntReg(reg_idx, thread->threadId());
}
template <class Impl>
-TheISA::FloatRegBits
+RegVal
O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
{
return cpu->readArchFloatRegBits(reg_idx, thread->threadId());
template <class Impl>
void
-O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
+O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, RegVal val)
{
cpu->setArchIntReg(reg_idx, val, thread->threadId());
template <class Impl>
void
-O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val)
+O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, RegVal val)
{
cpu->setArchFloatRegBits(reg_idx, val, thread->threadId());
template <class Impl>
void
-O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const RegVal &val)
{
cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
template <class Impl>
void
-O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
+O3ThreadContext<Impl>::setMiscReg(int misc_reg, const RegVal &val)
{
cpu->setMiscReg(misc_reg, val, thread->threadId());
class SimpleExecContext : public ExecContext {
protected:
- typedef TheISA::MiscReg MiscReg;
- typedef TheISA::FloatReg FloatReg;
- typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
{ }
/** Reads an integer register. */
- IntReg readIntRegOperand(const StaticInst *si, int idx) override
+ RegVal
+ readIntRegOperand(const StaticInst *si, int idx) override
{
numIntRegReads++;
const RegId& reg = si->srcRegIdx(idx);
}
/** Sets an integer register to a value. */
- void setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
+ void
+ setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
{
numIntRegWrites++;
const RegId& reg = si->destRegIdx(idx);
/** Reads a floating point register in its binary format, instead
* of by value. */
- FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override
+ RegVal
+ readFloatRegOperandBits(const StaticInst *si, int idx) override
{
numFpRegReads++;
const RegId& reg = si->srcRegIdx(idx);
/** Sets the bits of a floating point register of single width
* to a binary value. */
- void setFloatRegOperandBits(const StaticInst *si, int idx,
- FloatRegBits val) override
+ void
+ setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
{
numFpRegWrites++;
const RegId& reg = si->destRegIdx(idx);
}
/** Reads a vector register. */
- const VecRegContainer&
+ const VecRegContainer &
readVecRegOperand(const StaticInst *si, int idx) const override
{
numVecRegReads++;
}
/** Reads a vector register for modification. */
- VecRegContainer&
+ VecRegContainer &
getWritableVecRegOperand(const StaticInst *si, int idx) override
{
numVecRegWrites++;
}
/** Sets a vector register to a value. */
- void setVecRegOperand(const StaticInst *si, int idx,
- const VecRegContainer& val) override
+ void
+ setVecRegOperand(const StaticInst *si, int idx,
+ const VecRegContainer& val) override
{
numVecRegWrites++;
const RegId& reg = si->destRegIdx(idx);
/** @} */
/** Reads an element of a vector register. */
- VecElem readVecElemOperand(const StaticInst *si, int idx) const override
+ VecElem
+ readVecElemOperand(const StaticInst *si, int idx) const override
{
numVecRegReads++;
const RegId& reg = si->destRegIdx(idx);
}
/** Sets an element of a vector register to a value. */
- void setVecElemOperand(const StaticInst *si, int idx,
- const VecElem val) override
+ void
+ setVecElemOperand(const StaticInst *si, int idx,
+ const VecElem val) override
{
numVecRegWrites++;
const RegId& reg = si->destRegIdx(idx);
thread->setVecElem(reg, val);
}
- CCReg readCCRegOperand(const StaticInst *si, int idx) override
+ CCReg
+ readCCRegOperand(const StaticInst *si, int idx) override
{
numCCRegReads++;
const RegId& reg = si->srcRegIdx(idx);
return thread->readCCReg(reg.index());
}
- void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
+ void
+ setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
{
numCCRegWrites++;
const RegId& reg = si->destRegIdx(idx);
thread->setCCReg(reg.index(), val);
}
- MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
+ RegVal
+ readMiscRegOperand(const StaticInst *si, int idx) override
{
numIntRegReads++;
const RegId& reg = si->srcRegIdx(idx);
return thread->readMiscReg(reg.index());
}
- void setMiscRegOperand(const StaticInst *si, int idx,
- const MiscReg &val) override
+ void
+ setMiscRegOperand(const StaticInst *si, int idx,
+ const RegVal &val) override
{
numIntRegWrites++;
const RegId& reg = si->destRegIdx(idx);
* Reads a miscellaneous register, handling any architectural
* side effects due to reading that register.
*/
- MiscReg readMiscReg(int misc_reg) override
+ RegVal
+ readMiscReg(int misc_reg) override
{
numIntRegReads++;
return thread->readMiscReg(misc_reg);
* Sets a miscellaneous register, handling any architectural
* side effects due to writing that register.
*/
- void setMiscReg(int misc_reg, const MiscReg &val) override
+ void
+ setMiscReg(int misc_reg, const RegVal &val) override
{
numIntRegWrites++;
thread->setMiscReg(misc_reg, val);
}
- PCState pcState() const override
+ PCState
+ pcState() const override
{
return thread->pcState();
}
- void pcState(const PCState &val) override
+ void
+ pcState(const PCState &val) override
{
thread->pcState(val);
}
- Fault readMem(Addr addr, uint8_t *data, unsigned int size,
- Request::Flags flags) override
+ Fault
+ readMem(Addr addr, uint8_t *data, unsigned int size,
+ Request::Flags flags) override
{
return cpu->readMem(addr, data, size, flags);
}
- Fault initiateMemRead(Addr addr, unsigned int size,
- Request::Flags flags) override
+ Fault
+ initiateMemRead(Addr addr, unsigned int size,
+ Request::Flags flags) override
{
return cpu->initiateMemRead(addr, size, flags);
}
- Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
- Request::Flags flags, uint64_t *res) override
+ Fault
+ writeMem(uint8_t *data, unsigned int size, Addr addr,
+ Request::Flags flags, uint64_t *res) override
{
return cpu->writeMem(data, size, addr, flags, res);
}
/**
* Sets the number of consecutive store conditional failures.
*/
- void setStCondFailures(unsigned int sc_failures) override
+ void
+ setStCondFailures(unsigned int sc_failures) override
{
thread->setStCondFailures(sc_failures);
}
/**
* Returns the number of consecutive store conditional failures.
*/
- unsigned int readStCondFailures() const override
+ unsigned int
+ readStCondFailures() const override
{
return thread->readStCondFailures();
}
/**
* Executes a syscall specified by the callnum.
*/
- void syscall(int64_t callnum, Fault *fault) override
+ void
+ syscall(int64_t callnum, Fault *fault) override
{
if (FullSystem)
panic("Syscall emulation isn't available in FS mode.");
}
/** Returns a pointer to the ThreadContext. */
- ThreadContext *tcBase() override
- {
- return thread->getTC();
- }
+ ThreadContext *tcBase() override { return thread->getTC(); }
/**
* Somewhat Alpha-specific function that handles returning from an
* error or interrupt.
*/
- Fault hwrei() override
- {
- return thread->hwrei();
- }
+ Fault hwrei() override { return thread->hwrei(); }
/**
* Check for special simulator handling of specific PAL calls. If
* return value is false, actual PAL call will be suppressed.
*/
- bool simPalCheck(int palFunc) override
+ bool
+ simPalCheck(int palFunc) override
{
return thread->simPalCheck(palFunc);
}
- bool readPredicate() const override
+ bool
+ readPredicate() const override
{
return thread->readPredicate();
}
- void setPredicate(bool val) override
+ void
+ setPredicate(bool val) override
{
thread->setPredicate(val);
/**
* Invalidate a page in the DTLB <i>and</i> ITLB.
*/
- void demapPage(Addr vaddr, uint64_t asn) override
+ void
+ demapPage(Addr vaddr, uint64_t asn) override
{
thread->demapPage(vaddr, asn);
}
- void armMonitor(Addr address) override
+ void
+ armMonitor(Addr address) override
{
cpu->armMonitor(thread->threadId(), address);
}
- bool mwait(PacketPtr pkt) override
+ bool
+ mwait(PacketPtr pkt) override
{
return cpu->mwait(thread->threadId(), pkt);
}
- void mwaitAtomic(ThreadContext *tc) override
+ void
+ mwaitAtomic(ThreadContext *tc) override
{
cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb);
}
- AddressMonitor *getAddrMonitor() override
+ AddressMonitor *
+ getAddrMonitor() override
{
return cpu->getCpuAddrMonitor(thread->threadId());
}
#if THE_ISA == MIPS_ISA
- MiscReg readRegOtherThread(const RegId& reg,
- ThreadID tid = InvalidThreadID)
+ RegVal
+ readRegOtherThread(const RegId& reg, ThreadID tid=InvalidThreadID)
override
{
panic("Simple CPU models do not support multithreaded "
"register access.");
}
- void setRegOtherThread(const RegId& reg, MiscReg val,
- ThreadID tid = InvalidThreadID) override
+ void
+ setRegOtherThread(const RegId& reg, RegVal val,
+ ThreadID tid=InvalidThreadID) override
{
panic("Simple CPU models do not support multithreaded "
"register access.");
}
-
#endif
};
{
protected:
typedef TheISA::MachInst MachInst;
- typedef TheISA::MiscReg MiscReg;
- typedef TheISA::FloatReg FloatReg;
- typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
typedef ThreadContext::Status Status;
protected:
- FloatRegBits floatRegs[TheISA::NumFloatRegs];
- TheISA::IntReg intRegs[TheISA::NumIntRegs];
+ RegVal floatRegs[TheISA::NumFloatRegs];
+ RegVal intRegs[TheISA::NumIntRegs];
VecRegContainer vecRegs[TheISA::NumVecRegs];
#ifdef ISA_HAS_CC_REGS
TheISA::CCReg ccRegs[TheISA::NumCCRegs];
//
// New accessors for new decoder.
//
- uint64_t readIntReg(int reg_idx)
+ RegVal
+ readIntReg(int reg_idx)
{
int flatIndex = isa->flattenIntIndex(reg_idx);
assert(flatIndex < TheISA::NumIntRegs);
return regVal;
}
- FloatRegBits readFloatRegBits(int reg_idx)
+ RegVal
+ readFloatRegBits(int reg_idx)
{
int flatIndex = isa->flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
- FloatRegBits regVal(readFloatRegBitsFlat(flatIndex));
+ RegVal regVal(readFloatRegBitsFlat(flatIndex));
DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n",
reg_idx, flatIndex, regVal);
return regVal;
#endif
}
- void setIntReg(int reg_idx, uint64_t val)
+ void
+ setIntReg(int reg_idx, RegVal val)
{
int flatIndex = isa->flattenIntIndex(reg_idx);
assert(flatIndex < TheISA::NumIntRegs);
setIntRegFlat(flatIndex, val);
}
- void setFloatRegBits(int reg_idx, FloatRegBits val)
+ void
+ setFloatRegBits(int reg_idx, RegVal val)
{
int flatIndex = isa->flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
reg_idx, flatIndex, val);
}
- void setVecReg(const RegId& reg, const VecRegContainer& val)
+ void
+ setVecReg(const RegId& reg, const VecRegContainer& val)
{
int flatIndex = isa->flattenVecIndex(reg.index());
assert(flatIndex < TheISA::NumVecRegs);
reg.index(), flatIndex, val.print());
}
- void setVecElem(const RegId& reg, const VecElem& val)
+ void
+ setVecElem(const RegId& reg, const VecElem& val)
{
int flatIndex = isa->flattenVecElemIndex(reg.index());
assert(flatIndex < TheISA::NumVecRegs);
" %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val);
}
- void setCCReg(int reg_idx, CCReg val)
+ void
+ setCCReg(int reg_idx, CCReg val)
{
#ifdef ISA_HAS_CC_REGS
int flatIndex = isa->flattenCCIndex(reg_idx);
predicate = val;
}
- MiscReg
- readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const
+ RegVal
+ readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const
{
return isa->readMiscRegNoEffect(misc_reg);
}
- MiscReg
- readMiscReg(int misc_reg, ThreadID tid = 0)
+ RegVal
+ readMiscReg(int misc_reg, ThreadID tid=0)
{
return isa->readMiscReg(misc_reg, tc);
}
void
- setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
+ setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid = 0)
{
return isa->setMiscRegNoEffect(misc_reg, val);
}
void
- setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
+ setMiscReg(int misc_reg, const RegVal &val, ThreadID tid = 0)
{
return isa->setMiscReg(misc_reg, val, tc);
}
void setStCondFailures(unsigned sc_failures)
{ storeCondFailures = sc_failures; }
- void syscall(int64_t callnum, Fault *fault)
+ void
+ syscall(int64_t callnum, Fault *fault)
{
process->syscall(callnum, tc, fault);
}
- uint64_t readIntRegFlat(int idx) { return intRegs[idx]; }
- void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; }
+ RegVal readIntRegFlat(int idx) { return intRegs[idx]; }
+ void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; }
- FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs[idx]; }
- void setFloatRegBitsFlat(int idx, FloatRegBits val) {
- floatRegs[idx] = val;
- }
+ RegVal readFloatRegBitsFlat(int idx) { return floatRegs[idx]; }
+ void setFloatRegBitsFlat(int idx, RegVal val) { floatRegs[idx] = val; }
- const VecRegContainer& readVecRegFlat(const RegIndex& reg) const
+ const VecRegContainer &
+ readVecRegFlat(const RegIndex& reg) const
{
return vecRegs[reg];
}
- VecRegContainer& getWritableVecRegFlat(const RegIndex& reg)
+ VecRegContainer &
+ getWritableVecRegFlat(const RegIndex& reg)
{
return vecRegs[reg];
}
- void setVecRegFlat(const RegIndex& reg, const VecRegContainer& val)
+ void
+ setVecRegFlat(const RegIndex& reg, const VecRegContainer& val)
{
vecRegs[reg] = val;
}
template <typename T>
- VecLaneT<T, true> readVecLaneFlat(const RegIndex& reg, int lId) const
+ VecLaneT<T, true>
+ readVecLaneFlat(const RegIndex& reg, int lId) const
{
return vecRegs[reg].laneView<T>(lId);
}
template <typename LD>
- void setVecLaneFlat(const RegIndex& reg, int lId, const LD& val)
+ void
+ setVecLaneFlat(const RegIndex& reg, int lId, const LD& val)
{
vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val;
}
- const VecElem& readVecElemFlat(const RegIndex& reg,
- const ElemIndex& elemIndex) const
+ const VecElem &
+ readVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex) const
{
return vecRegs[reg].as<TheISA::VecElem>()[elemIndex];
}
- void setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex,
- const VecElem val)
+ void
+ setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex,
+ const VecElem val)
{
vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val;
}
// First loop through the integer registers.
for (int i = 0; i < TheISA::NumIntRegs; ++i) {
- TheISA::IntReg t1 = one->readIntReg(i);
- TheISA::IntReg t2 = two->readIntReg(i);
+ RegVal t1 = one->readIntReg(i);
+ RegVal t2 = two->readIntReg(i);
if (t1 != t2)
panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
i, t1, t2);
// Then loop through the floating point registers.
for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
- TheISA::FloatRegBits t1 = one->readFloatRegBits(i);
- TheISA::FloatRegBits t2 = two->readFloatRegBits(i);
+ RegVal t1 = one->readFloatRegBits(i);
+ RegVal t2 = two->readFloatRegBits(i);
if (t1 != t2)
panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
i, t1, t2);
i, t1, t2);
}
for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
- TheISA::MiscReg t1 = one->readMiscRegNoEffect(i);
- TheISA::MiscReg t2 = two->readMiscRegNoEffect(i);
+ RegVal t1 = one->readMiscRegNoEffect(i);
+ RegVal t2 = two->readMiscRegNoEffect(i);
if (t1 != t2)
panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
i, t1, t2);
{
using namespace TheISA;
- FloatRegBits floatRegs[NumFloatRegs];
+ RegVal floatRegs[NumFloatRegs];
for (int i = 0; i < NumFloatRegs; ++i)
floatRegs[i] = tc.readFloatRegBitsFlat(i);
// This is a bit ugly, but needed to maintain backwards
}
SERIALIZE_CONTAINER(vecRegs);
- IntReg intRegs[NumIntRegs];
+ RegVal intRegs[NumIntRegs];
for (int i = 0; i < NumIntRegs; ++i)
intRegs[i] = tc.readIntRegFlat(i);
SERIALIZE_ARRAY(intRegs, NumIntRegs);
{
using namespace TheISA;
- FloatRegBits floatRegs[NumFloatRegs];
+ RegVal floatRegs[NumFloatRegs];
// This is a bit ugly, but needed to maintain backwards
// compatibility.
arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs);
tc.setVecRegFlat(i, vecRegs[i]);
}
- IntReg intRegs[NumIntRegs];
+ RegVal intRegs[NumIntRegs];
UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
for (int i = 0; i < NumIntRegs; ++i)
tc.setIntRegFlat(i, intRegs[i]);
{
protected:
typedef TheISA::MachInst MachInst;
- typedef TheISA::IntReg IntReg;
- typedef TheISA::FloatReg FloatReg;
- typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::CCReg CCReg;
- typedef TheISA::MiscReg MiscReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
public:
//
// New accessors for new decoder.
//
- virtual uint64_t readIntReg(int reg_idx) = 0;
+ virtual RegVal readIntReg(int reg_idx) = 0;
- virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
+ virtual RegVal readFloatRegBits(int reg_idx) = 0;
virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
virtual CCReg readCCReg(int reg_idx) = 0;
- virtual void setIntReg(int reg_idx, uint64_t val) = 0;
+ virtual void setIntReg(int reg_idx, RegVal val) = 0;
- virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
+ virtual void setFloatRegBits(int reg_idx, RegVal val) = 0;
virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
virtual MicroPC microPC() = 0;
- virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0;
+ virtual RegVal readMiscRegNoEffect(int misc_reg) const = 0;
- virtual MiscReg readMiscReg(int misc_reg) = 0;
+ virtual RegVal readMiscReg(int misc_reg) = 0;
- virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
+ virtual void setMiscRegNoEffect(int misc_reg, const RegVal &val) = 0;
- virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
+ virtual void setMiscReg(int misc_reg, const RegVal &val) = 0;
virtual RegId flattenRegId(const RegId& regId) const = 0;
- virtual uint64_t
+ virtual RegVal
readRegOtherThread(const RegId& misc_reg, ThreadID tid)
{
return 0;
}
virtual void
- setRegOtherThread(const RegId& misc_reg, const MiscReg &val, ThreadID tid)
+ setRegOtherThread(const RegId& misc_reg, const RegVal &val, ThreadID tid)
{
}
* serialization code to access all registers.
*/
- virtual uint64_t readIntRegFlat(int idx) = 0;
- virtual void setIntRegFlat(int idx, uint64_t val) = 0;
+ virtual RegVal readIntRegFlat(int idx) = 0;
+ virtual void setIntRegFlat(int idx, RegVal val) = 0;
- virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
- virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
+ virtual RegVal readFloatRegBitsFlat(int idx) = 0;
+ virtual void setFloatRegBitsFlat(int idx, RegVal val) = 0;
virtual const VecRegContainer& readVecRegFlat(int idx) const = 0;
virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0;
//
// New accessors for new decoder.
//
- uint64_t readIntReg(int reg_idx)
+ RegVal readIntReg(int reg_idx)
{ return actualTC->readIntReg(reg_idx); }
- FloatRegBits readFloatRegBits(int reg_idx)
+ RegVal readFloatRegBits(int reg_idx)
{ return actualTC->readFloatRegBits(reg_idx); }
const VecRegContainer& readVecReg(const RegId& reg) const
CCReg readCCReg(int reg_idx)
{ return actualTC->readCCReg(reg_idx); }
- void setIntReg(int reg_idx, uint64_t val)
+ void setIntReg(int reg_idx, RegVal val)
{ actualTC->setIntReg(reg_idx, val); }
- void setFloatRegBits(int reg_idx, FloatRegBits val)
+ void setFloatRegBits(int reg_idx, RegVal val)
{ actualTC->setFloatRegBits(reg_idx, val); }
void setVecReg(const RegId& reg, const VecRegContainer& val)
void setPredicate(bool val)
{ actualTC->setPredicate(val); }
- MiscReg readMiscRegNoEffect(int misc_reg) const
+ RegVal readMiscRegNoEffect(int misc_reg) const
{ return actualTC->readMiscRegNoEffect(misc_reg); }
- MiscReg readMiscReg(int misc_reg)
+ RegVal readMiscReg(int misc_reg)
{ return actualTC->readMiscReg(misc_reg); }
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+ void setMiscRegNoEffect(int misc_reg, const RegVal &val)
{ return actualTC->setMiscRegNoEffect(misc_reg, val); }
- void setMiscReg(int misc_reg, const MiscReg &val)
+ void setMiscReg(int misc_reg, const RegVal &val)
{ return actualTC->setMiscReg(misc_reg, val); }
RegId flattenRegId(const RegId& regId) const
Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
- uint64_t readIntRegFlat(int idx)
+ RegVal readIntRegFlat(int idx)
{ return actualTC->readIntRegFlat(idx); }
- void setIntRegFlat(int idx, uint64_t val)
+ void setIntRegFlat(int idx, RegVal val)
{ actualTC->setIntRegFlat(idx, val); }
- FloatRegBits readFloatRegBitsFlat(int idx)
+ RegVal readFloatRegBitsFlat(int idx)
{ return actualTC->readFloatRegBitsFlat(idx); }
- void setFloatRegBitsFlat(int idx, FloatRegBits val)
+ void setFloatRegBitsFlat(int idx, RegVal val)
{ actualTC->setFloatRegBitsFlat(idx, val); }
const VecRegContainer& readVecRegFlat(int id) const
void
-GenericTimer::setMiscReg(int reg, unsigned cpu, MiscReg val)
+GenericTimer::setMiscReg(int reg, unsigned cpu, RegVal val)
{
CoreTimers &core(getTimers(cpu));
}
-MiscReg
+RegVal
GenericTimer::readMiscReg(int reg, unsigned cpu)
{
CoreTimers &core(getTimers(cpu));
void
-GenericTimerISA::setMiscReg(int reg, MiscReg val)
+GenericTimerISA::setMiscReg(int reg, RegVal val)
{
DPRINTF(Timer, "Setting %s := 0x%x\n", miscRegName[reg], val);
parent.setMiscReg(reg, cpu, val);
}
-MiscReg
+RegVal
GenericTimerISA::readMiscReg(int reg)
{
- MiscReg value = parent.readMiscReg(reg, cpu);
+ RegVal value = parent.readMiscReg(reg, cpu);
DPRINTF(Timer, "Reading %s as 0x%x\n", miscRegName[reg], value);
return value;
}
void unserialize(CheckpointIn &cp) override;
public:
- void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val);
- ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu);
+ void setMiscReg(int misc_reg, unsigned cpu, RegVal val);
+ RegVal readMiscReg(int misc_reg, unsigned cpu);
protected:
struct CoreTimers {
GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
: parent(_parent), cpu(_cpu) {}
- void setMiscReg(int misc_reg, ArmISA::MiscReg val) override;
- ArmISA::MiscReg readMiscReg(int misc_reg) override;
+ void setMiscReg(int misc_reg, RegVal val) override;
+ RegVal readMiscReg(int misc_reg) override;
protected:
GenericTimer &parent;
return wf;
}
-TheGpuISA::MiscReg
+RegVal
GPUExecContext::readMiscReg(int opIdx) const
{
assert(gpuISA);
}
void
-GPUExecContext::writeMiscReg(int opIdx, TheGpuISA::MiscReg operandVal)
+GPUExecContext::writeMiscReg(int opIdx, RegVal operandVal)
{
assert(gpuISA);
gpuISA->writeMiscReg(opIdx, operandVal);
#define __GPU_EXEC_CONTEXT_HH__
#include "arch/gpu_isa.hh"
+#include "base/types.hh"
#include "config/the_gpu_isa.hh"
class ComputeUnit;
Wavefront* wavefront();
ComputeUnit* computeUnit();
- TheGpuISA::MiscReg readMiscReg(int opIdx) const;
- void writeMiscReg(int opIdx, TheGpuISA::MiscReg operandVal);
+ RegVal readMiscReg(int opIdx) const;
+ void writeMiscReg(int opIdx, RegVal operandVal);
protected:
ComputeUnit *cu;
//The index is multiplied by the size of a MiscReg so that
//any memory dependence calculations will not see these as
//overlapping.
- req->setPaddr(regNum * sizeof(MiscReg));
+ req->setPaddr(regNum * sizeof(RegVal));
return NoFault;
} else if (prefix == IntAddrPrefixIO) {
// TODO If CPL > IOPL or in virtual mode, check the I/O permission
if (IOPort == 0xCF8 && req->getSize() == 4) {
req->setFlags(Request::MMAPPED_IPR);
- req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
+ req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(RegVal));
} else if ((IOPort & ~mask(2)) == 0xCFC) {
req->setFlags(Request::UNCACHEABLE);
void
Process::clone(ThreadContext *otc, ThreadContext *ntc,
- Process *np, TheISA::IntReg flags)
+ Process *np, RegVal flags)
{
#ifndef CLONE_VM
#define CLONE_VM 0
desc->doSyscall(callnum, this, tc, fault);
}
-IntReg
+RegVal
Process::getSyscallArg(ThreadContext *tc, int &i, int width)
{
return getSyscallArg(tc, i);
DrainState drain() override;
virtual void syscall(int64_t callnum, ThreadContext *tc, Fault *fault);
- virtual TheISA::IntReg getSyscallArg(ThreadContext *tc, int &i) = 0;
- virtual TheISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width);
- virtual void setSyscallArg(ThreadContext *tc, int i,
- TheISA::IntReg val) = 0;
+ virtual RegVal getSyscallArg(ThreadContext *tc, int &i) = 0;
+ virtual RegVal getSyscallArg(ThreadContext *tc, int &i, int width);
+ virtual void setSyscallArg(ThreadContext *tc, int i, RegVal val) = 0;
virtual void setSyscallReturn(ThreadContext *tc,
SyscallReturn return_value) = 0;
virtual SyscallDesc *getDesc(int callnum) = 0;
ThreadContext *new_tc, bool alloc_page);
virtual void clone(ThreadContext *old_tc, ThreadContext *new_tc,
- Process *new_p, TheISA::IntReg flags);
+ Process *new_p, RegVal flags);
// thread contexts associated with this process
std::vector<ContextID> contextIds;
SyscallDesc::doSyscall(int callnum, Process *process, ThreadContext *tc,
Fault *fault)
{
- TheISA::IntReg arg[6] M5_VAR_USED;
+ RegVal arg[6] M5_VAR_USED;
/**
* Step through the first six parameters for the system call and
{
int index = 0;
- TheISA::IntReg flags = p->getSyscallArg(tc, index);
- TheISA::IntReg newStack = p->getSyscallArg(tc, index);
+ RegVal flags = p->getSyscallArg(tc, index);
+ RegVal newStack = p->getSyscallArg(tc, index);
Addr ptidPtr = p->getSyscallArg(tc, index);
#if THE_ISA == RISCV_ISA or THE_ISA == ARM_ISA
projects / gem5.git / commitdiff