i386.md: New peephole2's to convert imul by 3, 5 or 9 into the equivalent lea instruc...

	* config/i386/i386.md: New peephole2's to convert imul by 3, 5 or
	9 into the equivalent lea instruction.

Co-Authored-By: Richard Henderson <rth@redhat.com>
From-SVN: r85366

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e46f01bd7069aeb6f8a2be00ee77a14e72560da4..9535b8cef84a14b5d4d9cd153d4b5bb0585b0268 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2004-07-30  Roger Sayle  <roger@eyesopen.com>
+           Richard Henderson  <rth@redhat.com>
+
+       * config/i386/i386.md: New peephole2's to convert imul by 3, 5 or
+       9 into the equivalent lea instruction.
+
 2004-07-30  Richard Henderson  <rth@redhat.com>
 
        * gimplify.c (gimplify_expr) <case CONST_DECL>: Don't replace

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 9421cc72cd778bdf84bdb3d6b427803ef7198da4..12c051e010f729709adb24b49597d9762b12a257 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -19326,6 +19326,69 @@
              (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
   "")
 \f
+;; Convert imul by three, five and nine into lea
+(define_peephole2
+  [(parallel
+    [(set (match_operand:SI 0 "register_operand" "")
+         (mult:SI (match_operand:SI 1 "register_operand" "")
+                  (match_operand:SI 2 "const_int_operand" "")))
+     (clobber (reg:CC FLAGS_REG))])]
+  "INTVAL (operands[2]) == 3
+   || INTVAL (operands[2]) == 5
+   || INTVAL (operands[2]) == 9"
+  [(set (match_dup 0)
+        (plus:SI (mult:SI (match_dup 1) (match_dup 2))
+                 (match_dup 1)))]
+  { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
+
+(define_peephole2
+  [(parallel
+    [(set (match_operand:SI 0 "register_operand" "")
+          (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
+                   (match_operand:SI 2 "const_int_operand" "")))
+     (clobber (reg:CC FLAGS_REG))])]
+  "!optimize_size 
+   && (INTVAL (operands[2]) == 3
+       || INTVAL (operands[2]) == 5
+       || INTVAL (operands[2]) == 9)"
+  [(set (match_dup 0) (match_dup 1))
+   (set (match_dup 0)
+        (plus:SI (mult:SI (match_dup 0) (match_dup 2))
+                 (match_dup 0)))]
+  { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
+
+(define_peephole2
+  [(parallel
+    [(set (match_operand:DI 0 "register_operand" "")
+         (mult:DI (match_operand:DI 1 "register_operand" "")
+                  (match_operand:DI 2 "const_int_operand" "")))
+     (clobber (reg:CC FLAGS_REG))])]
+  "TARGET_64BIT
+   && (INTVAL (operands[2]) == 3
+       || INTVAL (operands[2]) == 5
+       || INTVAL (operands[2]) == 9)"
+  [(set (match_dup 0)
+        (plus:DI (mult:DI (match_dup 1) (match_dup 2))
+                 (match_dup 1)))]
+  { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
+
+(define_peephole2
+  [(parallel
+    [(set (match_operand:DI 0 "register_operand" "")
+          (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
+                   (match_operand:DI 2 "const_int_operand" "")))
+     (clobber (reg:CC FLAGS_REG))])]
+  "TARGET_64BIT
+   && !optimize_size 
+   && (INTVAL (operands[2]) == 3
+       || INTVAL (operands[2]) == 5
+       || INTVAL (operands[2]) == 9)"
+  [(set (match_dup 0) (match_dup 1))
+   (set (match_dup 0)
+        (plus:DI (mult:DI (match_dup 0) (match_dup 2))
+                 (match_dup 0)))]
+  { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
+
 ;; Imul $32bit_imm, mem, reg is vector decoded, while
 ;; imul $32bit_imm, reg, reg is direct decoded.
 (define_peephole2