Re-added clean after techmap in synth_xilinx
authorClifford Wolf <clifford@clifford.at>
Mon, 22 Apr 2019 07:03:11 +0000 (09:03 +0200)
committerClifford Wolf <clifford@clifford.at>
Mon, 22 Apr 2019 07:03:11 +0000 (09:03 +0200)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
techlibs/xilinx/synth_xilinx.cc

index da6c0a4b25bd0ff1b5acc4d36236b4b89050739f..d66722195e0af30a3bd69ebe4d01663c29c68dbc 100644 (file)
@@ -124,6 +124,7 @@ struct SynthXilinxPass : public Pass
                log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
                log("        dffinit -ff FDRE   Q INIT -ff FDCE   Q INIT -ff FDPE   Q INIT -ff FDSE   Q INIT \\\n");
                log("                -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
+               log("        clean\n");
                log("\n");
                log("    check:\n");
                log("        hierarchy -check\n");
@@ -280,6 +281,7 @@ struct SynthXilinxPass : public Pass
                        Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
                        Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
                                        "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
+                       Pass::call(design, "clean");
                }
 
                if (check_label(active, run_from, run_to, "check"))