AVX-512. 69/n. Add vpmulhrsw insn support.

gcc/
        * config/i386/sse.md
        (define_insn "avx512bw_umulhrswv32hi3<mask_name>"): New.
        (define_expand "<ssse3_avx2>_pmulhrsw<mode>3_mask"): Ditto.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>
From-SVN: r216186

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 79606b70fb503b753f057410126b78b33963f5db..4416b51b219e292975d01edd278a5d0805cda202 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2014-10-14  Alexander Ivchenko  <alexander.ivchenko@intel.com>
+           Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+           Anna Tikhonova  <anna.tikhonova@intel.com>
+           Ilya Tocar  <ilya.tocar@intel.com>
+           Andrey Turetskiy  <andrey.turetskiy@intel.com>
+           Ilya Verbin  <ilya.verbin@intel.com>
+           Kirill Yukhin  <kirill.yukhin@intel.com>
+           Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+        * config/i386/sse.md
+        (define_insn "avx512bw_umulhrswv32hi3<mask_name>"): New.
+        (define_expand "<ssse3_avx2>_pmulhrsw<mode>3_mask"): Ditto.
+
 2014-10-14  Alexander Ivchenko  <alexander.ivchenko@intel.com>
            Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
            Anna Tikhonova  <anna.tikhonova@intel.com>

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index c917393458549e382c5eff28eabaa69a6cb8634d..30fc1dc5fa1f41c8eb5908a7095d8ec386e684a4 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -13273,6 +13273,41 @@
    (set_attr "prefix" "evex")
    (set_attr "mode" "XI")])
 
+(define_insn "avx512bw_umulhrswv32hi3<mask_name>"
+  [(set (match_operand:V32HI 0 "register_operand" "=v")
+       (truncate:V32HI
+         (lshiftrt:V32SI
+           (plus:V32SI
+             (lshiftrt:V32SI
+               (mult:V32SI
+                 (sign_extend:V32SI
+                   (match_operand:V32HI 1 "nonimmediate_operand" "%v"))
+                 (sign_extend:V32SI
+                   (match_operand:V32HI 2 "nonimmediate_operand" "vm")))
+               (const_int 14))
+             (const_vector:V32HI [(const_int 1) (const_int 1)
+                                  (const_int 1) (const_int 1)
+                                  (const_int 1) (const_int 1)
+                                  (const_int 1) (const_int 1)
+                                  (const_int 1) (const_int 1)
+                                  (const_int 1) (const_int 1)
+                                  (const_int 1) (const_int 1)
+                                  (const_int 1) (const_int 1)
+                                  (const_int 1) (const_int 1)
+                                  (const_int 1) (const_int 1)
+                                  (const_int 1) (const_int 1)
+                                  (const_int 1) (const_int 1)
+                                  (const_int 1) (const_int 1)
+                                  (const_int 1) (const_int 1)
+                                  (const_int 1) (const_int 1)
+                                  (const_int 1) (const_int 1)]))
+           (const_int 1))))]
+  "TARGET_AVX512BW"
+  "vpmulhrsw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+  [(set_attr "type" "sseimul")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "XI")])
+
 (define_insn "ssse3_pmaddubsw128"
   [(set (match_operand:V8HI 0 "register_operand" "=x,x")
        (ss_plus:V8HI
@@ -13350,6 +13385,29 @@
 (define_mode_iterator PMULHRSW
   [V4HI V8HI (V16HI "TARGET_AVX2")])
 
+(define_expand "<ssse3_avx2>_pmulhrsw<mode>3_mask"
+  [(set (match_operand:PMULHRSW 0 "register_operand")
+       (vec_merge:PMULHRSW
+         (truncate:PMULHRSW
+           (lshiftrt:<ssedoublemode>
+             (plus:<ssedoublemode>
+               (lshiftrt:<ssedoublemode>
+                 (mult:<ssedoublemode>
+                   (sign_extend:<ssedoublemode>
+                     (match_operand:PMULHRSW 1 "nonimmediate_operand"))
+                   (sign_extend:<ssedoublemode>
+                     (match_operand:PMULHRSW 2 "nonimmediate_operand")))
+                 (const_int 14))
+               (match_dup 5))
+             (const_int 1)))
+         (match_operand:PMULHRSW 3 "register_operand")
+         (match_operand:<avx512fmaskmode> 4 "register_operand")))]
+  "TARGET_AVX512BW && TARGET_AVX512VL"
+{
+  operands[5] = CONST1_RTX(<MODE>mode);
+  ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);
+})
+
 (define_expand "<ssse3_avx2>_pmulhrsw<mode>3"
   [(set (match_operand:PMULHRSW 0 "register_operand")
        (truncate:PMULHRSW