Added english description for lbzux instruction

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index e66c461f659885035de53f01926b2d413aae1a47..71059cb034bc53f1b0424969bfa59b22fe0b546b 100644 (file)
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -92,6 +92,12 @@ Pseudo-code:
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
     RA <- EA
 
+Description:Let the effective address (EA) be the sum (RA)+ (RB).
+The byte in storage addressed by EA is loaded into
+RT56:63. RT0:55 are set to 0.
+EA is placed into register RA.
+If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None