amd: assume CMASK is always rb/pipe_aligned, remove ac_surface.u.gfx9.cmask

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index b3c4c99486dc0401ef59a4adb661f5f173337c9d..1ad9bfbb5fb6c456dc14c2a54b086cc1fc3a10cd 100644 (file)
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1478,14 +1478,11 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
                        cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
                        cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
 
-                       if (in->numSamples > 1) {
-                               /* FMASK is always aligned. */
-                               cin.cMaskFlags.pipeAligned = 1;
-                               cin.cMaskFlags.rbAligned = 1;
-                       } else {
-                               cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned;
-                               cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned;
-                       }
+                       assert(in->flags.metaPipeUnaligned == 0);
+                       assert(in->flags.metaRbUnaligned == 0);
+
+                       cin.cMaskFlags.pipeAligned = 1;
+                       cin.cMaskFlags.rbAligned = 1;
                        cin.colorFlags = in->flags;
                        cin.resourceType = in->resourceType;
                        cin.unalignedWidth = in->width;
@@ -1501,8 +1498,6 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
                        if (ret != ADDR_OK)
                                return ret;
 
-                       surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
-                       surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
                        surf->cmask_size = cout.cmaskBytes;
                        surf->cmask_alignment = cout.baseAlign;
                }
@@ -1609,7 +1604,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
        else
                AddrSurfInfoIn.numSlices = config->info.array_size;
 
-       /* This is propagated to HTILE/DCC/CMASK. */
+       /* This is propagated to HTILE/DCC. */
        AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
        AddrSurfInfoIn.flags.metaRbUnaligned = 0;
 

diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 8fbf7488c4a0a1c6e36176fa5467411c655e07ee..5a1381980f2782ee6e176d86f5b06b18a291d585 100644 (file)
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -151,7 +151,6 @@ struct gfx9_surf_layout {
 
     struct gfx9_surf_meta_flags dcc;   /* metadata of color */
     struct gfx9_surf_meta_flags htile; /* metadata of depth and stencil */
-    struct gfx9_surf_meta_flags cmask; /* metadata of fmask */
 
     enum gfx9_resource_type     resource_type; /* 1D, 2D or 3D */
     uint16_t                    surf_pitch; /* in blocks */

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index ceedb4a0c5abf257cfce9768a7c3b752fa51371b..883d7d49efc48a385332c8abc2ea65ddbe143b21 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -6469,18 +6469,20 @@ radv_initialise_color_surface(struct radv_device *device,
        cb->cb_color_base = va >> 8;
 
        if (device->physical_device->rad_info.chip_class >= GFX9) {
-               struct gfx9_surf_meta_flags meta;
-               if (iview->image->dcc_offset)
-                       meta = surf->u.gfx9.dcc;
-               else
-                       meta = surf->u.gfx9.cmask;
-
                if (device->physical_device->rad_info.chip_class >= GFX10) {
                        cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
                                S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
-                               S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
+                               S_028EE0_CMASK_PIPE_ALIGNED(1) |
                                S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
                } else {
+                       struct gfx9_surf_meta_flags meta = {
+                               .rb_aligned = 1,
+                               .pipe_aligned = 1,
+                       };
+
+                       if (iview->image->dcc_offset)
+                               meta = surf->u.gfx9.dcc;
+
                        cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
                                S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
                                S_028C74_RB_ALIGNED(meta.rb_aligned) |

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 44d049351406ee4a22d220685f092d702fff0e7e..1387715892451d1b53f68f2cd2f648c675db6a5d 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -844,7 +844,7 @@ gfx10_make_texture_descriptor(struct radv_device *device,
                fmask_state[4] = S_00A010_DEPTH(last_layer) |
                                 S_00A010_BASE_ARRAY(first_layer);
                fmask_state[5] = 0;
-               fmask_state[6] = S_00A018_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned);
+               fmask_state[6] = S_00A018_META_PIPE_ALIGNED(1);
                fmask_state[7] = 0;
        } else if (fmask_state)
                memset(fmask_state, 0, 8 * 4);
@@ -1032,8 +1032,8 @@ si_make_texture_descriptor(struct radv_device *device,
                        fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
                        fmask_state[4] |= S_008F20_DEPTH(last_layer) |
                                          S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
-                       fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
-                                         S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
+                       fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(1) |
+                                         S_008F24_META_RB_ALIGNED(1);
 
                        if (radv_image_is_tc_compat_cmask(image)) {
                                va = gpu_address + image->offset + image->cmask_offset;

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 2f6c437a58ba36978605cd04af2c8a998ca5c740..5fef04b3cb2cf02237d5bda74bc190c680e92ebf 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3049,7 +3049,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
          cb_color_attrib3 = cb->cb_color_attrib3 |
                             S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
                             S_028EE0_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
-                            S_028EE0_CMASK_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
+                            S_028EE0_CMASK_PIPE_ALIGNED(1) |
                             S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.dcc.pipe_aligned);
 
          radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 14);
@@ -3077,12 +3077,13 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
          radeon_set_context_reg(cs, R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb->cb_color_attrib2);
          radeon_set_context_reg(cs, R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_color_attrib3);
       } else if (sctx->chip_class == GFX9) {
-         struct gfx9_surf_meta_flags meta;
+         struct gfx9_surf_meta_flags meta = {
+            .rb_aligned = 1,
+            .pipe_aligned = 1,
+         };
 
          if (tex->surface.dcc_offset)
             meta = tex->surface.u.gfx9.dcc;
-         else
-            meta = tex->surface.u.gfx9.cmask;
 
          /* Set mutable surface parameters. */
          cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
@@ -3878,7 +3879,7 @@ static void gfx10_make_texture_descriptor(
          S_00A00C_TYPE(si_tex_dim(screen, tex, target, 0));
       fmask_state[4] = S_00A010_DEPTH(last_layer) | S_00A010_BASE_ARRAY(first_layer);
       fmask_state[5] = 0;
-      fmask_state[6] = S_00A018_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned);
+      fmask_state[6] = S_00A018_META_PIPE_ALIGNED(1);
       fmask_state[7] = 0;
    }
 }
@@ -4201,8 +4202,8 @@ static void si_make_texture_descriptor(struct si_screen *screen, struct si_textu
          fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
          fmask_state[4] |=
             S_008F20_DEPTH(last_layer) | S_008F20_PITCH(tex->surface.u.gfx9.fmask.epitch);
-         fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
-                           S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
+         fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(1) |
+                           S_008F24_META_RB_ALIGNED(1);
       } else {
          fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
          fmask_state[4] |= S_008F20_DEPTH(depth - 1) |

diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 1c2c170c97ee95ece03fc8a431ba963cc1b0eb07..2ec19e5f28d9462bbb24e4a2c588cba9160dcd1d 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -1065,10 +1065,9 @@ void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex,
       if (tex->cmask_buffer) {
          u_log_printf(log,
                       "  CMask: offset=%" PRIu64 ", size=%u, "
-                      "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
+                      "alignment=%u\n",
                       tex->surface.cmask_offset, tex->surface.cmask_size,
-                      tex->surface.cmask_alignment, tex->surface.u.gfx9.cmask.rb_aligned,
-                      tex->surface.u.gfx9.cmask.pipe_aligned);
+                      tex->surface.cmask_alignment);
       }
 
       if (tex->surface.htile_offset) {