typedef TheISA::ExtMachInst ExtMachInst;
// Logical register index type.
typedef TheISA::RegIndex RegIndex;
- // Integer register index type.
+ // Integer register type.
typedef TheISA::IntReg IntReg;
+ // Floating point register type.
+ typedef TheISA::FloatReg FloatReg;
// The DynInstPtr type.
typedef typename Impl::DynInstPtr DynInstPtr;
instResult.integer = val;
}
- void setFloatRegSingle(const StaticInst *si, int idx, float val)
+ void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ {
+ if (width == 32)
+ instResult.fp = val;
+ else if (width == 64)
+ instResult.dbl = val;
+ else
+ panic("Unsupported width!");
+ }
+
+ void setFloatReg(const StaticInst *si, int idx, FloatReg val)
{
instResult.fp = val;
}
- void setFloatRegDouble(const StaticInst *si, int idx, double val)
+ void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
{
- instResult.dbl = val;
+ instResult.integer = val;
}
- void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
+ void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
{
instResult.integer = val;
}
return TheISA::genAlignmentFault();
}
- fault = cpu->translateDataReadReq(req);
+ fault = cpu->translateDataReadReq(req, thread);
if (fault == NoFault) {
effAddr = req->getVaddr();
physEffAddr = req->getPaddr();
memReqFlags = req->getFlags();
-#if FULL_SYSTEM
+#if 0
if (cpu->system->memctrl->badaddr(physEffAddr)) {
fault = TheISA::genMachineCheckFault();
data = (T)-1;
return TheISA::genAlignmentFault();
}
- fault = cpu->translateDataWriteReq(req);
+ fault = cpu->translateDataWriteReq(req, thread);
if (fault == NoFault) {
effAddr = req->getVaddr();
physEffAddr = req->getPaddr();
memReqFlags = req->getFlags();
-#if FULL_SYSTEM
+#if 0
if (cpu->system->memctrl->badaddr(physEffAddr)) {
fault = TheISA::genMachineCheckFault();
} else {
itb = p->itb;
dtb = p->dtb;
systemPtr = NULL;
- memPtr = NULL;
#else
process = p->process;
#endif
void
CheckerCPU::setMemory(MemObject *mem)
{
- memPtr = mem;
#if !FULL_SYSTEM
+ memPtr = mem;
thread = new SimpleThread(this, /* thread_num */ 0, process,
/* asid */ 0, mem);
thread->setStatus(ThreadContext::Suspended);
tc = thread->getTC();
threadContexts.push_back(tc);
-#else
- if (systemPtr) {
- thread = new SimpleThread(this, 0, systemPtr, itb, dtb, memPtr, false);
-
- thread->setStatus(ThreadContext::Suspended);
- tc = thread->getTC();
- threadContexts.push_back(tc);
- delete thread->kernelStats;
- thread->kernelStats = NULL;
- }
#endif
}
-#if FULL_SYSTEM
void
CheckerCPU::setSystem(System *system)
{
+#if FULL_SYSTEM
systemPtr = system;
- if (memPtr) {
- thread = new SimpleThread(this, 0, systemPtr, itb, dtb, memPtr, false);
+ thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
- thread->setStatus(ThreadContext::Suspended);
- tc = thread->getTC();
- threadContexts.push_back(tc);
- delete thread->kernelStats;
- thread->kernelStats = NULL;
- }
-}
+ thread->setStatus(ThreadContext::Suspended);
+ tc = thread->getTC();
+ threadContexts.push_back(tc);
+ delete thread->kernelStats;
+ thread->kernelStats = NULL;
#endif
+}
void
CheckerCPU::setIcachePort(Port *icache_port)
Addr
CheckerCPU::dbg_vtophys(Addr addr)
{
- return vtophys(xcProxy, addr);
+ return vtophys(tc, addr);
}
#endif // FULL_SYSTEM
if (fault != NoFault) {
#if FULL_SYSTEM
- fault->invoke(xcProxy);
+ fault->invoke(tc);
willChangePC = true;
newPC = thread->readPC();
DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
int count = 0;
do {
oldpc = thread->readPC();
- system->pcEventQueue.service(xcProxy);
+ system->pcEventQueue.service(tc);
count++;
} while (oldpc != thread->readPC());
if (count > 1) {
#if FULL_SYSTEM
AlphaITB *itb;
AlphaDTB *dtb;
- FunctionalMemory *mem;
#else
Process *process;
#endif
MemObject *memPtr;
-#if FULL_SYSTEM
void setSystem(System *system);
System *systemPtr;
-#endif
void setIcachePort(Port *icache_port);
int readIntrFlag() { return thread->readIntrFlag(); }
void setIntrFlag(int val) { thread->setIntrFlag(val); }
bool inPalMode() { return thread->inPalMode(); }
- void ev5_trap(Fault fault) { fault->invoke(xcProxy); }
+ void ev5_trap(Fault fault) { fault->invoke(tc); }
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
#else
// Assume that the normal CPU's call to syscall was successful.
#if FULL_SYSTEM
SimObjectParam<AlphaITB *> itb;
SimObjectParam<AlphaDTB *> dtb;
- SimObjectParam<MemObject *> mem;
SimObjectParam<System *> system;
Param<int> cpu_id;
Param<Tick> profile;
#if FULL_SYSTEM
INIT_PARAM(itb, "Instruction TLB"),
INIT_PARAM(dtb, "Data TLB"),
- INIT_PARAM(mem, "memory"),
INIT_PARAM(system, "system object"),
INIT_PARAM(cpu_id, "processor ID"),
INIT_PARAM(profile, ""),
#if FULL_SYSTEM
params->itb = itb;
params->dtb = dtb;
- params->mem = mem;
params->system = system;
params->cpu_id = cpu_id;
params->profile = profile;
int readCpuId() { return actualTC->readCpuId(); }
- TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
-
#if FULL_SYSTEM
System *getSystemPtr() { return actualTC->getSystemPtr(); }
AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); }
Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
+
+ FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
+
+ VirtualPort *getVirtPort(ThreadContext *tc = NULL)
+ { return actualTC->getVirtPort(); }
+
+ void delVirtPort(VirtualPort *vp) { actualTC->delVirtPort(vp); }
#else
+ TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
+
Process *getProcessPtr() { return actualTC->getProcessPtr(); }
#endif
* external objects try to update state through this interface,
* the CPU will create an event to squash all in-flight
* instructions in order to ensure state is maintained correctly.
+ * It must be defined specifically for the AlphaFullCPU because
+ * not all architectural state is located within the O3ThreadState
+ * (such as the commit PC, and registers), and specific actions
+ * must be taken when using this interface (such as squashing all
+ * in-flight instructions when doing a write to this interface).
*/
class AlphaTC : public ThreadContext
{
/** Reads this CPU's ID. */
virtual int readCpuId() { return cpu->cpu_id; }
- virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
-
#if FULL_SYSTEM
/** Returns a pointer to the system. */
virtual System *getSystemPtr() { return cpu->system; }
/** Returns a pointer to this thread's kernel statistics. */
virtual Kernel::Statistics *getKernelStats()
{ return thread->kernelStats; }
+
+ virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
+
+ virtual VirtualPort *getVirtPort(ThreadContext *src_tc = NULL);
+
+ void delVirtPort(VirtualPort *vp);
#else
+ virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
+
/** Returns a pointer to this thread's process. */
virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
#endif
#if FULL_SYSTEM
/** Translates instruction requestion. */
- Fault translateInstReq(RequestPtr &req)
+ Fault translateInstReq(RequestPtr &req, Thread *thread)
{
- return itb->translate(req);
+ return itb->translate(req, thread->getTC());
}
/** Translates data read request. */
- Fault translateDataReadReq(RequestPtr &req)
+ Fault translateDataReadReq(RequestPtr &req, Thread *thread)
{
- return dtb->translate(req, false);
+ return dtb->translate(req, thread->getTC(), false);
}
/** Translates data write request. */
- Fault translateDataWriteReq(RequestPtr &req)
+ Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
{
- return dtb->translate(req, true);
+ return dtb->translate(req, thread->getTC(), true);
}
#else
/** Translates instruction requestion in syscall emulation mode. */
- Fault translateInstReq(RequestPtr &req)
+ Fault translateInstReq(RequestPtr &req, Thread *thread)
{
- int tid = req->getThreadNum();
- return this->thread[tid]->getProcessPtr()->pTable->translate(req);
+ return thread->getProcessPtr()->pTable->translate(req);
}
/** Translates data read request in syscall emulation mode. */
- Fault translateDataReadReq(RequestPtr &req)
+ Fault translateDataReadReq(RequestPtr &req, Thread *thread)
{
- int tid = req->getThreadNum();
- return this->thread[tid]->getProcessPtr()->pTable->translate(req);
+ return thread->getProcessPtr()->pTable->translate(req);
}
/** Translates data write request in syscall emulation mode. */
- Fault translateDataWriteReq(RequestPtr &req)
+ Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
{
- int tid = req->getThreadNum();
- return this->thread[tid]->getProcessPtr()->pTable->translate(req);
+ return thread->getProcessPtr()->pTable->translate(req);
}
#endif
#include "arch/isa_traits.hh"
#include "cpu/quiesce_event.hh"
#include "kern/kernel_stats.hh"
+#include "sim/system.hh"
#endif
using namespace TheISA;
#if FULL_SYSTEM
// SMT is not supported in FS mode yet.
assert(this->numThreads == 1);
- this->thread[i] = new Thread(this, 0, params->mem);
+ this->thread[i] = new Thread(this, 0);
this->thread[i]->setStatus(ThreadContext::Suspended);
#else
if (i < params->workload.size()) {
FunctionalPort *phys_port;
VirtualPort *virt_port;
phys_port = new FunctionalPort(csprintf("%s-%d-funcport",
- cpu->name(), tid));
- mem_port = system->physmem->getPort("functional");
+ name(), i));
+ mem_port = this->system->physmem->getPort("functional");
mem_port->setPeer(phys_port);
phys_port->setPeer(mem_port);
virt_port = new VirtualPort(csprintf("%s-%d-vport",
- cpu->name(), tid));
- mem_port = system->physmem->getPort("functional");
+ name(), i));
+ mem_port = this->system->physmem->getPort("functional");
mem_port->setPeer(virt_port);
virt_port->setPeer(mem_port);
}
#if FULL_SYSTEM
+template <class Impl>
+VirtualPort *
+AlphaFullCPU<Impl>::AlphaTC::getVirtPort(ThreadContext *src_tc)
+{
+ if (!src_tc)
+ return thread->getVirtPort();
+
+ VirtualPort *vp;
+ Port *mem_port;
+
+ vp = new VirtualPort("tc-vport", src_tc);
+ mem_port = cpu->system->physmem->getPort("functional");
+ mem_port->setPeer(vp);
+ vp->setPeer(mem_port);
+ return vp;
+}
+
template <class Impl>
void
AlphaFullCPU<Impl>::AlphaTC::dumpFuncProfile()
AlphaFullCPU<Impl>::AlphaTC::takeOverFrom(ThreadContext *old_context)
{
// some things should already be set up
- assert(getMemPort() == old_context->getMemPort());
#if FULL_SYSTEM
assert(getSystemPtr() == old_context->getSystemPtr());
#else
thread->trapPending = false;
}
+#if FULL_SYSTEM
+template <class Impl>
+void
+AlphaFullCPU<Impl>::AlphaTC::delVirtPort(VirtualPort *vp)
+{
+ delete vp->getPeer();
+ delete vp;
+}
+#endif
+
template <class Impl>
void
AlphaFullCPU<Impl>::AlphaTC::activate(int delay)
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
{
this->cpu->setFloatReg(_destRegIdx[idx], val, width);
- BaseDynInst<Impl>::setFloatRegSingle(si, idx, val);
+ BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
}
void setFloatReg(const StaticInst *si, int idx, FloatReg val)
{
this->cpu->setFloatReg(_destRegIdx[idx], val);
- BaseDynInst<Impl>::setFloatRegDouble(si, idx, val);
+ BaseDynInst<Impl>::setFloatReg(si, idx, val);
}
void setFloatRegBits(const StaticInst *si, int idx,
FloatRegBits val, int width)
{
this->cpu->setFloatRegBits(_destRegIdx[idx], val, width);
- this->instResult.integer = val;
+ BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
}
void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
{
this->cpu->setFloatRegBits(_destRegIdx[idx], val);
- BaseDynInst<Impl>::setFloatRegInt(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
}
/** Returns the physical register index of the i'th destination
!thread[tid]->trapPending);
oldpc = PC[tid];
cpu->system->pcEventQueue.service(
- thread[tid]->getXCProxy());
+ thread[tid]->getTC());
count++;
} while (oldpc != PC[tid]);
if (count > 1) {
#if FULL_SYSTEM
system(params->system),
- memCtrl(system->memctrl),
physmem(system->physmem),
#endif // FULL_SYSTEM
mem(params->mem),
/** Pointer to the system. */
System *system;
- /** Pointer to the memory controller. */
- MemoryController *memCtrl;
/** Pointer to physical memory. */
PhysicalMemory *physmem;
#endif
#include "arch/tlb.hh"
#include "arch/vtophys.hh"
#include "base/remote_gdb.hh"
-#include "mem/functional/memory_control.hh"
-#include "mem/functional/physical.hh"
#include "sim/system.hh"
#endif // FULL_SYSTEM
// Translate the instruction request.
//#if FULL_SYSTEM
- fault = cpu->translateInstReq(mem_req);
+ fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
//#else
// fault = pTable->translate(memReq[tid]);
//#endif
// If translation was successful, attempt to read the first
// instruction.
if (fault == NoFault) {
-#if FULL_SYSTEM
+#if 0
if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
memReq[tid]->flags & UNCACHEABLE) {
DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
assert(reg_idx < numPhysicalIntRegs);
DPRINTF(IEW, "RegFile: Access to int register %i, has data "
- "%i\n", int(reg_idx), intRegFile[reg_idx]);
+ "%#x\n", int(reg_idx), intRegFile[reg_idx]);
return intRegFile[reg_idx];
}
FloatReg floatReg = floatRegFile[reg_idx].d;
DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has "
- "data %8.8d\n", int(reg_idx), (double)floatReg);
+ "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
return floatReg;
}
FloatReg floatReg = floatRegFile[reg_idx].d;
DPRINTF(IEW, "RegFile: Access to float register %i, has "
- "data %8.8d\n", int(reg_idx), (double)floatReg);
+ "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
return floatReg;
}
FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
- DPRINTF(IEW, "RegFile: Access to %d byte float register %i as int, "
- "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits);
+ DPRINTF(IEW, "RegFile: Access to float register %i as int, "
+ "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
return floatRegBits;
}
FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
DPRINTF(IEW, "RegFile: Access to float register %i as int, "
- "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits);
+ "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
return floatRegBits;
}
{
assert(reg_idx < numPhysicalIntRegs);
- DPRINTF(IEW, "RegFile: Setting int register %i to %lli\n",
+ DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
int(reg_idx), val);
if (reg_idx != TheISA::ZeroReg)
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
- DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
- int(reg_idx), (double)val);
+ DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
+ int(reg_idx), (uint64_t)val);
if (reg_idx != TheISA::ZeroReg)
- floatRegFile[reg_idx].d = width;
+ floatRegFile[reg_idx].d = val;
}
/** Sets a double precision floating point register to the given value. */
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
- DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
- int(reg_idx), (double)val);
+ DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
+ int(reg_idx), (uint64_t)val);
if (reg_idx != TheISA::ZeroReg)
floatRegFile[reg_idx].d = val;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
- DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
+ DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
int(reg_idx), (uint64_t)val);
floatRegFile[reg_idx].q = val;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
- DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
+ DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
int(reg_idx), (uint64_t)val);
floatRegFile[reg_idx].q = val;
public:
/** (signed) integer register file. */
- std::vector<IntReg> intRegFile;
+ IntReg *intRegFile;
/** Floating point register file. */
- std::vector<PhysFloatReg> floatRegFile;
+ PhysFloatReg *floatRegFile;
/** Miscellaneous register file. */
MiscRegFile miscRegs[Impl::MaxThreads];
: numPhysicalIntRegs(_numPhysicalIntRegs),
numPhysicalFloatRegs(_numPhysicalFloatRegs)
{
- intRegFile.resize(numPhysicalIntRegs);
- floatRegFile.resize(numPhysicalFloatRegs);
+ intRegFile = new IntReg[numPhysicalIntRegs];
+ floatRegFile = new PhysFloatReg[numPhysicalFloatRegs];
for (int i = 0; i < Impl::MaxThreads; ++i) {
miscRegs[i].clear();
}
- //memset(intRegFile, 0, sizeof(*intRegFile));
- //memset(floatRegFile, 0, sizeof(*floatRegFile));
+ memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs);
+ memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);
}
#endif
bool trapPending;
#if FULL_SYSTEM
- O3ThreadState(FullCPU *_cpu, int _thread_num, )
+ O3ThreadState(FullCPU *_cpu, int _thread_num)
: ThreadState(-1, _thread_num),
inSyscall(0), trapPending(0)
{ }
int readCpuId() { return thread->cpuId; }
- TranslatingPort *getMemPort() { return /*thread->port*/NULL; }
-
#if FULL_SYSTEM
System *getSystemPtr() { return cpu->system; }
AlphaDTB * getDTBPtr() { return cpu->dtb; }
Kernel::Statistics *getKernelStats() { return thread->kernelStats; }
+
+ FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
+
+ VirtualPort *getVirtPort(ThreadContext *tc = NULL)
+ { return thread->getVirtPort(tc); }
+
+ void delVirtPort(VirtualPort *vp)
+ { thread->delVirtPort(vp); }
#else
+ TranslatingPort *getMemPort() { return thread->port; }
+
Process *getProcessPtr() { return thread->process; }
#endif
AlphaITB *itb;
AlphaDTB *dtb;
System *system;
-
- // the following two fields are redundant, since we can always
- // look them up through the system pointer, but we'll leave them
- // here for now for convenience
- MemoryController *memctrl;
PhysicalMemory *physmem;
#endif
- // L1 instruction cache
-// MemInterface *icacheInterface;
-
- // L1 data cache
-// MemInterface *dcacheInterface;
-
- /** Pointer to memory. */
- FunctionalMemory *mem;
-
FrontEnd *frontEnd;
BackEnd *backEnd;
bool validInstAddr(Addr addr) { return true; }
bool validDataAddr(Addr addr) { return true; }
- Fault translateInstReq(MemReqPtr &req)
+ Fault translateInstReq(Request *req)
{
- return itb->translate(req);
+ return itb->translate(req, tc);
}
- Fault translateDataReadReq(MemReqPtr &req)
+ Fault translateDataReadReq(Request *req)
{
- return dtb->translate(req, false);
+ return dtb->translate(req, tc, false);
}
- Fault translateDataWriteReq(MemReqPtr &req)
+ Fault translateDataWriteReq(Request *req)
{
- return dtb->translate(req, true);
+ return dtb->translate(req, tc, true);
}
#else
typedef TheISA::MiscReg MiscReg;
#if FULL_SYSTEM
- OzoneThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem)
- : ThreadState(-1, _thread_num, _mem),
+ OzoneThreadState(FullCPU *_cpu, int _thread_num)
+ : ThreadState(-1, _thread_num),
inSyscall(0), trapPending(0)
{
memset(®s, 0, sizeof(TheISA::RegFile));
memset(®s, 0, sizeof(TheISA::RegFile));
}
- OzoneThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
+ OzoneThreadState(FullCPU *_cpu, int _thread_num,
int _asid)
- : ThreadState(-1, _thread_num, _mem, NULL, _asid),
+ : ThreadState(-1, _thread_num, NULL, NULL, _asid),
cpu(_cpu), inSyscall(0), trapPending(0)
{
memset(®s, 0, sizeof(TheISA::RegFile));
Kernel::Statistics *getKernelStats() { return kernelStats; }
+ FunctionalPort *getPhysPort() { return physPort; }
+
void setPhysPort(FunctionalPort *port) { physPort = port; }
+ VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return virtPort; }
+
void setVirtPort(VirtualPort *port) { virtPort = port; }
#else
Process *getProcessPtr() { return process; }
// Index of hardware thread context on the CPU that this represents.
int tid;
+ public:
/** Last time activate was called on this thread. */
Tick lastActivate;
*/
TheISA::MachInst inst;
+ public:
/**
* Temporary storage to pass the source address from copy_load to
* copy_store.
*/
Addr copySrcPhysAddr;
- public:
/*
* number of executed instructions, for matching with syscall trace
* points in EIO files.
projects / gem5.git / commitdiff