Add in operand which holds the condition code bits of the flag register.

--HG--
extra : convert_revision : 416052f41fccc8286b3bdbe8d559512a761224f2

diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index b2ac17d667d7804c8a05c1f7aab00ea31a0c97df..83df583ea0b02ddf71ebd49287546bf577b4ab55 100644 (file)
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -103,5 +103,6 @@ def operands {{
         'Index':         ('IntReg', 'uqw', 'index', 'IsInteger', 5),
         'Data':          ('IntReg', 'uqw', 'data', 'IsInteger', 6),
         'RIP':           ('NPC', 'uqw', None, (None, None, 'IsControl'), 10),
+        'ccFlagBits':       ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
         'Mem':           ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
 }};