back.rtlil: always initialize the entire memory.

This avoids reading 'x from the memory in simulation. In general,
FPGA memories can only be initialized in block granularity, and
zero-initializing is cheap, so this is not a significant issue with
resource consumption.

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index c2b8809da4ff0364e918cf92c546a8b0033f0fc9..6fff6d25114f39df6629a5889402fa0ed55b8502 100644 (file)
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -624,7 +624,11 @@ def convert_fragment(builder, fragment, name, top):
                             memories[memory] = module.memory(width=memory.width, size=memory.depth,
                                                              name=memory.name)
                             addr_bits = bits_for(memory.depth)
-                            for addr, data in enumerate(memory.init):
+                            for addr in range(memory.depth):
+                                if addr < len(memory.init):
+                                    data = memory.init[addr]
+                                else:
+                                    data = 0
                                 module.cell("$meminit", ports={
                                     "\\ADDR": rhs_compiler(ast.Const(addr, addr_bits)),
                                     "\\DATA": rhs_compiler(ast.Const(data, memory.width)),