DONE;
})
+(define_insn_and_split "*anddi3_doubleword"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
+ (and:DI
+ (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm")))
+ (clobber (reg:CC FLAGS_REG))]
+ "!TARGET_64BIT && TARGET_STV && TARGET_SSE2
+ && ix86_binary_operator_ok (AND, DImode, operands)"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);
+ if (operands[2] == const0_rtx)
+ {
+ operands[1] = const0_rtx;
+ ix86_expand_move (SImode, &operands[0]);
+ }
+ else if (operands[2] != constm1_rtx)
+ ix86_expand_binary_operator (AND, SImode, &operands[0]);
+ else if (operands[5] == constm1_rtx)
+ emit_note (NOTE_INSN_DELETED);
+ if (operands[5] == const0_rtx)
+ {
+ operands[4] = const0_rtx;
+ ix86_expand_move (SImode, &operands[3]);
+ }
+ else if (operands[5] != constm1_rtx)
+ ix86_expand_binary_operator (AND, SImode, &operands[3]);
+ DONE;
+})
+
(define_insn "*anddi_1"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r,!k")
(and:DI
(const_string "*")))
(set_attr "mode" "SI,DI,DI,SI,DI")])
-(define_insn_and_split "*anddi3_doubleword"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
- (and:DI
- (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && TARGET_STV && TARGET_SSE2
- && ix86_binary_operator_ok (AND, DImode, operands)"
- "#"
- "&& reload_completed"
- [(const_int 0)]
-{
- split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);
- if (operands[2] == const0_rtx)
- {
- operands[1] = const0_rtx;
- ix86_expand_move (SImode, &operands[0]);
- }
- else if (operands[2] != constm1_rtx)
- ix86_expand_binary_operator (AND, SImode, &operands[0]);
- else if (operands[5] == constm1_rtx)
- emit_note (NOTE_INSN_DELETED);
- if (operands[5] == const0_rtx)
- {
- operands[4] = const0_rtx;
- ix86_expand_move (SImode, &operands[3]);
- }
- else if (operands[5] != constm1_rtx)
- ix86_expand_binary_operator (AND, SImode, &operands[3]);
- DONE;
-})
-
(define_insn "*andsi_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,Ya,!k")
(and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm,k")
""
"ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
-(define_insn "*<code><mode>_1"
- [(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,rm,k")
- (any_or:SWI48
- (match_operand:SWI48 1 "nonimmediate_operand" "%0,0,k")
- (match_operand:SWI48 2 "<general_operand>" "<g>,r<i>,k")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "@
- <logic>{<imodesuffix>}\t{%2, %0|%0, %2}
- <logic>{<imodesuffix>}\t{%2, %0|%0, %2}
- k<logic><mskmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "alu,alu,msklog")
- (set_attr "mode" "<MODE>")])
-
(define_insn_and_split "*<code>di3_doubleword"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
(any_or:DI
DONE;
})
-(define_insn_and_split "*andndi3_doubleword"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (and:DI
- (not:DI (match_operand:DI 1 "register_operand" "r"))
- (match_operand:DI 2 "nonimmediate_operand" "rm")))
+(define_insn "*<code><mode>_1"
+ [(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,rm,k")
+ (any_or:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand" "%0,0,k")
+ (match_operand:SWI48 2 "<general_operand>" "<g>,r<i>,k")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_BMI && !TARGET_64BIT && TARGET_STV && TARGET_SSE"
- "#"
- "&& reload_completed"
- [(parallel [(set (match_dup 0)
- (and:SI (not:SI (match_dup 1)) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))])
- (parallel [(set (match_dup 3)
- (and:SI (not:SI (match_dup 4)) (match_dup 5)))
- (clobber (reg:CC FLAGS_REG))])]
- "split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);")
+ "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "@
+ <logic>{<imodesuffix>}\t{%2, %0|%0, %2}
+ <logic>{<imodesuffix>}\t{%2, %0|%0, %2}
+ k<logic><mskmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "type" "alu,alu,msklog")
+ (set_attr "mode" "<MODE>")])
(define_insn "*<code>hi_1"
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,rm,!k")
(any_or:HI
(match_operand:HI 1 "nonimmediate_operand" "%0,0,k")
- (match_operand:HI 2 "general_operand" "<g>,r<i>,k")))
+ (match_operand:HI 2 "general_operand" "rmn,rn,k")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, HImode, operands)"
"@
(set_attr "mode" "<MODE>")])
;; BMI instructions.
+
+(define_insn_and_split "*andndi3_doubleword"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (and:DI
+ (not:DI (match_operand:DI 1 "register_operand" "r"))
+ (match_operand:DI 2 "nonimmediate_operand" "rm")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_BMI && !TARGET_64BIT && TARGET_STV && TARGET_SSE"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (and:SI (not:SI (match_dup 1)) (match_dup 2)))
+ (clobber (reg:CC FLAGS_REG))])
+ (parallel [(set (match_dup 3)
+ (and:SI (not:SI (match_dup 4)) (match_dup 5)))
+ (clobber (reg:CC FLAGS_REG))])]
+ "split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);")
+
(define_insn "*bmi_andn_<mode>"
[(set (match_operand:SWI48 0 "register_operand" "=r,r")
(and:SWI48