*configptr_ptr = config_addr;
configptr_ptr.copyOut(xc->mem);
+ // Register this as a valid address range with the process
+ process->nxm_start = base_addr;
+ process->nxm_end = cur_addr;
+
return 0;
}
if env['SYSTEM'] == 'Simple':
from SimpleConfig import *
- BaseCPU.workload = Super.workload
+ BaseCPU.workload = parent.workload
SimpleStandAlone.cpu = [ CPU() for i in xrange(int(env['NP'])) ]
root = SimpleStandAlone
elif env['SYSTEM'] == 'Detailed':
from DetailedConfig import *
- BaseCPU.workload = Super.workload
+ BaseCPU.workload = parent.workload
DetailedStandAlone.cpu = [ DetailedCPU() for i in xrange(int(env['NP'])) ]
root = DetailedStandAlone
else:
Fault
SimpleCPU::read(Addr addr, T &data, unsigned flags)
{
- if (status() == DcacheMissStall) {
+ if (status() == DcacheMissStall || status() == DcacheMissSwitch) {
Fault fault = xc->read(memReq,data);
if (traceData) {
traceData->setAddr(addr);
- if (fault == No_Fault)
- traceData->setData(data);
}
return fault;
}
// do functional access
fault = xc->read(memReq, data);
- if (traceData) {
- traceData->setAddr(addr);
- if (fault == No_Fault)
- traceData->setData(data);
- }
}
} else if(fault == No_Fault) {
// do functional access
fault = xc->read(memReq, data);
- if (traceData) {
- traceData->setAddr(addr);
- if (fault == No_Fault)
- traceData->setData(data);
- }
}
if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
Fault
SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
- if (traceData) {
- traceData->setAddr(addr);
- traceData->setData(data);
- }
-
memReq->reset(addr, sizeof(T), flags);
// translate to physical address
case DcacheMissStall:
if (memReq->cmd.isRead()) {
curStaticInst->execute(this,traceData);
+ if (traceData)
+ traceData->finalize();
}
dcacheStallCycles += curTick - lastDcacheStall;
_status = Running;
case DcacheMissSwitch:
if (memReq->cmd.isRead()) {
curStaticInst->execute(this,traceData);
+ if (traceData)
+ traceData->finalize();
}
_status = SwitchedOut;
sampler->signalSwitched();
comLoadEventQueue[0]->serviceEvents(numLoad);
}
- if (traceData)
+ // If we have a dcache miss, then we can't finialize the instruction
+ // trace yet because we want to populate it with the data later
+ if (traceData &&
+ !(status() == DcacheMissStall && memReq->cmd.isRead())) {
traceData->finalize();
+ }
traceFunctions(xc->regs.pc);
DPRINTF(Ethernet, "ID is %d\n", ip->id());
TcpPtr tcp(ip);
if (tcp) {
- DPRINTF(Ethernet, "Src Port=%d, Dest Port=%d\n",
- tcp->sport(), tcp->dport());
+ DPRINTF(Ethernet,
+ "Src Port=%d, Dest Port=%d, Seq=%d, Ack=%d\n",
+ tcp->sport(), tcp->dport(), tcp->seq(),
+ tcp->ack());
}
}
}
DPRINTF(Ethernet, "ID is %d\n", ip->id());
TcpPtr tcp(ip);
if (tcp) {
- DPRINTF(Ethernet, "Src Port=%d, Dest Port=%d\n",
- tcp->sport(), tcp->dport());
+ DPRINTF(Ethernet,
+ "Src Port=%d, Dest Port=%d, Seq=%d, Ack=%d\n",
+ tcp->sport(), tcp->dport(), tcp->seq(), tcp->ack());
}
}
}
#endif
- DDUMP(Ethernet, txFifo.front()->data, txFifo.front()->length);
+ DDUMP(EthernetData, txFifo.front()->data, txFifo.front()->length);
txBytes += txFifo.front()->length;
txPackets++;
}
if (rxFifo.avail() < packet->length) {
- DPRINTF(Ethernet,
- "packet will not fit in receive buffer...packet dropped\n");
+#if TRACING_ON
+ IpPtr ip(packet);
+ TcpPtr tcp(ip);
+ if (ip) {
+ DPRINTF(Ethernet,
+ "packet won't fit in receive buffer...pkt ID %d dropped\n",
+ ip->id());
+ if (tcp) {
+ DPRINTF(Ethernet, "Seq=%d\n", tcp->seq());
+ }
+ }
+#endif
droppedPackets++;
devIntrPost(ISR_RXORN);
return false;
from __future__ import generators
import os, re, sys, types, inspect
+from m5 import panic
from convert import *
noDot = False
#####################################################################
class Proxy(object):
- def __init__(self, path = ()):
+ def __init__(self, path):
self._object = None
- self._path = path
+ if path == 'any':
+ self._path = None
+ else:
+ # path is a list of (attr,index) tuples
+ self._path = [(path,None)]
+ self._index = None
+ self._multiplier = None
def __getattr__(self, attr):
- return Proxy(self._path + (attr, ))
+ if attr == '__bases__':
+ return super(Proxy, self).__getattr__(self, attr)
+ self._path.append((attr,None))
+ return self
def __setattr__(self, attr, value):
if not attr.startswith('_'):
raise AttributeError, 'cannot set attribute %s' % attr
super(Proxy, self).__setattr__(attr, value)
- def _convert(self):
- obj = self._object
- for attr in self._path:
- obj = obj.__getattribute__(attr)
+ # support indexing on proxies (e.g., parent.cpu[0])
+ def __getitem__(self, key):
+ if not isinstance(key, int):
+ raise TypeError, "Proxy object requires integer index"
+ if self._path == None:
+ raise IndexError, "Index applied to 'any' proxy"
+ # replace index portion of last path element with new index
+ self._path[-1] = (self._path[-1][0], key)
+ return self
+
+ # support multiplying proxies by constants
+ def __mul__(self, other):
+ if not isinstance(other, int):
+ raise TypeError, "Proxy multiplier must be integer"
+ if self._multiplier == None:
+ self._multiplier = other
+ else:
+ # support chained multipliers
+ self._multiplier *= other
+ return self
+
+ def _mulcheck(self, result):
+ if self._multiplier == None:
+ return result
+ if not isinstance(result, int):
+ raise TypeError, "Proxy with multiplier resolves to " \
+ "non-integer value"
+ return result * self._multiplier
+
+ def unproxy(self, base, ptype):
+ obj = base
+ done = False
+ while not done:
+ if obj is None:
+ raise AttributeError, \
+ 'Parent of %s type %s not found at path %s' \
+ % (base.name, ptype, self._path)
+ result, done = obj.find(ptype, self._path)
+ obj = obj.parent
+
+ if isinstance(result, Proxy):
+ result = result.unproxy(obj, ptype)
+
+ return self._mulcheck(result)
+
+ def getindex(obj, index):
+ if index == None:
+ return obj
+ try:
+ obj = obj[index]
+ except TypeError:
+ if index != 0:
+ raise
+ # if index is 0 and item is not subscriptable, just
+ # use item itself (so cpu[0] works on uniprocessors)
return obj
+ getindex = staticmethod(getindex)
+
+class ProxyFactory(object):
+ def __getattr__(self, attr):
+ return Proxy(attr)
-Super = Proxy()
+# global object for handling parent.foo proxies
+parent = ProxyFactory()
def isSubClass(value, cls):
try:
if issubclass(child.realtype, realtype):
if obj is not None:
raise AttributeError, \
- 'Super matched more than one: %s %s' % \
+ 'parent.any matched more than one: %s %s' % \
(obj.path, child.path)
obj = child
return obj, obj is not None
try:
obj = self
- for node in path[:-1]:
- obj = obj.child_names[node]
+ for (node,index) in path[:-1]:
+ if obj.child_names.has_key(node):
+ obj = obj.child_names[node]
+ else:
+ obj = obj.top_child_names[node]
+ obj = Proxy.getindex(obj, index)
- last = path[-1]
+ (last,index) = path[-1]
if obj.child_names.has_key(last):
value = obj.child_names[last]
- if issubclass(value.realtype, realtype):
- return value, True
+ return Proxy.getindex(value, index), True
+ elif obj.top_child_names.has_key(last):
+ value = obj.top_child_names[last]
+ return Proxy.getindex(value, index), True
elif obj.param_names.has_key(last):
value = obj.param_names[last]
realtype._convert(value.value)
- return value.value, True
+ return Proxy.getindex(value.value, index), True
except KeyError:
pass
return None, False
- def unproxy(self, ptype, value):
- if not isinstance(value, Proxy):
- return value
-
- if value is None:
- raise AttributeError, 'Error while fixing up %s' % self.path
-
- obj = self
- done = False
- while not done:
- if obj is None:
- raise AttributeError, \
- 'Parent of %s type %s not found at path %s' \
- % (self.name, ptype, value._path)
- found, done = obj.find(ptype, value._path)
- if isinstance(found, Proxy):
- done = False
- obj = obj.parent
-
- return found
+ def unproxy(self, param, ptype):
+ if not isinstance(param, Proxy):
+ return param
+ return param.unproxy(self, ptype)
def fixup(self):
self.all[self.path] = self
try:
if isinstance(pval, (list, tuple)):
- param.value = [ self.unproxy(ptype, pv) for pv in pval ]
+ param.value = [ self.unproxy(pv, ptype) for pv in pval ]
else:
- param.value = self.unproxy(ptype, pval)
+ param.value = self.unproxy(pval, ptype)
except:
print 'Error while fixing up %s:%s' % (self.path, param.name)
raise
def __str__(self):
return str(self._getattr())
+ def __len__(self):
+ return len(self._getattr())
+
# Regular parameter.
class _Param(object):
def __init__(self, ptype, *args, **kwargs):
# 'from config import *' is invoked. Try to keep this reasonably
# short to avoid polluting other namespaces.
__all__ = ['ConfigNode', 'SimObject', 'ParamContext', 'Param', 'VectorParam',
- 'Super', 'Enum',
+ 'parent', 'Enum',
'Int', 'Unsigned', 'Int8', 'UInt8', 'Int16', 'UInt16',
'Int32', 'UInt32', 'Int64', 'UInt64',
'Counter', 'Addr', 'Tick', 'Percent',
simobj AlphaConsole(PioDevice):
type = 'AlphaConsole'
- cpu = Param.BaseCPU(Super, "Processor")
+ cpu = Param.BaseCPU(parent.any, "Processor")
disk = Param.SimpleDisk("Simple Disk")
num_cpus = Param.Int(1, "Number of CPUs")
- sim_console = Param.SimConsole(Super, "The Simulator Console")
- system = Param.BaseSystem(Super, "system object")
+ sim_console = Param.SimConsole(parent.any, "The Simulator Console")
+ system = Param.BaseSystem(parent.any, "system object")
dtb = Param.AlphaDTB("Data TLB")
itb = Param.AlphaITB("Instruction TLB")
mem = Param.FunctionalMemory("memory")
- system = Param.BaseSystem(Super, "system object")
+ system = Param.BaseSystem(parent.any, "system object")
else:
workload = VectorParam.Process("processes to run")
simobj BaseSystem(SimObject):
type = 'BaseSystem'
abstract = True
- memctrl = Param.MemoryController(Super, "memory controller")
- physmem = Param.PhysicalMemory(Super, "phsyical memory")
+ memctrl = Param.MemoryController(parent.any, "memory controller")
+ physmem = Param.PhysicalMemory(parent.any, "phsyical memory")
kernel = Param.String("file that contains the kernel code")
console = Param.String("file that contains the console code")
pal = Param.String("file that contains palcode")
type = 'PioDevice'
abstract = True
addr = Param.Addr("Device Address")
- mmu = Param.MemoryController(Super, "Memory Controller")
+ mmu = Param.MemoryController(parent.any, "Memory Controller")
io_bus = Param.Bus(NULL, "The IO Bus to attach to")
pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles")
simobj PioDevice(FooPioDevice):
type = 'PioDevice'
abstract = True
- platform = Param.Platform(Super, "Platform")
+ platform = Param.Platform(parent.any, "Platform")
simobj DmaDevice(PioDevice):
type = 'DmaDevice'
intr_delay = Param.Tick(0, "Interrupt Delay in microseconds")
payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
- physmem = Param.PhysicalMemory(Super, "Physical Memory")
- tlaser = Param.Turbolaser(Super, "Turbolaser")
+ physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
+ tlaser = Param.Turbolaser(parent.any, "Turbolaser")
simobj NSGigE(PciDevice):
type = 'NSGigE'
intr_delay = Param.Tick(0, "Interrupt Delay in microseconds")
payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
- physmem = Param.PhysicalMemory(Super, "Physical Memory")
+ physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
simobj EtherDevInt(EtherInt):
type = 'EtherDevInt'
delay = Param.Tick(1, "Fixed disk delay in microseconds")
driveID = Param.IdeID('master', "Drive ID")
image = Param.DiskImage("Disk image")
- physmem = Param.PhysicalMemory(Super, "Physical memory")
+ physmem = Param.PhysicalMemory(parent.any, "Physical memory")
simobj IdeController(PciDevice):
type = 'IdeController'
simobj IntrControl(SimObject):
type = 'IntrControl'
- cpu = Param.BaseCPU(Super, "the cpu")
+ cpu = Param.BaseCPU(parent.any, "the cpu")
pci_bus = Param.Int("PCI bus")
pci_dev = Param.Int("PCI device number")
pci_func = Param.Int("PCI function code")
- configdata = Param.PciConfigData(Super, "PCI Config data")
- configspace = Param.PciConfigAll(Super, "PCI Configspace")
+ configdata = Param.PciConfigData(parent.any, "PCI Config data")
+ configspace = Param.PciConfigAll(parent.any, "PCI Configspace")
type = 'PhysicalMemory'
range = Param.AddrRange("Device Address")
file = Param.String('', "memory mapped file")
- mmu = Param.MemoryController(Super, "Memory Controller")
+ mmu = Param.MemoryController(parent.any, "Memory Controller")
type = 'Platform'
abstract = True
interrupt_frequency = Param.Tick(1200, "frequency of interrupts")
- intrctrl = Param.IntrControl(Super, "interrupt controller")
+ intrctrl = Param.IntrControl(parent.any, "interrupt controller")
simobj SimConsole(SimObject):
type = 'SimConsole'
append_name = Param.Bool(True, "append name() to filename")
- intr_control = Param.IntrControl(Super, "interrupt controller")
+ intr_control = Param.IntrControl(parent.any, "interrupt controller")
listener = Param.ConsoleListener("console listener")
number = Param.Int(0, "console number")
output = Param.String('console', "file to dump output to")
simobj SimpleDisk(SimObject):
type = 'SimpleDisk'
disk = Param.DiskImage("Disk Image")
- physmem = Param.PhysicalMemory(Super, "Physical Memory")
+ physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
simobj Tsunami(Platform):
type = 'Tsunami'
pciconfig = Param.PciConfigAll("PCI configuration")
- system = Param.BaseSystem(Super, "system")
+ system = Param.BaseSystem(parent.any, "system")
interrupt_frequency = Param.Int(1024, "frequency of interrupts")
simobj TsunamiCChip(FooPioDevice):
type = 'TsunamiCChip'
- tsunami = Param.Tsunami(Super, "Tsunami")
+ tsunami = Param.Tsunami(parent.any, "Tsunami")
simobj TsunamiFake(FooPioDevice):
type = 'TsunamiFake'
type = 'TsunamiIO'
time = Param.UInt64(1136073600,
"System time to use (0 for actual time, default is 1/1/06)")
- tsunami = Param.Tsunami(Super, "Tsunami")
+ tsunami = Param.Tsunami(parent.any, "Tsunami")
simobj TsunamiPChip(FooPioDevice):
type = 'TsunamiPChip'
- tsunami = Param.Tsunami(Super, "Tsunami")
+ tsunami = Param.Tsunami(parent.any, "Tsunami")
simobj Uart(PioDevice):
type = 'Uart'
- console = Param.SimConsole(Super, "The console")
+ console = Param.SimConsole(parent.any, "The console")
size = Param.Addr(0x8, "Device size")
return other / self.convert(other)
+ # __getitem__ uses dict.get() to return 'False' if the key is not
+ # found (rather than raising KeyError). Note that this does *not*
+ # set the key's value to 'False' in the dict, so that even after
+ # we call env['foo'] we still get a meaningful answer from "'foo'
+ # in env" (which calls dict.__contains__, which we do not
+ # override).
def __getitem__(self, key):
return self.Proxy(dict.get(self, key, 'False'))
}
mmap_start = mmap_end = 0;
+ nxm_start = nxm_end = 0;
// other parameters will be initialized when the program is loaded
}
Addr mmap_start;
Addr mmap_end;
+ // Base of region for nxm data
+ Addr nxm_start;
+ Addr nxm_end;
+
std::string prog_fname; // file name
Addr prog_entry; // entry point (initial PC)
bool validDataAddr(Addr addr)
{
return ((data_base <= addr && addr < brk_point) ||
- ((stack_base - 16*1024*1024) <= addr && addr < stack_base) ||
+ (next_thread_stack_base <= addr && addr < stack_base) ||
(text_base <= addr && addr < (text_base + text_size)) ||
- (mmap_start <= addr && addr < mmap_end));
+ (mmap_start <= addr && addr < mmap_end) ||
+ (nxm_start <= addr && addr < nxm_end));
}
virtual void syscall(ExecContext *xc) = 0;
// user didn't give an address... pick one from our "mmap region"
start = p->mmap_end;
p->mmap_end += RoundUp<Addr>(length, VMPageSize);
+ if (p->nxm_start != 0) {
+ //If we have an nxm space, make sure we haven't colided
+ assert(p->mmap_end < p->nxm_start);
+ }
}
if (!(flags & OS::TGT_MAP_ANONYMOUS)) {
projects / gem5.git / commitdiff