pytholite: support signed registers

diff --git a/migen/pytholite/compiler.py b/migen/pytholite/compiler.py
index c9fcb218764f76f8726ca8ded2c3d19e501c5647..d25fe45579dc7fc9664fc39dd2bb873c67346834 100644 (file)
--- a/migen/pytholite/compiler.py
+++ b/migen/pytholite/compiler.py
@@ -96,12 +96,12 @@ class _Compiler:
                if callee == transel.Register:
                        if len(value.args) != 1:
                                raise TypeError("Register() takes exactly 1 argument")
-                       nbits = ast.literal_eval(value.args[0])
+                       bits_sign = ast.literal_eval(value.args[0])
                        if isinstance(node.targets[0], ast.Name):
                                targetname = node.targets[0].id
                        else:
                                targetname = "unk"
-                       reg = ImplRegister(targetname, nbits)
+                       reg = ImplRegister(targetname, bits_sign)
                        self.registers.append(reg)
                        for target in node.targets:
                                if isinstance(target, ast.Name):

diff --git a/migen/pytholite/reg.py b/migen/pytholite/reg.py
index 0f577fd38d15e6bf24e45da34eceb9f92ed57dc9..32bb348cd302cdcf6bd38b363ac21c90b9640dc2 100644 (file)
--- a/migen/pytholite/reg.py
+++ b/migen/pytholite/reg.py
@@ -24,9 +24,9 @@ class LowerAbstractLoad(fhdl.NodeTransformer):
                        return node
 
 class ImplRegister:
-       def __init__(self, name, nbits):
+       def __init__(self, name, bits_sign):
                self.name = name
-               self.storage = Signal(nbits, name=self.name)
+               self.storage = Signal(bits_sign, name=self.name)
                self.source_encoding = {}
                self.id_to_source = {}
                self.finalized = False

diff --git a/migen/pytholite/transel.py b/migen/pytholite/transel.py
index d46b1998d8c42d6aea7fa753b1c91cbac68827e7..123c2d85a146d4f370e11469527359117143f944 100644 (file)
--- a/migen/pytholite/transel.py
+++ b/migen/pytholite/transel.py
@@ -8,12 +8,21 @@ def bitslice(val, low, up=None):
        return (val & mask) >> low
 
 class Register:
-       def __init__(self, nbits):
-               self._nbits = nbits
+       def __init__(self, bits_sign):
+               if isinstance(bits_sign, tuple):
+                       self._nbits, self._signed = bits_sign
+               else:
+                       self._nbits, self._signed = bits_sign, False
                self._val = 0
        
        def _set_store(self, val):
-               self._val = val & (2**self._nbits - 1)
+               if self._signed:
+                       sbw = 2**(self._nbits - 1)
+                       self._val = val & (sbw - 1)
+                       if val & sbw:
+                               self._val -= sbw
+               else:
+                       self._val = val & (2**self._nbits - 1)
        store = property(None, _set_store)
 
        def __nonzero__(self):