X86: Implement a locking version of SUB.

diff --git a/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py
index 10c06efb609224760ef8bc3a875202c13c08a9ef..c8a2d1d1c55d959c06da215645ad33bbaab3a388 100644 (file)
--- a/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py
+++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py
@@ -183,6 +183,23 @@ def macroop SUB_P_I
     st t1, seg, riprel, disp
 };
 
+def macroop SUB_LOCKED_M_I
+{
+    limm t2, imm
+    ldstl t1, seg, sib, disp
+    sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
+    stul t1, seg, sib, disp
+};
+
+def macroop SUB_LOCKED_P_I
+{
+    rdip t7
+    limm t2, imm
+    ldstl t1, seg, riprel, disp
+    sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
+    stul t1, seg, riprel, disp
+};
+
 def macroop SUB_M_R
 {
     ldst t1, seg, sib, disp
@@ -198,6 +215,21 @@ def macroop SUB_P_R
     st t1, seg, riprel, disp
 };
 
+def macroop SUB_LOCKED_M_R
+{
+    ldstl t1, seg, sib, disp
+    sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
+    stul t1, seg, sib, disp
+};
+
+def macroop SUB_LOCKED_P_R
+{
+    rdip t7
+    ldstl t1, seg, riprel, disp
+    sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
+    stul t1, seg, riprel, disp
+};
+
 def macroop ADC_R_R
 {
     adc reg, reg, regm, flags=(OF,SF,ZF,AF,PF,CF)