* Makefile.am (ALL_MACHINES): Add cpu-epiphany.lo .
(ALL_MACHINES_CFILES): Add cpu-epiphany.c .
(BFD32_BACKENDS): Add elf32-epiphany.lo .
(BFD32_BACKENDS_CFILES): Add elf32-epiphany.c .
* Makefile.in, bfd-in2.h, configure, libbfd.h: Regenerate.
* archures.c (bfd_arch_epiphany): Add.
(bfd_mach_epiphany16, bfd_mach_epiphany32): Define.
(bfd_epiphany_arch): Declare.
(bfd_archures_list): Add &bfd_epiphany_arch.
* config.bfd (epiphany-*-elf): New target case.
* configure.in (bfd_elf32_epiphany_vec): New target vector case.
* reloc.c (BFD_RELOC_EPIPHANY_SIMM8): New relocation.
(BFD_RELOC_EPIPHANY_SIMM24, BFD_RELOC_EPIPHANY_HIGH): Likewise.
(BFD_RELOC_EPIPHANY_LOW, BFD_RELOC_EPIPHANY_SIMM11): Likewise.
(BFD_RELOC_EPIPHANY_IMM11, BFD_RELOC_EPIPHANY_IMM8): Likewise.
* targets.c (bfd_elf32_epiphany_vec): Declare.
(_bfd_target_vector): Add bfd_elf32_epiphany_vec.
* po/SRC-POTFILES.in, po/bfd.pot: Regenerate.
* cpu-epiphany.c, elf32-epiphany.c: New files.
binutils:
* readelf.c (include "elf/epiphany.h")
(guess_is_rela, dump_relocation): Handle EM_ADAPTEVA_EPIPHANY.
(get_machine_name, is_32bit_abs_reloc, is_32bit_pcrel_reloc): Likewise.
(is_16bit_abs_reloc, is_none_reloc): Likewise.
* po/binutils.pot: Regenerate.
cpu:
* cpu/epiphany.cpu, cpu/epiphany.opc: New files.
gas:
* NEWS: Mention addition of Adapteva Epiphany support.
* config/tc-epiphany.c, config/tc-epiphany.h: New files.
* Makefile.am (TARGET_CPU_CFILES): Add config/tc-epiphany.c .
(TARGET_CPU_HFILES): Add config/tc-epiphany.h .
* Makefile.in, configure, doc/Makefile.in, po/POTFILES.in: Regenerate.
* configure.in: Also set using_cgen for epiphany.
* configure.tgt: Handle epiphany.
* doc/Makefile.am (CPU_DOCS): Add c-epiphany.texi .
* doc/all.texi: Set EPIPHANY.
* doc/as.texinfo: Add EPIPHANY-specific text.
* doc/c-epiphany.texi: New file.
* po/gas.pot: Regenerate.
gas/testsuite:
* gas/epiphany: New directory.
include:
* dis-asm.h (print_insn_epiphany): Declare.
* elf/epiphany.h: New file.
* elf/common.h (EM_ADAPTEVA_EPIPHANY): Define.
ld:
* NEWS: Mention addition of Adapteva Epiphany support.
* Makefile.am (ALL_EMULATION_SOURCES): Add eelf32epiphany.c .
(eelf32epiphany.c): New rule.
* Makefile.in: Regenerate.
* configure.tgt: Handle epiphany-*-elf.
* po/ld.pot: Regenerate.
* testsuite/ld-srec/srec.exp: xfail epiphany.
* emulparams/elf32epiphany.sh: New file.
opcodes:
* Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
(TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c,
epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
(CLEANFILES): Add stamp-epiphany.
(EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it.
(stamp-epiphany): New rule.
* Makefile.in, configure, po/POTFILES.in, po/opcodes.pot: Regenerate.
* configure.in: Handle bfd_epiphany_arch.
* disassemble.c (ARCH_epiphany): Define.
(disassembler): Handle bfd_arch_epiphany.
* epiphany-asm.c, epiphany-desc.c, epiphany-desc.h: New files.
* epiphany-dis.c, epiphany-ibld.c, epiphany-opc.c: Likewise.
* epiphany-opc.h: Likewise.
+2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
+
+ * Makefile.am (ALL_MACHINES): Add cpu-epiphany.lo.
+ (ALL_MACHINES_CFILES): Add cpu-epiphany.c.
+ (BFD32_BACKENDS): Add elf32-epiphany.lo.
+ (BFD32_BACKENDS_CFILES): Add elf32-epiphany.c.
+ * archures.c (bfd_arch_epiphany): Add.
+ (bfd_mach_epiphany16, bfd_mach_epiphany32): Define.
+ (bfd_epiphany_arch): Declare.
+ (bfd_archures_list): Add &bfd_epiphany_arch.
+ * config.bfd (epiphany-*-elf): New target case.
+ * configure.in (bfd_elf32_epiphany_vec): New target vector case.
+ * reloc.c (BFD_RELOC_EPIPHANY_SIMM8): New relocation.
+ (BFD_RELOC_EPIPHANY_SIMM24, BFD_RELOC_EPIPHANY_HIGH): Likewise.
+ (BFD_RELOC_EPIPHANY_LOW, BFD_RELOC_EPIPHANY_SIMM11): Likewise.
+ (BFD_RELOC_EPIPHANY_IMM11, BFD_RELOC_EPIPHANY_IMM8): Likewise.
+ * targets.c (bfd_elf32_epiphany_vec): Declare.
+ (_bfd_target_vector): Add bfd_elf32_epiphany_vec.
+ * Makefile.in: Regenerate.
+ * bfd-in2.h: Regenerate.
+ * configure: Regenerate.
+ * libbfd.h: Regenerate.
+ * po/SRC-POTFILES.in: Regenerate.
+ * po/bfd.pot: Regenerate.
+ * cpu-epiphany.c: New file.
+ * elf32-epiphany.c: New file.
+
2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
* elfxx-mips.c (_bfd_mips_elf_symbol_processing): Remove
cpu-d10v.lo \
cpu-d30v.lo \
cpu-dlx.lo \
+ cpu-epiphany.lo \
cpu-fr30.lo \
cpu-frv.lo \
cpu-h8300.lo \
cpu-d10v.c \
cpu-d30v.c \
cpu-dlx.c \
+ cpu-epiphany.c \
cpu-fr30.c \
cpu-frv.c \
cpu-h8300.c \
elf32-d10v.lo \
elf32-d30v.lo \
elf32-dlx.lo \
+ elf32-epiphany.lo \
elf32-fr30.lo \
elf32-frv.lo \
elf32-gen.lo \
elf32-d10v.c \
elf32-d30v.c \
elf32-dlx.c \
+ elf32-epiphany.c \
elf32-fr30.c \
elf32-frv.c \
elf32-gen.c \
cpu-d10v.lo \
cpu-d30v.lo \
cpu-dlx.lo \
+ cpu-epiphany.lo \
cpu-fr30.lo \
cpu-frv.lo \
cpu-h8300.lo \
cpu-d10v.c \
cpu-d30v.c \
cpu-dlx.c \
+ cpu-epiphany.c \
cpu-fr30.c \
cpu-frv.c \
cpu-h8300.c \
elf32-d10v.lo \
elf32-d30v.lo \
elf32-dlx.lo \
+ elf32-epiphany.lo \
elf32-fr30.lo \
elf32-frv.lo \
elf32-gen.lo \
elf32-d10v.c \
elf32-d30v.c \
elf32-dlx.c \
+ elf32-epiphany.c \
elf32-fr30.c \
elf32-frv.c \
elf32-gen.c \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-d10v.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-d30v.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-dlx.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-epiphany.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-fr30.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-frv.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-h8300.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-d10v.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-d30v.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-dlx.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-epiphany.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-fr30.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-frv.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-gen.Plo@am__quote@
. bfd_arch_iq2000, {* Vitesse IQ2000. *}
.#define bfd_mach_iq2000 1
.#define bfd_mach_iq10 2
+. bfd_arch_epiphany, {* Adapteva EPIPHANY *}
+.#define bfd_mach_epiphany16 1
+.#define bfd_mach_epiphany32 2
. bfd_arch_mt,
.#define bfd_mach_ms1 1
.#define bfd_mach_mrisc2 2
extern const bfd_arch_info_type bfd_d10v_arch;
extern const bfd_arch_info_type bfd_d30v_arch;
extern const bfd_arch_info_type bfd_dlx_arch;
+extern const bfd_arch_info_type bfd_epiphany_arch;
extern const bfd_arch_info_type bfd_fr30_arch;
extern const bfd_arch_info_type bfd_frv_arch;
extern const bfd_arch_info_type bfd_h8300_arch;
&bfd_d10v_arch,
&bfd_d30v_arch,
&bfd_dlx_arch,
+ &bfd_epiphany_arch,
&bfd_fr30_arch,
&bfd_frv_arch,
&bfd_h8300_arch,
bfd_arch_iq2000, /* Vitesse IQ2000. */
#define bfd_mach_iq2000 1
#define bfd_mach_iq10 2
+ bfd_arch_epiphany, /* Adapteva EPIPHANY */
+#define bfd_mach_epiphany16 1
+#define bfd_mach_epiphany32 2
bfd_arch_mt,
#define bfd_mach_ms1 1
#define bfd_mach_mrisc2 2
BFD_RELOC_TILEGX_TLS_DTPMOD32,
BFD_RELOC_TILEGX_TLS_DTPOFF32,
BFD_RELOC_TILEGX_TLS_TPOFF32,
+
+/* Adapteva EPIPHANY - 8 bit signed pc-relative displacement */
+ BFD_RELOC_EPIPHANY_SIMM8,
+
+/* Adapteva EPIPHANY - 24 bit signed pc-relative displacement */
+ BFD_RELOC_EPIPHANY_SIMM24,
+
+/* Adapteva EPIPHANY - 16 most-significant bits of absolute address */
+ BFD_RELOC_EPIPHANY_HIGH,
+
+/* Adapteva EPIPHANY - 16 least-significant bits of absolute address */
+ BFD_RELOC_EPIPHANY_LOW,
+
+/* Adapteva EPIPHANY - 11 bit signed number - add/sub immediate */
+ BFD_RELOC_EPIPHANY_SIMM11,
+
+/* Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement) */
+ BFD_RELOC_EPIPHANY_IMM11,
+
+/* Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction. */
+ BFD_RELOC_EPIPHANY_IMM8,
BFD_RELOC_UNUSED };
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
reloc_howto_type *bfd_reloc_type_lookup
targ_defvec=bfd_elf32_d30v_vec
;;
+ epiphany-*-elf)
+ targ_defvec=bfd_elf32_epiphany_vec
+ ;;
+
fido-*-elf* )
targ_defvec=bfd_elf32_m68k_vec
targ_selvecs="m68kcoff_vec ieee_vec"
bfd_elf32_d10v_vec) tb="$tb elf32-d10v.lo elf32.lo $elf" ;;
bfd_elf32_d30v_vec) tb="$tb elf32-d30v.lo elf32.lo $elf" ;;
bfd_elf32_dlx_big_vec) tb="$tb elf32-dlx.lo elf32.lo $elf" ;;
+ bfd_elf32_epiphany_vec) tb="$tb elf32-epiphany.lo elf32.lo $elf" ;;
bfd_elf32_fr30_vec) tb="$tb elf32-fr30.lo elf32.lo $elf" ;;
bfd_elf32_frv_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;;
bfd_elf32_frvfdpic_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;;
bfd_elf32_d10v_vec) tb="$tb elf32-d10v.lo elf32.lo $elf" ;;
bfd_elf32_d30v_vec) tb="$tb elf32-d30v.lo elf32.lo $elf" ;;
bfd_elf32_dlx_big_vec) tb="$tb elf32-dlx.lo elf32.lo $elf" ;;
+ bfd_elf32_epiphany_vec) tb="$tb elf32-epiphany.lo elf32.lo $elf" ;;
bfd_elf32_fr30_vec) tb="$tb elf32-fr30.lo elf32.lo $elf" ;;
bfd_elf32_frv_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;;
bfd_elf32_frvfdpic_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;;
--- /dev/null
+/* BFD support for the Adapteva EPIPHANY processor.
+ Copyright 2011 Free Software Foundation, Inc.
+ Contributed by Embecosm on behalf of Adapteva, Inc.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libbfd.h"
+
+const bfd_arch_info_type bfd_epiphany16_arch =
+{
+ 32, /* Bits per word */
+ 32, /* Bits per address. */
+ 8, /* Bits per byte. */
+ bfd_arch_epiphany, /* Architecture. */
+ bfd_mach_epiphany16, /* Machine. */
+ "epiphany", /* Architecture name. */
+ "epiphany16", /* Machine name. */
+ 1, /* Section align power. */
+ FALSE, /* The default ? */
+ bfd_default_compatible, /* Architecture comparison fn. */
+ bfd_default_scan, /* String to architecture convert fn. */
+ NULL /* Next in list. */
+};
+
+const bfd_arch_info_type bfd_epiphany_arch =
+{
+ 32, /* Bits per word - not really true. */
+ 32, /* Bits per address. */
+ 8, /* Bits per byte. */
+ bfd_arch_epiphany, /* Architecture. */
+ bfd_mach_epiphany32, /* Machine. */
+ "epiphany", /* Architecture name. */
+ "epiphany32", /* Machine name. */
+ 2, /* Section align power. */
+ TRUE, /* The default ? */
+ bfd_default_compatible, /* Architecture comparison fn. */
+ bfd_default_scan, /* String to architecture convert fn. */
+ & bfd_epiphany16_arch /* Next in list. */
+};
--- /dev/null
+/* Adapteva epiphany specific support for 32-bit ELF
+ Copyright 2011
+ Free Software Foundation, Inc.
+ Contributed by Embecosm on behalf of Adapteva, Inc.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libbfd.h"
+#include "elf-bfd.h"
+#include "elf/epiphany.h"
+#include "libiberty.h"
+
+/* Struct used to pass miscellaneous paramaters which
+ helps to avoid overly long parameter lists. */
+struct misc
+{
+ Elf_Internal_Shdr * symtab_hdr;
+ Elf_Internal_Rela * irelbase;
+ bfd_byte * contents;
+ Elf_Internal_Sym * isymbuf;
+};
+
+struct epiphany_opcode
+{
+ unsigned short opcode;
+ unsigned short mask;
+};
+
+static bfd_boolean epiphany_relaxed = FALSE;
+
+/* Relocation tables. */
+static reloc_howto_type epiphany_elf_howto_table [] =
+{
+#define AHOW(t,rs,s,bs,pr,bp,co,name,sm,dm) \
+ HOWTO(t, /* type */ \
+ rs, /* rightshift */ \
+ s, /* size (0 = byte, 1 = short, 2 = long) */ \
+ bs, /* bitsize */ \
+ pr, /* pc_relative */ \
+ bp, /* bitpos */ \
+ co, /* complain_on_overflow */ \
+ bfd_elf_generic_reloc,/* special_function */ \
+ name, /* name */ \
+ FALSE, /* partial_inplace */ \
+ sm, /* src_mask */ \
+ dm, /* dst_mask */ \
+ pr) /* pcrel_offset */
+
+ /* This reloc does nothing. */
+ AHOW (R_EPIPHANY_NONE, 0, 0,32, FALSE, 0, complain_overflow_dont, "R_EPIPHANY_NONE", 0, 0),
+
+ /* 8 bit absolute (not likely) */
+ AHOW (R_EPIPHANY_8, 0, 0, 8, FALSE, 0, complain_overflow_bitfield, "R_EPIPHANY_8", 0x000000ff, 0x000000ff),
+ /* 16 bit absolute */
+ AHOW (R_EPIPHANY_16, 0, 1,16, FALSE, 0, complain_overflow_bitfield, "R_EPIPHANY_16", 0x0000ffff, 0x00ff1fe0),
+ /* A 32 bit absolute relocation. */
+ AHOW (R_EPIPHANY_32, 0, 2,32, FALSE, 0, complain_overflow_dont, "R_EPIPHANY_32", 0xffffffff, 0xffffffff),
+
+ /* 8 bit relative relocation */
+ HOWTO ( R_EPIPHANY_8_PCREL, 0, 0, 8, TRUE, 0, complain_overflow_bitfield, bfd_elf_generic_reloc, "R_EPIPHANY_8_PCREL", FALSE, 0x000000ff, 0x000000ff, FALSE),
+ /* 16 bit relative relocation */
+ HOWTO ( R_EPIPHANY_16_PCREL, 0, 1, 16, TRUE, 0, complain_overflow_bitfield, bfd_elf_generic_reloc, "R_EPIPHANY_8_PCREL", FALSE, 0x000000ff, 0x000000ff, FALSE),
+ /* 32 bit relative relocation */
+ HOWTO ( R_EPIPHANY_32_PCREL, 0, 2, 32, TRUE, 0, complain_overflow_bitfield, bfd_elf_generic_reloc, "R_EPIPHANY_8_PCREL", FALSE, 0x000000ff, 0x000000ff, FALSE),
+
+ /* 8 bit pc-relative relocation */
+ AHOW (R_EPIPHANY_SIMM8, 1, 0, 8, TRUE, 8, complain_overflow_signed, "R_EPIPHANY_SIMM8", 0x000000ff, 0x0000ff00),
+ /* 24 bit pc-relative relocation */
+ AHOW (R_EPIPHANY_SIMM24, 1, 2,24, TRUE, 8, complain_overflow_signed, "R_EPIPHANY_SIMM24", 0x00ffffff, 0xffffff00),
+
+ /* %HIGH(EA) */
+ AHOW (R_EPIPHANY_HIGH, 0, 2,16, FALSE, 0, complain_overflow_dont, "R_EPIPHANY_HIGH", 0x0ff01fe0, 0x0ff01fe0),
+
+ /* %LOW(EA) */
+ AHOW (R_EPIPHANY_LOW, 0, 2,16, FALSE, 0, complain_overflow_dont, "R_EPIPHANY_LOW", 0x0ff01fe0, 0x0ff01fe0),
+
+ /* simm11 */
+ AHOW (R_EPIPHANY_SIMM11, 0, 2,11, FALSE, 0, complain_overflow_bitfield, "R_EPIPHANY_SIMM11", 0x00ff0380, 0x00ff0380),
+ /* imm12 - sign-magnitude */
+ AHOW (R_EPIPHANY_IMM11, 0, 2,11, FALSE, 0, complain_overflow_bitfield, "R_EPIPHANY_IMM12", 0x00ff0380, 0x00ff0380),
+ /* imm8 */
+ AHOW (R_EPIPHANY_IMM8, 0, 1, 8, FALSE, 8, complain_overflow_signed, "R_EPIPHANY_IMM8", 0x0000ff00, 0x0000ff00)
+
+
+};
+#undef AHOW
+
+/* Map BFD reloc types to EPIPHANY ELF reloc types. */
+
+static reloc_howto_type *
+epiphany_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+ bfd_reloc_code_real_type code)
+{
+ /* Note that the epiphany_elf_howto_table is indxed by the R_
+ constants. Thus, the order that the howto records appear in the
+ table *must* match the order of the relocation types defined in
+ include/elf/epiphany.h. */
+
+ switch (code)
+ {
+ case BFD_RELOC_NONE:
+ return &epiphany_elf_howto_table[ (int) R_EPIPHANY_NONE];
+
+ case BFD_RELOC_EPIPHANY_SIMM8:
+ return &epiphany_elf_howto_table[ (int) R_EPIPHANY_SIMM8];
+ case BFD_RELOC_EPIPHANY_SIMM24:
+ return &epiphany_elf_howto_table[ (int) R_EPIPHANY_SIMM24];
+
+ case BFD_RELOC_8_PCREL:
+ return &epiphany_elf_howto_table[ (int) R_EPIPHANY_8_PCREL];
+ case BFD_RELOC_16_PCREL:
+ return &epiphany_elf_howto_table[ (int) R_EPIPHANY_16_PCREL];
+ case BFD_RELOC_32_PCREL:
+ return &epiphany_elf_howto_table[ (int) R_EPIPHANY_32_PCREL];
+
+ case BFD_RELOC_8:
+ return &epiphany_elf_howto_table[ (int) R_EPIPHANY_8];
+ case BFD_RELOC_16:
+ return &epiphany_elf_howto_table[ (int) R_EPIPHANY_16];
+ case BFD_RELOC_32:
+ return &epiphany_elf_howto_table[ (int) R_EPIPHANY_32];
+
+ case BFD_RELOC_EPIPHANY_HIGH:
+ return & epiphany_elf_howto_table[ (int) R_EPIPHANY_HIGH];
+ case BFD_RELOC_EPIPHANY_LOW:
+ return & epiphany_elf_howto_table[ (int) R_EPIPHANY_LOW];
+
+ case BFD_RELOC_EPIPHANY_SIMM11:
+ return & epiphany_elf_howto_table[ (int) R_EPIPHANY_SIMM11];
+ case BFD_RELOC_EPIPHANY_IMM11:
+ return & epiphany_elf_howto_table[ (int) R_EPIPHANY_IMM11];
+
+ case BFD_RELOC_EPIPHANY_IMM8:
+ return & epiphany_elf_howto_table[ (int) R_EPIPHANY_IMM8];
+
+ default:
+ /* Pacify gcc -Wall. */
+ return NULL;
+ }
+ return NULL;
+}
+
+static reloc_howto_type *
+epiphany_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE (epiphany_elf_howto_table); i++)
+ if (epiphany_elf_howto_table[i].name != NULL
+ && strcasecmp (epiphany_elf_howto_table[i].name, r_name) == 0)
+ return &epiphany_elf_howto_table[i];
+
+ return NULL;
+}
+
+#define PAGENO(ABSADDR) ((ABSADDR) & 0xFFFFC000)
+#define BASEADDR(SEC) ((SEC)->output_section->vma + (SEC)->output_offset)
+
+/* This function handles relaxing for the epiphany.
+ Dummy placeholder for future optimizations. */
+
+static bfd_boolean
+epiphany_elf_relax_section (bfd *abfd, asection *sec,
+ struct bfd_link_info *link_info,
+ bfd_boolean *again)
+{
+ Elf_Internal_Shdr *symtab_hdr;
+ Elf_Internal_Rela *internal_relocs;
+ bfd_byte *contents = NULL;
+ Elf_Internal_Sym *isymbuf = NULL;
+ static asection * first_section = NULL;
+ static unsigned long search_addr;
+ static unsigned long page_start = 0;
+ static unsigned long page_end = 0;
+ static unsigned int pass = 0;
+ static bfd_boolean new_pass = FALSE;
+ static bfd_boolean changed = FALSE;
+ struct misc misc ATTRIBUTE_UNUSED;
+ asection *stab;
+
+ /* Assume nothing changes. */
+ *again = FALSE;
+
+ if (first_section == NULL)
+ {
+ epiphany_relaxed = TRUE;
+ first_section = sec;
+ }
+
+ if (first_section == sec)
+ {
+ pass++;
+ new_pass = TRUE;
+ }
+
+ /* We don't have to do anything for a relocatable link,
+ if this section does not have relocs, or if this is
+ not a code section. */
+ if (link_info->relocatable
+ || (sec->flags & SEC_RELOC) == 0
+ || sec->reloc_count == 0
+ || (sec->flags & SEC_CODE) == 0)
+ return TRUE;
+
+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+
+ internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL,
+ link_info->keep_memory);
+ if (internal_relocs == NULL)
+ goto error_return;
+
+ /* Make sure the stac.rela stuff gets read in. */
+ stab = bfd_get_section_by_name (abfd, ".stab");
+
+ if (stab)
+ {
+ /* So stab does exits. */
+ Elf_Internal_Rela * irelbase ATTRIBUTE_UNUSED;
+
+ irelbase = _bfd_elf_link_read_relocs (abfd, stab, NULL, NULL,
+ link_info->keep_memory);
+ }
+
+ /* Get section contents cached copy if it exists. */
+ if (contents == NULL)
+ {
+ /* Get cached copy if it exists. */
+ if (elf_section_data (sec)->this_hdr.contents != NULL)
+ contents = elf_section_data (sec)->this_hdr.contents;
+ else
+ {
+ /* Go get them off disk. */
+ if (!bfd_malloc_and_get_section (abfd, sec, &contents))
+ goto error_return;
+ }
+ }
+
+ /* Read this BFD's symbols cached copy if it exists. */
+ if (isymbuf == NULL && symtab_hdr->sh_info != 0)
+ {
+ isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
+ if (isymbuf == NULL)
+ isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
+ symtab_hdr->sh_info, 0,
+ NULL, NULL, NULL);
+ if (isymbuf == NULL)
+ goto error_return;
+ }
+
+ misc.symtab_hdr = symtab_hdr;
+ misc.isymbuf = isymbuf;
+ misc.irelbase = internal_relocs;
+ misc.contents = contents;
+
+ /* This is where all the relaxation actually get done. */
+ if ((pass == 1) || (new_pass && !changed))
+ {
+ /* On the first pass we simply search for the lowest page that
+ we havn't relaxed yet. Note that the pass count is reset
+ each time a page is complete in order to move on to the next page.
+ If we can't find any more pages then we are finished. */
+ if (new_pass)
+ {
+ pass = 1;
+ new_pass = FALSE;
+ changed = TRUE; /* Pre-initialize to break out of pass 1. */
+ search_addr = 0xFFFFFFFF;
+ }
+
+ if ((BASEADDR (sec) + sec->size < search_addr)
+ && (BASEADDR (sec) + sec->size > page_end))
+ {
+ if (BASEADDR (sec) <= page_end)
+ search_addr = page_end + 1;
+ else
+ search_addr = BASEADDR (sec);
+
+ /* Found a page => more work to do. */
+ *again = TRUE;
+ }
+ }
+ else
+ {
+ if (new_pass)
+ {
+ new_pass = FALSE;
+ changed = FALSE;
+ page_start = PAGENO (search_addr);
+ page_end = page_start | 0x00003FFF;
+ }
+
+ /* Only process sections in range. */
+ if ((BASEADDR (sec) + sec->size >= page_start)
+ && (BASEADDR (sec) <= page_end))
+ {
+#if 0
+ if (!epiphany_elf_relax_section_page (abfd, sec, &changed, &misc,
+ page_start, page_end))
+#endif
+ return FALSE;
+ }
+ *again = TRUE;
+ }
+
+ /* Perform some house keeping after relaxing the section. */
+
+ if (isymbuf != NULL
+ && symtab_hdr->contents != (unsigned char *) isymbuf)
+ {
+ if (! link_info->keep_memory)
+ free (isymbuf);
+ else
+ symtab_hdr->contents = (unsigned char *) isymbuf;
+ }
+
+ if (contents != NULL
+ && elf_section_data (sec)->this_hdr.contents != contents)
+ {
+ if (! link_info->keep_memory)
+ free (contents);
+ else
+ {
+ /* Cache the section contents for elf_link_input_bfd. */
+ elf_section_data (sec)->this_hdr.contents = contents;
+ }
+ }
+
+ if (internal_relocs != NULL
+ && elf_section_data (sec)->relocs != internal_relocs)
+ free (internal_relocs);
+
+ return TRUE;
+
+ error_return:
+ if (isymbuf != NULL
+ && symtab_hdr->contents != (unsigned char *) isymbuf)
+ free (isymbuf);
+ if (contents != NULL
+ && elf_section_data (sec)->this_hdr.contents != contents)
+ free (contents);
+ if (internal_relocs != NULL
+ && elf_section_data (sec)->relocs != internal_relocs)
+ free (internal_relocs);
+ return FALSE;
+}
+
+/* Set the howto pointer for a EPIPHANY ELF reloc. */
+
+static void
+epiphany_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
+ arelent * cache_ptr,
+ Elf_Internal_Rela * dst)
+{
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+ cache_ptr->howto = & epiphany_elf_howto_table [r_type];
+}
+
+/* Perform a single relocation.
+ By default we use the standard BFD routines. */
+
+static bfd_reloc_status_type
+epiphany_final_link_relocate (reloc_howto_type * howto,
+ bfd * input_bfd,
+ asection * input_section,
+ bfd_byte * contents,
+ Elf_Internal_Rela * rel,
+ bfd_vma relocation)
+{
+ switch (howto->type)
+ {
+ /* Handle 16 bit immediates. */
+ case R_EPIPHANY_HIGH:
+ relocation += rel->r_addend;
+ relocation >>= 16;
+ goto common;
+
+ case R_EPIPHANY_LOW:
+ relocation += rel->r_addend;
+ common:
+ relocation = ((relocation & 0xff00L) << 12)
+ | ((relocation & 0x00ffL) << 5);
+ /* Sanity check the address. */
+ if (rel->r_offset > bfd_get_section_limit (input_bfd, input_section))
+ return bfd_reloc_outofrange;
+
+ return _bfd_relocate_contents (howto, input_bfd, relocation,
+ contents + rel->r_offset);
+
+ case R_EPIPHANY_SIMM11:
+ relocation += rel->r_addend;
+ /* Check signed overflow. */
+ if ((int)relocation > 1023 || (int)relocation < -1024)
+ return bfd_reloc_outofrange;
+ goto disp11;
+
+ case R_EPIPHANY_IMM11:
+ relocation += rel->r_addend;
+ if ((unsigned int) relocation > 0x7ff)
+ return bfd_reloc_outofrange;
+ disp11:
+ relocation = ((relocation & 7) << 5)
+ || ((relocation & 0x7f8 ) << 13);
+ return _bfd_relocate_contents (howto, input_bfd, relocation,
+ contents + rel->r_offset);
+
+ /* Pass others through. */
+ default:
+ break;
+ }
+
+ /* Only install relocation if above tests did not disqualify it. */
+ return _bfd_final_link_relocate (howto, input_bfd, input_section,
+ contents, rel->r_offset,
+ relocation, rel->r_addend);
+}
+
+/* Relocate an EPIPHANY ELF section.
+
+ The RELOCATE_SECTION function is called by the new ELF backend linker
+ to handle the relocations for a section.
+
+ The relocs are always passed as Rela structures; if the section
+ actually uses Rel structures, the r_addend field will always be
+ zero.
+
+ This function is responsible for adjusting the section contents as
+ necessary, and (if using Rela relocs and generating a relocatable
+ output file) adjusting the reloc addend as necessary.
+
+ This function does not have to worry about setting the reloc
+ address or the reloc symbol index.
+
+ LOCAL_SYMS is a pointer to the swapped in local symbols.
+
+ LOCAL_SECTIONS is an array giving the section in the input file
+ corresponding to the st_shndx field of each local symbol.
+
+ The global hash table entry for the global symbols can be found
+ via elf_sym_hashes (input_bfd).
+
+ When generating relocatable output, this function must handle
+ STB_LOCAL/STT_SECTION symbols specially. The output symbol is
+ going to be the section symbol corresponding to the output
+ section, which means that the addend must be adjusted
+ accordingly. */
+
+static bfd_boolean
+epiphany_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
+ struct bfd_link_info *info,
+ bfd *input_bfd,
+ asection *input_section,
+ bfd_byte *contents,
+ Elf_Internal_Rela *relocs,
+ Elf_Internal_Sym *local_syms,
+ asection **local_sections)
+{
+ Elf_Internal_Shdr *symtab_hdr;
+ struct elf_link_hash_entry **sym_hashes;
+ Elf_Internal_Rela *rel;
+ Elf_Internal_Rela *relend;
+
+ symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr;
+ sym_hashes = elf_sym_hashes (input_bfd);
+ relend = relocs + input_section->reloc_count;
+
+ for (rel = relocs; rel < relend; rel ++)
+ {
+ reloc_howto_type * howto;
+ unsigned long r_symndx;
+ Elf_Internal_Sym * sym;
+ asection * sec;
+ struct elf_link_hash_entry * h;
+ bfd_vma relocation;
+ bfd_reloc_status_type r;
+ const char * name = NULL;
+ int r_type ATTRIBUTE_UNUSED;
+
+ r_type = ELF32_R_TYPE (rel->r_info);
+ r_symndx = ELF32_R_SYM (rel->r_info);
+ howto = epiphany_elf_howto_table + ELF32_R_TYPE (rel->r_info);
+ h = NULL;
+ sym = NULL;
+ sec = NULL;
+
+ if (r_symndx < symtab_hdr->sh_info)
+ {
+ sym = local_syms + r_symndx;
+ sec = local_sections [r_symndx];
+ relocation = BASEADDR (sec) + sym->st_value;
+
+ name = bfd_elf_string_from_elf_section
+ (input_bfd, symtab_hdr->sh_link, sym->st_name);
+ name = (name == NULL) ? bfd_section_name (input_bfd, sec) : name;
+ }
+ else
+ {
+ bfd_boolean warned ATTRIBUTE_UNUSED;
+ bfd_boolean unresolved_reloc ATTRIBUTE_UNUSED;
+
+ RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
+ r_symndx, symtab_hdr, sym_hashes,
+ h, sec, relocation,
+ unresolved_reloc, warned);
+
+ name = h->root.root.string;
+ }
+
+ if (sec != NULL && elf_discarded_section (sec))
+ RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
+ rel, relend, howto, contents);
+
+ if (info->relocatable)
+ continue;
+
+ /* Finally, the sole EPIPHANY-specific part. */
+ r = epiphany_final_link_relocate (howto, input_bfd, input_section,
+ contents, rel, relocation);
+
+ if (r != bfd_reloc_ok)
+ {
+ const char * msg = NULL;
+
+ switch (r)
+ {
+ case bfd_reloc_overflow:
+ r = info->callbacks->reloc_overflow
+ (info, (h ? &h->root : NULL), name, howto->name,
+ (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
+ break;
+
+ case bfd_reloc_undefined:
+ r = info->callbacks->undefined_symbol
+ (info, name, input_bfd, input_section, rel->r_offset, TRUE);
+ break;
+
+ case bfd_reloc_outofrange:
+ msg = _("internal error: out of range error");
+ break;
+
+ /* This is how epiphany_final_link_relocate tells us of a
+ non-kosher reference between insn & data address spaces. */
+ case bfd_reloc_notsupported:
+ if (sym != NULL) /* Only if it's not an unresolved symbol. */
+ msg = _("unsupported relocation between data/insn address spaces");
+ break;
+
+ case bfd_reloc_dangerous:
+ msg = _("internal error: dangerous relocation");
+ break;
+
+ default:
+ msg = _("internal error: unknown error");
+ break;
+ }
+
+ if (msg)
+ r = info->callbacks->warning
+ (info, msg, name, input_bfd, input_section, rel->r_offset);
+
+ if (! r)
+ return FALSE;
+ }
+ }
+
+ return TRUE;
+}
+
+/* We only have a little-endian target. */
+#define TARGET_LITTLE_SYM bfd_elf32_epiphany_vec
+#define TARGET_LITTLE_NAME "elf32-epiphany"
+
+#define ELF_ARCH bfd_arch_epiphany
+#define ELF_MACHINE_CODE EM_ADAPTEVA_EPIPHANY
+
+#define ELF_MAXPAGESIZE 0x8000 /* No pages on the EPIPHANY. */
+
+#define elf_info_to_howto_rel NULL
+#define elf_info_to_howto epiphany_info_to_howto_rela
+
+#define elf_backend_can_gc_sections 1
+#define elf_backend_rela_normal 1
+#define elf_backend_relocate_section epiphany_elf_relocate_section
+
+#define elf_symbol_leading_char '_'
+#define bfd_elf32_bfd_reloc_type_lookup epiphany_reloc_type_lookup
+#define bfd_elf32_bfd_reloc_name_lookup epiphany_reloc_name_lookup
+#define bfd_elf32_bfd_relax_section epiphany_elf_relax_section
+
+#include "elf32-target.h"
"BFD_RELOC_TILEGX_TLS_DTPMOD32",
"BFD_RELOC_TILEGX_TLS_DTPOFF32",
"BFD_RELOC_TILEGX_TLS_TPOFF32",
+ "BFD_RELOC_EPIPHANY_SIMM8",
+ "BFD_RELOC_EPIPHANY_SIMM24",
+ "BFD_RELOC_EPIPHANY_HIGH",
+ "BFD_RELOC_EPIPHANY_LOW",
+ "BFD_RELOC_EPIPHANY_SIMM11",
+ "BFD_RELOC_EPIPHANY_IMM11",
+ "BFD_RELOC_EPIPHANY_IMM8",
"@@overflow: BFD_RELOC_UNUSED@@",
};
#endif
cpu-d10v.c
cpu-d30v.c
cpu-dlx.c
+cpu-epiphany.c
cpu-fr30.c
cpu-frv.c
cpu-h8300.c
cpu-ia64.c
cpu-ip2k.c
cpu-iq2000.c
+cpu-k1om.c
cpu-l1om.c
cpu-lm32.c
cpu-m10200.c
elf32-d10v.c
elf32-d30v.c
elf32-dlx.c
+elf32-epiphany.c
elf32-fr30.c
elf32-frv.c
elf32-gen.c
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n"
-"POT-Creation-Date: 2011-06-02 14:25+0100\n"
+"POT-Creation-Date: 2011-10-25 11:58+0100\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n"
"%s: can not represent section for symbol `%s' in a.out object file format"
msgstr ""
-#: aoutx.h:1579 vms-alpha.c:7668
+#: aoutx.h:1579 vms-alpha.c:7671
msgid "*unknown*"
msgstr ""
-#: aoutx.h:4017 aoutx.h:4343
+#: aoutx.h:4018 aoutx.h:4344
msgid "%P: %B: unexpected relocation type\n"
msgstr ""
-#: aoutx.h:5374
+#: aoutx.h:5375
#, c-format
msgid "%s: relocatable link from %s to %s not supported"
msgstr ""
-#: archive.c:2194
+#: archive.c:2203
msgid "Warning: writing archive was slow: rewriting timestamp\n"
msgstr ""
-#: archive.c:2482
+#: archive.c:2491
msgid "Reading archive file mod timestamp"
msgstr ""
-#: archive.c:2506
+#: archive.c:2515
msgid "Writing updated armap timestamp"
msgstr ""
msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx."
msgstr ""
-#: bout.c:1146 elf-m10300.c:2075 elf32-avr.c:1654 elf32-frv.c:5731
-#: elfxx-sparc.c:2796 reloc.c:5677 reloc16.c:162 elf32-ia64.c:360
+#: bout.c:1146 elf-m10300.c:2063 elf32-avr.c:1654 elf32-frv.c:5734
+#: elfxx-sparc.c:2802 reloc.c:6115 reloc16.c:162 elf32-ia64.c:360
#: elf64-ia64.c:360
msgid "%P%F: --relax and -r may not be used together\n"
msgstr ""
-#: cache.c:226
+#: cache.c:227
msgid "reopening %B: %s\n"
msgstr ""
msgid "%B: unsupported relocation: ALPHA_R_GPRELLOW"
msgstr ""
-#: coff-alpha.c:1575 elf32-m32r.c:2493 elf64-alpha.c:4079 elf64-alpha.c:4228
-#: elf32-ia64.c:3845 elf64-ia64.c:3845
+#: coff-alpha.c:1575 elf32-m32r.c:2484 elf64-alpha.c:4074 elf64-alpha.c:4224
+#: elf32-ia64.c:3839 elf64-ia64.c:3839
msgid "%B: unknown relocation type %d"
msgstr ""
msgid "%B: unable to find ARM glue '%s' for `%s'"
msgstr ""
-#: coff-arm.c:1369 elf32-arm.c:6980
+#: coff-arm.c:1369 elf32-arm.c:7023
#, c-format
msgid ""
"%B(%s): warning: interworking not enabled.\n"
msgid "error: %B is compiled for APCS-%d, whereas %B is compiled for APCS-%d"
msgstr ""
-#: coff-arm.c:2226 elf32-arm.c:15580
+#: coff-arm.c:2226 elf32-arm.c:15621
#, c-format
msgid ""
"error: %B passes floats in float registers, whereas %B passes them in "
"integer registers"
msgstr ""
-#: coff-arm.c:2229 elf32-arm.c:15584
+#: coff-arm.c:2229 elf32-arm.c:15625
#, c-format
msgid ""
"error: %B passes floats in integer registers, whereas %B passes them in "
"position independent"
msgstr ""
-#: coff-arm.c:2274 elf32-arm.c:15649
+#: coff-arm.c:2274 elf32-arm.c:15690
#, c-format
msgid "Warning: %B supports interworking, whereas %B does not"
msgstr ""
-#: coff-arm.c:2277 elf32-arm.c:15655
+#: coff-arm.c:2277 elf32-arm.c:15696
#, c-format
msgid "Warning: %B does not support interworking, whereas %B does"
msgstr ""
msgid "private flags = %x:"
msgstr ""
-#: coff-arm.c:2309 elf32-arm.c:11752
+#: coff-arm.c:2309 elf32-arm.c:11806
#, c-format
msgid " [floats passed in float registers]"
msgstr ""
msgid " [floats passed in integer registers]"
msgstr ""
-#: coff-arm.c:2314 elf32-arm.c:11755
+#: coff-arm.c:2314 elf32-arm.c:11809
#, c-format
msgid " [position independent]"
msgstr ""
msgid " [interworking not supported]"
msgstr ""
-#: coff-arm.c:2370 elf32-arm.c:10787
+#: coff-arm.c:2370 elf32-arm.c:10841
#, c-format
msgid ""
"Warning: Not setting interworking flag of %B since it has already been "
"specified as non-interworking"
msgstr ""
-#: coff-arm.c:2374 elf32-arm.c:10791
+#: coff-arm.c:2374 elf32-arm.c:10845
#, c-format
msgid "Warning: Clearing the interworking flag of %B due to outside request"
msgstr ""
msgid "relocation `%s' not yet implemented"
msgstr ""
-#: coff-i860.c:605 coff-tic54x.c:398 coffcode.h:5192
+#: coff-i860.c:605 coff-tic54x.c:398 coffcode.h:5198
msgid "%B: warning: illegal symbol index %ld in relocs"
msgstr ""
-#: coff-i960.c:143 coff-i960.c:506
+#: coff-i960.c:144 coff-i960.c:507
msgid "uncertain calling convention for non-COFF symbol"
msgstr ""
-#: coff-m68k.c:506 elf32-bfin.c:5689 elf32-cr16.c:2897 elf32-m68k.c:4677
+#: coff-m68k.c:506 elf32-bfin.c:5690 elf32-cr16.c:2897 elf32-m68k.c:4677
msgid "unsupported reloc type"
msgstr ""
-#: coff-mips.c:688 elf32-mips.c:1014 elf32-score.c:430 elf32-score7.c:330
-#: elf64-mips.c:2019 elfn32-mips.c:1832
+#: coff-mips.c:688 elf32-mips.c:1516 elf32-score.c:431 elf32-score7.c:330
+#: elf64-mips.c:2618 elfn32-mips.c:2431
msgid "GP relative relocation when _gp not defined"
msgstr ""
msgid "Unrecognized reloc"
msgstr ""
-#: coff-rs6000.c:2676
+#: coff-rs6000.c:2720
#, c-format
msgid "%s: unsupported relocation type 0x%02x"
msgstr ""
-#: coff-rs6000.c:2761
+#: coff-rs6000.c:2805
#, c-format
msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry"
msgstr ""
-#: coff-rs6000.c:3512 coff64-rs6000.c:2111
+#: coff-rs6000.c:3556 coff64-rs6000.c:2111
msgid "%B: symbol `%s' has unrecognized smclas %d"
msgstr ""
msgid "ignoring reloc %s\n"
msgstr ""
-#: coffcode.h:991
+#: coffcode.h:997
msgid "%B: warning: COMDAT symbol '%s' does not match section name '%s'"
msgstr ""
#. Generate a warning message rather using the 'unhandled'
#. variable as this will allow some .sys files generate by
#. other toolchains to be processed. See bugzilla issue 196.
-#: coffcode.h:1215
+#: coffcode.h:1221
msgid ""
"%B: Warning: Ignoring section flag IMAGE_SCN_MEM_NOT_PAGED in section %s"
msgstr ""
-#: coffcode.h:1282
+#: coffcode.h:1288
msgid "%B (%s): Section flag %s (0x%x) ignored"
msgstr ""
-#: coffcode.h:2424
+#: coffcode.h:2430
#, c-format
msgid "Unrecognized TI COFF target id '0x%x'"
msgstr ""
-#: coffcode.h:2738
+#: coffcode.h:2744
msgid "%B: reloc against a non-existant symbol index: %ld"
msgstr ""
-#: coffcode.h:3296
+#: coffcode.h:3302
msgid "%B: too many sections (%d)"
msgstr ""
-#: coffcode.h:3712
+#: coffcode.h:3718
msgid "%B: section %s: string table overflow at offset %ld"
msgstr ""
-#: coffcode.h:4517
+#: coffcode.h:4523
msgid "%B: warning: line number table read failed"
msgstr ""
-#: coffcode.h:4547
+#: coffcode.h:4553
msgid "%B: warning: illegal symbol index %ld in line numbers"
msgstr ""
-#: coffcode.h:4561
+#: coffcode.h:4567
msgid "%B: warning: duplicate line number information for `%s'"
msgstr ""
-#: coffcode.h:4961
+#: coffcode.h:4967
msgid "%B: Unrecognized storage class %d for %s symbol `%s'"
msgstr ""
-#: coffcode.h:5087
+#: coffcode.h:5093
msgid "warning: %B: local symbol `%s' has no section"
msgstr ""
-#: coffcode.h:5231
+#: coffcode.h:5237
msgid "%B: illegal relocation type %d at address 0x%lx"
msgstr ""
-#: coffgen.c:1578
+#: coffgen.c:1595
msgid "%B: bad string table size %lu"
msgstr ""
-#: cofflink.c:533 elflink.c:4353
+#: coffgen.c:2500 elflink.c:12689 linker.c:3122
+msgid "%F%P: already_linked_table: %E\n"
+msgstr ""
+
+#: cofflink.c:533 elflink.c:4323
msgid "Warning: type of symbol `%s' changed from %d to %d in %B"
msgstr ""
-#: cofflink.c:2330
+#: cofflink.c:2329
msgid "%B: relocs in section `%A', but it has no contents"
msgstr ""
-#: cofflink.c:2392 elflink.c:9554
+#: cofflink.c:2391 elflink.c:9545
msgid ""
"%X`%s' referenced in section `%A' of %B: defined in discarded section `%A' "
"of %B\n"
msgid "warning: unable to update contents of %s section in %s"
msgstr ""
-#: dwarf2.c:490
+#: dwarf2.c:496
#, c-format
msgid "Dwarf Error: Can't find %s section."
msgstr ""
-#: dwarf2.c:518
+#: dwarf2.c:525
#, c-format
msgid "Dwarf Error: Offset (%lu) greater than or equal to %s size (%lu)."
msgstr ""
-#: dwarf2.c:940
+#: dwarf2.c:949
#, c-format
msgid "Dwarf Error: Invalid or unhandled FORM value: %u."
msgstr ""
-#: dwarf2.c:1191
+#: dwarf2.c:1200
msgid "Dwarf Error: mangled line number section (bad file number)."
msgstr ""
-#: dwarf2.c:1443
+#: dwarf2.c:1453
#, c-format
msgid "Dwarf Error: Unhandled .debug_line version %d."
msgstr ""
-#: dwarf2.c:1465
+#: dwarf2.c:1475
msgid "Dwarf Error: Invalid maximum operations per instruction."
msgstr ""
-#: dwarf2.c:1652
+#: dwarf2.c:1662
msgid "Dwarf Error: mangled line number section."
msgstr ""
-#: dwarf2.c:1978 dwarf2.c:2098 dwarf2.c:2383
+#: dwarf2.c:1989 dwarf2.c:2109 dwarf2.c:2394
#, c-format
msgid "Dwarf Error: Could not find abbrev number %u."
msgstr ""
-#: dwarf2.c:2344
+#: dwarf2.c:2355
#, c-format
msgid ""
"Dwarf Error: found dwarf version '%u', this reader only handles version 2, 3 "
"and 4 information."
msgstr ""
-#: dwarf2.c:2351
+#: dwarf2.c:2362
#, c-format
msgid ""
"Dwarf Error: found address size '%u', this reader can not handle sizes "
"greater than '%u'."
msgstr ""
-#: dwarf2.c:2374
+#: dwarf2.c:2385
#, c-format
msgid "Dwarf Error: Bad abbrev number: %u."
msgstr ""
-#: ecoff.c:1237
+#: ecoff.c:1239
#, c-format
msgid "Unknown basic type %d"
msgstr ""
-#: ecoff.c:1494
+#: ecoff.c:1496
#, c-format
msgid ""
"\n"
" End+1 symbol: %ld"
msgstr ""
-#: ecoff.c:1501 ecoff.c:1504
+#: ecoff.c:1503 ecoff.c:1506
#, c-format
msgid ""
"\n"
" First symbol: %ld"
msgstr ""
-#: ecoff.c:1516
+#: ecoff.c:1518
#, c-format
msgid ""
"\n"
" End+1 symbol: %-7ld Type: %s"
msgstr ""
-#: ecoff.c:1523
+#: ecoff.c:1525
#, c-format
msgid ""
"\n"
" Local symbol: %ld"
msgstr ""
-#: ecoff.c:1531
+#: ecoff.c:1533
#, c-format
msgid ""
"\n"
" struct; End+1 symbol: %ld"
msgstr ""
-#: ecoff.c:1536
+#: ecoff.c:1538
#, c-format
msgid ""
"\n"
" union; End+1 symbol: %ld"
msgstr ""
-#: ecoff.c:1541
+#: ecoff.c:1543
#, c-format
msgid ""
"\n"
" enum; End+1 symbol: %ld"
msgstr ""
-#: ecoff.c:1547
+#: ecoff.c:1549
#, c-format
msgid ""
"\n"
msgid "error: %B: Object tag '%d, %s' is incompatible with tag '%d, %s'"
msgstr ""
-#: elf-eh-frame.c:913
+#: elf-eh-frame.c:917
msgid "%P: error in %B(%A); no .eh_frame_hdr table will be created.\n"
msgstr ""
-#: elf-eh-frame.c:1165
+#: elf-eh-frame.c:1189
msgid ""
"%P: fde encoding in %B(%A) prevents .eh_frame_hdr table being created.\n"
msgstr ""
-#: elf-eh-frame.c:1583
+#: elf-eh-frame.c:1605
msgid "%P: DW_EH_PE_datarel unspecified for this architecture.\n"
msgstr ""
"pie\n"
msgstr ""
-#: elf-m10200.c:450 elf-m10300.c:1571 elf32-avr.c:1221 elf32-bfin.c:3209
-#: elf32-cr16.c:1482 elf32-cr16c.c:780 elf32-cris.c:2077 elf32-crx.c:922
-#: elf32-d10v.c:509 elf32-fr30.c:609 elf32-frv.c:4102 elf32-h8300.c:509
-#: elf32-i860.c:1211 elf32-ip2k.c:1468 elf32-iq2000.c:684 elf32-lm32.c:1168
-#: elf32-m32c.c:553 elf32-m32r.c:3111 elf32-m68hc1x.c:1138 elf32-mep.c:535
-#: elf32-microblaze.c:1231 elf32-moxie.c:282 elf32-msp430.c:486 elf32-mt.c:395
-#: elf32-openrisc.c:404 elf32-score.c:2731 elf32-score7.c:2540
-#: elf32-spu.c:5042 elf32-v850.c:2143 elf32-xstormy16.c:941 elf64-mmix.c:1522
+#: elf-m10200.c:450 elf-m10300.c:1563 elf32-avr.c:1221 elf32-bfin.c:3213
+#: elf32-cr16.c:1482 elf32-cr16c.c:780 elf32-cris.c:2081 elf32-crx.c:922
+#: elf32-d10v.c:509 elf32-epiphany.c:556 elf32-fr30.c:609 elf32-frv.c:4105
+#: elf32-h8300.c:509 elf32-i860.c:1211 elf32-ip2k.c:1468 elf32-iq2000.c:684
+#: elf32-lm32.c:1168 elf32-m32c.c:553 elf32-m32r.c:3106 elf32-m68hc1x.c:1138
+#: elf32-mep.c:535 elf32-microblaze.c:1231 elf32-moxie.c:282
+#: elf32-msp430.c:486 elf32-mt.c:395 elf32-openrisc.c:404 elf32-score.c:2729
+#: elf32-score7.c:2537 elf32-spu.c:5044 elf32-tilepro.c:3214 elf32-v850.c:2143
+#: elf32-xstormy16.c:935 elf64-mmix.c:1590 elfxx-tilegx.c:3577
msgid "internal error: out of range error"
msgstr ""
-#: elf-m10200.c:454 elf-m10300.c:1575 elf32-avr.c:1225 elf32-bfin.c:3213
-#: elf32-cr16.c:1486 elf32-cr16c.c:784 elf32-cris.c:2081 elf32-crx.c:926
-#: elf32-d10v.c:513 elf32-fr30.c:613 elf32-frv.c:4106 elf32-h8300.c:513
+#: elf-m10200.c:454 elf-m10300.c:1567 elf32-avr.c:1225 elf32-bfin.c:3217
+#: elf32-cr16.c:1486 elf32-cr16c.c:784 elf32-cris.c:2085 elf32-crx.c:926
+#: elf32-d10v.c:513 elf32-fr30.c:613 elf32-frv.c:4109 elf32-h8300.c:513
#: elf32-i860.c:1215 elf32-iq2000.c:688 elf32-lm32.c:1172 elf32-m32c.c:557
-#: elf32-m32r.c:3115 elf32-m68hc1x.c:1142 elf32-mep.c:539
+#: elf32-m32r.c:3110 elf32-m68hc1x.c:1142 elf32-mep.c:539
#: elf32-microblaze.c:1235 elf32-moxie.c:286 elf32-msp430.c:490
-#: elf32-openrisc.c:408 elf32-score.c:2735 elf32-score7.c:2544
-#: elf32-spu.c:5046 elf32-v850.c:2147 elf32-xstormy16.c:945 elf64-mmix.c:1526
-#: elfxx-mips.c:9193
+#: elf32-openrisc.c:408 elf32-score.c:2733 elf32-score7.c:2541
+#: elf32-spu.c:5048 elf32-tilepro.c:3218 elf32-v850.c:2147
+#: elf32-xstormy16.c:939 elf64-mmix.c:1594 elfxx-mips.c:9465
+#: elfxx-tilegx.c:3581
msgid "internal error: unsupported relocation error"
msgstr ""
#: elf-m10200.c:458 elf32-cr16.c:1490 elf32-cr16c.c:788 elf32-crx.c:930
-#: elf32-d10v.c:517 elf32-h8300.c:517 elf32-lm32.c:1176 elf32-m32r.c:3119
-#: elf32-m68hc1x.c:1146 elf32-microblaze.c:1239 elf32-score.c:2739
-#: elf32-score7.c:2548 elf32-spu.c:5050
+#: elf32-d10v.c:517 elf32-h8300.c:517 elf32-lm32.c:1176 elf32-m32r.c:3114
+#: elf32-m68hc1x.c:1146 elf32-microblaze.c:1239 elf32-score.c:2737
+#: elf32-score7.c:2545 elf32-spu.c:5052
msgid "internal error: dangerous error"
msgstr ""
-#: elf-m10200.c:462 elf-m10300.c:1591 elf32-avr.c:1233 elf32-bfin.c:3221
-#: elf32-cr16.c:1494 elf32-cr16c.c:792 elf32-cris.c:2089 elf32-crx.c:934
-#: elf32-d10v.c:521 elf32-fr30.c:621 elf32-frv.c:4114 elf32-h8300.c:521
-#: elf32-i860.c:1223 elf32-ip2k.c:1483 elf32-iq2000.c:696 elf32-lm32.c:1180
-#: elf32-m32c.c:565 elf32-m32r.c:3123 elf32-m68hc1x.c:1150 elf32-mep.c:547
-#: elf32-microblaze.c:1243 elf32-moxie.c:294 elf32-msp430.c:498 elf32-mt.c:403
-#: elf32-openrisc.c:416 elf32-score.c:2748 elf32-score7.c:2552
-#: elf32-spu.c:5054 elf32-v850.c:2167 elf32-xstormy16.c:953 elf64-mmix.c:1534
+#: elf-m10200.c:462 elf-m10300.c:1580 elf32-avr.c:1233 elf32-bfin.c:3225
+#: elf32-cr16.c:1494 elf32-cr16c.c:792 elf32-cris.c:2093 elf32-crx.c:934
+#: elf32-d10v.c:521 elf32-epiphany.c:571 elf32-fr30.c:621 elf32-frv.c:4117
+#: elf32-h8300.c:521 elf32-i860.c:1223 elf32-ip2k.c:1483 elf32-iq2000.c:696
+#: elf32-lm32.c:1180 elf32-m32c.c:565 elf32-m32r.c:3118 elf32-m68hc1x.c:1150
+#: elf32-mep.c:547 elf32-microblaze.c:1243 elf32-moxie.c:294
+#: elf32-msp430.c:498 elf32-mt.c:403 elf32-openrisc.c:416 elf32-score.c:2746
+#: elf32-score7.c:2549 elf32-spu.c:5056 elf32-tilepro.c:3226 elf32-v850.c:2167
+#: elf32-xstormy16.c:947 elf64-mmix.c:1602 elfxx-tilegx.c:3589
msgid "internal error: unknown error"
msgstr ""
-#: elf-m10300.c:1515 elf32-arm.c:10365 elf32-i386.c:4107 elf32-m32r.c:2604
-#: elf32-m68k.c:4156 elf32-s390.c:3010 elf32-sh.c:4223 elf32-xtensa.c:3067
-#: elf64-s390.c:2985 elf64-sh64.c:1636 elf64-x86-64.c:3882 elfxx-sparc.c:3807
+#: elf-m10300.c:1507 elf32-arm.c:10419 elf32-i386.c:4264 elf32-m32r.c:2599
+#: elf32-m68k.c:4156 elf32-s390.c:3003 elf32-sh.c:4218 elf32-tilepro.c:3117
+#: elf32-xtensa.c:3066 elf64-s390.c:2978 elf64-sh64.c:1640 elf64-x86-64.c:4110
+#: elfxx-sparc.c:3835 elfxx-tilegx.c:3500
msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"
msgstr ""
-#: elf-m10300.c:1580
+#: elf-m10300.c:1572
msgid ""
"error: inappropriate relocation type for shared library (did you forget -"
"fpic?)"
msgstr ""
-#: elf-m10300.c:1583
-msgid ""
-"%B: error: taking the address of protected function '%s' cannot be done when "
-"making a shared library"
-msgstr ""
-
-#: elf-m10300.c:1586
+#: elf-m10300.c:1575
msgid "internal error: suspicious relocation type used in shared library"
msgstr ""
-#: elf-m10300.c:4384 elf32-arm.c:12743 elf32-cr16.c:2451 elf32-cris.c:3044
-#: elf32-hppa.c:1894 elf32-i370.c:503 elf32-i386.c:2043 elf32-lm32.c:1868
-#: elf32-m32r.c:1927 elf32-m68k.c:3252 elf32-s390.c:1652 elf32-sh.c:2931
-#: elf32-tic6x.c:2160 elf32-vax.c:1040 elf64-s390.c:1635 elf64-sh64.c:3377
-#: elf64-x86-64.c:1985 elfxx-sparc.c:2104
+#: elf-m10300.c:4372 elf32-arm.c:12800 elf32-cr16.c:2451 elf32-cris.c:3057
+#: elf32-hppa.c:1894 elf32-i370.c:503 elf32-i386.c:2182 elf32-lm32.c:1868
+#: elf32-m32r.c:1927 elf32-m68k.c:3253 elf32-s390.c:1652 elf32-sh.c:2931
+#: elf32-tic6x.c:2162 elf32-tilepro.c:1940 elf32-vax.c:1041 elf64-s390.c:1635
+#: elf64-sh64.c:3381 elf64-x86-64.c:2176 elfxx-sparc.c:2119
+#: elfxx-tilegx.c:2261
#, c-format
msgid "dynamic variable `%s' is zero size"
msgstr ""
msgid "%B: no group info for section %A"
msgstr ""
-#: elf.c:737 elf.c:3121 elflink.c:10144
+#: elf.c:737 elf.c:3121 elflink.c:10135
msgid "%B: warning: sh_link not set for section `%A'"
msgstr ""
msgid "%B: section %A lma %#lx adjusted to %#lx"
msgstr ""
-#: elf.c:4774
+#: elf.c:4776
msgid "%B: section `%A' can't be allocated in segment %d"
msgstr ""
-#: elf.c:4822
+#: elf.c:4824
msgid "%B: warning: allocated section `%s' not in segment"
msgstr ""
-#: elf.c:5322
+#: elf.c:5324
msgid "%B: symbol `%s' required but not present"
msgstr ""
-#: elf.c:5660
+#: elf.c:5662
msgid "%B: warning: Empty loadable segment detected, is this intentional ?\n"
msgstr ""
-#: elf.c:6688
+#: elf.c:6692
#, c-format
msgid ""
"Unable to find equivalent output section for symbol '%s' from section '%s'"
msgstr ""
-#: elf.c:7684
+#: elf.c:7692
msgid "%B: unsupported relocation type %s"
msgstr ""
-#: elf32-arm.c:3590
+#: elf32-arm.c:3617
msgid ""
"%B(%s): warning: interworking not enabled.\n"
" first occurrence: %B: Thumb call to ARM"
msgstr ""
-#: elf32-arm.c:3637
+#: elf32-arm.c:3664
msgid ""
"%B(%s): warning: interworking not enabled.\n"
" first occurrence: %B: ARM call to Thumb"
msgstr ""
-#: elf32-arm.c:3849 elf32-arm.c:5286
+#: elf32-arm.c:3878 elf32-arm.c:5315
#, c-format
msgid "%s: cannot create stub entry %s"
msgstr ""
-#: elf32-arm.c:5402
+#: elf32-arm.c:5431
#, c-format
msgid "unable to find THUMB glue '%s' for '%s'"
msgstr ""
-#: elf32-arm.c:5438
+#: elf32-arm.c:5467
#, c-format
msgid "unable to find ARM glue '%s' for '%s'"
msgstr ""
-#: elf32-arm.c:5964
+#: elf32-arm.c:6005
msgid "%B: BE8 images only valid in big-endian mode."
msgstr ""
#. Give a warning, but do as the user requests anyway.
-#: elf32-arm.c:6194
+#: elf32-arm.c:6235
msgid ""
"%B: warning: selected VFP11 erratum workaround is not necessary for target "
"architecture"
msgstr ""
-#: elf32-arm.c:6738 elf32-arm.c:6758
+#: elf32-arm.c:6779 elf32-arm.c:6799
msgid "%B: unable to find VFP11 veneer `%s'"
msgstr ""
-#: elf32-arm.c:6806
+#: elf32-arm.c:6848
#, c-format
msgid "Invalid TARGET2 relocation type '%s'."
msgstr ""
-#: elf32-arm.c:6890
+#: elf32-arm.c:6933
msgid ""
"%B(%s): warning: interworking not enabled.\n"
" first occurrence: %B: thumb call to arm"
msgstr ""
-#: elf32-arm.c:7674
+#: elf32-arm.c:7717
msgid "%B(%A+0x%lx):unexpected Thumb instruction '0x%x' in TLS trampoline"
msgstr ""
-#: elf32-arm.c:7713
+#: elf32-arm.c:7756
msgid "%B(%A+0x%lx):unexpected ARM instruction '0x%x' in TLS trampoline"
msgstr ""
-#: elf32-arm.c:8166
+#: elf32-arm.c:8209
msgid "\\%B: Warning: Arm BLX instruction targets Arm function '%s'."
msgstr ""
-#: elf32-arm.c:8575
+#: elf32-arm.c:8622
msgid "%B: Warning: Thumb BLX instruction targets thumb function '%s'."
msgstr ""
-#: elf32-arm.c:9408
+#: elf32-arm.c:9460
msgid ""
"%B(%A+0x%lx):unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"
msgstr ""
-#: elf32-arm.c:9431
+#: elf32-arm.c:9483
msgid ""
"%B(%A+0x%lx):unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"
msgstr ""
-#: elf32-arm.c:9460
+#: elf32-arm.c:9512
msgid "%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"
msgstr ""
-#: elf32-arm.c:9675
+#: elf32-arm.c:9727
msgid ""
"%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group "
"relocations"
msgstr ""
-#: elf32-arm.c:9715 elf32-arm.c:9802 elf32-arm.c:9885 elf32-arm.c:9970
+#: elf32-arm.c:9767 elf32-arm.c:9854 elf32-arm.c:9937 elf32-arm.c:10022
msgid "%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"
msgstr ""
-#: elf32-arm.c:10209 elf32-sh.c:4112 elf64-sh64.c:1544
+#: elf32-arm.c:10261 elf32-sh.c:4103 elf64-sh64.c:1544
msgid "%B(%A+0x%lx): %s relocation against SEC_MERGE section"
msgstr ""
-#: elf32-arm.c:10320 elf32-m68k.c:4191 elf32-xtensa.c:2805
+#: elf32-arm.c:10372 elf32-m68k.c:4191 elf32-xtensa.c:2802
msgid "%B(%A+0x%lx): %s used with TLS symbol %s"
msgstr ""
-#: elf32-arm.c:10321 elf32-m68k.c:4192 elf32-xtensa.c:2806
+#: elf32-arm.c:10373 elf32-m68k.c:4192 elf32-xtensa.c:2803
msgid "%B(%A+0x%lx): %s used with non-TLS symbol %s"
msgstr ""
-#: elf32-arm.c:10399 elf32-tic6x.c:2751
+#: elf32-arm.c:10453 elf32-tic6x.c:2753
msgid "out of range"
msgstr ""
-#: elf32-arm.c:10403 elf32-tic6x.c:2755
+#: elf32-arm.c:10457 elf32-tic6x.c:2757
msgid "unsupported relocation"
msgstr ""
-#: elf32-arm.c:10411 elf32-tic6x.c:2763
+#: elf32-arm.c:10465 elf32-tic6x.c:2765
msgid "unknown error"
msgstr ""
-#: elf32-arm.c:10836
+#: elf32-arm.c:10890
msgid ""
"Warning: Clearing the interworking flag of %B because non-interworking code "
"in %B has been linked with it"
msgstr ""
-#: elf32-arm.c:10930
+#: elf32-arm.c:10984
msgid "%B: Unknown mandatory EABI object attribute %d"
msgstr ""
-#: elf32-arm.c:10938
+#: elf32-arm.c:10992
msgid "Warning: %B: Unknown EABI object attribute %d"
msgstr ""
-#: elf32-arm.c:11119
+#: elf32-arm.c:11173
msgid "error: %B: Unknown CPU architecture"
msgstr ""
-#: elf32-arm.c:11157
+#: elf32-arm.c:11211
msgid "error: %B: Conflicting CPU architectures %d/%d"
msgstr ""
-#: elf32-arm.c:11206
+#: elf32-arm.c:11260
msgid ""
"Error: %B has both the current and legacy Tag_MPextension_use attributes"
msgstr ""
-#: elf32-arm.c:11231
+#: elf32-arm.c:11285
msgid "error: %B uses VFP register arguments, %B does not"
msgstr ""
-#: elf32-arm.c:11376
+#: elf32-arm.c:11430
msgid "error: %B: unable to merge virtualization attributes with %B"
msgstr ""
-#: elf32-arm.c:11402
+#: elf32-arm.c:11456
msgid "error: %B: Conflicting architecture profiles %c/%c"
msgstr ""
-#: elf32-arm.c:11503
+#: elf32-arm.c:11557
msgid "Warning: %B: Conflicting platform configuration"
msgstr ""
-#: elf32-arm.c:11512
+#: elf32-arm.c:11566
msgid "error: %B: Conflicting use of R9"
msgstr ""
-#: elf32-arm.c:11524
+#: elf32-arm.c:11578
msgid "error: %B: SB relative addressing conflicts with use of R9"
msgstr ""
-#: elf32-arm.c:11537
+#: elf32-arm.c:11591
msgid ""
"warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; "
"use of wchar_t values across objects may fail"
msgstr ""
-#: elf32-arm.c:11568
+#: elf32-arm.c:11622
msgid ""
"warning: %B uses %s enums yet the output is to use %s enums; use of enum "
"values across objects may fail"
msgstr ""
-#: elf32-arm.c:11580
+#: elf32-arm.c:11634
msgid "error: %B uses iWMMXt register arguments, %B does not"
msgstr ""
-#: elf32-arm.c:11597
+#: elf32-arm.c:11651
msgid "error: fp16 format mismatch between %B and %B"
msgstr ""
-#: elf32-arm.c:11621
+#: elf32-arm.c:11675
msgid "DIV usage mismatch between %B and %B"
msgstr ""
-#: elf32-arm.c:11640
+#: elf32-arm.c:11694
msgid "%B has has both the current and legacy Tag_MPextension_use attributes"
msgstr ""
#. Ignore init flag - it may not be set, despite the flags field
#. containing valid data.
#. Ignore init flag - it may not be set, despite the flags field containing valid data.
-#: elf32-arm.c:11728 elf32-bfin.c:5075 elf32-cris.c:4162 elf32-m68hc1x.c:1282
-#: elf32-m68k.c:1235 elf32-score.c:3996 elf32-score7.c:3803 elf32-vax.c:528
-#: elfxx-mips.c:12857
+#: elf32-arm.c:11782 elf32-bfin.c:5079 elf32-cris.c:4169 elf32-m68hc1x.c:1282
+#: elf32-m68k.c:1236 elf32-score.c:3994 elf32-score7.c:3800 elf32-vax.c:529
+#: elfxx-mips.c:14103
#, c-format
msgid "private flags = %lx:"
msgstr ""
-#: elf32-arm.c:11737
+#: elf32-arm.c:11791
#, c-format
msgid " [interworking enabled]"
msgstr ""
-#: elf32-arm.c:11745
+#: elf32-arm.c:11799
#, c-format
msgid " [VFP float format]"
msgstr ""
-#: elf32-arm.c:11747
+#: elf32-arm.c:11801
#, c-format
msgid " [Maverick float format]"
msgstr ""
-#: elf32-arm.c:11749
+#: elf32-arm.c:11803
#, c-format
msgid " [FPA float format]"
msgstr ""
-#: elf32-arm.c:11758
+#: elf32-arm.c:11812
#, c-format
msgid " [new ABI]"
msgstr ""
-#: elf32-arm.c:11761
+#: elf32-arm.c:11815
#, c-format
msgid " [old ABI]"
msgstr ""
-#: elf32-arm.c:11764
+#: elf32-arm.c:11818
#, c-format
msgid " [software FP]"
msgstr ""
-#: elf32-arm.c:11773
+#: elf32-arm.c:11827
#, c-format
msgid " [Version1 EABI]"
msgstr ""
-#: elf32-arm.c:11776 elf32-arm.c:11787
+#: elf32-arm.c:11830 elf32-arm.c:11841
#, c-format
msgid " [sorted symbol table]"
msgstr ""
-#: elf32-arm.c:11778 elf32-arm.c:11789
+#: elf32-arm.c:11832 elf32-arm.c:11843
#, c-format
msgid " [unsorted symbol table]"
msgstr ""
-#: elf32-arm.c:11784
+#: elf32-arm.c:11838
#, c-format
msgid " [Version2 EABI]"
msgstr ""
-#: elf32-arm.c:11792
+#: elf32-arm.c:11846
#, c-format
msgid " [dynamic symbols use segment index]"
msgstr ""
-#: elf32-arm.c:11795
+#: elf32-arm.c:11849
#, c-format
msgid " [mapping symbols precede others]"
msgstr ""
-#: elf32-arm.c:11802
+#: elf32-arm.c:11856
#, c-format
msgid " [Version3 EABI]"
msgstr ""
-#: elf32-arm.c:11806
+#: elf32-arm.c:11860
#, c-format
msgid " [Version4 EABI]"
msgstr ""
-#: elf32-arm.c:11810
+#: elf32-arm.c:11864
#, c-format
msgid " [Version5 EABI]"
msgstr ""
-#: elf32-arm.c:11813
+#: elf32-arm.c:11867
#, c-format
msgid " [BE8]"
msgstr ""
-#: elf32-arm.c:11816
+#: elf32-arm.c:11870
#, c-format
msgid " [LE8]"
msgstr ""
-#: elf32-arm.c:11822
+#: elf32-arm.c:11876
#, c-format
msgid " <EABI version unrecognised>"
msgstr ""
-#: elf32-arm.c:11829
+#: elf32-arm.c:11883
#, c-format
msgid " [relocatable executable]"
msgstr ""
-#: elf32-arm.c:11832
+#: elf32-arm.c:11886
#, c-format
msgid " [has entry point]"
msgstr ""
-#: elf32-arm.c:11837
+#: elf32-arm.c:11891
#, c-format
msgid "<Unrecognised flag bits set>"
msgstr ""
-#: elf32-arm.c:12135 elf32-i386.c:1323 elf32-s390.c:1000 elf32-tic6x.c:2827
-#: elf32-xtensa.c:1009 elf64-s390.c:960 elf64-x86-64.c:1172 elfxx-sparc.c:1370
+#: elf32-arm.c:12189 elf32-i386.c:1461 elf32-s390.c:1000 elf32-tic6x.c:2829
+#: elf32-tilepro.c:1336 elf32-xtensa.c:1009 elf64-s390.c:960
+#: elf64-x86-64.c:1364 elfxx-sparc.c:1371 elfxx-tilegx.c:1586
msgid "%B: bad symbol index: %d"
msgstr ""
-#: elf32-arm.c:12283 elf64-x86-64.c:1370 elf64-x86-64.c:1541 elfxx-mips.c:7949
+#: elf32-arm.c:12337 elf64-x86-64.c:1561 elf64-x86-64.c:1732 elfxx-mips.c:8223
msgid ""
"%B: relocation %s against `%s' can not be used when making a shared object; "
"recompile with -fPIC"
msgstr ""
-#: elf32-arm.c:13412
+#: elf32-arm.c:13460
#, c-format
msgid "Errors encountered processing file %s"
msgstr ""
-#: elf32-arm.c:14795
+#: elf32-arm.c:14837
msgid "%B: error: Cortex-A8 erratum stub is allocated in unsafe location"
msgstr ""
#. There's not much we can do apart from complain if this
#. happens.
-#: elf32-arm.c:14822
+#: elf32-arm.c:14864
msgid "%B: error: Cortex-A8 erratum stub out of range (input file too large)"
msgstr ""
-#: elf32-arm.c:14916 elf32-arm.c:14938
+#: elf32-arm.c:14958 elf32-arm.c:14980
msgid "%B: error: VFP11 veneer out of range"
msgstr ""
-#: elf32-arm.c:15477
+#: elf32-arm.c:15518
msgid "error: %B is already in final BE8 format"
msgstr ""
-#: elf32-arm.c:15553
+#: elf32-arm.c:15594
msgid ""
"error: Source object %B has EABI version %d, but target %B has EABI version "
"%d"
msgstr ""
-#: elf32-arm.c:15569
+#: elf32-arm.c:15610
msgid "error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"
msgstr ""
-#: elf32-arm.c:15594
+#: elf32-arm.c:15635
msgid "error: %B uses VFP instructions, whereas %B does not"
msgstr ""
-#: elf32-arm.c:15598
+#: elf32-arm.c:15639
msgid "error: %B uses FPA instructions, whereas %B does not"
msgstr ""
-#: elf32-arm.c:15608
+#: elf32-arm.c:15649
msgid "error: %B uses Maverick instructions, whereas %B does not"
msgstr ""
-#: elf32-arm.c:15612
+#: elf32-arm.c:15653
msgid "error: %B does not use Maverick instructions, whereas %B does"
msgstr ""
-#: elf32-arm.c:15631
+#: elf32-arm.c:15672
msgid "error: %B uses software FP, whereas %B uses hardware FP"
msgstr ""
-#: elf32-arm.c:15635
+#: elf32-arm.c:15676
msgid "error: %B uses hardware FP, whereas %B uses software FP"
msgstr ""
-#: elf32-avr.c:1229 elf32-bfin.c:3217 elf32-cris.c:2085 elf32-fr30.c:617
-#: elf32-frv.c:4110 elf32-i860.c:1219 elf32-ip2k.c:1479 elf32-iq2000.c:692
-#: elf32-m32c.c:561 elf32-mep.c:543 elf32-moxie.c:290 elf32-msp430.c:494
-#: elf32-mt.c:399 elf32-openrisc.c:412 elf32-v850.c:2151 elf32-xstormy16.c:949
-#: elf64-mmix.c:1530
+#: elf32-avr.c:1229 elf32-bfin.c:3221 elf32-cris.c:2089 elf32-epiphany.c:567
+#: elf32-fr30.c:617 elf32-frv.c:4113 elf32-i860.c:1219 elf32-ip2k.c:1479
+#: elf32-iq2000.c:692 elf32-m32c.c:561 elf32-mep.c:543 elf32-moxie.c:290
+#: elf32-msp430.c:494 elf32-mt.c:399 elf32-openrisc.c:412 elf32-tilepro.c:3222
+#: elf32-v850.c:2151 elf32-xstormy16.c:943 elf64-mmix.c:1598
+#: elfxx-tilegx.c:3585
msgid "internal error: dangerous relocation"
msgstr ""
msgid "relocation should be even number"
msgstr ""
-#: elf32-bfin.c:1591
+#: elf32-bfin.c:1593
msgid "%B(%A+0x%lx): unresolvable relocation against symbol `%s'"
msgstr ""
-#: elf32-bfin.c:1624 elf32-i386.c:4150 elf32-m68k.c:4233 elf32-s390.c:3062
-#: elf64-s390.c:3037 elf64-x86-64.c:3923
+#: elf32-bfin.c:1626 elf32-i386.c:4307 elf32-m68k.c:4233 elf32-s390.c:3055
+#: elf64-s390.c:3030 elf64-x86-64.c:4151
msgid "%B(%A+0x%lx): reloc against `%s': error %d"
msgstr ""
-#: elf32-bfin.c:2723
+#: elf32-bfin.c:2725
msgid "%B: relocation at `%A+0x%x' references symbol `%s' with nonzero addend"
msgstr ""
-#: elf32-bfin.c:2737
+#: elf32-bfin.c:2741
msgid "relocation references symbol not defined in the module"
msgstr ""
-#: elf32-bfin.c:2834
+#: elf32-bfin.c:2838
msgid "R_BFIN_FUNCDESC references dynamic symbol with nonzero addend"
msgstr ""
-#: elf32-bfin.c:2875 elf32-bfin.c:2998
+#: elf32-bfin.c:2879 elf32-bfin.c:3002
msgid "cannot emit fixups in read-only section"
msgstr ""
-#: elf32-bfin.c:2906 elf32-bfin.c:3036 elf32-lm32.c:1103 elf32-sh.c:5021
+#: elf32-bfin.c:2910 elf32-bfin.c:3040 elf32-lm32.c:1103 elf32-sh.c:5016
msgid "cannot emit dynamic relocations in read-only section"
msgstr ""
-#: elf32-bfin.c:2956
+#: elf32-bfin.c:2960
msgid "R_BFIN_FUNCDESC_VALUE references dynamic symbol with nonzero addend"
msgstr ""
-#: elf32-bfin.c:3121
+#: elf32-bfin.c:3125
msgid "relocations between different segments are not supported"
msgstr ""
-#: elf32-bfin.c:3122
+#: elf32-bfin.c:3126
msgid "warning: relocation references a different segment"
msgstr ""
-#: elf32-bfin.c:4967
+#: elf32-bfin.c:4971
msgid "%B: unsupported relocation type %i"
msgstr ""
-#: elf32-bfin.c:5121 elf32-frv.c:6805
+#: elf32-bfin.c:5125 elf32-frv.c:6808
#, c-format
msgid "%s: cannot link non-fdpic object file into fdpic executable"
msgstr ""
-#: elf32-bfin.c:5125 elf32-frv.c:6809
+#: elf32-bfin.c:5129 elf32-frv.c:6812
#, c-format
msgid "%s: cannot link fdpic object file into non-fdpic executable"
msgstr ""
-#: elf32-bfin.c:5279
+#: elf32-bfin.c:5283
#, c-format
msgid "*** check this relocation %s"
msgstr ""
-#: elf32-cris.c:1172
+#: elf32-cris.c:1176
msgid "%B, section %A: unresolvable relocation %s against symbol `%s'"
msgstr ""
-#: elf32-cris.c:1234
+#: elf32-cris.c:1238
msgid "%B, section %A: No PLT nor GOT for relocation %s against symbol `%s'"
msgstr ""
-#: elf32-cris.c:1236
+#: elf32-cris.c:1240
msgid "%B, section %A: No PLT for relocation %s against symbol `%s'"
msgstr ""
-#: elf32-cris.c:1242 elf32-cris.c:1375 elf32-cris.c:1635 elf32-cris.c:1718
-#: elf32-cris.c:1871 elf32-tic6x.c:2660
+#: elf32-cris.c:1246 elf32-cris.c:1379 elf32-cris.c:1639 elf32-cris.c:1722
+#: elf32-cris.c:1875 elf32-tic6x.c:2662
msgid "[whose name is lost]"
msgstr ""
-#: elf32-cris.c:1361 elf32-tic6x.c:2645
+#: elf32-cris.c:1365 elf32-tic6x.c:2647
msgid ""
"%B, section %A: relocation %s with non-zero addend %d against local symbol"
msgstr ""
-#: elf32-cris.c:1369 elf32-cris.c:1712 elf32-cris.c:1865 elf32-tic6x.c:2653
+#: elf32-cris.c:1373 elf32-cris.c:1716 elf32-cris.c:1869 elf32-tic6x.c:2655
msgid ""
"%B, section %A: relocation %s with non-zero addend %d against symbol `%s'"
msgstr ""
-#: elf32-cris.c:1395
+#: elf32-cris.c:1399
msgid "%B, section %A: relocation %s is not allowed for global symbol: `%s'"
msgstr ""
-#: elf32-cris.c:1411
+#: elf32-cris.c:1415
msgid "%B, section %A: relocation %s with no GOT created"
msgstr ""
#. We shouldn't get here for GCC-emitted code.
-#: elf32-cris.c:1626
+#: elf32-cris.c:1630
msgid ""
"%B, section %A: relocation %s has an undefined reference to `%s', perhaps a "
"declaration mixup?"
msgstr ""
-#: elf32-cris.c:1998
+#: elf32-cris.c:2002
msgid ""
"%B, section %A: relocation %s is not allowed for symbol: `%s' which is "
"defined outside the program, perhaps a declaration mixup?"
msgstr ""
-#: elf32-cris.c:2051
+#: elf32-cris.c:2055
msgid "(too many global variables for -fpic: recompile with -fPIC)"
msgstr ""
-#: elf32-cris.c:2058
+#: elf32-cris.c:2062
msgid ""
"(thread-local data too big for -fpic or -msmall-tls: recompile with -fPIC or "
"-mno-small-tls)"
msgstr ""
-#: elf32-cris.c:3248
+#: elf32-cris.c:3261
msgid ""
"%B, section %A:\n"
" v10/v32 compatible object %s must not contain a PIC relocation"
msgstr ""
-#: elf32-cris.c:3353
+#: elf32-cris.c:3366
msgid ""
"%B, section %A:\n"
" relocation %s not valid in a shared object; typically an option mixup, "
"recompile with -fPIC"
msgstr ""
-#: elf32-cris.c:3567
+#: elf32-cris.c:3580
msgid ""
"%B, section %A:\n"
" relocation %s should not be used in a shared object; recompile with -fPIC"
msgstr ""
-#: elf32-cris.c:3992
+#: elf32-cris.c:4002
msgid ""
"%B, section `%A', to symbol `%s':\n"
" relocation %s should not be used in a shared object; recompile with -fPIC"
msgstr ""
-#: elf32-cris.c:4111
+#: elf32-cris.c:4118
msgid "Unexpected machine number"
msgstr ""
-#: elf32-cris.c:4165
+#: elf32-cris.c:4172
#, c-format
msgid " [symbols have a _ prefix]"
msgstr ""
-#: elf32-cris.c:4168
+#: elf32-cris.c:4175
#, c-format
msgid " [v10 and v32]"
msgstr ""
-#: elf32-cris.c:4171
+#: elf32-cris.c:4178
#, c-format
msgid " [v32]"
msgstr ""
-#: elf32-cris.c:4216
+#: elf32-cris.c:4223
msgid "%B: uses _-prefixed symbols, but writing file with non-prefixed symbols"
msgstr ""
-#: elf32-cris.c:4217
+#: elf32-cris.c:4224
msgid "%B: uses non-prefixed symbols, but writing file with _-prefixed symbols"
msgstr ""
-#: elf32-cris.c:4236
+#: elf32-cris.c:4243
msgid "%B contains CRIS v32 code, incompatible with previous objects"
msgstr ""
-#: elf32-cris.c:4238
+#: elf32-cris.c:4245
msgid "%B contains non-CRIS-v32 code, incompatible with previous objects"
msgstr ""
msgid "BFD Link Error: jump (PC rel26) to section (%s) not supported"
msgstr ""
+#. Only if it's not an unresolved symbol.
+#: elf32-epiphany.c:563 elf32-ip2k.c:1475
+msgid "unsupported relocation between data/insn address spaces"
+msgstr ""
+
#: elf32-frv.c:1509 elf32-frv.c:1658
msgid "relocation requires zero addend"
msgstr ""
msgid "%H: relocation to `%s+%v' may have caused the error above\n"
msgstr ""
-#: elf32-frv.c:2902
+#: elf32-frv.c:2905
msgid "%H: relocation references symbol not defined in the module\n"
msgstr ""
-#: elf32-frv.c:2978
+#: elf32-frv.c:2981
msgid "%H: R_FRV_GETTLSOFF not applied to a call instruction\n"
msgstr ""
-#: elf32-frv.c:3019
+#: elf32-frv.c:3022
msgid "%H: R_FRV_GOTTLSDESC12 not applied to an lddi instruction\n"
msgstr ""
-#: elf32-frv.c:3090
+#: elf32-frv.c:3093
msgid "%H: R_FRV_GOTTLSDESCHI not applied to a sethi instruction\n"
msgstr ""
-#: elf32-frv.c:3127
+#: elf32-frv.c:3130
msgid "%H: R_FRV_GOTTLSDESCLO not applied to a setlo or setlos instruction\n"
msgstr ""
-#: elf32-frv.c:3174
+#: elf32-frv.c:3177
msgid "%H: R_FRV_TLSDESC_RELAX not applied to an ldd instruction\n"
msgstr ""
-#: elf32-frv.c:3258
+#: elf32-frv.c:3261
msgid "%H: R_FRV_GETTLSOFF_RELAX not applied to a calll instruction\n"
msgstr ""
-#: elf32-frv.c:3312
+#: elf32-frv.c:3315
msgid "%H: R_FRV_GOTTLSOFF12 not applied to an ldi instruction\n"
msgstr ""
-#: elf32-frv.c:3342
+#: elf32-frv.c:3345
msgid "%H: R_FRV_GOTTLSOFFHI not applied to a sethi instruction\n"
msgstr ""
-#: elf32-frv.c:3371
+#: elf32-frv.c:3374
msgid "%H: R_FRV_GOTTLSOFFLO not applied to a setlo or setlos instruction\n"
msgstr ""
-#: elf32-frv.c:3401
+#: elf32-frv.c:3404
msgid "%H: R_FRV_TLSOFF_RELAX not applied to an ld instruction\n"
msgstr ""
-#: elf32-frv.c:3446
+#: elf32-frv.c:3449
msgid "%H: R_FRV_TLSMOFFHI not applied to a sethi instruction\n"
msgstr ""
-#: elf32-frv.c:3473
+#: elf32-frv.c:3476
msgid "R_FRV_TLSMOFFLO not applied to a setlo or setlos instruction\n"
msgstr ""
-#: elf32-frv.c:3594
+#: elf32-frv.c:3597
msgid "%H: R_FRV_FUNCDESC references dynamic symbol with nonzero addend\n"
msgstr ""
-#: elf32-frv.c:3635 elf32-frv.c:3757
+#: elf32-frv.c:3638 elf32-frv.c:3760
msgid "%H: cannot emit fixups in read-only section\n"
msgstr ""
-#: elf32-frv.c:3666 elf32-frv.c:3800
+#: elf32-frv.c:3669 elf32-frv.c:3803
msgid "%H: cannot emit dynamic relocations in read-only section\n"
msgstr ""
-#: elf32-frv.c:3715
+#: elf32-frv.c:3718
msgid ""
"%H: R_FRV_FUNCDESC_VALUE references dynamic symbol with nonzero addend\n"
msgstr ""
-#: elf32-frv.c:3971
+#: elf32-frv.c:3974
msgid "%H: reloc against `%s' references a different segment\n"
msgstr ""
-#: elf32-frv.c:4121
+#: elf32-frv.c:4124
msgid "%H: reloc against `%s': %s\n"
msgstr ""
-#: elf32-frv.c:6397
+#: elf32-frv.c:6400
msgid "%B: unsupported relocation type %i\n"
msgstr ""
-#: elf32-frv.c:6719
+#: elf32-frv.c:6722
#, c-format
msgid ""
"%s: compiled with %s and linked with modules that use non-pic relocations"
msgstr ""
-#: elf32-frv.c:6772 elf32-iq2000.c:845 elf32-m32c.c:807
+#: elf32-frv.c:6775 elf32-iq2000.c:845 elf32-m32c.c:807
#, c-format
msgid "%s: compiled with %s and linked with modules compiled with %s"
msgstr ""
-#: elf32-frv.c:6784
+#: elf32-frv.c:6787
#, c-format
msgid ""
"%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x"
"%lx)"
msgstr ""
-#: elf32-frv.c:6834 elf32-iq2000.c:882 elf32-m32c.c:843 elf32-mt.c:576
-#: elf32-rx.c:2937
+#: elf32-frv.c:6837 elf32-iq2000.c:882 elf32-m32c.c:843 elf32-mt.c:576
+#: elf32-rx.c:3001
#, c-format
msgid "private flags = 0x%lx:"
msgstr ""
msgid "%B: Relocations in generic ELF (EM: %d)"
msgstr ""
-#: elf32-hppa.c:850 elf32-hppa.c:3610
+#: elf32-hppa.c:850 elf32-hppa.c:3598
msgid "%B(%A+0x%lx): cannot reach %s, recompile with -ffunction-sections"
msgstr ""
"with -fPIC"
msgstr ""
-#: elf32-hppa.c:2803
+#: elf32-hppa.c:2791
msgid "%B: duplicate export stub %s"
msgstr ""
-#: elf32-hppa.c:3449
+#: elf32-hppa.c:3437
msgid ""
"%B(%A+0x%lx): %s fixup for insn 0x%x is not supported in a non-shared link"
msgstr ""
-#: elf32-hppa.c:4296
+#: elf32-hppa.c:4284
msgid "%B(%A+0x%lx): cannot handle %s for %s"
msgstr ""
-#: elf32-hppa.c:4608
+#: elf32-hppa.c:4603
msgid ".got section not immediately after .plt section"
msgstr ""
#. Unknown relocation.
-#: elf32-i386.c:372 elf32-m68k.c:383 elf32-ppc.c:1675 elf32-s390.c:379
-#: elf32-tic6x.c:2682 elf64-ppc.c:2285 elf64-s390.c:403 elf64-x86-64.c:243
+#: elf32-i386.c:373 elf32-m68k.c:384 elf32-ppc.c:1676 elf32-s390.c:379
+#: elf32-tic6x.c:2684 elf64-ppc.c:2300 elf64-s390.c:403 elf64-x86-64.c:265
msgid "%B: invalid relocation type %d"
msgstr ""
-#: elf32-i386.c:1266 elf64-x86-64.c:1116
+#: elf32-i386.c:1404 elf64-x86-64.c:1308
msgid ""
"%B: TLS transition from %s to %s against `%s' at 0x%lx in section `%A' failed"
msgstr ""
-#: elf32-i386.c:1411 elf32-i386.c:3090 elf64-x86-64.c:1296 elf64-x86-64.c:2909
-#: elfxx-sparc.c:3077
+#: elf32-i386.c:1549 elf32-i386.c:3244 elf64-x86-64.c:1487 elf64-x86-64.c:3125
+#: elfxx-sparc.c:3083
msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' isn't handled by %s"
msgstr ""
-#: elf32-i386.c:1573 elf32-s390.c:1182 elf32-sh.c:6367 elf32-xtensa.c:1182
-#: elf64-s390.c:1151 elfxx-sparc.c:1547
+#: elf32-i386.c:1711 elf32-s390.c:1182 elf32-sh.c:6362 elf32-tilepro.c:1434
+#: elf32-xtensa.c:1182 elf64-s390.c:1151 elfxx-sparc.c:1548
+#: elfxx-tilegx.c:1701
msgid "%B: `%s' accessed both as normal and thread local symbol"
msgstr ""
-#: elf32-i386.c:2405 elf64-x86-64.c:2320
+#: elf32-i386.c:2539 elf64-x86-64.c:2506
msgid "%P: %B: warning: relocation against `%s' in readonly section `%A'.\n"
msgstr ""
-#: elf32-i386.c:2496 elf64-x86-64.c:2407
+#: elf32-i386.c:2629 elf64-x86-64.c:2593
msgid "%P: %B: warning: relocation in readonly section `%A'.\n"
msgstr ""
-#: elf32-i386.c:2932
+#: elf32-i386.c:3086 elf32-tilepro.c:2557 elfxx-tilegx.c:2871
msgid "%B: unrecognized relocation (0x%x) in section `%A'"
msgstr ""
-#: elf32-i386.c:3339 elf64-x86-64.c:3295
+#: elf32-i386.c:3494 elf64-x86-64.c:3513
msgid "hidden symbol"
msgstr ""
-#: elf32-i386.c:3342 elf64-x86-64.c:3298
+#: elf32-i386.c:3497 elf64-x86-64.c:3516
msgid "internal symbol"
msgstr ""
-#: elf32-i386.c:3345 elf64-x86-64.c:3301
+#: elf32-i386.c:3500 elf64-x86-64.c:3519
msgid "protected symbol"
msgstr ""
-#: elf32-i386.c:3348 elf64-x86-64.c:3304
+#: elf32-i386.c:3503 elf64-x86-64.c:3522
msgid "symbol"
msgstr ""
-#: elf32-i386.c:3353
+#: elf32-i386.c:3508
msgid ""
"%B: relocation R_386_GOTOFF against undefined %s `%s' can not be used when "
"making a shared object"
msgstr ""
-#: elf32-i386.c:3363
+#: elf32-i386.c:3518
msgid ""
"%B: relocation R_386_GOTOFF against protected function `%s' can not be used "
"when making a shared object"
msgstr ""
-#: elf32-i386.c:4660 elf64-x86-64.c:4378
+#: elf32-i386.c:4839 elf32-tilepro.c:3467 elf64-x86-64.c:4609
+#: elfxx-tilegx.c:3847
#, c-format
msgid "discarded output section: `%A'"
msgstr ""
msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)."
msgstr ""
-#. Only if it's not an unresolved symbol.
-#: elf32-ip2k.c:1475
-msgid "unsupported relocation between data/insn address spaces"
-msgstr ""
-
#: elf32-iq2000.c:858 elf32-m32c.c:819
#, c-format
msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"
msgid "SDA relocation when _SDA_BASE_ not defined"
msgstr ""
-#: elf32-m32r.c:3048
+#: elf32-m32r.c:3043
msgid "%B: The target (%s) of an %s relocation is in the wrong section (%A)"
msgstr ""
-#: elf32-m32r.c:3576
+#: elf32-m32r.c:3571
msgid "%B: Instruction set mismatch with previous modules"
msgstr ""
-#: elf32-m32r.c:3597
+#: elf32-m32r.c:3592
#, c-format
msgid "private flags = %lx"
msgstr ""
-#: elf32-m32r.c:3602
+#: elf32-m32r.c:3597
#, c-format
msgid ": m32r instructions"
msgstr ""
-#: elf32-m32r.c:3603
+#: elf32-m32r.c:3598
#, c-format
msgid ": m32rx instructions"
msgstr ""
-#: elf32-m32r.c:3604
+#: elf32-m32r.c:3599
#, c-format
msgid ": m32r2 instructions"
msgstr ""
msgid "%B: linking files compiled for HCS12 with others compiled for HC12"
msgstr ""
-#: elf32-m68hc1x.c:1257 elf32-ppc.c:4214 elf64-sparc.c:705 elfxx-mips.c:12719
+#: elf32-m68hc1x.c:1257 elf32-ppc.c:4227 elf64-sparc.c:706 elfxx-mips.c:13965
msgid "%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"
msgstr ""
msgid " [memory=flat]"
msgstr ""
-#: elf32-m68k.c:1250 elf32-m68k.c:1251 vms-alpha.c:7311 vms-alpha.c:7326
+#: elf32-m68k.c:1251 elf32-m68k.c:1252 vms-alpha.c:7314 vms-alpha.c:7329
msgid "unknown"
msgstr ""
-#: elf32-m68k.c:1714
+#: elf32-m68k.c:1715
msgid "%B: GOT overflow: Number of relocations with 8-bit offset > %d"
msgstr ""
-#: elf32-m68k.c:1720
+#: elf32-m68k.c:1721
msgid "%B: GOT overflow: Number of relocations with 8- or 16-bit offset > %d"
msgstr ""
-#: elf32-m68k.c:3959
+#: elf32-m68k.c:3957
msgid "%B(%A+0x%lx): R_68K_TLS_LE32 relocation not permitted in shared object"
msgstr ""
msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)"
msgstr ""
-#: elf32-microblaze.c:1155 elfxx-sparc.c:3451
+#: elf32-microblaze.c:1155 elf32-tilepro.c:2891 elfxx-sparc.c:3457
+#: elfxx-tilegx.c:3230
msgid "%B: probably compiled without -fPIC?"
msgstr ""
msgid "%B: bad relocation section name `%s'"
msgstr ""
-#: elf32-mips.c:1045 elf64-mips.c:2084 elfn32-mips.c:1888
+#: elf32-mips.c:1549 elf64-mips.c:2683 elfn32-mips.c:2487
msgid "literal relocation occurs for an external symbol"
msgstr ""
-#: elf32-mips.c:1085 elf32-score.c:569 elf32-score7.c:469 elf64-mips.c:2127
-#: elfn32-mips.c:1929
+#: elf32-mips.c:1596 elf32-score.c:570 elf32-score7.c:469 elf64-mips.c:2726
+#: elfn32-mips.c:2528
msgid "32bits gp relative relocation occurs for an external symbol"
msgstr ""
-#: elf32-ppc.c:1740
+#: elf32-ppc.c:1741
#, c-format
msgid "generic linker can't handle %s"
msgstr ""
-#: elf32-ppc.c:2183
+#: elf32-ppc.c:2184
msgid "corrupt %s section in %B"
msgstr ""
-#: elf32-ppc.c:2202
+#: elf32-ppc.c:2203
msgid "unable to read in %s section from %B"
msgstr ""
-#: elf32-ppc.c:2243
+#: elf32-ppc.c:2244
msgid "warning: unable to set size of %s section in %B"
msgstr ""
-#: elf32-ppc.c:2293
+#: elf32-ppc.c:2294
msgid "failed to allocate space for new APUinfo section."
msgstr ""
-#: elf32-ppc.c:2312
+#: elf32-ppc.c:2313
msgid "failed to compute new APUinfo section."
msgstr ""
-#: elf32-ppc.c:2315
+#: elf32-ppc.c:2316
msgid "failed to install new APUinfo section."
msgstr ""
-#: elf32-ppc.c:3343
+#: elf32-ppc.c:3356
msgid "%B: relocation %s cannot be used when making a shared object"
msgstr ""
#. It does not make sense to have a procedure linkage
#. table entry for a local symbol.
-#: elf32-ppc.c:3687
-msgid "%H: %s reloc against local symbol\n"
+#: elf32-ppc.c:3700
+msgid "%P: %H: %s reloc against local symbol\n"
msgstr ""
-#: elf32-ppc.c:4026 elf32-ppc.c:4041 elfxx-mips.c:12423 elfxx-mips.c:12449
-#: elfxx-mips.c:12471 elfxx-mips.c:12497
+#: elf32-ppc.c:4039 elf32-ppc.c:4054 elfxx-mips.c:13651 elfxx-mips.c:13677
+#: elfxx-mips.c:13699 elfxx-mips.c:13725
msgid "Warning: %B uses hard float, %B uses soft float"
msgstr ""
-#: elf32-ppc.c:4029 elf32-ppc.c:4033
+#: elf32-ppc.c:4042 elf32-ppc.c:4046
msgid ""
"Warning: %B uses double-precision hard float, %B uses single-precision hard "
"float"
msgstr ""
-#: elf32-ppc.c:4037
+#: elf32-ppc.c:4050
msgid "Warning: %B uses soft float, %B uses single-precision hard float"
msgstr ""
-#: elf32-ppc.c:4044 elf32-ppc.c:4048 elfxx-mips.c:12403 elfxx-mips.c:12407
+#: elf32-ppc.c:4057 elf32-ppc.c:4061 elfxx-mips.c:13631 elfxx-mips.c:13635
msgid "Warning: %B uses unknown floating point ABI %d"
msgstr ""
-#: elf32-ppc.c:4090 elf32-ppc.c:4094
+#: elf32-ppc.c:4103 elf32-ppc.c:4107
msgid "Warning: %B uses unknown vector ABI %d"
msgstr ""
-#: elf32-ppc.c:4098
+#: elf32-ppc.c:4111
msgid "Warning: %B uses vector ABI \"%s\", %B uses \"%s\""
msgstr ""
-#: elf32-ppc.c:4115 elf32-ppc.c:4118
+#: elf32-ppc.c:4128 elf32-ppc.c:4131
msgid "Warning: %B uses r3/r4 for small structure returns, %B uses memory"
msgstr ""
-#: elf32-ppc.c:4121 elf32-ppc.c:4125
+#: elf32-ppc.c:4134 elf32-ppc.c:4138
msgid "Warning: %B uses unknown small structure return convention %d"
msgstr ""
-#: elf32-ppc.c:4179
+#: elf32-ppc.c:4192
msgid ""
"%B: compiled with -mrelocatable and linked with modules compiled normally"
msgstr ""
-#: elf32-ppc.c:4187
+#: elf32-ppc.c:4200
msgid ""
"%B: compiled normally and linked with modules compiled with -mrelocatable"
msgstr ""
-#: elf32-ppc.c:4275
-msgid "Using bss-plt due to %B"
+#: elf32-ppc.c:4309
+msgid "%P: bss-plt forced due to %B\n"
+msgstr ""
+
+#: elf32-ppc.c:4312
+msgid "%P: bss-plt forced by profiling\n"
msgstr ""
#. Uh oh, we didn't find the expected call. We
#. could just mark this symbol to exclude it
#. from tls optimization but it's safer to skip
#. the entire optimization.
-#: elf32-ppc.c:4771 elf64-ppc.c:7778
+#: elf32-ppc.c:4809 elf64-ppc.c:7858
msgid "%H arg lost __tls_get_addr, TLS optimization disabled\n"
msgstr ""
-#: elf32-ppc.c:5006 elf64-ppc.c:6494
-#, c-format
-msgid "dynamic variable `%s' is zero size\n"
+#: elf32-ppc.c:5044 elf64-ppc.c:6528
+msgid "%P: dynamic variable `%s' is zero size\n"
msgstr ""
-#: elf32-ppc.c:7204 elf64-ppc.c:12431
-msgid "%B: unknown relocation type %d for symbol %s\n"
+#: elf32-ppc.c:7263 elf64-ppc.c:12675
+msgid "%P: %B: unknown relocation type %d for symbol %s\n"
msgstr ""
-#: elf32-ppc.c:7465
-msgid "%H: non-zero addend on %s reloc against `%s'\n"
+#: elf32-ppc.c:7524
+msgid "%P: %H: non-zero addend on %s reloc against `%s'\n"
msgstr ""
-#: elf32-ppc.c:7661 elf64-ppc.c:12936
-msgid "%H: relocation %s for indirect function %s unsupported\n"
+#: elf32-ppc.c:7720 elf64-ppc.c:13181
+msgid "%P: %H: relocation %s for indirect function %s unsupported\n"
msgstr ""
-#: elf32-ppc.c:7889 elf32-ppc.c:7919 elf32-ppc.c:7966
+#: elf32-ppc.c:7948 elf32-ppc.c:7978 elf32-ppc.c:8025
msgid ""
-"%B: the target (%s) of a %s relocation is in the wrong output section (%s)\n"
+"%P: %B: the target (%s) of a %s relocation is in the wrong output section "
+"(%s)\n"
msgstr ""
-#: elf32-ppc.c:8038
-msgid "%B: relocation %s is not yet supported for symbol %s\n"
+#: elf32-ppc.c:8097
+msgid "%P: %B: relocation %s is not yet supported for symbol %s\n"
msgstr ""
-#: elf32-ppc.c:8097 elf64-ppc.c:13237
-msgid "%H: unresolvable %s relocation against symbol `%s'\n"
+#: elf32-ppc.c:8158 elf64-ppc.c:13467
+msgid "%P: %H: unresolvable %s relocation against symbol `%s'\n"
msgstr ""
-#: elf32-ppc.c:8144 elf64-ppc.c:13282
-msgid "%H: %s reloc against `%s': error %d\n"
+#: elf32-ppc.c:8205 elf64-ppc.c:13512
+msgid "%P: %H: %s reloc against `%s': error %d\n"
msgstr ""
-#: elf32-ppc.c:8635
-#, c-format
-msgid "%s not defined in linker created %s\n"
+#: elf32-ppc.c:8696
+msgid "%P: %s not defined in linker created %s\n"
msgstr ""
-#: elf32-rx.c:553
+#: elf32-rx.c:563
msgid "%B:%A: Warning: deprecated Red Hat reloc "
msgstr ""
-#: elf32-rx.c:1095
+#. Check for unsafe relocs in PID mode. These are any relocs where
+#. an absolute address is being computed. There are special cases
+#. for relocs against symbols that are known to be referenced in
+#. crt0.o before the PID base address register has been initialised.
+#: elf32-rx.c:581
+msgid "%B(%A): unsafe PID relocation %s at 0x%08lx (against %s in %s)"
+msgstr ""
+
+#: elf32-rx.c:1157
msgid "Warning: RX_SYM reloc with an unknown symbol"
msgstr ""
-#: elf32-rx.c:1260
+#: elf32-rx.c:1324
msgid "%B(%A): error: call to undefined function '%s'"
msgstr ""
-#: elf32-rx.c:1274
+#: elf32-rx.c:1338
msgid "%B(%A): warning: unaligned access to symbol '%s' in the small data area"
msgstr ""
-#: elf32-rx.c:1278
+#: elf32-rx.c:1342
msgid "%B(%A): internal error: out of range error"
msgstr ""
-#: elf32-rx.c:1282
+#: elf32-rx.c:1346
msgid "%B(%A): internal error: unsupported relocation error"
msgstr ""
-#: elf32-rx.c:1286
+#: elf32-rx.c:1350
msgid "%B(%A): internal error: dangerous relocation"
msgstr ""
-#: elf32-rx.c:1290
+#: elf32-rx.c:1354
msgid "%B(%A): internal error: unknown error"
msgstr ""
-#: elf32-rx.c:2940
+#: elf32-rx.c:3004
#, c-format
msgid " [64-bit doubles]"
msgstr ""
-#: elf32-rx.c:2942
+#: elf32-rx.c:3006
#, c-format
msgid " [dsp]"
msgstr ""
-#: elf32-s390.c:2209 elf64-s390.c:2196
+#: elf32-s390.c:2200 elf64-s390.c:2187
msgid "%B(%A+0x%lx): invalid instruction for TLS relocation %s"
msgstr ""
-#: elf32-score.c:1522 elf32-score7.c:1382 elfxx-mips.c:3324
+#: elf32-score.c:1520 elf32-score7.c:1379 elfxx-mips.c:3435
msgid "not enough GOT space for local GOT entries"
msgstr ""
-#: elf32-score.c:2744
+#: elf32-score.c:2742
msgid "address not word align"
msgstr ""
-#: elf32-score.c:2829 elf32-score7.c:2634
+#: elf32-score.c:2827 elf32-score7.c:2631
#, c-format
msgid "%s: Malformed reloc detected for section %s"
msgstr ""
-#: elf32-score.c:2880 elf32-score7.c:2685
+#: elf32-score.c:2878 elf32-score7.c:2682
msgid "%B: CALL15 reloc at 0x%lx not against global symbol"
msgstr ""
-#: elf32-score.c:3999 elf32-score7.c:3806
+#: elf32-score.c:3997 elf32-score7.c:3803
#, c-format
msgid " [pic]"
msgstr ""
-#: elf32-score.c:4003 elf32-score7.c:3810
+#: elf32-score.c:4001 elf32-score7.c:3807
#, c-format
msgid " [fix dep]"
msgstr ""
-#: elf32-score.c:4045 elf32-score7.c:3852
+#: elf32-score.c:4043 elf32-score7.c:3849
msgid "%B: warning: linking PIC files with non-PIC files"
msgstr ""
msgid "%B: 0x%lx: fatal: reloc overflow while relaxing"
msgstr ""
-#: elf32-sh.c:4057 elf64-sh64.c:1514
+#: elf32-sh.c:4048 elf64-sh64.c:1514
msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled"
msgstr ""
-#: elf32-sh.c:4304
+#: elf32-sh.c:4299
msgid "%B: 0x%lx: fatal: unaligned branch target for relax-support relocation"
msgstr ""
-#: elf32-sh.c:4337 elf32-sh.c:4352
+#: elf32-sh.c:4332 elf32-sh.c:4347
msgid "%B: 0x%lx: fatal: unaligned %s relocation 0x%lx"
msgstr ""
-#: elf32-sh.c:4366
+#: elf32-sh.c:4361
msgid "%B: 0x%lx: fatal: R_SH_PSHA relocation %d not in range -32..32"
msgstr ""
-#: elf32-sh.c:4380
+#: elf32-sh.c:4375
msgid "%B: 0x%lx: fatal: R_SH_PSHL relocation %d not in range -32..32"
msgstr ""
-#: elf32-sh.c:4524 elf32-sh.c:4994
+#: elf32-sh.c:4519 elf32-sh.c:4989
msgid "%B(%A+0x%lx): cannot emit fixup to `%s' in read-only section"
msgstr ""
-#: elf32-sh.c:5101
+#: elf32-sh.c:5096
msgid "%B(%A+0x%lx): %s relocation against external symbol \"%s\""
msgstr ""
-#: elf32-sh.c:5574
+#: elf32-sh.c:5569
#, c-format
msgid "%X%C: relocation to \"%s\" references a different segment\n"
msgstr ""
-#: elf32-sh.c:5580
+#: elf32-sh.c:5575
#, c-format
msgid "%C: warning: relocation to \"%s\" references a different segment\n"
msgstr ""
-#: elf32-sh.c:6358 elf32-sh.c:6441
+#: elf32-sh.c:6353 elf32-sh.c:6436
msgid "%B: `%s' accessed both as normal and FDPIC symbol"
msgstr ""
-#: elf32-sh.c:6363 elf32-sh.c:6445
+#: elf32-sh.c:6358 elf32-sh.c:6440
msgid "%B: `%s' accessed both as FDPIC and thread local symbol"
msgstr ""
-#: elf32-sh.c:6393
+#: elf32-sh.c:6388
msgid "%B: Function descriptor relocation with non-zero addend"
msgstr ""
-#: elf32-sh.c:6629 elf64-alpha.c:4648
+#: elf32-sh.c:6624 elf64-alpha.c:4652
msgid "%B: TLS local exec code cannot be linked into shared objects"
msgstr ""
-#: elf32-sh64.c:223 elf64-sh64.c:2314
+#: elf32-sh64.c:223 elf64-sh64.c:2318
#, c-format
msgid "%s: compiled as 32-bit object and %s is 64-bit"
msgstr ""
-#: elf32-sh64.c:226 elf64-sh64.c:2317
+#: elf32-sh64.c:226 elf64-sh64.c:2321
#, c-format
msgid "%s: compiled as 64-bit object and %s is 32-bit"
msgstr ""
-#: elf32-sh64.c:228 elf64-sh64.c:2319
+#: elf32-sh64.c:228 elf64-sh64.c:2323
#, c-format
msgid "%s: object size does not match that of target %s"
msgstr ""
-#: elf32-sh64.c:451 elf64-sh64.c:2833
+#: elf32-sh64.c:451 elf64-sh64.c:2837
#, c-format
msgid "%s: encountered datalabel symbol in input"
msgstr ""
msgid "%s: could not write out sorted .cranges entries"
msgstr ""
-#: elf32-sparc.c:89
+#: elf32-sparc.c:90
msgid "%B: compiled for a 64 bit system and target is 32 bit"
msgstr ""
-#: elf32-sparc.c:102
+#: elf32-sparc.c:103
msgid "%B: linking little endian files with big endian files"
msgstr ""
msgid "fatal error while creating .fixup"
msgstr ""
-#: elf32-spu.c:5006
+#: elf32-spu.c:5008
msgid "%B(%s+0x%lx): unresolvable %s relocation against symbol `%s'"
msgstr ""
msgid "warning: generating a shared library containing non-PID code"
msgstr ""
-#: elf32-tic6x.c:2539
+#: elf32-tic6x.c:2541
msgid "%B: SB-relative relocation but __c6xabi_DSBT_BASE not defined"
msgstr ""
-#: elf32-tic6x.c:2759
+#: elf32-tic6x.c:2761
msgid "dangerous relocation"
msgstr ""
-#: elf32-tic6x.c:3740
+#: elf32-tic6x.c:3733
msgid "%B: error: unknown mandatory EABI object attribute %d"
msgstr ""
-#: elf32-tic6x.c:3748
+#: elf32-tic6x.c:3741
msgid "%B: warning: unknown EABI object attribute %d"
msgstr ""
-#: elf32-tic6x.c:3860 elf32-tic6x.c:3868
+#: elf32-tic6x.c:3853 elf32-tic6x.c:3861
msgid "error: %B requires more stack alignment than %B preserves"
msgstr ""
-#: elf32-tic6x.c:3878 elf32-tic6x.c:3887
+#: elf32-tic6x.c:3871 elf32-tic6x.c:3880
msgid "error: unknown Tag_ABI_array_object_alignment value in %B"
msgstr ""
-#: elf32-tic6x.c:3896 elf32-tic6x.c:3905
+#: elf32-tic6x.c:3889 elf32-tic6x.c:3898
msgid "error: unknown Tag_ABI_array_object_align_expected value in %B"
msgstr ""
-#: elf32-tic6x.c:3913 elf32-tic6x.c:3920
+#: elf32-tic6x.c:3906 elf32-tic6x.c:3913
msgid "error: %B requires more array alignment than %B preserves"
msgstr ""
-#: elf32-tic6x.c:3942
+#: elf32-tic6x.c:3935
msgid "warning: %B and %B differ in wchar_t size"
msgstr ""
-#: elf32-tic6x.c:3960
+#: elf32-tic6x.c:3953
msgid "warning: %B and %B differ in whether code is compiled for DSBT"
msgstr ""
msgid "v850e2v3 architecture"
msgstr ""
-#: elf32-vax.c:531
+#: elf32-vax.c:532
#, c-format
msgid " [nonpic]"
msgstr ""
-#: elf32-vax.c:534
+#: elf32-vax.c:535
#, c-format
msgid " [d-float]"
msgstr ""
-#: elf32-vax.c:537
+#: elf32-vax.c:538
#, c-format
msgid " [g-float]"
msgstr ""
-#: elf32-vax.c:654
+#: elf32-vax.c:655
#, c-format
msgid ""
"%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of "
"%ld"
msgstr ""
-#: elf32-vax.c:1587
+#: elf32-vax.c:1585
#, c-format
msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored"
msgstr ""
-#: elf32-vax.c:1714
+#: elf32-vax.c:1712
#, c-format
msgid "%s: warning: %s relocation against symbol `%s' from %s section"
msgstr ""
-#: elf32-vax.c:1720
+#: elf32-vax.c:1718
#, c-format
msgid "%s: warning: %s relocation to 0x%x from %s section"
msgstr ""
-#: elf32-xstormy16.c:451 elf32-ia64.c:2342 elf64-ia64.c:2342
+#: elf32-xstormy16.c:451 elf32-ia64.c:2336 elf64-ia64.c:2336
msgid "non-zero addend in @fptr reloc"
msgstr ""
msgid "%B(%A): invalid property table"
msgstr ""
-#: elf32-xtensa.c:2780
+#: elf32-xtensa.c:2777
msgid "%B(%A+0x%lx): relocation offset out of range (size=0x%x)"
msgstr ""
-#: elf32-xtensa.c:2859 elf32-xtensa.c:2980
+#: elf32-xtensa.c:2856 elf32-xtensa.c:2977
msgid "dynamic relocation in read-only section"
msgstr ""
-#: elf32-xtensa.c:2956
+#: elf32-xtensa.c:2953
msgid "TLS relocation invalid without dynamic sections"
msgstr ""
-#: elf32-xtensa.c:3173
+#: elf32-xtensa.c:3172
msgid "internal inconsistency in size of .got.loc section"
msgstr ""
-#: elf32-xtensa.c:3486
+#: elf32-xtensa.c:3485
msgid "%B: incompatible machine type. Output is 0x%x. Input is 0x%x"
msgstr ""
-#: elf32-xtensa.c:4715 elf32-xtensa.c:4723
+#: elf32-xtensa.c:4714 elf32-xtensa.c:4722
msgid "Attempt to convert L32R/CALLX to CALL failed"
msgstr ""
-#: elf32-xtensa.c:6333 elf32-xtensa.c:6409 elf32-xtensa.c:7525
+#: elf32-xtensa.c:6332 elf32-xtensa.c:6408 elf32-xtensa.c:7524
msgid ""
"%B(%A+0x%lx): could not decode instruction; possible configuration mismatch"
msgstr ""
-#: elf32-xtensa.c:7265
+#: elf32-xtensa.c:7264
msgid ""
"%B(%A+0x%lx): could not decode instruction for XTENSA_ASM_SIMPLIFY "
"relocation; possible configuration mismatch"
msgstr ""
-#: elf32-xtensa.c:9024
+#: elf32-xtensa.c:9023
msgid "invalid relocation address"
msgstr ""
-#: elf32-xtensa.c:9073
+#: elf32-xtensa.c:9072
msgid "overflow after relaxation"
msgstr ""
-#: elf32-xtensa.c:10205
+#: elf32-xtensa.c:10204
msgid "%B(%A+0x%lx): unexpected fix for %s relocation"
msgstr ""
msgid "GPDISP relocation did not find ldah and lda instructions"
msgstr ""
-#: elf64-alpha.c:2495
+#: elf64-alpha.c:2497
msgid "%B: .got subsegment exceeds 64K (size %d)"
msgstr ""
-#: elf64-alpha.c:4392 elf64-alpha.c:4404
+#: elf64-alpha.c:4387 elf64-alpha.c:4399
msgid "%B: gp-relative relocation against dynamic symbol %s"
msgstr ""
-#: elf64-alpha.c:4430 elf64-alpha.c:4565
+#: elf64-alpha.c:4425 elf64-alpha.c:4565
msgid "%B: pc-relative relocation against dynamic symbol %s"
msgstr ""
-#: elf64-alpha.c:4458
+#: elf64-alpha.c:4453
msgid "%B: change in gp: BRSGP %s"
msgstr ""
-#: elf64-alpha.c:4483
+#: elf64-alpha.c:4478
msgid "<unknown>"
msgstr ""
-#: elf64-alpha.c:4488
+#: elf64-alpha.c:4483
msgid "%B: !samegp reloc against symbol without .prologue: %s"
msgstr ""
msgid "%B: pc-relative relocation against undefined weak symbol %s"
msgstr ""
-#: elf64-alpha.c:4632
+#: elf64-alpha.c:4636
msgid "%B: dtp-relative relocation against dynamic symbol %s"
msgstr ""
-#: elf64-alpha.c:4655
+#: elf64-alpha.c:4659
msgid "%B: tp-relative relocation against dynamic symbol %s"
msgstr ""
-#: elf64-hppa.c:2094
+#: elf64-hppa.c:2083
#, c-format
msgid "stub entry for %s cannot load .plt, dp offset = %ld"
msgstr ""
-#: elf64-hppa.c:3292
-msgid "%B(%A+0x%lx): cannot reach %s"
+#: elf64-hppa.c:3275
+msgid "%B(%A+0x"
+msgstr ""
+
+#: elf64-mmix.c:1034
+msgid ""
+"invalid input relocation when producing non-ELF, non-mmo format output.\n"
+" Please use the objcopy program to convert from ELF or mmo,\n"
+" or assemble using \"-no-expand\" (for gcc, \"-Wa,-no-expand\""
+msgstr ""
+
+#: elf64-mmix.c:1218
+msgid ""
+"invalid input relocation when producing non-ELF, non-mmo format output.\n"
+" Please use the objcopy program to convert from ELF or mmo,\n"
+" or compile using the gcc-option \"-mno-base-addresses\"."
msgstr ""
-#: elf64-mmix.c:1177
+#: elf64-mmix.c:1244
#, c-format
msgid ""
"%s: Internal inconsistency error for value for\n"
"%08lx\n"
msgstr ""
-#: elf64-mmix.c:1607
+#: elf64-mmix.c:1670
#, c-format
msgid ""
"%s: base-plus-offset relocation against register symbol: (unknown) in %s"
msgstr ""
-#: elf64-mmix.c:1612
+#: elf64-mmix.c:1675
#, c-format
msgid "%s: base-plus-offset relocation against register symbol: %s in %s"
msgstr ""
-#: elf64-mmix.c:1656
+#: elf64-mmix.c:1719
#, c-format
msgid "%s: register relocation against non-register symbol: (unknown) in %s"
msgstr ""
-#: elf64-mmix.c:1661
+#: elf64-mmix.c:1724
#, c-format
msgid "%s: register relocation against non-register symbol: %s in %s"
msgstr ""
-#: elf64-mmix.c:1698
+#: elf64-mmix.c:1761
#, c-format
msgid "%s: directive LOCAL valid only with a register or absolute value"
msgstr ""
-#: elf64-mmix.c:1726
+#: elf64-mmix.c:1789
#, c-format
msgid ""
"%s: LOCAL directive: Register $%ld is not a local register. First global "
"register is $%ld."
msgstr ""
-#: elf64-mmix.c:2190
+#: elf64-mmix.c:2253
#, c-format
msgid ""
"%s: Error: multiple definition of `%s'; start of %s is set in a earlier "
"linked file\n"
msgstr ""
-#: elf64-mmix.c:2248
+#: elf64-mmix.c:2311
msgid "Register section has contents\n"
msgstr ""
-#: elf64-mmix.c:2440
+#: elf64-mmix.c:2503
#, c-format
msgid ""
"Internal inconsistency: remaining %u != max %u.\n"
" Please report this bug."
msgstr ""
-#: elf64-ppc.c:2744 libbfd.c:1012
-msgid "%B: compiled for a big endian system and target is little endian"
-msgstr ""
-
-#: elf64-ppc.c:2747 libbfd.c:1014
-msgid "%B: compiled for a little endian system and target is big endian"
+#: elf64-ppc.c:4185
+msgid "%P: %B: cannot create stub entry %s\n"
msgstr ""
-#: elf64-ppc.c:4160
-msgid "%B: cannot create stub entry %s\n"
-msgstr ""
-
-#: elf64-ppc.c:6484
-#, c-format
+#: elf64-ppc.c:6518
msgid ""
-"copy reloc against `%s' requires lazy plt linking; avoid setting "
+"%P: copy reloc against `%s' requires lazy plt linking; avoid setting "
"LD_BIND_NOW=1 or upgrade gcc\n"
msgstr ""
-#: elf64-ppc.c:6912
-msgid "dynreloc miscount for %B, section %A\n"
+#: elf64-ppc.c:6788
+msgid "%B: undefined symbol on R_PPC64_TOCSAVE relocation"
+msgstr ""
+
+#: elf64-ppc.c:6992
+msgid "%P: dynreloc miscount for %B, section %A\n"
msgstr ""
-#: elf64-ppc.c:6996
+#: elf64-ppc.c:7076
msgid "%B: .opd is not a regular array of opd entries"
msgstr ""
-#: elf64-ppc.c:7005
+#: elf64-ppc.c:7085
msgid "%B: unexpected reloc type %u in .opd section"
msgstr ""
-#: elf64-ppc.c:7026
+#: elf64-ppc.c:7106
msgid "%B: undefined sym `%s' in .opd section"
msgstr ""
-#: elf64-ppc.c:7584
+#: elf64-ppc.c:7664
msgid "%H __tls_get_addr lost arg, TLS optimization disabled\n"
msgstr ""
-#: elf64-ppc.c:7929 elf64-ppc.c:8450
+#: elf64-ppc.c:8003 elf64-ppc.c:8564
#, c-format
msgid "%s defined on removed toc entry"
msgstr ""
-#: elf64-ppc.c:9474
-#, c-format
-msgid "cannot find opd entry toc for %s\n"
+#: elf64-ppc.c:8521
+msgid "%P: %H: %s relocation references optimized away TOC entry\n"
msgstr ""
-#: elf64-ppc.c:9556
-#, c-format
-msgid "long branch stub `%s' offset overflow\n"
+#: elf64-ppc.c:9598
+msgid "%P: cannot find opd entry toc for %s\n"
msgstr ""
-#: elf64-ppc.c:9615
-#, c-format
-msgid "can't find branch stub `%s'\n"
+#: elf64-ppc.c:9680
+msgid "%P: long branch stub `%s' offset overflow\n"
msgstr ""
-#: elf64-ppc.c:9677 elf64-ppc.c:9819
-#, c-format
-msgid "linkage table error against `%s'\n"
+#: elf64-ppc.c:9739
+msgid "%P: can't find branch stub `%s'\n"
msgstr ""
-#: elf64-ppc.c:9993
-#, c-format
-msgid "can't build branch stub `%s'\n"
+#: elf64-ppc.c:9801 elf64-ppc.c:9943
+msgid "%P: linkage table error against `%s'\n"
+msgstr ""
+
+#: elf64-ppc.c:10126
+msgid "%P: can't build branch stub `%s'\n"
msgstr ""
-#: elf64-ppc.c:10814
+#: elf64-ppc.c:10941
msgid "%B section %A exceeds stub group size"
msgstr ""
-#: elf64-ppc.c:11457
-msgid "stubs don't match calculated size\n"
+#: elf64-ppc.c:11666 elf64-ppc.c:11699
+msgid "%P: %s offset too large for .eh_frame sdata4 encoding"
msgstr ""
-#: elf64-ppc.c:11469
+#: elf64-ppc.c:11744
+msgid "%P: stubs don't match calculated size\n"
+msgstr ""
+
+#: elf64-ppc.c:11756
#, c-format
msgid ""
"linker stubs in %u group%s\n"
" plt call %lu"
msgstr ""
-#: elf64-ppc.c:11819
-msgid "%H: %s used with TLS symbol %s\n"
+#: elf64-ppc.c:12042
+msgid "%P: %H: %s used with TLS symbol %s\n"
msgstr ""
-#: elf64-ppc.c:11820
-msgid "%H: %s used with non-TLS symbol %s\n"
+#: elf64-ppc.c:12043
+msgid "%P: %H: %s used with non-TLS symbol %s\n"
msgstr ""
-#: elf64-ppc.c:12318
+#: elf64-ppc.c:12556
msgid ""
-"%H: automatic multiple TOCs not supported using your crt files; recompile "
-"with -mminimal-toc or upgrade gcc\n"
+"%P: %H: automatic multiple TOCs not supported using your crt files; "
+"recompile with -mminimal-toc or upgrade gcc\n"
msgstr ""
-#: elf64-ppc.c:12324
+#: elf64-ppc.c:12562
msgid ""
-"%H: sibling call optimization to `%s' does not allow automatic multiple "
+"%P: %H: sibling call optimization to `%s' does not allow automatic multiple "
"TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `"
"%s' extern\n"
msgstr ""
-#: elf64-ppc.c:13041
-msgid "%B: relocation %s is not supported for symbol %s\n"
+#: elf64-ppc.c:13286
+msgid "%P: %B: relocation %s is not supported for symbol %s\n"
msgstr ""
-#: elf64-ppc.c:13218
-msgid "%H: error: %s not a multiple of %u\n"
+#: elf64-ppc.c:13446
+msgid "%P: %H: error: %s not a multiple of %u\n"
msgstr ""
-#: elf64-sh64.c:1682
+#: elf64-sh64.c:1686
#, c-format
msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n"
msgstr ""
-#: elf64-sparc.c:445
+#: elf64-sparc.c:446
msgid "%B: Only registers %%g[2367] can be declared using STT_REGISTER"
msgstr ""
-#: elf64-sparc.c:465
+#: elf64-sparc.c:466
msgid "Register %%g%d used incompatibly: %s in %B, previously %s in %B"
msgstr ""
-#: elf64-sparc.c:488
+#: elf64-sparc.c:489
msgid "Symbol `%s' has differing types: REGISTER in %B, previously %s in %B"
msgstr ""
-#: elf64-sparc.c:533
+#: elf64-sparc.c:534
msgid "Symbol `%s' has differing types: %s in %B, previously REGISTER in %B"
msgstr ""
-#: elf64-sparc.c:686
+#: elf64-sparc.c:687
msgid "%B: linking UltraSPARC specific with HAL specific code"
msgstr ""
-#: elf64-x86-64.c:1236
+#: elf64-x86-64.c:1427
msgid "%B: relocation %s against symbol `%s' isn't supported in x32 mode"
msgstr ""
-#: elf64-x86-64.c:1465
+#: elf64-x86-64.c:1656
msgid "%B: '%s' accessed both as normal and thread local symbol"
msgstr ""
-#: elf64-x86-64.c:2934
+#: elf64-x86-64.c:3150
msgid ""
"%B: relocation %s against STT_GNU_IFUNC symbol `%s' has non-zero addend: %d"
msgstr ""
-#: elf64-x86-64.c:3193
+#: elf64-x86-64.c:3411
msgid ""
"%B: relocation R_X86_64_GOTOFF64 against protected function `%s' can not be "
"used when making a shared object"
msgstr ""
-#: elf64-x86-64.c:3305
+#: elf64-x86-64.c:3523
msgid "; recompile with -fPIC"
msgstr ""
-#: elf64-x86-64.c:3310
+#: elf64-x86-64.c:3528
msgid ""
"%B: relocation %s against %s `%s' can not be used when making a shared object"
"%s"
msgstr ""
-#: elf64-x86-64.c:3312
+#: elf64-x86-64.c:3530
msgid ""
"%B: relocation %s against undefined %s `%s' can not be used when making a "
"shared object%s"
msgstr ""
-#: elfcode.h:827
+#: elfcode.h:767
#, c-format
msgid "warning: %s has a corrupt string table index - ignoring"
msgstr ""
-#: elfcode.h:1237
+#: elfcode.h:1177
#, c-format
msgid "%s: version count (%ld) does not match symbol count (%ld)"
msgstr ""
-#: elfcode.h:1491
+#: elfcode.h:1431
#, c-format
msgid "%s(%s): relocation %d has invalid symbol index %ld"
msgstr ""
msgid "Warning: %B is truncated: expected core file size >= %lu, found: %lu."
msgstr ""
-#: elflink.c:1119
+#: elflink.c:1117
msgid ""
"%s: TLS definition in %B section %A mismatches non-TLS definition in %B "
"section %A"
msgstr ""
-#: elflink.c:1123
+#: elflink.c:1121
msgid "%s: TLS reference in %B mismatches non-TLS reference in %B"
msgstr ""
-#: elflink.c:1127
+#: elflink.c:1125
msgid "%s: TLS definition in %B section %A mismatches non-TLS reference in %B"
msgstr ""
-#: elflink.c:1131
+#: elflink.c:1129
msgid "%s: TLS reference in %B mismatches non-TLS definition in %B section %A"
msgstr ""
-#: elflink.c:1764
+#: elflink.c:1762
msgid "%B: unexpected redefinition of indirect versioned symbol `%s'"
msgstr ""
-#: elflink.c:2077
+#: elflink.c:2063
msgid "%B: version node not found for symbol %s"
msgstr ""
-#: elflink.c:2167
+#: elflink.c:2154
msgid ""
"%B: bad reloc symbol index (0x%lx >= 0x%lx) for offset 0x%lx in section `%A'"
msgstr ""
-#: elflink.c:2178
+#: elflink.c:2165
msgid ""
"%B: non-zero symbol index (0x%lx) for offset 0x%lx in section `%A' when the "
"object file has no symbol table"
msgstr ""
-#: elflink.c:2368
+#: elflink.c:2355
msgid "%B: relocation size mismatch in %B section %A"
msgstr ""
-#: elflink.c:2663
+#: elflink.c:2639
#, c-format
msgid "warning: type and size of dynamic symbol `%s' are not defined"
msgstr ""
-#: elflink.c:3421
+#: elflink.c:3391
msgid "%P: alternate ELF machine code found (%d) in %B, expecting %d\n"
msgstr ""
-#: elflink.c:4067
+#: elflink.c:4037
msgid "%B: %s: invalid version %u (max %d)"
msgstr ""
-#: elflink.c:4103
+#: elflink.c:4073
msgid "%B: %s: invalid needed version %d"
msgstr ""
-#: elflink.c:4299
+#: elflink.c:4269
msgid ""
"Warning: alignment %u of common symbol `%s' in %B is greater than the "
"alignment (%u) of its section %A"
msgstr ""
-#: elflink.c:4305
+#: elflink.c:4275
msgid "Warning: alignment %u of symbol `%s' in %B is smaller than %u in %B"
msgstr ""
-#: elflink.c:4320
+#: elflink.c:4290
msgid "Warning: size of symbol `%s' changed from %lu in %B to %lu in %B"
msgstr ""
-#: elflink.c:4489
+#: elflink.c:4463
msgid "%B: undefined reference to symbol '%s'"
msgstr ""
-#: elflink.c:4492
+#: elflink.c:4466
msgid ""
"note: '%s' is defined in DSO %B so try adding it to the linker command line"
msgstr ""
-#: elflink.c:5795
+#: elflink.c:5781
#, c-format
msgid "%s: undefined version: %s"
msgstr ""
-#: elflink.c:5863
+#: elflink.c:5849
msgid "%B: .preinit_array section is not allowed in DSO"
msgstr ""
-#: elflink.c:7617
+#: elflink.c:7604
#, c-format
msgid "undefined %s reference in complex symbol: %s"
msgstr ""
-#: elflink.c:7771
+#: elflink.c:7758
#, c-format
msgid "unknown operator '%c' in complex symbol"
msgstr ""
-#: elflink.c:8110 elflink.c:8127 elflink.c:8164 elflink.c:8181
+#: elflink.c:8097 elflink.c:8114 elflink.c:8151 elflink.c:8168
msgid "%B: Unable to sort relocs - they are in more than one size"
msgstr ""
-#: elflink.c:8141 elflink.c:8195
+#: elflink.c:8128 elflink.c:8182
msgid "%B: Unable to sort relocs - they are of an unknown size"
msgstr ""
-#: elflink.c:8246
+#: elflink.c:8233
msgid "Not enough memory to sort relocations"
msgstr ""
-#: elflink.c:8439
+#: elflink.c:8426
msgid "%B: Too many sections: %d (>= %d)"
msgstr ""
-#: elflink.c:8686
+#: elflink.c:8675
msgid "%B: internal symbol `%s' in %B is referenced by DSO"
msgstr ""
-#: elflink.c:8688
+#: elflink.c:8677
msgid "%B: hidden symbol `%s' in %B is referenced by DSO"
msgstr ""
-#: elflink.c:8690
+#: elflink.c:8679
msgid "%B: local symbol `%s' in %B is referenced by DSO"
msgstr ""
-#: elflink.c:8785
+#: elflink.c:8776
msgid "%B: could not find output section %A for input section %A"
msgstr ""
-#: elflink.c:8908
+#: elflink.c:8899
msgid "%B: protected symbol `%s' isn't defined"
msgstr ""
-#: elflink.c:8910
+#: elflink.c:8901
msgid "%B: internal symbol `%s' isn't defined"
msgstr ""
-#: elflink.c:8912
+#: elflink.c:8903
msgid "%B: hidden symbol `%s' isn't defined"
msgstr ""
-#: elflink.c:9441
+#: elflink.c:9432
msgid "error: %B: size of section %A is not multiple of address size"
msgstr ""
-#: elflink.c:9488
+#: elflink.c:9479
msgid ""
"error: %B contains a reloc (0x%s) for section %A that references a non-"
"existent global symbol"
msgstr ""
-#: elflink.c:10223
+#: elflink.c:10214
msgid "%A has both ordered [`%A' in %B] and unordered [`%A' in %B] sections"
msgstr ""
-#: elflink.c:10228
+#: elflink.c:10219
#, c-format
msgid "%A has both ordered and unordered sections"
msgstr ""
-#: elflink.c:10793
+#: elflink.c:10784
msgid "%B: file class %s incompatible with %s"
msgstr ""
-#: elflink.c:11104 elflink.c:11148
+#: elflink.c:11093 elflink.c:11137
msgid "%B: could not find output section %s"
msgstr ""
-#: elflink.c:11109
+#: elflink.c:11098
#, c-format
msgid "warning: %s section has zero size"
msgstr ""
-#: elflink.c:11214
-msgid "%P: warning: creating a DT_TEXTREL in a shared object.\n"
-msgstr ""
-
-#: elflink.c:11401
-msgid "%P%X: can not read symbols: %E\n"
+#: elflink.c:11143
+#, c-format
+msgid "warning: section '%s' is being made into a note"
msgstr ""
-#: elflink.c:11750
-msgid "Removing unused section '%s' in file '%B'"
+#: elflink.c:11212
+msgid "%P%X: read-only segment has dynamic relocations.\n"
msgstr ""
-#: elflink.c:11962
-msgid "Warning: gc-sections option ignored"
+#: elflink.c:11215
+msgid "%P: warning: creating a DT_TEXTREL in a shared object.\n"
msgstr ""
-#: elflink.c:12511
-msgid "%B: ignoring duplicate section `%A'"
+#: elflink.c:11402
+msgid "%P%X: can not read symbols: %E\n"
msgstr ""
-#: elflink.c:12518 elflink.c:12525
-msgid "%B: duplicate section `%A' has different size"
+#: elflink.c:11792
+msgid "Removing unused section '%s' in file '%B'"
msgstr ""
-#: elflink.c:12533 elflink.c:12538
-msgid "%B: warning: could not read contents of section `%A'"
+#: elflink.c:11998
+msgid "Warning: gc-sections option ignored"
msgstr ""
-#: elflink.c:12542
-msgid "%B: warning: duplicate section `%A' has different contents"
+#: elflink.c:12277
+#, c-format
+msgid "Unrecognized INPUT_SECTION_FLAG %s\n"
msgstr ""
-#: elflink.c:12643 linker.c:3086
-msgid "%F%P: already_linked_table: %E\n"
+#: elfxx-mips.c:1234
+msgid "static procedure (no name)"
msgstr ""
-#: elfxx-mips.c:1221
-msgid "static procedure (no name)"
+#: elfxx-mips.c:5259
+msgid "MIPS16 and microMIPS functions cannot call each other"
msgstr ""
-#: elfxx-mips.c:5628
+#: elfxx-mips.c:5856
msgid ""
"%B: %A+0x%lx: Direct jumps between ISA modes are not allowed; consider "
"recompiling with interlinking enabled."
msgstr ""
-#: elfxx-mips.c:6288 elfxx-mips.c:6511
+#: elfxx-mips.c:6519 elfxx-mips.c:6742
msgid "%B: Warning: bad `%s' option size %u smaller than its header"
msgstr ""
-#: elfxx-mips.c:7262 elfxx-mips.c:7387
+#: elfxx-mips.c:7495 elfxx-mips.c:7620
msgid "%B: Warning: cannot determine the target function for stub section `%s'"
msgstr ""
-#: elfxx-mips.c:7516
+#: elfxx-mips.c:7749
msgid "%B: Malformed reloc detected for section %s"
msgstr ""
-#: elfxx-mips.c:7556
+#: elfxx-mips.c:7801
msgid "%B: GOT reloc at 0x%lx not expected in executables"
msgstr ""
-#: elfxx-mips.c:7678
+#: elfxx-mips.c:7930
msgid "%B: CALL16 reloc at 0x%lx not against global symbol"
msgstr ""
-#: elfxx-mips.c:8372
+#: elfxx-mips.c:8645
#, c-format
msgid "non-dynamic relocations refer to dynamic symbol %s"
msgstr ""
-#: elfxx-mips.c:9075
+#: elfxx-mips.c:9347
msgid ""
"%B: Can't find matching LO16 reloc against `%s' for %s at 0x%lx in section `"
"%A'"
msgstr ""
-#: elfxx-mips.c:9214
+#: elfxx-mips.c:9486
msgid ""
"small-data section exceeds 64KB; lower small-data size limit (see option -G)"
msgstr ""
-#: elfxx-mips.c:12038
+#: elfxx-mips.c:9505
+msgid "JALX to a non-word-aligned address"
+msgstr ""
+
+#: elfxx-mips.c:13266
#, c-format
msgid "%s: illegal section name `%s'"
msgstr ""
-#: elfxx-mips.c:12417 elfxx-mips.c:12443
+#: elfxx-mips.c:13645 elfxx-mips.c:13671
msgid "Warning: %B uses -msingle-float, %B uses -mdouble-float"
msgstr ""
-#: elfxx-mips.c:12429 elfxx-mips.c:12485
+#: elfxx-mips.c:13657 elfxx-mips.c:13713
msgid "Warning: %B uses -msingle-float, %B uses -mips32r2 -mfp64"
msgstr ""
-#: elfxx-mips.c:12455 elfxx-mips.c:12491
+#: elfxx-mips.c:13683 elfxx-mips.c:13719
msgid "Warning: %B uses -mdouble-float, %B uses -mips32r2 -mfp64"
msgstr ""
-#: elfxx-mips.c:12533
+#: elfxx-mips.c:13761
msgid "%B: endianness incompatible with that of the selected emulation"
msgstr ""
-#: elfxx-mips.c:12544
+#: elfxx-mips.c:13772
msgid "%B: ABI is incompatible with that of the selected emulation"
msgstr ""
-#: elfxx-mips.c:12628
+#: elfxx-mips.c:13856
msgid "%B: warning: linking abicalls files with non-abicalls files"
msgstr ""
-#: elfxx-mips.c:12645
+#: elfxx-mips.c:13873
msgid "%B: linking 32-bit code with 64-bit code"
msgstr ""
-#: elfxx-mips.c:12673
+#: elfxx-mips.c:13901
msgid "%B: linking %s module with previous %s modules"
msgstr ""
-#: elfxx-mips.c:12696
+#: elfxx-mips.c:13924
msgid "%B: ABI mismatch: linking %s module with previous %s modules"
msgstr ""
-#: elfxx-mips.c:12860
+#: elfxx-mips.c:13948
+msgid "%B: ASE mismatch: linking %s module with previous %s modules"
+msgstr ""
+
+#: elfxx-mips.c:14106
#, c-format
msgid " [abi=O32]"
msgstr ""
-#: elfxx-mips.c:12862
+#: elfxx-mips.c:14108
#, c-format
msgid " [abi=O64]"
msgstr ""
-#: elfxx-mips.c:12864
+#: elfxx-mips.c:14110
#, c-format
msgid " [abi=EABI32]"
msgstr ""
-#: elfxx-mips.c:12866
+#: elfxx-mips.c:14112
#, c-format
msgid " [abi=EABI64]"
msgstr ""
-#: elfxx-mips.c:12868
+#: elfxx-mips.c:14114
#, c-format
msgid " [abi unknown]"
msgstr ""
-#: elfxx-mips.c:12870
+#: elfxx-mips.c:14116
#, c-format
msgid " [abi=N32]"
msgstr ""
-#: elfxx-mips.c:12872
+#: elfxx-mips.c:14118
#, c-format
msgid " [abi=64]"
msgstr ""
-#: elfxx-mips.c:12874
+#: elfxx-mips.c:14120
#, c-format
msgid " [no abi set]"
msgstr ""
-#: elfxx-mips.c:12895
+#: elfxx-mips.c:14141
#, c-format
msgid " [unknown ISA]"
msgstr ""
-#: elfxx-mips.c:12906
+#: elfxx-mips.c:14155
#, c-format
msgid " [not 32bitmode]"
msgstr ""
-#: elfxx-sparc.c:595
+#: elfxx-sparc.c:596
#, c-format
msgid "invalid relocation type %d"
msgstr ""
-#: i386linux.c:454 m68klinux.c:458 sparclinux.c:452
+#: elfxx-tilegx.c:3952
+msgid "%B: Cannot link together %s and %s objects."
+msgstr ""
+
+#: i386linux.c:451 m68klinux.c:456 sparclinux.c:450
#, c-format
msgid "Output file requires shared library `%s'\n"
msgstr ""
-#: i386linux.c:462 m68klinux.c:466 sparclinux.c:460
+#: i386linux.c:459 m68klinux.c:464 sparclinux.c:458
#, c-format
msgid "Output file requires shared library `%s.so.%s'\n"
msgstr ""
-#: i386linux.c:651 i386linux.c:701 m68klinux.c:658 m68klinux.c:706
-#: sparclinux.c:650 sparclinux.c:700
+#: i386linux.c:648 i386linux.c:698 m68klinux.c:656 m68klinux.c:704
+#: sparclinux.c:648 sparclinux.c:698
#, c-format
msgid "Symbol %s not defined for fixups\n"
msgstr ""
-#: i386linux.c:725 m68klinux.c:730 sparclinux.c:724
+#: i386linux.c:722 m68klinux.c:728 sparclinux.c:722
msgid "Warning: fixup count mismatch\n"
msgstr ""
msgid "%B: unable to get decompressed section %A"
msgstr ""
+#: libbfd.c:1012
+msgid "%B: compiled for a big endian system and target is little endian"
+msgstr ""
+
+#: libbfd.c:1014
+msgid "%B: compiled for a little endian system and target is big endian"
+msgstr ""
+
#: libbfd.c:1043
#, c-format
msgid "Deprecated %s called at %s line %d in %s\n"
msgid "Deprecated %s called\n"
msgstr ""
-#: linker.c:1859
+#: linker.c:1872
msgid "%B: indirect symbol `%s' to `%s' is a loop"
msgstr ""
-#: linker.c:2726
+#: linker.c:2736
#, c-format
msgid "Attempt to do relocatable link with %s input and %s output"
msgstr ""
-#: linker.c:3053
-msgid "%B: warning: ignoring duplicate section `%A'\n"
+#: linker.c:3021
+msgid "%B: ignoring duplicate section `%A'\n"
msgstr ""
-#: linker.c:3067
-msgid "%B: warning: duplicate section `%A' has different size\n"
+#: linker.c:3030 linker.c:3039
+msgid "%B: duplicate section `%A' has different size\n"
msgstr ""
-#: mach-o.c:381
+#: linker.c:3047 linker.c:3052
+msgid "%B: could not read contents of section `%A'\n"
+msgstr ""
+
+#: linker.c:3056
+msgid "%B: duplicate section `%A' has different contents\n"
+msgstr ""
+
+#: mach-o.c:407
msgid "bfd_mach_o_canonicalize_symtab: unable to load symbols"
msgstr ""
-#: mach-o.c:1253
+#: mach-o.c:1301
#, c-format
msgid "unable to write unknown load command 0x%lx"
msgstr ""
-#: mach-o.c:1654
+#: mach-o.c:1789
#, c-format
msgid "bfd_mach_o_read_symtab_symbol: unable to read %d bytes at %lu"
msgstr ""
-#: mach-o.c:1671
+#: mach-o.c:1807
#, c-format
-msgid "bfd_mach_o_read_symtab_symbol: symbol name out of range (%lu >= %lu)"
+msgid "bfd_mach_o_read_symtab_symbol: name out of range (%lu >= %lu)"
msgstr ""
-#: mach-o.c:1756
+#: mach-o.c:1892
#, c-format
msgid ""
"bfd_mach_o_read_symtab_symbol: symbol \"%s\" specified invalid section %d "
"(max %lu): setting to undefined"
msgstr ""
-#: mach-o.c:1764
+#: mach-o.c:1900
#, c-format
msgid ""
"bfd_mach_o_read_symtab_symbol: symbol \"%s\" is unsupported 'indirect' "
"reference: setting to undefined"
msgstr ""
-#: mach-o.c:1770
+#: mach-o.c:1906
#, c-format
msgid ""
"bfd_mach_o_read_symtab_symbol: symbol \"%s\" specified invalid type field 0x"
"%x: setting to undefined"
msgstr ""
-#: mach-o.c:1840
+#: mach-o.c:1979
msgid "bfd_mach_o_read_symtab_symbols: unable to allocate memory for symbols"
msgstr ""
-#: mach-o.c:1874
+#: mach-o.c:2014
#, c-format
msgid "bfd_mach_o_read_dysymtab_symbol: unable to read %lu bytes at %lu"
msgstr ""
-#: mach-o.c:2556
+#: mach-o.c:2734
#, c-format
msgid "unable to read unknown load command 0x%lx"
msgstr ""
-#: mach-o.c:2736
+#: mach-o.c:2915
#, c-format
msgid "bfd_mach_o_scan: unknown architecture 0x%lx/0x%lx"
msgstr ""
-#: mach-o.c:2832
+#: mach-o.c:3011
#, c-format
msgid "unknown header byte-order value 0x%lx"
msgstr ""
-#: mach-o.c:3402
+#: mach-o.c:3577
msgid "Mach-O header:\n"
msgstr ""
-#: mach-o.c:3403
+#: mach-o.c:3578
#, c-format
msgid " magic : %08lx\n"
msgstr ""
-#: mach-o.c:3404
+#: mach-o.c:3579
#, c-format
msgid " cputype : %08lx (%s)\n"
msgstr ""
-#: mach-o.c:3406
+#: mach-o.c:3581
#, c-format
msgid " cpusubtype: %08lx\n"
msgstr ""
-#: mach-o.c:3407
+#: mach-o.c:3582
#, c-format
msgid " filetype : %08lx (%s)\n"
msgstr ""
-#: mach-o.c:3410
+#: mach-o.c:3585
#, c-format
msgid " ncmds : %08lx (%lu)\n"
msgstr ""
-#: mach-o.c:3411
+#: mach-o.c:3586
#, c-format
msgid " sizeofcmds: %08lx\n"
msgstr ""
-#: mach-o.c:3412
+#: mach-o.c:3587
#, c-format
msgid " flags : %08lx ("
msgstr ""
-#: mach-o.c:3414 vms-alpha.c:7671
+#: mach-o.c:3589 vms-alpha.c:7674
msgid ")\n"
msgstr ""
-#: mach-o.c:3415
+#: mach-o.c:3590
#, c-format
msgid " reserved : %08x\n"
msgstr ""
-#: mach-o.c:3425
+#: mach-o.c:3600
msgid "Segments and Sections:\n"
msgstr ""
-#: mach-o.c:3426
+#: mach-o.c:3601
msgid " #: Segment name Section name Address\n"
msgstr ""
msgid "%B: bad pair/reflo after refhi\n"
msgstr ""
-#: pef.c:519
+#: pef.c:520
#, c-format
msgid "bfd_pef_scan: unknown architecture 0x%lx"
msgstr ""
msgid "%B: Unrecognised import name type; %x"
msgstr ""
-#: peicode.h:1162
+#: peicode.h:1166
msgid "%B: Unrecognised machine type (0x%x) in Import Library Format archive"
msgstr ""
-#: peicode.h:1174
+#: peicode.h:1178
msgid ""
"%B: Recognised but unhandled machine type (0x%x) in Import Library Format "
"archive"
msgstr ""
-#: peicode.h:1192
+#: peicode.h:1196
msgid "%B: size field is zero in Import Library Format header"
msgstr ""
-#: peicode.h:1223
+#: peicode.h:1227
msgid "%B: string not null terminated in ILF object file."
msgstr ""
msgid "Partition[%d] length = 0x%.8lx (%ld)\n"
msgstr ""
+#: reloc.c:6160
+msgid "INPUT_SECTION_FLAGS are not supported.\n"
+msgstr ""
+
#: rs6000-core.c:448
#, c-format
msgid "%s: warning core file truncated"
msgid "SEC_RELOC with no relocs in section %s"
msgstr ""
-#: vms-alpha.c:3822 vms-alpha.c:4053
+#: vms-alpha.c:3822 vms-alpha.c:4049
#, c-format
msgid "Size error in section %s"
msgstr ""
-#: vms-alpha.c:3992
+#: vms-alpha.c:3991
msgid "Spurious ALPHA_R_BSR reloc"
msgstr ""
-#: vms-alpha.c:4040
+#: vms-alpha.c:4036
#, c-format
msgid "Unhandled relocation %s"
msgstr ""
-#: vms-alpha.c:4330
+#: vms-alpha.c:4326
#, c-format
msgid "unknown source command %d"
msgstr ""
-#: vms-alpha.c:4391
+#: vms-alpha.c:4387
msgid "DST__K_SET_LINUM_INCR not implemented"
msgstr ""
-#: vms-alpha.c:4397
+#: vms-alpha.c:4393
msgid "DST__K_SET_LINUM_INCR_W not implemented"
msgstr ""
-#: vms-alpha.c:4403
+#: vms-alpha.c:4399
msgid "DST__K_RESET_LINUM_INCR not implemented"
msgstr ""
-#: vms-alpha.c:4409
+#: vms-alpha.c:4405
msgid "DST__K_BEG_STMT_MODE not implemented"
msgstr ""
-#: vms-alpha.c:4415
+#: vms-alpha.c:4411
msgid "DST__K_END_STMT_MODE not implemented"
msgstr ""
-#: vms-alpha.c:4442
+#: vms-alpha.c:4438
msgid "DST__K_SET_PC not implemented"
msgstr ""
-#: vms-alpha.c:4448
+#: vms-alpha.c:4444
msgid "DST__K_SET_PC_W not implemented"
msgstr ""
-#: vms-alpha.c:4454
+#: vms-alpha.c:4450
msgid "DST__K_SET_PC_L not implemented"
msgstr ""
-#: vms-alpha.c:4460
+#: vms-alpha.c:4456
msgid "DST__K_SET_STMTNUM not implemented"
msgstr ""
-#: vms-alpha.c:4503
+#: vms-alpha.c:4499
#, c-format
msgid "unknown line command %d"
msgstr ""
-#: vms-alpha.c:4957 vms-alpha.c:4974 vms-alpha.c:4988 vms-alpha.c:5003
-#: vms-alpha.c:5015 vms-alpha.c:5026 vms-alpha.c:5038
+#: vms-alpha.c:4953 vms-alpha.c:4970 vms-alpha.c:4984 vms-alpha.c:4999
+#: vms-alpha.c:5011 vms-alpha.c:5022 vms-alpha.c:5034
#, c-format
msgid "Unknown reloc %s + %s"
msgstr ""
-#: vms-alpha.c:5093
+#: vms-alpha.c:5089
#, c-format
msgid "Unknown reloc %s"
msgstr ""
-#: vms-alpha.c:5106
+#: vms-alpha.c:5102
msgid "Invalid section index in ETIR"
msgstr ""
-#: vms-alpha.c:5153
+#: vms-alpha.c:5109
+msgid "Relocation for non-REL psect"
+msgstr ""
+
+#: vms-alpha.c:5156
#, c-format
msgid "Unknown symbol in command %s"
msgstr ""
-#: vms-alpha.c:5668
+#: vms-alpha.c:5671
#, c-format
msgid " EMH %u (len=%u): "
msgstr ""
-#: vms-alpha.c:5677
+#: vms-alpha.c:5680
#, c-format
msgid "Module header\n"
msgstr ""
-#: vms-alpha.c:5678
+#: vms-alpha.c:5681
#, c-format
msgid " structure level: %u\n"
msgstr ""
-#: vms-alpha.c:5679
+#: vms-alpha.c:5682
#, c-format
msgid " max record size: %u\n"
msgstr ""
-#: vms-alpha.c:5682
+#: vms-alpha.c:5685
#, c-format
msgid " module name : %.*s\n"
msgstr ""
-#: vms-alpha.c:5684
+#: vms-alpha.c:5687
#, c-format
msgid " module version : %.*s\n"
msgstr ""
-#: vms-alpha.c:5686
+#: vms-alpha.c:5689
#, c-format
msgid " compile date : %.17s\n"
msgstr ""
-#: vms-alpha.c:5691
+#: vms-alpha.c:5694
#, c-format
msgid "Language Processor Name\n"
msgstr ""
-#: vms-alpha.c:5692
+#: vms-alpha.c:5695
#, c-format
msgid " language name: %.*s\n"
msgstr ""
-#: vms-alpha.c:5699
+#: vms-alpha.c:5702
#, c-format
msgid "Source Files Header\n"
msgstr ""
-#: vms-alpha.c:5700
+#: vms-alpha.c:5703
#, c-format
msgid " file: %.*s\n"
msgstr ""
-#: vms-alpha.c:5707
+#: vms-alpha.c:5710
#, c-format
msgid "Title Text Header\n"
msgstr ""
-#: vms-alpha.c:5708
+#: vms-alpha.c:5711
#, c-format
msgid " title: %.*s\n"
msgstr ""
-#: vms-alpha.c:5715
+#: vms-alpha.c:5718
#, c-format
msgid "Copyright Header\n"
msgstr ""
-#: vms-alpha.c:5716
+#: vms-alpha.c:5719
#, c-format
msgid " copyright: %.*s\n"
msgstr ""
-#: vms-alpha.c:5722
+#: vms-alpha.c:5725
#, c-format
msgid "unhandled emh subtype %u\n"
msgstr ""
-#: vms-alpha.c:5732
+#: vms-alpha.c:5735
#, c-format
msgid " EEOM (len=%u):\n"
msgstr ""
-#: vms-alpha.c:5733
+#: vms-alpha.c:5736
#, c-format
msgid " number of cond linkage pairs: %u\n"
msgstr ""
-#: vms-alpha.c:5735
+#: vms-alpha.c:5738
#, c-format
msgid " completion code: %u\n"
msgstr ""
-#: vms-alpha.c:5739
+#: vms-alpha.c:5742
#, c-format
msgid " transfer addr flags: 0x%02x\n"
msgstr ""
-#: vms-alpha.c:5740
+#: vms-alpha.c:5743
#, c-format
msgid " transfer addr psect: %u\n"
msgstr ""
-#: vms-alpha.c:5742
+#: vms-alpha.c:5745
#, c-format
msgid " transfer address : 0x%08x\n"
msgstr ""
-#: vms-alpha.c:5751
+#: vms-alpha.c:5754
msgid " WEAK"
msgstr ""
-#: vms-alpha.c:5753
+#: vms-alpha.c:5756
msgid " DEF"
msgstr ""
-#: vms-alpha.c:5755
+#: vms-alpha.c:5758
msgid " UNI"
msgstr ""
-#: vms-alpha.c:5757 vms-alpha.c:5778
+#: vms-alpha.c:5760 vms-alpha.c:5781
msgid " REL"
msgstr ""
-#: vms-alpha.c:5759
+#: vms-alpha.c:5762
msgid " COMM"
msgstr ""
-#: vms-alpha.c:5761
+#: vms-alpha.c:5764
msgid " VECEP"
msgstr ""
-#: vms-alpha.c:5763
+#: vms-alpha.c:5766
msgid " NORM"
msgstr ""
-#: vms-alpha.c:5765
+#: vms-alpha.c:5768
msgid " QVAL"
msgstr ""
-#: vms-alpha.c:5772
+#: vms-alpha.c:5775
msgid " PIC"
msgstr ""
-#: vms-alpha.c:5774
+#: vms-alpha.c:5777
msgid " LIB"
msgstr ""
-#: vms-alpha.c:5776
+#: vms-alpha.c:5779
msgid " OVR"
msgstr ""
-#: vms-alpha.c:5780
+#: vms-alpha.c:5783
msgid " GBL"
msgstr ""
-#: vms-alpha.c:5782
+#: vms-alpha.c:5785
msgid " SHR"
msgstr ""
-#: vms-alpha.c:5784
+#: vms-alpha.c:5787
msgid " EXE"
msgstr ""
-#: vms-alpha.c:5786
+#: vms-alpha.c:5789
msgid " RD"
msgstr ""
-#: vms-alpha.c:5788
+#: vms-alpha.c:5791
msgid " WRT"
msgstr ""
-#: vms-alpha.c:5790
+#: vms-alpha.c:5793
msgid " VEC"
msgstr ""
-#: vms-alpha.c:5792
+#: vms-alpha.c:5795
msgid " NOMOD"
msgstr ""
-#: vms-alpha.c:5794
+#: vms-alpha.c:5797
msgid " COM"
msgstr ""
-#: vms-alpha.c:5796
+#: vms-alpha.c:5799
msgid " 64B"
msgstr ""
-#: vms-alpha.c:5805
+#: vms-alpha.c:5808
#, c-format
msgid " EGSD (len=%u):\n"
msgstr ""
-#: vms-alpha.c:5817
+#: vms-alpha.c:5820
#, c-format
msgid " EGSD entry %2u (type: %u, len: %u): "
msgstr ""
-#: vms-alpha.c:5829
+#: vms-alpha.c:5832
#, c-format
msgid "PSC - Program section definition\n"
msgstr ""
-#: vms-alpha.c:5830 vms-alpha.c:5847
+#: vms-alpha.c:5833 vms-alpha.c:5850
#, c-format
msgid " alignment : 2**%u\n"
msgstr ""
-#: vms-alpha.c:5831 vms-alpha.c:5848
+#: vms-alpha.c:5834 vms-alpha.c:5851
#, c-format
msgid " flags : 0x%04x"
msgstr ""
-#: vms-alpha.c:5835
+#: vms-alpha.c:5838
#, c-format
msgid " alloc (len): %u (0x%08x)\n"
msgstr ""
-#: vms-alpha.c:5836 vms-alpha.c:5893 vms-alpha.c:5942
+#: vms-alpha.c:5839 vms-alpha.c:5896 vms-alpha.c:5945
#, c-format
msgid " name : %.*s\n"
msgstr ""
-#: vms-alpha.c:5846
+#: vms-alpha.c:5849
#, c-format
msgid "SPSC - Shared Image Program section def\n"
msgstr ""
-#: vms-alpha.c:5852
+#: vms-alpha.c:5855
#, c-format
msgid " alloc (len) : %u (0x%08x)\n"
msgstr ""
-#: vms-alpha.c:5853
+#: vms-alpha.c:5856
#, c-format
msgid " image offset : 0x%08x\n"
msgstr ""
-#: vms-alpha.c:5855
+#: vms-alpha.c:5858
#, c-format
msgid " symvec offset : 0x%08x\n"
msgstr ""
-#: vms-alpha.c:5857
+#: vms-alpha.c:5860
#, c-format
msgid " name : %.*s\n"
msgstr ""
-#: vms-alpha.c:5870
+#: vms-alpha.c:5873
#, c-format
msgid "SYM - Global symbol definition\n"
msgstr ""
-#: vms-alpha.c:5871 vms-alpha.c:5931 vms-alpha.c:5952 vms-alpha.c:5971
+#: vms-alpha.c:5874 vms-alpha.c:5934 vms-alpha.c:5955 vms-alpha.c:5974
#, c-format
msgid " flags: 0x%04x"
msgstr ""
-#: vms-alpha.c:5874
+#: vms-alpha.c:5877
#, c-format
msgid " psect offset: 0x%08x\n"
msgstr ""
-#: vms-alpha.c:5878
+#: vms-alpha.c:5881
#, c-format
msgid " code address: 0x%08x\n"
msgstr ""
-#: vms-alpha.c:5880
+#: vms-alpha.c:5883
#, c-format
msgid " psect index for entry point : %u\n"
msgstr ""
-#: vms-alpha.c:5883 vms-alpha.c:5959 vms-alpha.c:5978
+#: vms-alpha.c:5886 vms-alpha.c:5962 vms-alpha.c:5981
#, c-format
msgid " psect index : %u\n"
msgstr ""
-#: vms-alpha.c:5885 vms-alpha.c:5961 vms-alpha.c:5980
+#: vms-alpha.c:5888 vms-alpha.c:5964 vms-alpha.c:5983
#, c-format
msgid " name : %.*s\n"
msgstr ""
-#: vms-alpha.c:5892
+#: vms-alpha.c:5895
#, c-format
msgid "SYM - Global symbol reference\n"
msgstr ""
-#: vms-alpha.c:5904
+#: vms-alpha.c:5907
#, c-format
msgid "IDC - Ident Consistency check\n"
msgstr ""
-#: vms-alpha.c:5905
+#: vms-alpha.c:5908
#, c-format
msgid " flags : 0x%08x"
msgstr ""
-#: vms-alpha.c:5909
+#: vms-alpha.c:5912
#, c-format
msgid " id match : %x\n"
msgstr ""
-#: vms-alpha.c:5911
+#: vms-alpha.c:5914
#, c-format
msgid " error severity: %x\n"
msgstr ""
-#: vms-alpha.c:5914
+#: vms-alpha.c:5917
#, c-format
msgid " entity name : %.*s\n"
msgstr ""
-#: vms-alpha.c:5916
+#: vms-alpha.c:5919
#, c-format
msgid " object name : %.*s\n"
msgstr ""
-#: vms-alpha.c:5919
+#: vms-alpha.c:5922
#, c-format
msgid " binary ident : 0x%08x\n"
msgstr ""
-#: vms-alpha.c:5922
+#: vms-alpha.c:5925
#, c-format
msgid " ascii ident : %.*s\n"
msgstr ""
-#: vms-alpha.c:5930
+#: vms-alpha.c:5933
#, c-format
msgid "SYMG - Universal symbol definition\n"
msgstr ""
-#: vms-alpha.c:5934
+#: vms-alpha.c:5937
#, c-format
msgid " symbol vector offset: 0x%08x\n"
msgstr ""
-#: vms-alpha.c:5936
+#: vms-alpha.c:5939
#, c-format
msgid " entry point: 0x%08x\n"
msgstr ""
-#: vms-alpha.c:5938
+#: vms-alpha.c:5941
#, c-format
msgid " proc descr : 0x%08x\n"
msgstr ""
-#: vms-alpha.c:5940
+#: vms-alpha.c:5943
#, c-format
msgid " psect index: %u\n"
msgstr ""
-#: vms-alpha.c:5951
+#: vms-alpha.c:5954
#, c-format
msgid "SYMV - Vectored symbol definition\n"
msgstr ""
-#: vms-alpha.c:5955
+#: vms-alpha.c:5958
#, c-format
msgid " vector : 0x%08x\n"
msgstr ""
-#: vms-alpha.c:5957 vms-alpha.c:5976
+#: vms-alpha.c:5960 vms-alpha.c:5979
#, c-format
msgid " psect offset: %u\n"
msgstr ""
-#: vms-alpha.c:5970
+#: vms-alpha.c:5973
#, c-format
msgid "SYMM - Global symbol definition with version\n"
msgstr ""
-#: vms-alpha.c:5974
+#: vms-alpha.c:5977
#, c-format
msgid " version mask: 0x%08x\n"
msgstr ""
-#: vms-alpha.c:5985
+#: vms-alpha.c:5988
#, c-format
msgid "unhandled egsd entry type %u\n"
msgstr ""
-#: vms-alpha.c:6019
+#: vms-alpha.c:6022
#, c-format
msgid " linkage index: %u, replacement insn: 0x%08x\n"
msgstr ""
-#: vms-alpha.c:6022
+#: vms-alpha.c:6025
#, c-format
msgid " psect idx 1: %u, offset 1: 0x%08x %08x\n"
msgstr ""
-#: vms-alpha.c:6026
+#: vms-alpha.c:6029
#, c-format
msgid " psect idx 2: %u, offset 2: 0x%08x %08x\n"
msgstr ""
-#: vms-alpha.c:6031
+#: vms-alpha.c:6034
#, c-format
msgid " psect idx 3: %u, offset 3: 0x%08x %08x\n"
msgstr ""
-#: vms-alpha.c:6036
+#: vms-alpha.c:6039
#, c-format
msgid " global name: %.*s\n"
msgstr ""
-#: vms-alpha.c:6046
+#: vms-alpha.c:6049
#, c-format
msgid " %s (len=%u+%u):\n"
msgstr ""
-#: vms-alpha.c:6061
+#: vms-alpha.c:6064
#, c-format
msgid " (type: %3u, size: 4+%3u): "
msgstr ""
-#: vms-alpha.c:6065
+#: vms-alpha.c:6068
#, c-format
msgid "STA_GBL (stack global) %.*s\n"
msgstr ""
-#: vms-alpha.c:6069
+#: vms-alpha.c:6072
#, c-format
msgid "STA_LW (stack longword) 0x%08x\n"
msgstr ""
-#: vms-alpha.c:6073
+#: vms-alpha.c:6076
#, c-format
msgid "STA_QW (stack quadword) 0x%08x %08x\n"
msgstr ""
-#: vms-alpha.c:6078
+#: vms-alpha.c:6081
#, c-format
msgid "STA_PQ (stack psect base + offset)\n"
msgstr ""
-#: vms-alpha.c:6079
+#: vms-alpha.c:6082
#, c-format
msgid " psect: %u, offset: 0x%08x %08x\n"
msgstr ""
-#: vms-alpha.c:6085
+#: vms-alpha.c:6088
#, c-format
msgid "STA_LI (stack literal)\n"
msgstr ""
-#: vms-alpha.c:6088
+#: vms-alpha.c:6091
#, c-format
msgid "STA_MOD (stack module)\n"
msgstr ""
-#: vms-alpha.c:6091
+#: vms-alpha.c:6094
#, c-format
msgid "STA_CKARG (compare procedure argument)\n"
msgstr ""
-#: vms-alpha.c:6095
+#: vms-alpha.c:6098
#, c-format
msgid "STO_B (store byte)\n"
msgstr ""
-#: vms-alpha.c:6098
+#: vms-alpha.c:6101
#, c-format
msgid "STO_W (store word)\n"
msgstr ""
-#: vms-alpha.c:6101
+#: vms-alpha.c:6104
#, c-format
msgid "STO_LW (store longword)\n"
msgstr ""
-#: vms-alpha.c:6104
+#: vms-alpha.c:6107
#, c-format
msgid "STO_QW (store quadword)\n"
msgstr ""
-#: vms-alpha.c:6110
+#: vms-alpha.c:6113
#, c-format
msgid "STO_IMMR (store immediate repeat) %u bytes\n"
msgstr ""
-#: vms-alpha.c:6117
+#: vms-alpha.c:6120
#, c-format
msgid "STO_GBL (store global) %.*s\n"
msgstr ""
-#: vms-alpha.c:6121
+#: vms-alpha.c:6124
#, c-format
msgid "STO_CA (store code address) %.*s\n"
msgstr ""
-#: vms-alpha.c:6125
+#: vms-alpha.c:6128
#, c-format
msgid "STO_RB (store relative branch)\n"
msgstr ""
-#: vms-alpha.c:6128
+#: vms-alpha.c:6131
#, c-format
msgid "STO_AB (store absolute branch)\n"
msgstr ""
-#: vms-alpha.c:6131
+#: vms-alpha.c:6134
#, c-format
msgid "STO_OFF (store offset to psect)\n"
msgstr ""
-#: vms-alpha.c:6137
+#: vms-alpha.c:6140
#, c-format
msgid "STO_IMM (store immediate) %u bytes\n"
msgstr ""
-#: vms-alpha.c:6144
+#: vms-alpha.c:6147
#, c-format
msgid "STO_GBL_LW (store global longword) %.*s\n"
msgstr ""
-#: vms-alpha.c:6148
+#: vms-alpha.c:6151
#, c-format
msgid "STO_OFF (store LP with procedure signature)\n"
msgstr ""
-#: vms-alpha.c:6151
+#: vms-alpha.c:6154
#, c-format
msgid "STO_BR_GBL (store branch global) *todo*\n"
msgstr ""
-#: vms-alpha.c:6154
+#: vms-alpha.c:6157
#, c-format
msgid "STO_BR_PS (store branch psect + offset) *todo*\n"
msgstr ""
-#: vms-alpha.c:6158
+#: vms-alpha.c:6161
#, c-format
msgid "OPR_NOP (no-operation)\n"
msgstr ""
-#: vms-alpha.c:6161
+#: vms-alpha.c:6164
#, c-format
msgid "OPR_ADD (add)\n"
msgstr ""
-#: vms-alpha.c:6164
+#: vms-alpha.c:6167
#, c-format
msgid "OPR_SUB (substract)\n"
msgstr ""
-#: vms-alpha.c:6167
+#: vms-alpha.c:6170
#, c-format
msgid "OPR_MUL (multiply)\n"
msgstr ""
-#: vms-alpha.c:6170
+#: vms-alpha.c:6173
#, c-format
msgid "OPR_DIV (divide)\n"
msgstr ""
-#: vms-alpha.c:6173
+#: vms-alpha.c:6176
#, c-format
msgid "OPR_AND (logical and)\n"
msgstr ""
-#: vms-alpha.c:6176
+#: vms-alpha.c:6179
#, c-format
msgid "OPR_IOR (logical inclusive or)\n"
msgstr ""
-#: vms-alpha.c:6179
+#: vms-alpha.c:6182
#, c-format
msgid "OPR_EOR (logical exclusive or)\n"
msgstr ""
-#: vms-alpha.c:6182
+#: vms-alpha.c:6185
#, c-format
msgid "OPR_NEG (negate)\n"
msgstr ""
-#: vms-alpha.c:6185
+#: vms-alpha.c:6188
#, c-format
msgid "OPR_COM (complement)\n"
msgstr ""
-#: vms-alpha.c:6188
+#: vms-alpha.c:6191
#, c-format
msgid "OPR_INSV (insert field)\n"
msgstr ""
-#: vms-alpha.c:6191
+#: vms-alpha.c:6194
#, c-format
msgid "OPR_ASH (arithmetic shift)\n"
msgstr ""
-#: vms-alpha.c:6194
+#: vms-alpha.c:6197
#, c-format
msgid "OPR_USH (unsigned shift)\n"
msgstr ""
-#: vms-alpha.c:6197
+#: vms-alpha.c:6200
#, c-format
msgid "OPR_ROT (rotate)\n"
msgstr ""
-#: vms-alpha.c:6200
+#: vms-alpha.c:6203
#, c-format
msgid "OPR_SEL (select)\n"
msgstr ""
-#: vms-alpha.c:6203
+#: vms-alpha.c:6206
#, c-format
msgid "OPR_REDEF (redefine symbol to curr location)\n"
msgstr ""
-#: vms-alpha.c:6206
+#: vms-alpha.c:6209
#, c-format
msgid "OPR_REDEF (define a literal)\n"
msgstr ""
-#: vms-alpha.c:6210
+#: vms-alpha.c:6213
#, c-format
msgid "STC_LP (store cond linkage pair)\n"
msgstr ""
-#: vms-alpha.c:6214
+#: vms-alpha.c:6217
#, c-format
msgid "STC_LP_PSB (store cond linkage pair + signature)\n"
msgstr ""
-#: vms-alpha.c:6215
+#: vms-alpha.c:6218
#, c-format
msgid " linkage index: %u, procedure: %.*s\n"
msgstr ""
-#: vms-alpha.c:6218
+#: vms-alpha.c:6221
#, c-format
msgid " signature: %.*s\n"
msgstr ""
-#: vms-alpha.c:6221
+#: vms-alpha.c:6224
#, c-format
msgid "STC_GBL (store cond global)\n"
msgstr ""
-#: vms-alpha.c:6222
+#: vms-alpha.c:6225
#, c-format
msgid " linkage index: %u, global: %.*s\n"
msgstr ""
-#: vms-alpha.c:6226
+#: vms-alpha.c:6229
#, c-format
msgid "STC_GCA (store cond code address)\n"
msgstr ""
-#: vms-alpha.c:6227
+#: vms-alpha.c:6230
#, c-format
msgid " linkage index: %u, procedure name: %.*s\n"
msgstr ""
-#: vms-alpha.c:6231
+#: vms-alpha.c:6234
#, c-format
msgid "STC_PS (store cond psect + offset)\n"
msgstr ""
-#: vms-alpha.c:6233
+#: vms-alpha.c:6236
#, c-format
msgid " linkage index: %u, psect: %u, offset: 0x%08x %08x\n"
msgstr ""
-#: vms-alpha.c:6240
+#: vms-alpha.c:6243
#, c-format
msgid "STC_NOP_GBL (store cond NOP at global addr)\n"
msgstr ""
-#: vms-alpha.c:6244
+#: vms-alpha.c:6247
#, c-format
msgid "STC_NOP_PS (store cond NOP at psect + offset)\n"
msgstr ""
-#: vms-alpha.c:6248
+#: vms-alpha.c:6251
#, c-format
msgid "STC_BSR_GBL (store cond BSR at global addr)\n"
msgstr ""
-#: vms-alpha.c:6252
+#: vms-alpha.c:6255
#, c-format
msgid "STC_BSR_PS (store cond BSR at psect + offset)\n"
msgstr ""
-#: vms-alpha.c:6256
+#: vms-alpha.c:6259
#, c-format
msgid "STC_LDA_GBL (store cond LDA at global addr)\n"
msgstr ""
-#: vms-alpha.c:6260
+#: vms-alpha.c:6263
#, c-format
msgid "STC_LDA_PS (store cond LDA at psect + offset)\n"
msgstr ""
-#: vms-alpha.c:6264
+#: vms-alpha.c:6267
#, c-format
msgid "STC_BOH_GBL (store cond BOH at global addr)\n"
msgstr ""
-#: vms-alpha.c:6268
+#: vms-alpha.c:6271
#, c-format
msgid "STC_BOH_PS (store cond BOH at psect + offset)\n"
msgstr ""
-#: vms-alpha.c:6273
+#: vms-alpha.c:6276
#, c-format
msgid "STC_NBH_GBL (store cond or hint at global addr)\n"
msgstr ""
-#: vms-alpha.c:6277
+#: vms-alpha.c:6280
#, c-format
msgid "STC_NBH_PS (store cond or hint at psect + offset)\n"
msgstr ""
-#: vms-alpha.c:6281
+#: vms-alpha.c:6284
#, c-format
msgid "CTL_SETRB (set relocation base)\n"
msgstr ""
-#: vms-alpha.c:6287
+#: vms-alpha.c:6290
#, c-format
msgid "CTL_AUGRB (augment relocation base) %u\n"
msgstr ""
-#: vms-alpha.c:6291
+#: vms-alpha.c:6294
#, c-format
msgid "CTL_DFLOC (define location)\n"
msgstr ""
-#: vms-alpha.c:6294
+#: vms-alpha.c:6297
#, c-format
msgid "CTL_STLOC (set location)\n"
msgstr ""
-#: vms-alpha.c:6297
+#: vms-alpha.c:6300
#, c-format
msgid "CTL_STKDL (stack defined location)\n"
msgstr ""
-#: vms-alpha.c:6300 vms-alpha.c:6714
+#: vms-alpha.c:6303 vms-alpha.c:6717
#, c-format
msgid "*unhandled*\n"
msgstr ""
-#: vms-alpha.c:6330 vms-alpha.c:6369
+#: vms-alpha.c:6333 vms-alpha.c:6372
#, c-format
msgid "cannot read GST record length\n"
msgstr ""
#. Ill-formed.
-#: vms-alpha.c:6351
+#: vms-alpha.c:6354
#, c-format
msgid "cannot find EMH in first GST record\n"
msgstr ""
-#: vms-alpha.c:6377
+#: vms-alpha.c:6380
#, c-format
msgid "cannot read GST record header\n"
msgstr ""
-#: vms-alpha.c:6390
+#: vms-alpha.c:6393
#, c-format
msgid " corrupted GST\n"
msgstr ""
-#: vms-alpha.c:6398
+#: vms-alpha.c:6401
#, c-format
msgid "cannot read GST record\n"
msgstr ""
-#: vms-alpha.c:6427
+#: vms-alpha.c:6430
#, c-format
msgid " unhandled EOBJ record type %u\n"
msgstr ""
-#: vms-alpha.c:6450
+#: vms-alpha.c:6453
#, c-format
msgid " bitcount: %u, base addr: 0x%08x\n"
msgstr ""
-#: vms-alpha.c:6463
+#: vms-alpha.c:6466
#, c-format
msgid " bitmap: 0x%08x (count: %u):\n"
msgstr ""
-#: vms-alpha.c:6470
+#: vms-alpha.c:6473
#, c-format
msgid " %08x"
msgstr ""
-#: vms-alpha.c:6495
+#: vms-alpha.c:6498
#, c-format
msgid " image %u (%u entries)\n"
msgstr ""
-#: vms-alpha.c:6500
+#: vms-alpha.c:6503
#, c-format
msgid " offset: 0x%08x, val: 0x%08x\n"
msgstr ""
-#: vms-alpha.c:6521
+#: vms-alpha.c:6524
#, c-format
msgid " image %u (%u entries), offsets:\n"
msgstr ""
-#: vms-alpha.c:6528
+#: vms-alpha.c:6531
#, c-format
msgid " 0x%08x"
msgstr ""
#. 64 bits.
-#: vms-alpha.c:6650
+#: vms-alpha.c:6653
#, c-format
msgid "64 bits *unhandled*\n"
msgstr ""
-#: vms-alpha.c:6654
+#: vms-alpha.c:6657
#, c-format
msgid "class: %u, dtype: %u, length: %u, pointer: 0x%08x\n"
msgstr ""
-#: vms-alpha.c:6665
+#: vms-alpha.c:6668
#, c-format
msgid "non-contiguous array of %s\n"
msgstr ""
-#: vms-alpha.c:6669
+#: vms-alpha.c:6672
#, c-format
msgid "dimct: %u, aflags: 0x%02x, digits: %u, scale: %u\n"
msgstr ""
-#: vms-alpha.c:6673
+#: vms-alpha.c:6676
#, c-format
msgid "arsize: %u, a0: 0x%08x\n"
msgstr ""
-#: vms-alpha.c:6677
+#: vms-alpha.c:6680
#, c-format
msgid "Strides:\n"
msgstr ""
-#: vms-alpha.c:6682
+#: vms-alpha.c:6685
#, c-format
msgid "[%u]: %u\n"
msgstr ""
-#: vms-alpha.c:6687
+#: vms-alpha.c:6690
#, c-format
msgid "Bounds:\n"
msgstr ""
-#: vms-alpha.c:6692
+#: vms-alpha.c:6695
#, c-format
msgid "[%u]: Lower: %u, upper: %u\n"
msgstr ""
-#: vms-alpha.c:6704
+#: vms-alpha.c:6707
#, c-format
msgid "unaligned bit-string of %s\n"
msgstr ""
-#: vms-alpha.c:6708
+#: vms-alpha.c:6711
#, c-format
msgid "base: %u, pos: %u\n"
msgstr ""
-#: vms-alpha.c:6728
+#: vms-alpha.c:6731
#, c-format
msgid "vflags: 0x%02x, value: 0x%08x "
msgstr ""
-#: vms-alpha.c:6734
+#: vms-alpha.c:6737
#, c-format
msgid "(no value)\n"
msgstr ""
-#: vms-alpha.c:6737
+#: vms-alpha.c:6740
#, c-format
msgid "(not active)\n"
msgstr ""
-#: vms-alpha.c:6740
+#: vms-alpha.c:6743
#, c-format
msgid "(not allocated)\n"
msgstr ""
-#: vms-alpha.c:6743
+#: vms-alpha.c:6746
#, c-format
msgid "(descriptor)\n"
msgstr ""
-#: vms-alpha.c:6747
+#: vms-alpha.c:6750
#, c-format
msgid "(trailing value)\n"
msgstr ""
-#: vms-alpha.c:6750
+#: vms-alpha.c:6753
#, c-format
msgid "(value spec follows)\n"
msgstr ""
-#: vms-alpha.c:6753
+#: vms-alpha.c:6756
#, c-format
msgid "(at bit offset %u)\n"
msgstr ""
-#: vms-alpha.c:6756
+#: vms-alpha.c:6759
#, c-format
msgid "(reg: %u, disp: %u, indir: %u, kind: "
msgstr ""
-#: vms-alpha.c:6763
+#: vms-alpha.c:6766
msgid "literal"
msgstr ""
-#: vms-alpha.c:6766
+#: vms-alpha.c:6769
msgid "address"
msgstr ""
-#: vms-alpha.c:6769
+#: vms-alpha.c:6772
msgid "desc"
msgstr ""
-#: vms-alpha.c:6772
+#: vms-alpha.c:6775
msgid "reg"
msgstr ""
-#: vms-alpha.c:6847
+#: vms-alpha.c:6850
#, c-format
msgid "Debug symbol table:\n"
msgstr ""
-#: vms-alpha.c:6858
+#: vms-alpha.c:6861
#, c-format
msgid "cannot read DST header\n"
msgstr ""
-#: vms-alpha.c:6863
+#: vms-alpha.c:6866
#, c-format
msgid " type: %3u, len: %3u (at 0x%08x): "
msgstr ""
-#: vms-alpha.c:6877
+#: vms-alpha.c:6880
#, c-format
msgid "cannot read DST symbol\n"
msgstr ""
-#: vms-alpha.c:6920
+#: vms-alpha.c:6923
#, c-format
msgid "standard data: %s\n"
msgstr ""
-#: vms-alpha.c:6923 vms-alpha.c:7007
+#: vms-alpha.c:6926 vms-alpha.c:7010
#, c-format
msgid " name: %.*s\n"
msgstr ""
-#: vms-alpha.c:6930
+#: vms-alpha.c:6933
#, c-format
msgid "modbeg\n"
msgstr ""
-#: vms-alpha.c:6931
+#: vms-alpha.c:6934
#, c-format
msgid " flags: %d, language: %u, major: %u, minor: %u\n"
msgstr ""
-#: vms-alpha.c:6937 vms-alpha.c:7203
+#: vms-alpha.c:6940 vms-alpha.c:7206
#, c-format
msgid " module name: %.*s\n"
msgstr ""
-#: vms-alpha.c:6940
+#: vms-alpha.c:6943
#, c-format
msgid " compiler : %.*s\n"
msgstr ""
-#: vms-alpha.c:6945
+#: vms-alpha.c:6948
#, c-format
msgid "modend\n"
msgstr ""
-#: vms-alpha.c:6952
+#: vms-alpha.c:6955
msgid "rtnbeg\n"
msgstr ""
-#: vms-alpha.c:6953
+#: vms-alpha.c:6956
#, c-format
msgid " flags: %u, address: 0x%08x, pd-address: 0x%08x\n"
msgstr ""
-#: vms-alpha.c:6958
+#: vms-alpha.c:6961
#, c-format
msgid " routine name: %.*s\n"
msgstr ""
-#: vms-alpha.c:6966
+#: vms-alpha.c:6969
#, c-format
msgid "rtnend: size 0x%08x\n"
msgstr ""
-#: vms-alpha.c:6974
+#: vms-alpha.c:6977
#, c-format
msgid "prolog: bkpt address 0x%08x\n"
msgstr ""
-#: vms-alpha.c:6982
+#: vms-alpha.c:6985
#, c-format
msgid "epilog: flags: %u, count: %u\n"
msgstr ""
-#: vms-alpha.c:6991
+#: vms-alpha.c:6994
#, c-format
msgid "blkbeg: address: 0x%08x, name: %.*s\n"
msgstr ""
-#: vms-alpha.c:7000
+#: vms-alpha.c:7003
#, c-format
msgid "blkend: size: 0x%08x\n"
msgstr ""
-#: vms-alpha.c:7006
+#: vms-alpha.c:7009
#, c-format
msgid "typspec (len: %u)\n"
msgstr ""
-#: vms-alpha.c:7013
+#: vms-alpha.c:7016
#, c-format
msgid "septyp, name: %.*s\n"
msgstr ""
-#: vms-alpha.c:7022
+#: vms-alpha.c:7025
#, c-format
msgid "recbeg: name: %.*s\n"
msgstr ""
-#: vms-alpha.c:7029
+#: vms-alpha.c:7032
#, c-format
msgid "recend\n"
msgstr ""
-#: vms-alpha.c:7032
+#: vms-alpha.c:7035
#, c-format
msgid "enumbeg, len: %u, name: %.*s\n"
msgstr ""
-#: vms-alpha.c:7036
+#: vms-alpha.c:7039
#, c-format
msgid "enumelt, name: %.*s\n"
msgstr ""
-#: vms-alpha.c:7040
+#: vms-alpha.c:7043
#, c-format
msgid "enumend\n"
msgstr ""
-#: vms-alpha.c:7057
+#: vms-alpha.c:7060
#, c-format
msgid "discontiguous range (nbr: %u)\n"
msgstr ""
-#: vms-alpha.c:7059
+#: vms-alpha.c:7062
#, c-format
msgid " address: 0x%08x, size: %u\n"
msgstr ""
-#: vms-alpha.c:7069
+#: vms-alpha.c:7072
#, c-format
msgid "line num (len: %u)\n"
msgstr ""
-#: vms-alpha.c:7086
+#: vms-alpha.c:7089
#, c-format
msgid "delta_pc_w %u\n"
msgstr ""
-#: vms-alpha.c:7093
+#: vms-alpha.c:7096
#, c-format
msgid "incr_linum(b): +%u\n"
msgstr ""
-#: vms-alpha.c:7099
+#: vms-alpha.c:7102
#, c-format
msgid "incr_linum_w: +%u\n"
msgstr ""
-#: vms-alpha.c:7105
+#: vms-alpha.c:7108
#, c-format
msgid "incr_linum_l: +%u\n"
msgstr ""
-#: vms-alpha.c:7111
+#: vms-alpha.c:7114
#, c-format
msgid "set_line_num(w) %u\n"
msgstr ""
-#: vms-alpha.c:7116
+#: vms-alpha.c:7119
#, c-format
msgid "set_line_num_b %u\n"
msgstr ""
-#: vms-alpha.c:7121
+#: vms-alpha.c:7124
#, c-format
msgid "set_line_num_l %u\n"
msgstr ""
-#: vms-alpha.c:7126
+#: vms-alpha.c:7129
#, c-format
msgid "set_abs_pc: 0x%08x\n"
msgstr ""
-#: vms-alpha.c:7130
+#: vms-alpha.c:7133
#, c-format
msgid "delta_pc_l: +0x%08x\n"
msgstr ""
-#: vms-alpha.c:7135
+#: vms-alpha.c:7138
#, c-format
msgid "term(b): 0x%02x"
msgstr ""
-#: vms-alpha.c:7137
+#: vms-alpha.c:7140
#, c-format
msgid " pc: 0x%08x\n"
msgstr ""
-#: vms-alpha.c:7142
+#: vms-alpha.c:7145
#, c-format
msgid "term_w: 0x%04x"
msgstr ""
-#: vms-alpha.c:7144
+#: vms-alpha.c:7147
#, c-format
msgid " pc: 0x%08x\n"
msgstr ""
-#: vms-alpha.c:7150
+#: vms-alpha.c:7153
#, c-format
msgid "delta pc +%-4d"
msgstr ""
-#: vms-alpha.c:7153
+#: vms-alpha.c:7156
#, c-format
msgid " pc: 0x%08x line: %5u\n"
msgstr ""
-#: vms-alpha.c:7158
+#: vms-alpha.c:7161
#, c-format
msgid " *unhandled* cmd %u\n"
msgstr ""
-#: vms-alpha.c:7173
+#: vms-alpha.c:7176
#, c-format
msgid "source (len: %u)\n"
msgstr ""
-#: vms-alpha.c:7187
+#: vms-alpha.c:7190
#, c-format
msgid " declfile: len: %u, flags: %u, fileid: %u\n"
msgstr ""
-#: vms-alpha.c:7191
+#: vms-alpha.c:7194
#, c-format
msgid " rms: cdt: 0x%08x %08x, ebk: 0x%08x, ffb: 0x%04x, rfo: %u\n"
msgstr ""
-#: vms-alpha.c:7200
+#: vms-alpha.c:7203
#, c-format
msgid " filename : %.*s\n"
msgstr ""
-#: vms-alpha.c:7209
+#: vms-alpha.c:7212
#, c-format
msgid " setfile %u\n"
msgstr ""
-#: vms-alpha.c:7214 vms-alpha.c:7219
+#: vms-alpha.c:7217 vms-alpha.c:7222
#, c-format
msgid " setrec %u\n"
msgstr ""
-#: vms-alpha.c:7224 vms-alpha.c:7229
+#: vms-alpha.c:7227 vms-alpha.c:7232
#, c-format
msgid " setlnum %u\n"
msgstr ""
-#: vms-alpha.c:7234 vms-alpha.c:7239
+#: vms-alpha.c:7237 vms-alpha.c:7242
#, c-format
msgid " deflines %u\n"
msgstr ""
-#: vms-alpha.c:7243
+#: vms-alpha.c:7246
#, c-format
msgid " formfeed\n"
msgstr ""
-#: vms-alpha.c:7247
+#: vms-alpha.c:7250
#, c-format
msgid " *unhandled* cmd %u\n"
msgstr ""
-#: vms-alpha.c:7259
+#: vms-alpha.c:7262
#, c-format
msgid "*unhandled* dst type %u\n"
msgstr ""
-#: vms-alpha.c:7291
+#: vms-alpha.c:7294
#, c-format
msgid "cannot read EIHD\n"
msgstr ""
-#: vms-alpha.c:7294
+#: vms-alpha.c:7297
#, c-format
msgid "EIHD: (size: %u, nbr blocks: %u)\n"
msgstr ""
-#: vms-alpha.c:7297
+#: vms-alpha.c:7300
#, c-format
msgid " majorid: %u, minorid: %u\n"
msgstr ""
-#: vms-alpha.c:7305
+#: vms-alpha.c:7308
msgid "executable"
msgstr ""
-#: vms-alpha.c:7308
+#: vms-alpha.c:7311
msgid "linkable image"
msgstr ""
-#: vms-alpha.c:7314
+#: vms-alpha.c:7317
#, c-format
msgid " image type: %u (%s)"
msgstr ""
-#: vms-alpha.c:7320
+#: vms-alpha.c:7323
msgid "native"
msgstr ""
-#: vms-alpha.c:7323
+#: vms-alpha.c:7326
msgid "CLI"
msgstr ""
-#: vms-alpha.c:7329
+#: vms-alpha.c:7332
#, c-format
msgid ", subtype: %u (%s)\n"
msgstr ""
-#: vms-alpha.c:7335
+#: vms-alpha.c:7338
#, c-format
msgid " offsets: isd: %u, activ: %u, symdbg: %u, imgid: %u, patch: %u\n"
msgstr ""
-#: vms-alpha.c:7339
+#: vms-alpha.c:7342
#, c-format
msgid " fixup info rva: "
msgstr ""
-#: vms-alpha.c:7341
+#: vms-alpha.c:7344
#, c-format
msgid ", symbol vector rva: "
msgstr ""
-#: vms-alpha.c:7344
+#: vms-alpha.c:7347
#, c-format
msgid ""
"\n"
" version array off: %u\n"
msgstr ""
-#: vms-alpha.c:7348
+#: vms-alpha.c:7351
#, c-format
msgid " img I/O count: %u, nbr channels: %u, req pri: %08x%08x\n"
msgstr ""
-#: vms-alpha.c:7354
+#: vms-alpha.c:7357
#, c-format
msgid " linker flags: %08x:"
msgstr ""
-#: vms-alpha.c:7384
+#: vms-alpha.c:7387
#, c-format
msgid " ident: 0x%08x, sysver: 0x%08x, match ctrl: %u, symvect_size: %u\n"
msgstr ""
-#: vms-alpha.c:7390
+#: vms-alpha.c:7393
#, c-format
msgid " BPAGE: %u"
msgstr ""
-#: vms-alpha.c:7396
+#: vms-alpha.c:7399
#, c-format
msgid ", ext fixup offset: %u, no_opt psect off: %u"
msgstr ""
-#: vms-alpha.c:7399
+#: vms-alpha.c:7402
#, c-format
msgid ", alias: %u\n"
msgstr ""
-#: vms-alpha.c:7407
+#: vms-alpha.c:7410
#, c-format
msgid "system version array information:\n"
msgstr ""
-#: vms-alpha.c:7411
+#: vms-alpha.c:7414
#, c-format
msgid "cannot read EIHVN header\n"
msgstr ""
-#: vms-alpha.c:7421
+#: vms-alpha.c:7424
#, c-format
msgid "cannot read EIHVN version\n"
msgstr ""
-#: vms-alpha.c:7424
+#: vms-alpha.c:7427
#, c-format
msgid " %02u "
msgstr ""
-#: vms-alpha.c:7428
+#: vms-alpha.c:7431
msgid "BASE_IMAGE "
msgstr ""
-#: vms-alpha.c:7431
+#: vms-alpha.c:7434
msgid "MEMORY_MANAGEMENT"
msgstr ""
-#: vms-alpha.c:7434
+#: vms-alpha.c:7437
msgid "IO "
msgstr ""
-#: vms-alpha.c:7437
+#: vms-alpha.c:7440
msgid "FILES_VOLUMES "
msgstr ""
-#: vms-alpha.c:7440
+#: vms-alpha.c:7443
msgid "PROCESS_SCHED "
msgstr ""
-#: vms-alpha.c:7443
+#: vms-alpha.c:7446
msgid "SYSGEN "
msgstr ""
-#: vms-alpha.c:7446
+#: vms-alpha.c:7449
msgid "CLUSTERS_LOCKMGR "
msgstr ""
-#: vms-alpha.c:7449
+#: vms-alpha.c:7452
msgid "LOGICAL_NAMES "
msgstr ""
-#: vms-alpha.c:7452
+#: vms-alpha.c:7455
msgid "SECURITY "
msgstr ""
-#: vms-alpha.c:7455
+#: vms-alpha.c:7458
msgid "IMAGE_ACTIVATOR "
msgstr ""
-#: vms-alpha.c:7458
+#: vms-alpha.c:7461
msgid "NETWORKS "
msgstr ""
-#: vms-alpha.c:7461
+#: vms-alpha.c:7464
msgid "COUNTERS "
msgstr ""
-#: vms-alpha.c:7464
+#: vms-alpha.c:7467
msgid "STABLE "
msgstr ""
-#: vms-alpha.c:7467
+#: vms-alpha.c:7470
msgid "MISC "
msgstr ""
-#: vms-alpha.c:7470
+#: vms-alpha.c:7473
msgid "CPU "
msgstr ""
-#: vms-alpha.c:7473
+#: vms-alpha.c:7476
msgid "VOLATILE "
msgstr ""
-#: vms-alpha.c:7476
+#: vms-alpha.c:7479
msgid "SHELL "
msgstr ""
-#: vms-alpha.c:7479
+#: vms-alpha.c:7482
msgid "POSIX "
msgstr ""
-#: vms-alpha.c:7482
+#: vms-alpha.c:7485
msgid "MULTI_PROCESSING "
msgstr ""
-#: vms-alpha.c:7485
+#: vms-alpha.c:7488
msgid "GALAXY "
msgstr ""
-#: vms-alpha.c:7488
+#: vms-alpha.c:7491
msgid "*unknown* "
msgstr ""
-#: vms-alpha.c:7491
+#: vms-alpha.c:7494
#, c-format
msgid ": %u.%u\n"
msgstr ""
-#: vms-alpha.c:7504 vms-alpha.c:7763
+#: vms-alpha.c:7507 vms-alpha.c:7766
#, c-format
msgid "cannot read EIHA\n"
msgstr ""
-#: vms-alpha.c:7507
+#: vms-alpha.c:7510
#, c-format
msgid "Image activation: (size=%u)\n"
msgstr ""
-#: vms-alpha.c:7509
+#: vms-alpha.c:7512
#, c-format
msgid " First address : 0x%08x 0x%08x\n"
msgstr ""
-#: vms-alpha.c:7512
+#: vms-alpha.c:7515
#, c-format
msgid " Second address: 0x%08x 0x%08x\n"
msgstr ""
-#: vms-alpha.c:7515
+#: vms-alpha.c:7518
#, c-format
msgid " Third address : 0x%08x 0x%08x\n"
msgstr ""
-#: vms-alpha.c:7518
+#: vms-alpha.c:7521
#, c-format
msgid " Fourth address: 0x%08x 0x%08x\n"
msgstr ""
-#: vms-alpha.c:7521
+#: vms-alpha.c:7524
#, c-format
msgid " Shared image : 0x%08x 0x%08x\n"
msgstr ""
-#: vms-alpha.c:7532
+#: vms-alpha.c:7535
#, c-format
msgid "cannot read EIHI\n"
msgstr ""
-#: vms-alpha.c:7535
+#: vms-alpha.c:7538
#, c-format
msgid "Image identification: (major: %u, minor: %u)\n"
msgstr ""
-#: vms-alpha.c:7538
+#: vms-alpha.c:7541
#, c-format
msgid " image name : %.*s\n"
msgstr ""
-#: vms-alpha.c:7540
+#: vms-alpha.c:7543
#, c-format
msgid " link time : %s\n"
msgstr ""
-#: vms-alpha.c:7542
+#: vms-alpha.c:7545
#, c-format
msgid " image ident : %.*s\n"
msgstr ""
-#: vms-alpha.c:7544
+#: vms-alpha.c:7547
#, c-format
msgid " linker ident : %.*s\n"
msgstr ""
-#: vms-alpha.c:7546
+#: vms-alpha.c:7549
#, c-format
msgid " image build ident: %.*s\n"
msgstr ""
-#: vms-alpha.c:7556
+#: vms-alpha.c:7559
#, c-format
msgid "cannot read EIHS\n"
msgstr ""
-#: vms-alpha.c:7559
+#: vms-alpha.c:7562
#, c-format
msgid "Image symbol & debug table: (major: %u, minor: %u)\n"
msgstr ""
-#: vms-alpha.c:7564
+#: vms-alpha.c:7567
#, c-format
msgid " debug symbol table : vbn: %u, size: %u (0x%x)\n"
msgstr ""
-#: vms-alpha.c:7568
+#: vms-alpha.c:7571
#, c-format
msgid " global symbol table: vbn: %u, records: %u\n"
msgstr ""
-#: vms-alpha.c:7572
+#: vms-alpha.c:7575
#, c-format
msgid " debug module table : vbn: %u, size: %u\n"
msgstr ""
-#: vms-alpha.c:7585
+#: vms-alpha.c:7588
#, c-format
msgid "cannot read EISD\n"
msgstr ""
-#: vms-alpha.c:7595
+#: vms-alpha.c:7598
#, c-format
msgid ""
"Image section descriptor: (major: %u, minor: %u, size: %u, offset: %u)\n"
msgstr ""
-#: vms-alpha.c:7602
+#: vms-alpha.c:7605
#, c-format
msgid " section: base: 0x%08x%08x size: 0x%08x\n"
msgstr ""
-#: vms-alpha.c:7607
+#: vms-alpha.c:7610
#, c-format
msgid " flags: 0x%04x"
msgstr ""
-#: vms-alpha.c:7644
+#: vms-alpha.c:7647
#, c-format
msgid " vbn: %u, pfc: %u, matchctl: %u type: %u ("
msgstr ""
-#: vms-alpha.c:7650
+#: vms-alpha.c:7653
msgid "NORMAL"
msgstr ""
-#: vms-alpha.c:7653
+#: vms-alpha.c:7656
msgid "SHRFXD"
msgstr ""
-#: vms-alpha.c:7656
+#: vms-alpha.c:7659
msgid "PRVFXD"
msgstr ""
-#: vms-alpha.c:7659
+#: vms-alpha.c:7662
msgid "SHRPIC"
msgstr ""
-#: vms-alpha.c:7662
+#: vms-alpha.c:7665
msgid "PRVPIC"
msgstr ""
-#: vms-alpha.c:7665
+#: vms-alpha.c:7668
msgid "USRSTACK"
msgstr ""
-#: vms-alpha.c:7673
+#: vms-alpha.c:7676
#, c-format
msgid " ident: 0x%08x, name: %.*s\n"
msgstr ""
-#: vms-alpha.c:7683
+#: vms-alpha.c:7686
#, c-format
msgid "cannot read DMT\n"
msgstr ""
-#: vms-alpha.c:7687
+#: vms-alpha.c:7690
#, c-format
msgid "Debug module table:\n"
msgstr ""
-#: vms-alpha.c:7696
+#: vms-alpha.c:7699
#, c-format
msgid "cannot read DMT header\n"
msgstr ""
-#: vms-alpha.c:7701
+#: vms-alpha.c:7704
#, c-format
msgid " module offset: 0x%08x, size: 0x%08x, (%u psects)\n"
msgstr ""
-#: vms-alpha.c:7711
+#: vms-alpha.c:7714
#, c-format
msgid "cannot read DMT psect\n"
msgstr ""
-#: vms-alpha.c:7714
+#: vms-alpha.c:7717
#, c-format
msgid " psect start: 0x%08x, length: %u\n"
msgstr ""
-#: vms-alpha.c:7727
+#: vms-alpha.c:7730
#, c-format
msgid "cannot read DST\n"
msgstr ""
-#: vms-alpha.c:7737
+#: vms-alpha.c:7740
#, c-format
msgid "cannot read GST\n"
msgstr ""
-#: vms-alpha.c:7741
+#: vms-alpha.c:7744
#, c-format
msgid "Global symbol table:\n"
msgstr ""
-#: vms-alpha.c:7769
+#: vms-alpha.c:7772
#, c-format
msgid "Image activator fixup: (major: %u, minor: %u)\n"
msgstr ""
-#: vms-alpha.c:7772
+#: vms-alpha.c:7775
#, c-format
msgid " iaflink : 0x%08x %08x\n"
msgstr ""
-#: vms-alpha.c:7775
+#: vms-alpha.c:7778
#, c-format
msgid " fixuplnk: 0x%08x %08x\n"
msgstr ""
-#: vms-alpha.c:7778
+#: vms-alpha.c:7781
#, c-format
msgid " size : %u\n"
msgstr ""
-#: vms-alpha.c:7780
+#: vms-alpha.c:7783
#, c-format
msgid " flags: 0x%08x\n"
msgstr ""
-#: vms-alpha.c:7784
+#: vms-alpha.c:7787
#, c-format
msgid " qrelfixoff: %5u, lrelfixoff: %5u\n"
msgstr ""
-#: vms-alpha.c:7788
+#: vms-alpha.c:7791
#, c-format
msgid " qdotadroff: %5u, ldotadroff: %5u\n"
msgstr ""
-#: vms-alpha.c:7792
+#: vms-alpha.c:7795
#, c-format
msgid " codeadroff: %5u, lpfixoff : %5u\n"
msgstr ""
-#: vms-alpha.c:7795
+#: vms-alpha.c:7798
#, c-format
msgid " chgprtoff : %5u\n"
msgstr ""
-#: vms-alpha.c:7798
+#: vms-alpha.c:7801
#, c-format
msgid " shlstoff : %5u, shrimgcnt : %5u\n"
msgstr ""
-#: vms-alpha.c:7800
+#: vms-alpha.c:7803
#, c-format
msgid " shlextra : %5u, permctx : %5u\n"
msgstr ""
-#: vms-alpha.c:7803
+#: vms-alpha.c:7806
#, c-format
msgid " base_va : 0x%08x\n"
msgstr ""
-#: vms-alpha.c:7805
+#: vms-alpha.c:7808
#, c-format
msgid " lppsbfixoff: %5u\n"
msgstr ""
-#: vms-alpha.c:7813
+#: vms-alpha.c:7816
#, c-format
msgid " Shareable images:\n"
msgstr ""
-#: vms-alpha.c:7817
+#: vms-alpha.c:7820
#, c-format
msgid " %u: size: %u, flags: 0x%02x, name: %.*s\n"
msgstr ""
-#: vms-alpha.c:7824
+#: vms-alpha.c:7827
#, c-format
msgid " quad-word relocation fixups:\n"
msgstr ""
-#: vms-alpha.c:7829
+#: vms-alpha.c:7832
#, c-format
msgid " long-word relocation fixups:\n"
msgstr ""
-#: vms-alpha.c:7834
+#: vms-alpha.c:7837
#, c-format
msgid " quad-word .address reference fixups:\n"
msgstr ""
-#: vms-alpha.c:7839
+#: vms-alpha.c:7842
#, c-format
msgid " long-word .address reference fixups:\n"
msgstr ""
-#: vms-alpha.c:7844
+#: vms-alpha.c:7847
#, c-format
msgid " Code Address Reference Fixups:\n"
msgstr ""
-#: vms-alpha.c:7849
+#: vms-alpha.c:7852
#, c-format
msgid " Linkage Pairs Referece Fixups:\n"
msgstr ""
-#: vms-alpha.c:7858
+#: vms-alpha.c:7861
#, c-format
msgid " Change Protection (%u entries):\n"
msgstr ""
-#: vms-alpha.c:7863
+#: vms-alpha.c:7866
#, c-format
msgid " base: 0x%08x %08x, size: 0x%08x, prot: 0x%08x "
msgstr ""
#. FIXME: we do not yet support relocatable link. It is not obvious
#. how to do it for debug infos.
-#: vms-alpha.c:8694
+#: vms-alpha.c:8706
msgid "%P: relocatable link is not supported\n"
msgstr ""
-#: vms-alpha.c:8764
+#: vms-alpha.c:8776
msgid "%P: multiple entry points: in modules %B and %B\n"
msgstr ""
-#: vms-lib.c:1421
+#: vms-lib.c:1423
#, c-format
msgid "could not open shared image '%s' from '%s'"
msgstr ""
msgid "warning: attempt to export undefined symbol `%s'"
msgstr ""
-#: xcofflink.c:3681
+#: xcofflink.c:3678
msgid "error: undefined symbol __rtinit"
msgstr ""
-#: xcofflink.c:4060
+#: xcofflink.c:4057
msgid "%B: loader reloc in unrecognized section `%s'"
msgstr ""
-#: xcofflink.c:4071
+#: xcofflink.c:4068
msgid "%B: `%s' in loader reloc but not loader sym"
msgstr ""
-#: xcofflink.c:4087
+#: xcofflink.c:4084
msgid "%B: loader reloc in read-only section %A"
msgstr ""
-#: xcofflink.c:5109
+#: xcofflink.c:5106
#, c-format
msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling"
msgstr ""
"branch."
msgstr ""
-#: elf32-ia64.c:2290 elf64-ia64.c:2290
+#: elf32-ia64.c:2284 elf64-ia64.c:2284
msgid "@pltoff reloc against local symbol"
msgstr ""
-#: elf32-ia64.c:3693 elf64-ia64.c:3693
+#: elf32-ia64.c:3687 elf64-ia64.c:3687
#, c-format
msgid "%s: short data segment overflowed (0x%lx >= 0x400000)"
msgstr ""
-#: elf32-ia64.c:3704 elf64-ia64.c:3704
+#: elf32-ia64.c:3698 elf64-ia64.c:3698
#, c-format
msgid "%s: __gp does not cover short data segment"
msgstr ""
-#: elf32-ia64.c:3971 elf64-ia64.c:3971
+#: elf32-ia64.c:3965 elf64-ia64.c:3965
msgid "%B: non-pic code with imm relocation against dynamic symbol `%s'"
msgstr ""
-#: elf32-ia64.c:4038 elf64-ia64.c:4038
+#: elf32-ia64.c:4032 elf64-ia64.c:4032
msgid "%B: @gprel relocation against dynamic symbol %s"
msgstr ""
-#: elf32-ia64.c:4101 elf64-ia64.c:4101
+#: elf32-ia64.c:4095 elf64-ia64.c:4095
msgid "%B: linking non-pic code in a position independent executable"
msgstr ""
-#: elf32-ia64.c:4238 elf64-ia64.c:4238
+#: elf32-ia64.c:4232 elf64-ia64.c:4232
msgid "%B: @internal branch to dynamic symbol %s"
msgstr ""
-#: elf32-ia64.c:4240 elf64-ia64.c:4240
+#: elf32-ia64.c:4234 elf64-ia64.c:4234
msgid "%B: speculation fixup to dynamic symbol %s"
msgstr ""
-#: elf32-ia64.c:4242 elf64-ia64.c:4242
+#: elf32-ia64.c:4236 elf64-ia64.c:4236
msgid "%B: @pcrel relocation against dynamic symbol %s"
msgstr ""
-#: elf32-ia64.c:4439 elf64-ia64.c:4439
+#: elf32-ia64.c:4433 elf64-ia64.c:4433
msgid "unsupported reloc"
msgstr ""
-#: elf32-ia64.c:4477 elf64-ia64.c:4477
+#: elf32-ia64.c:4471 elf64-ia64.c:4471
msgid ""
"%B: missing TLS section for relocation %s against `%s' at 0x%lx in section `"
"%A'."
msgstr ""
-#: elf32-ia64.c:4492 elf64-ia64.c:4492
+#: elf32-ia64.c:4486 elf64-ia64.c:4486
msgid ""
"%B: Can't relax br (%s) to `%s' at 0x%lx in section `%A' with size 0x%lx (> "
"0x1000000)."
msgstr ""
-#: elf32-ia64.c:4754 elf64-ia64.c:4754
+#: elf32-ia64.c:4748 elf64-ia64.c:4748
msgid "%B: linking trap-on-NULL-dereference with non-trapping files"
msgstr ""
-#: elf32-ia64.c:4763 elf64-ia64.c:4763
+#: elf32-ia64.c:4757 elf64-ia64.c:4757
msgid "%B: linking big-endian files with little-endian files"
msgstr ""
-#: elf32-ia64.c:4772 elf64-ia64.c:4772
+#: elf32-ia64.c:4766 elf64-ia64.c:4766
msgid "%B: linking 64-bit files with 32-bit files"
msgstr ""
-#: elf32-ia64.c:4781 elf64-ia64.c:4781
+#: elf32-ia64.c:4775 elf64-ia64.c:4775
msgid "%B: linking constant-gp files with non-constant-gp files"
msgstr ""
-#: elf32-ia64.c:4791 elf64-ia64.c:4791
+#: elf32-ia64.c:4785 elf64-ia64.c:4785
msgid "%B: linking auto-pic files with non-auto-pic files"
msgstr ""
ENUMDOC
Tilera TILE-Gx Relocations.
+ENUM
+ BFD_RELOC_EPIPHANY_SIMM8
+ENUMDOC
+ Adapteva EPIPHANY - 8 bit signed pc-relative displacement
+ENUM
+ BFD_RELOC_EPIPHANY_SIMM24
+ENUMDOC
+ Adapteva EPIPHANY - 24 bit signed pc-relative displacement
+ENUM
+ BFD_RELOC_EPIPHANY_HIGH
+ENUMDOC
+ Adapteva EPIPHANY - 16 most-significant bits of absolute address
+ENUM
+ BFD_RELOC_EPIPHANY_LOW
+ENUMDOC
+ Adapteva EPIPHANY - 16 least-significant bits of absolute address
+ENUM
+ BFD_RELOC_EPIPHANY_SIMM11
+ENUMDOC
+ Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
+ENUM
+ BFD_RELOC_EPIPHANY_IMM11
+ENUMDOC
+ Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
+ENUM
+ BFD_RELOC_EPIPHANY_IMM8
+ENUMDOC
+ Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
+
ENDSENUM
BFD_RELOC_UNUSED
extern const bfd_target bfd_elf32_d10v_vec;
extern const bfd_target bfd_elf32_d30v_vec;
extern const bfd_target bfd_elf32_dlx_big_vec;
+extern const bfd_target bfd_elf32_epiphany_vec;
extern const bfd_target bfd_elf32_fr30_vec;
extern const bfd_target bfd_elf32_frv_vec;
extern const bfd_target bfd_elf32_frvfdpic_vec;
&bfd_elf32_d10v_vec,
&bfd_elf32_d30v_vec,
&bfd_elf32_dlx_big_vec,
+ &bfd_elf32_epiphany_vec,
&bfd_elf32_fr30_vec,
&bfd_elf32_frv_vec,
&bfd_elf32_frvfdpic_vec,
+2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
+
+ * readelf.c: Include "elf/epiphany.h".
+ (guess_is_rela, dump_relocation): Handle EM_ADAPTEVA_EPIPHANY.
+ (get_machine_name, is_32bit_abs_reloc, is_32bit_pcrel_reloc): Likewise.
+ (is_16bit_abs_reloc, is_none_reloc): Likewise.
+ * po/binutils.pot: Regenerate.
+
2011-10-25 Kai Tietz <ktietz@redhat.com>
* winduni.h (unicode_from_ascii_len): New prototype.
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n"
-"POT-Creation-Date: 2011-10-13 16:24+0100\n"
+"POT-Creation-Date: 2011-10-25 11:20+0100\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n"
#: addr2line.c:101 ar.c:304 ar.c:333 coffdump.c:471 dlltool.c:3938
#: dllwrap.c:524 elfedit.c:653 nlmconv.c:1114 objcopy.c:576 objcopy.c:611
-#: readelf.c:3207 size.c:99 srconv.c:1743 strings.c:667 sysdump.c:653
+#: readelf.c:3214 size.c:99 srconv.c:1743 strings.c:667 sysdump.c:653
#: windmc.c:228 windres.c:695
#, c-format
msgid "Report bugs to %s\n"
msgid "Symbol %s, tag %d, number %d"
msgstr ""
-#: coffdump.c:345 readelf.c:12201 readelf.c:12275
+#: coffdump.c:345 readelf.c:12215 readelf.c:12289
#, c-format
msgid "Type"
msgstr ""
msgid "Wrong size in print_dwarf_vma"
msgstr ""
-#: dwarf.c:256 dwarf.c:3026
+#: dwarf.c:256 dwarf.c:3027
msgid "badly formed extended line op encountered!\n"
msgstr ""
msgid " define new File Table entry\n"
msgstr ""
-#: dwarf.c:281 dwarf.c:2554
+#: dwarf.c:281 dwarf.c:2555
#, c-format
msgid " Entry\tDir\tTime\tSize\tName\n"
msgstr ""
msgid "(location list)"
msgstr ""
-#: dwarf.c:1761 dwarf.c:4044
+#: dwarf.c:1761 dwarf.c:4045
#, c-format
msgid " [without DW_AT_frame_base]"
msgstr ""
-#: dwarf.c:1776
+#: dwarf.c:1777
#, c-format
msgid ""
"Offset %s used as value for DW_AT_import attribute of DIE at offset %lx is "
"too big.\n"
msgstr ""
-#: dwarf.c:1786
+#: dwarf.c:1787
#, c-format
msgid "[Abbrev Number: %ld"
msgstr ""
-#: dwarf.c:1977
+#: dwarf.c:1978
#, c-format
msgid "Unknown AT value: %lx"
msgstr ""
-#: dwarf.c:2048
+#: dwarf.c:2049
#, c-format
msgid "Reserved length value (0x%s) found in section %s\n"
msgstr ""
-#: dwarf.c:2060
+#: dwarf.c:2061
#, c-format
msgid "Corrupt unit length (0x%s) found in section %s\n"
msgstr ""
-#: dwarf.c:2068
+#: dwarf.c:2069
#, c-format
msgid "No comp units in %s section ?"
msgstr ""
-#: dwarf.c:2077
+#: dwarf.c:2078
#, c-format
msgid "Not enough memory for a debug info array of %u entries"
msgstr ""
-#: dwarf.c:2086 dwarf.c:3295 dwarf.c:3389 dwarf.c:3550 dwarf.c:3778
-#: dwarf.c:3910 dwarf.c:4080 dwarf.c:4149 dwarf.c:4353
+#: dwarf.c:2087 dwarf.c:3296 dwarf.c:3390 dwarf.c:3551 dwarf.c:3779
+#: dwarf.c:3911 dwarf.c:4081 dwarf.c:4150 dwarf.c:4354
#, c-format
msgid ""
"Contents of the %s section:\n"
"\n"
msgstr ""
-#: dwarf.c:2094
+#: dwarf.c:2095
#, c-format
msgid "Unable to locate %s section!\n"
msgstr ""
-#: dwarf.c:2175
+#: dwarf.c:2176
#, c-format
msgid " Compilation Unit @ offset 0x%s:\n"
msgstr ""
-#: dwarf.c:2177
+#: dwarf.c:2178
#, c-format
msgid " Length: 0x%s (%s)\n"
msgstr ""
-#: dwarf.c:2180
+#: dwarf.c:2181
#, c-format
msgid " Version: %d\n"
msgstr ""
-#: dwarf.c:2181
+#: dwarf.c:2182
#, c-format
msgid " Abbrev Offset: %s\n"
msgstr ""
-#: dwarf.c:2183
+#: dwarf.c:2184
#, c-format
msgid " Pointer Size: %d\n"
msgstr ""
-#: dwarf.c:2187
+#: dwarf.c:2188
#, c-format
msgid " Signature: "
msgstr ""
-#: dwarf.c:2191
+#: dwarf.c:2192
#, c-format
msgid " Type Offset: 0x%s\n"
msgstr ""
-#: dwarf.c:2199
+#: dwarf.c:2200
#, c-format
msgid ""
"Debug info is corrupted, length of CU at %s extends beyond end of section "
"(length = %s)\n"
msgstr ""
-#: dwarf.c:2212
+#: dwarf.c:2213
#, c-format
msgid "CU at offset %s contains corrupt or unsupported version number: %d.\n"
msgstr ""
-#: dwarf.c:2223
+#: dwarf.c:2224
#, c-format
msgid ""
"Debug info is corrupted, abbrev offset (%lx) is larger than abbrev section "
"size (%lx)\n"
msgstr ""
-#: dwarf.c:2273
+#: dwarf.c:2274
#, c-format
msgid ""
"Bogus end-of-siblings marker detected at offset %lx in .debug_info section\n"
msgstr ""
-#: dwarf.c:2277
+#: dwarf.c:2278
msgid "Further warnings about bogus end-of-sibling markers suppressed\n"
msgstr ""
-#: dwarf.c:2296
+#: dwarf.c:2297
#, c-format
msgid " <%d><%lx>: Abbrev Number: %lu"
msgstr ""
-#: dwarf.c:2300
+#: dwarf.c:2301
#, c-format
msgid " <%d><%lx>: ...\n"
msgstr ""
-#: dwarf.c:2319
+#: dwarf.c:2320
#, c-format
msgid ""
"DIE at offset %lx refers to abbreviation number %lu which does not exist\n"
msgstr ""
-#: dwarf.c:2421
+#: dwarf.c:2422
#, c-format
msgid ""
"Raw dump of debug contents of section %s:\n"
"\n"
msgstr ""
-#: dwarf.c:2459
+#: dwarf.c:2460
#, c-format
msgid ""
"The information in section %s appears to be corrupt - the section is too "
"small\n"
msgstr ""
-#: dwarf.c:2471 dwarf.c:2839
+#: dwarf.c:2472 dwarf.c:2840
msgid "Only DWARF version 2, 3 and 4 line info is currently supported.\n"
msgstr ""
-#: dwarf.c:2485 dwarf.c:2854
+#: dwarf.c:2486 dwarf.c:2855
msgid "Invalid maximum operations per insn.\n"
msgstr ""
-#: dwarf.c:2504 dwarf.c:3573
+#: dwarf.c:2505 dwarf.c:3574
#, c-format
msgid " Offset: 0x%lx\n"
msgstr ""
-#: dwarf.c:2505
+#: dwarf.c:2506
#, c-format
msgid " Length: %ld\n"
msgstr ""
-#: dwarf.c:2506
+#: dwarf.c:2507
#, c-format
msgid " DWARF Version: %d\n"
msgstr ""
-#: dwarf.c:2507
+#: dwarf.c:2508
#, c-format
msgid " Prologue Length: %d\n"
msgstr ""
-#: dwarf.c:2508
+#: dwarf.c:2509
#, c-format
msgid " Minimum Instruction Length: %d\n"
msgstr ""
-#: dwarf.c:2510
+#: dwarf.c:2511
#, c-format
msgid " Maximum Ops per Instruction: %d\n"
msgstr ""
-#: dwarf.c:2511
+#: dwarf.c:2512
#, c-format
msgid " Initial value of 'is_stmt': %d\n"
msgstr ""
-#: dwarf.c:2512
+#: dwarf.c:2513
#, c-format
msgid " Line Base: %d\n"
msgstr ""
-#: dwarf.c:2513
+#: dwarf.c:2514
#, c-format
msgid " Line Range: %d\n"
msgstr ""
-#: dwarf.c:2514
+#: dwarf.c:2515
#, c-format
msgid " Opcode Base: %d\n"
msgstr ""
-#: dwarf.c:2523
+#: dwarf.c:2524
#, c-format
msgid ""
"\n"
" Opcodes:\n"
msgstr ""
-#: dwarf.c:2526
+#: dwarf.c:2527
#, c-format
msgid " Opcode %d has %d args\n"
msgstr ""
-#: dwarf.c:2532
+#: dwarf.c:2533
#, c-format
msgid ""
"\n"
" The Directory Table is empty.\n"
msgstr ""
-#: dwarf.c:2535
+#: dwarf.c:2536
#, c-format
msgid ""
"\n"
" The Directory Table:\n"
msgstr ""
-#: dwarf.c:2550
+#: dwarf.c:2551
#, c-format
msgid ""
"\n"
" The File Name Table is empty.\n"
msgstr ""
-#: dwarf.c:2553
+#: dwarf.c:2554
#, c-format
msgid ""
"\n"
msgstr ""
#. Now display the statements.
-#: dwarf.c:2583
+#: dwarf.c:2584
#, c-format
msgid ""
"\n"
" Line Number Statements:\n"
msgstr ""
-#: dwarf.c:2602
+#: dwarf.c:2603
#, c-format
msgid " Special opcode %d: advance Address by %s to 0x%s"
msgstr ""
-#: dwarf.c:2616
+#: dwarf.c:2617
#, c-format
msgid " Special opcode %d: advance Address by %s to 0x%s[%d]"
msgstr ""
-#: dwarf.c:2624
+#: dwarf.c:2625
#, c-format
msgid " and Line by %s to %d\n"
msgstr ""
-#: dwarf.c:2634
+#: dwarf.c:2635
#, c-format
msgid " Copy\n"
msgstr ""
-#: dwarf.c:2644
+#: dwarf.c:2645
#, c-format
msgid " Advance PC by %s to 0x%s\n"
msgstr ""
-#: dwarf.c:2657
+#: dwarf.c:2658
#, c-format
msgid " Advance PC by %s to 0x%s[%d]\n"
msgstr ""
-#: dwarf.c:2668
+#: dwarf.c:2669
#, c-format
msgid " Advance Line by %s to %d\n"
msgstr ""
-#: dwarf.c:2676
+#: dwarf.c:2677
#, c-format
msgid " Set File Name to entry %s in the File Name Table\n"
msgstr ""
-#: dwarf.c:2684
+#: dwarf.c:2685
#, c-format
msgid " Set column to %s\n"
msgstr ""
-#: dwarf.c:2692
+#: dwarf.c:2693
#, c-format
msgid " Set is_stmt to %s\n"
msgstr ""
-#: dwarf.c:2697
+#: dwarf.c:2698
#, c-format
msgid " Set basic block\n"
msgstr ""
-#: dwarf.c:2707
+#: dwarf.c:2708
#, c-format
msgid " Advance PC by constant %s to 0x%s\n"
msgstr ""
-#: dwarf.c:2720
+#: dwarf.c:2721
#, c-format
msgid " Advance PC by constant %s to 0x%s[%d]\n"
msgstr ""
-#: dwarf.c:2732
+#: dwarf.c:2733
#, c-format
msgid " Advance PC by fixed size amount %s to 0x%s\n"
msgstr ""
-#: dwarf.c:2738
+#: dwarf.c:2739
#, c-format
msgid " Set prologue_end to true\n"
msgstr ""
-#: dwarf.c:2742
+#: dwarf.c:2743
#, c-format
msgid " Set epilogue_begin to true\n"
msgstr ""
-#: dwarf.c:2748
+#: dwarf.c:2749
#, c-format
msgid " Set ISA to %s\n"
msgstr ""
-#: dwarf.c:2752 dwarf.c:3167
+#: dwarf.c:2753 dwarf.c:3168
#, c-format
msgid " Unknown opcode %d with operands: "
msgstr ""
-#: dwarf.c:2786
+#: dwarf.c:2787
#, c-format
msgid ""
"Decoded dump of debug contents of section %s:\n"
"\n"
msgstr ""
-#: dwarf.c:2827
+#: dwarf.c:2828
msgid "The line info appears to be corrupt - the section is too small\n"
msgstr ""
-#: dwarf.c:2959
+#: dwarf.c:2960
#, c-format
msgid "CU: %s:\n"
msgstr ""
-#: dwarf.c:2960 dwarf.c:2971
+#: dwarf.c:2961 dwarf.c:2972
#, c-format
msgid "File name Line number Starting address\n"
msgstr ""
-#: dwarf.c:2967
+#: dwarf.c:2968
#, c-format
msgid "CU: %s/%s:\n"
msgstr ""
-#: dwarf.c:3058
+#: dwarf.c:3059
#, c-format
msgid "UNKNOWN: length %d\n"
msgstr ""
-#: dwarf.c:3163
+#: dwarf.c:3164
#, c-format
msgid " Set ISA to %lu\n"
msgstr ""
-#: dwarf.c:3329 dwarf.c:4194
+#: dwarf.c:3330 dwarf.c:4195
#, c-format
msgid ""
".debug_info offset of 0x%lx in %s section does not point to a CU header.\n"
msgstr ""
-#: dwarf.c:3343
+#: dwarf.c:3344
msgid "Only DWARF 2 and 3 pubnames are currently supported\n"
msgstr ""
-#: dwarf.c:3350
+#: dwarf.c:3351
#, c-format
msgid " Length: %ld\n"
msgstr ""
-#: dwarf.c:3352
+#: dwarf.c:3353
#, c-format
msgid " Version: %d\n"
msgstr ""
-#: dwarf.c:3354
+#: dwarf.c:3355
#, c-format
msgid " Offset into .debug_info section: 0x%lx\n"
msgstr ""
-#: dwarf.c:3356
+#: dwarf.c:3357
#, c-format
msgid " Size of area in .debug_info section: %ld\n"
msgstr ""
-#: dwarf.c:3359
+#: dwarf.c:3360
#, c-format
msgid ""
"\n"
" Offset\tName\n"
msgstr ""
-#: dwarf.c:3410
+#: dwarf.c:3411
#, c-format
msgid " DW_MACINFO_start_file - lineno: %d filenum: %d\n"
msgstr ""
-#: dwarf.c:3416
+#: dwarf.c:3417
#, c-format
msgid " DW_MACINFO_end_file\n"
msgstr ""
-#: dwarf.c:3424
+#: dwarf.c:3425
#, c-format
msgid " DW_MACINFO_define - lineno : %d macro : %s\n"
msgstr ""
-#: dwarf.c:3433
+#: dwarf.c:3434
#, c-format
msgid " DW_MACINFO_undef - lineno : %d macro : %s\n"
msgstr ""
-#: dwarf.c:3445
+#: dwarf.c:3446
#, c-format
msgid " DW_MACINFO_vendor_ext - constant : %d string : %s\n"
msgstr ""
-#: dwarf.c:3565
+#: dwarf.c:3566
#, c-format
msgid "Only GNU extension to DWARF 4 of %s is currently supported.\n"
msgstr ""
-#: dwarf.c:3575
+#: dwarf.c:3576
#, c-format
msgid " Version: %d\n"
msgstr ""
-#: dwarf.c:3576
+#: dwarf.c:3577
#, c-format
msgid " Offset size: %d\n"
msgstr ""
-#: dwarf.c:3581
+#: dwarf.c:3582
#, c-format
msgid " Offset into .debug_line: 0x%lx\n"
msgstr ""
-#: dwarf.c:3592
+#: dwarf.c:3593
#, c-format
msgid " Extension opcode arguments:\n"
msgstr ""
-#: dwarf.c:3600
+#: dwarf.c:3601
#, c-format
msgid " DW_MACRO_GNU_%02x has no arguments\n"
msgstr ""
-#: dwarf.c:3603
+#: dwarf.c:3604
#, c-format
msgid " DW_MACRO_GNU_%02x arguments: "
msgstr ""
-#: dwarf.c:3627
+#: dwarf.c:3628
#, c-format
msgid "Invalid extension opcode form %s\n"
msgstr ""
-#: dwarf.c:3644
+#: dwarf.c:3645
msgid ".debug_macro section not zero terminated\n"
msgstr ""
-#: dwarf.c:3665
+#: dwarf.c:3666
msgid "DW_MACRO_GNU_start_file used, but no .debug_line offset provided.\n"
msgstr ""
-#: dwarf.c:3671
+#: dwarf.c:3672
#, c-format
msgid " DW_MACRO_GNU_start_file - lineno: %d filenum: %d\n"
msgstr ""
-#: dwarf.c:3674
+#: dwarf.c:3675
#, c-format
msgid " DW_MACRO_GNU_start_file - lineno: %d filenum: %d filename: %s%s%s\n"
msgstr ""
-#: dwarf.c:3682
+#: dwarf.c:3683
#, c-format
msgid " DW_MACRO_GNU_end_file\n"
msgstr ""
-#: dwarf.c:3690
+#: dwarf.c:3691
#, c-format
msgid " DW_MACRO_GNU_define - lineno : %d macro : %s\n"
msgstr ""
-#: dwarf.c:3699
+#: dwarf.c:3700
#, c-format
msgid " DW_MACRO_GNU_undef - lineno : %d macro : %s\n"
msgstr ""
-#: dwarf.c:3709
+#: dwarf.c:3710
#, c-format
msgid " DW_MACRO_GNU_define_indirect - lineno : %d macro : %s\n"
msgstr ""
-#: dwarf.c:3719
+#: dwarf.c:3720
#, c-format
msgid " DW_MACRO_GNU_undef_indirect - lineno : %d macro : %s\n"
msgstr ""
-#: dwarf.c:3726
+#: dwarf.c:3727
#, c-format
msgid " DW_MACRO_GNU_transparent_include - offset : 0x%lx\n"
msgstr ""
-#: dwarf.c:3733
+#: dwarf.c:3734
#, c-format
msgid " Unknown macro opcode %02x seen\n"
msgstr ""
-#: dwarf.c:3745
+#: dwarf.c:3746
#, c-format
msgid " DW_MACRO_GNU_%02x\n"
msgstr ""
-#: dwarf.c:3748
+#: dwarf.c:3749
#, c-format
msgid " DW_MACRO_GNU_%02x -"
msgstr ""
-#: dwarf.c:3789
+#: dwarf.c:3790
#, c-format
msgid " Number TAG\n"
msgstr ""
-#: dwarf.c:3798
+#: dwarf.c:3799
msgid "has children"
msgstr ""
-#: dwarf.c:3798
+#: dwarf.c:3799
msgid "no children"
msgstr ""
-#: dwarf.c:3849 dwarf.c:4076 dwarf.c:4310
+#: dwarf.c:3850 dwarf.c:4077 dwarf.c:4311
#, c-format
msgid ""
"\n"
"The %s section is empty.\n"
msgstr ""
-#: dwarf.c:3855 dwarf.c:4316
+#: dwarf.c:3856 dwarf.c:4317
#, c-format
msgid ""
"Unable to load/parse the .debug_info section, so cannot interpret the %s "
"section.\n"
msgstr ""
-#: dwarf.c:3899
+#: dwarf.c:3900
msgid "No location lists in .debug_info section!\n"
msgstr ""
-#: dwarf.c:3904
+#: dwarf.c:3905
#, c-format
msgid "Location lists in %s section start at 0x%s\n"
msgstr ""
-#: dwarf.c:3911
+#: dwarf.c:3912
#, c-format
msgid " Offset Begin End Expression\n"
msgstr ""
-#: dwarf.c:3960
+#: dwarf.c:3961
#, c-format
msgid "There is a hole [0x%lx - 0x%lx] in .debug_loc section.\n"
msgstr ""
-#: dwarf.c:3964
+#: dwarf.c:3965
#, c-format
msgid "There is an overlap [0x%lx - 0x%lx] in .debug_loc section.\n"
msgstr ""
-#: dwarf.c:3972
+#: dwarf.c:3973
#, c-format
msgid "Offset 0x%lx is bigger than .debug_loc section size.\n"
msgstr ""
-#: dwarf.c:3981 dwarf.c:4016 dwarf.c:4026
+#: dwarf.c:3982 dwarf.c:4017 dwarf.c:4027
#, c-format
msgid "Location list starting at offset 0x%lx is not terminated.\n"
msgstr ""
-#: dwarf.c:4000 dwarf.c:4404
+#: dwarf.c:4001 dwarf.c:4405
#, c-format
msgid "<End of list>\n"
msgstr ""
-#: dwarf.c:4010
+#: dwarf.c:4011
#, c-format
msgid "(base address)\n"
msgstr ""
-#: dwarf.c:4047
+#: dwarf.c:4048
msgid " (start == end)"
msgstr ""
-#: dwarf.c:4049
+#: dwarf.c:4050
msgid " (start > end)"
msgstr ""
-#: dwarf.c:4059
+#: dwarf.c:4060
#, c-format
msgid "There are %ld unused bytes at the end of section %s\n"
msgstr ""
-#: dwarf.c:4205
+#: dwarf.c:4206
msgid "Only DWARF 2 and 3 aranges are currently supported.\n"
msgstr ""
-#: dwarf.c:4209
+#: dwarf.c:4210
#, c-format
msgid " Length: %ld\n"
msgstr ""
-#: dwarf.c:4211
+#: dwarf.c:4212
#, c-format
msgid " Version: %d\n"
msgstr ""
-#: dwarf.c:4212
+#: dwarf.c:4213
#, c-format
msgid " Offset into .debug_info: 0x%lx\n"
msgstr ""
-#: dwarf.c:4214
+#: dwarf.c:4215
#, c-format
msgid " Pointer Size: %d\n"
msgstr ""
-#: dwarf.c:4215
+#: dwarf.c:4216
#, c-format
msgid " Segment Size: %d\n"
msgstr ""
-#: dwarf.c:4221
+#: dwarf.c:4222
#, c-format
msgid "Invalid address size in %s section!\n"
msgstr ""
-#: dwarf.c:4231
+#: dwarf.c:4232
msgid "Pointer size + Segment size is not a power of two.\n"
msgstr ""
-#: dwarf.c:4236
+#: dwarf.c:4237
#, c-format
msgid ""
"\n"
" Address Length\n"
msgstr ""
-#: dwarf.c:4238
+#: dwarf.c:4239
#, c-format
msgid ""
"\n"
" Address Length\n"
msgstr ""
-#: dwarf.c:4326
+#: dwarf.c:4327
msgid "No range lists in .debug_info section!\n"
msgstr ""
-#: dwarf.c:4350
+#: dwarf.c:4351
#, c-format
msgid "Range lists in %s section start at 0x%lx\n"
msgstr ""
-#: dwarf.c:4354
+#: dwarf.c:4355
#, c-format
msgid " Offset Begin End\n"
msgstr ""
-#: dwarf.c:4375
+#: dwarf.c:4376
#, c-format
msgid "There is a hole [0x%lx - 0x%lx] in %s section.\n"
msgstr ""
-#: dwarf.c:4379
+#: dwarf.c:4380
#, c-format
msgid "There is an overlap [0x%lx - 0x%lx] in %s section.\n"
msgstr ""
-#: dwarf.c:4422
+#: dwarf.c:4423
msgid "(start == end)"
msgstr ""
-#: dwarf.c:4424
+#: dwarf.c:4425
msgid "(start > end)"
msgstr ""
-#: dwarf.c:4677
+#: dwarf.c:4678
msgid "bad register: "
msgstr ""
#. The documentation for the format of this file is in gdb/dwarf2read.c.
-#: dwarf.c:4680 dwarf.c:5489
+#: dwarf.c:4681 dwarf.c:5490
#, c-format
msgid "Contents of the %s section:\n"
msgstr ""
-#: dwarf.c:5450
+#: dwarf.c:5451
#, c-format
msgid " DW_CFA_??? (User defined call frame op: %#x)\n"
msgstr ""
-#: dwarf.c:5452
+#: dwarf.c:5453
#, c-format
msgid "unsupported or unknown Dwarf Call Frame Instruction number: %#x\n"
msgstr ""
-#: dwarf.c:5493
+#: dwarf.c:5494
#, c-format
msgid "Truncated header in the %s section.\n"
msgstr ""
-#: dwarf.c:5498
+#: dwarf.c:5499
#, c-format
msgid "Version %ld\n"
msgstr ""
-#: dwarf.c:5505
+#: dwarf.c:5506
msgid "The address table data in version 3 may be wrong.\n"
msgstr ""
-#: dwarf.c:5508
+#: dwarf.c:5509
msgid "Version 4 does not support case insensitive lookups.\n"
msgstr ""
-#: dwarf.c:5513
+#: dwarf.c:5514
#, c-format
msgid "Unsupported version %lu.\n"
msgstr ""
-#: dwarf.c:5529
+#: dwarf.c:5530
#, c-format
msgid "Corrupt header in the %s section.\n"
msgstr ""
-#: dwarf.c:5544
+#: dwarf.c:5545
#, c-format
msgid ""
"\n"
"CU table:\n"
msgstr ""
-#: dwarf.c:5550
+#: dwarf.c:5551
#, c-format
msgid "[%3u] 0x%lx - 0x%lx\n"
msgstr ""
-#: dwarf.c:5555
+#: dwarf.c:5556
#, c-format
msgid ""
"\n"
"TU table:\n"
msgstr ""
-#: dwarf.c:5562
+#: dwarf.c:5563
#, c-format
msgid "[%3u] 0x%lx 0x%lx "
msgstr ""
-#: dwarf.c:5569
+#: dwarf.c:5570
#, c-format
msgid ""
"\n"
"Address table:\n"
msgstr ""
-#: dwarf.c:5578
+#: dwarf.c:5579
#, c-format
msgid "%lu\n"
msgstr ""
-#: dwarf.c:5581
+#: dwarf.c:5582
#, c-format
msgid ""
"\n"
"Symbol table:\n"
msgstr ""
-#: dwarf.c:5615
+#: dwarf.c:5616
#, c-format
msgid "Displaying the debug contents of section %s is not yet supported.\n"
msgstr ""
-#: dwarf.c:5751 dwarf.c:5821
+#: dwarf.c:5752 dwarf.c:5822
#, c-format
msgid "Unrecognized debug option '%s'\n"
msgstr ""
msgid "Unhandled data length: %d\n"
msgstr ""
-#: elfcomm.c:263 elfcomm.c:277 elfcomm.c:645 readelf.c:3676 readelf.c:3984
-#: readelf.c:4027 readelf.c:4101 readelf.c:4180 readelf.c:4958 readelf.c:4982
-#: readelf.c:7390 readelf.c:7436 readelf.c:7635 readelf.c:8856 readelf.c:8870
-#: readelf.c:9416 readelf.c:9432 readelf.c:9475 readelf.c:9500 readelf.c:11890
-#: readelf.c:12082 readelf.c:12915
+#: elfcomm.c:263 elfcomm.c:277 elfcomm.c:645 readelf.c:3683 readelf.c:3991
+#: readelf.c:4034 readelf.c:4108 readelf.c:4187 readelf.c:4965 readelf.c:4989
+#: readelf.c:7397 readelf.c:7443 readelf.c:7642 readelf.c:8863 readelf.c:8877
+#: readelf.c:9423 readelf.c:9439 readelf.c:9482 readelf.c:9507 readelf.c:11904
+#: readelf.c:12096 readelf.c:12929
msgid "Out of memory\n"
msgstr ""
msgid "%s: failed to seek to first archive header\n"
msgstr ""
-#: elfcomm.c:321 elfcomm.c:611 elfedit.c:340 readelf.c:13404
+#: elfcomm.c:321 elfcomm.c:611 elfedit.c:340 readelf.c:13418
#, c-format
msgid "%s: failed to read archive header\n"
msgstr ""
msgid "%s: failed to seek to next file name\n"
msgstr ""
-#: elfcomm.c:616 elfedit.c:347 readelf.c:13410
+#: elfcomm.c:616 elfedit.c:347 readelf.c:13424
#, c-format
msgid "%s: did not find a valid archive header\n"
msgstr ""
msgid "%s: Failed to seek to ELF header\n"
msgstr ""
-#: elfedit.c:331 readelf.c:13396
+#: elfedit.c:331 readelf.c:13410
#, c-format
msgid "%s: failed to seek to next archive header\n"
msgstr ""
-#: elfedit.c:362 elfedit.c:371 readelf.c:13424 readelf.c:13433
+#: elfedit.c:362 elfedit.c:371 readelf.c:13438 readelf.c:13447
#, c-format
msgid "%s: bad archive file name\n"
msgstr ""
msgid "%s: failed to seek to archive member\n"
msgstr ""
-#: elfedit.c:454 readelf.c:13519
+#: elfedit.c:454 readelf.c:13533
#, c-format
msgid "'%s': No such file\n"
msgstr ""
-#: elfedit.c:456 readelf.c:13521
+#: elfedit.c:456 readelf.c:13535
#, c-format
msgid "Could not locate '%s'. System error message: %s\n"
msgstr ""
-#: elfedit.c:463 readelf.c:13528
+#: elfedit.c:463 readelf.c:13542
#, c-format
msgid "'%s' is not an ordinary file\n"
msgstr ""
-#: elfedit.c:489 readelf.c:13541
+#: elfedit.c:489 readelf.c:13555
#, c-format
msgid "%s: Failed to read file's magic number\n"
msgstr ""
msgid "%s: invalid output format"
msgstr ""
-#: nm.c:346 readelf.c:8609 readelf.c:8654
+#: nm.c:346 readelf.c:8616 readelf.c:8661
#, c-format
msgid "<processor specific>: %d"
msgstr ""
-#: nm.c:348 readelf.c:8618 readelf.c:8672
+#: nm.c:348 readelf.c:8625 readelf.c:8679
#, c-format
msgid "<OS specific>: %d"
msgstr ""
-#: nm.c:350 readelf.c:8621 readelf.c:8675
+#: nm.c:350 readelf.c:8628 readelf.c:8682
#, c-format
msgid "<unknown>: %d"
msgstr ""
msgid "Last stabs entries before error:\n"
msgstr ""
-#: readelf.c:267
+#: readelf.c:268
msgid "<none>"
msgstr ""
-#: readelf.c:268
+#: readelf.c:269
msgid "<no-name>"
msgstr ""
-#: readelf.c:269 readelf.c:5076 readelf.c:5587 readelf.c:8125 readelf.c:8243
-#: readelf.c:9226 readelf.c:9320 readelf.c:9381 readelf.c:12377
-#: readelf.c:12380
+#: readelf.c:270 readelf.c:5083 readelf.c:5594 readelf.c:8132 readelf.c:8250
+#: readelf.c:9233 readelf.c:9327 readelf.c:9388 readelf.c:12391
+#: readelf.c:12394
msgid "<corrupt>"
msgstr ""
-#: readelf.c:308
+#: readelf.c:309
#, c-format
msgid "Unable to seek to 0x%lx for %s\n"
msgstr ""
-#: readelf.c:323
+#: readelf.c:324
#, c-format
msgid "Out of memory allocating 0x%lx bytes for %s\n"
msgstr ""
-#: readelf.c:333
+#: readelf.c:334
#, c-format
msgid "Unable to read in 0x%lx bytes of %s\n"
msgstr ""
-#: readelf.c:636
+#: readelf.c:638
msgid "Don't know about relocations on this machine architecture\n"
msgstr ""
-#: readelf.c:657 readelf.c:755
+#: readelf.c:659 readelf.c:757
msgid "32-bit relocation data"
msgstr ""
-#: readelf.c:669 readelf.c:699 readelf.c:766 readelf.c:795
+#: readelf.c:671 readelf.c:701 readelf.c:768 readelf.c:797
msgid "out of memory parsing relocs\n"
msgstr ""
-#: readelf.c:687 readelf.c:784
+#: readelf.c:689 readelf.c:786
msgid "64-bit relocation data"
msgstr ""
-#: readelf.c:900
+#: readelf.c:902
#, c-format
msgid ""
" Offset Info Type Sym. Value Symbol's Name + Addend\n"
msgstr ""
-#: readelf.c:902
+#: readelf.c:904
#, c-format
msgid " Offset Info Type Sym.Value Sym. Name + Addend\n"
msgstr ""
-#: readelf.c:907
+#: readelf.c:909
#, c-format
msgid " Offset Info Type Sym. Value Symbol's Name\n"
msgstr ""
-#: readelf.c:909
+#: readelf.c:911
#, c-format
msgid " Offset Info Type Sym.Value Sym. Name\n"
msgstr ""
-#: readelf.c:917
+#: readelf.c:919
#, c-format
msgid ""
" Offset Info Type Symbol's Value "
"Symbol's Name + Addend\n"
msgstr ""
-#: readelf.c:919
+#: readelf.c:921
#, c-format
msgid ""
" Offset Info Type Sym. Value Sym. Name + "
"Addend\n"
msgstr ""
-#: readelf.c:924
+#: readelf.c:926
#, c-format
msgid ""
" Offset Info Type Symbol's Value "
"Symbol's Name\n"
msgstr ""
-#: readelf.c:926
+#: readelf.c:928
#, c-format
msgid ""
" Offset Info Type Sym. Value Sym. Name\n"
msgstr ""
-#: readelf.c:1239 readelf.c:1399 readelf.c:1407
+#: readelf.c:1245 readelf.c:1405 readelf.c:1413
#, c-format
msgid "unrecognized: %-7lx"
msgstr ""
-#: readelf.c:1264
+#: readelf.c:1270
#, c-format
msgid "<unknown addend: %lx>"
msgstr ""
-#: readelf.c:1271
+#: readelf.c:1277
#, c-format
msgid " bad symbol index: %08lx"
msgstr ""
-#: readelf.c:1357
+#: readelf.c:1363
#, c-format
msgid "<string table index: %3ld>"
msgstr ""
-#: readelf.c:1359
+#: readelf.c:1365
#, c-format
msgid "<corrupt string table index: %3ld>"
msgstr ""
-#: readelf.c:1752
+#: readelf.c:1758
#, c-format
msgid "Processor Specific: %lx"
msgstr ""
-#: readelf.c:1776
+#: readelf.c:1782
#, c-format
msgid "Operating System specific: %lx"
msgstr ""
-#: readelf.c:1780 readelf.c:2851
+#: readelf.c:1786 readelf.c:2858
#, c-format
msgid "<unknown>: %lx"
msgstr ""
-#: readelf.c:1793
+#: readelf.c:1799
msgid "NONE (None)"
msgstr ""
-#: readelf.c:1794
+#: readelf.c:1800
msgid "REL (Relocatable file)"
msgstr ""
-#: readelf.c:1795
+#: readelf.c:1801
msgid "EXEC (Executable file)"
msgstr ""
-#: readelf.c:1796
+#: readelf.c:1802
msgid "DYN (Shared object file)"
msgstr ""
-#: readelf.c:1797
+#: readelf.c:1803
msgid "CORE (Core file)"
msgstr ""
-#: readelf.c:1801
+#: readelf.c:1807
#, c-format
msgid "Processor Specific: (%x)"
msgstr ""
-#: readelf.c:1803
+#: readelf.c:1809
#, c-format
msgid "OS Specific: (%x)"
msgstr ""
-#: readelf.c:1805
+#: readelf.c:1811
#, c-format
msgid "<unknown>: %x"
msgstr ""
-#: readelf.c:1817
+#: readelf.c:1823
msgid "None"
msgstr ""
-#: readelf.c:1987
+#: readelf.c:1994
#, c-format
msgid "<unknown>: 0x%x"
msgstr ""
-#: readelf.c:2173
+#: readelf.c:2180
msgid ", <unknown>"
msgstr ""
-#: readelf.c:2259 readelf.c:7478
+#: readelf.c:2266 readelf.c:7485
msgid "unknown"
msgstr ""
-#: readelf.c:2260
+#: readelf.c:2267
msgid "unknown mac"
msgstr ""
-#: readelf.c:2324
+#: readelf.c:2331
msgid ", relocatable"
msgstr ""
-#: readelf.c:2327
+#: readelf.c:2334
msgid ", relocatable-lib"
msgstr ""
-#: readelf.c:2350
+#: readelf.c:2357
msgid ", unknown v850 architecture variant"
msgstr ""
-#: readelf.c:2407
+#: readelf.c:2414
msgid ", unknown CPU"
msgstr ""
-#: readelf.c:2422
+#: readelf.c:2429
msgid ", unknown ABI"
msgstr ""
-#: readelf.c:2445 readelf.c:2479
+#: readelf.c:2452 readelf.c:2486
msgid ", unknown ISA"
msgstr ""
-#: readelf.c:2656
+#: readelf.c:2663
msgid "Standalone App"
msgstr ""
-#: readelf.c:2665
+#: readelf.c:2672
msgid "Bare-metal C6000"
msgstr ""
-#: readelf.c:2675 readelf.c:3464 readelf.c:3480
+#: readelf.c:2682 readelf.c:3471 readelf.c:3487
#, c-format
msgid "<unknown: %x>"
msgstr ""
#. This message is probably going to be displayed in a 15
#. character wide field, so put the hex value first.
-#: readelf.c:3101
+#: readelf.c:3108
#, c-format
msgid "%08x: <unknown>"
msgstr ""
-#: readelf.c:3156
+#: readelf.c:3163
#, c-format
msgid "Usage: readelf <option(s)> elf-file(s)\n"
msgstr ""
-#: readelf.c:3157
+#: readelf.c:3164
#, c-format
msgid " Display information about the contents of ELF format files\n"
msgstr ""
-#: readelf.c:3158
+#: readelf.c:3165
#, c-format
msgid ""
" Options are:\n"
" Display the contents of DWARF2 debug sections\n"
msgstr ""
-#: readelf.c:3190
+#: readelf.c:3197
#, c-format
msgid ""
" --dwarf-depth=N Do not display DIEs at depth N or greater\n"
" or deeper\n"
msgstr ""
-#: readelf.c:3195
+#: readelf.c:3202
#, c-format
msgid ""
" -i --instruction-dump=<number|name>\n"
" Disassemble the contents of section <number|name>\n"
msgstr ""
-#: readelf.c:3199
+#: readelf.c:3206
#, c-format
msgid ""
" -I --histogram Display histogram of bucket list lengths\n"
" -v --version Display the version number of readelf\n"
msgstr ""
-#: readelf.c:3228 readelf.c:3257 readelf.c:3261 readelf.c:13609
+#: readelf.c:3235 readelf.c:3264 readelf.c:3268 readelf.c:13623
msgid "Out of memory allocating dump request table.\n"
msgstr ""
-#: readelf.c:3433
+#: readelf.c:3440
#, c-format
msgid "Invalid option '-%c'\n"
msgstr ""
-#: readelf.c:3448
+#: readelf.c:3455
msgid "Nothing to do.\n"
msgstr ""
-#: readelf.c:3460 readelf.c:3476 readelf.c:8061
+#: readelf.c:3467 readelf.c:3483 readelf.c:8068
msgid "none"
msgstr ""
-#: readelf.c:3477
+#: readelf.c:3484
msgid "2's complement, little endian"
msgstr ""
-#: readelf.c:3478
+#: readelf.c:3485
msgid "2's complement, big endian"
msgstr ""
-#: readelf.c:3496
+#: readelf.c:3503
msgid "Not an ELF file - it has the wrong magic bytes at the start\n"
msgstr ""
-#: readelf.c:3506
+#: readelf.c:3513
#, c-format
msgid "ELF Header:\n"
msgstr ""
-#: readelf.c:3507
+#: readelf.c:3514
#, c-format
msgid " Magic: "
msgstr ""
-#: readelf.c:3511
+#: readelf.c:3518
#, c-format
msgid " Class: %s\n"
msgstr ""
-#: readelf.c:3513
+#: readelf.c:3520
#, c-format
msgid " Data: %s\n"
msgstr ""
-#: readelf.c:3515
+#: readelf.c:3522
#, c-format
msgid " Version: %d %s\n"
msgstr ""
-#: readelf.c:3520
+#: readelf.c:3527
#, c-format
msgid "<unknown: %lx>"
msgstr ""
-#: readelf.c:3522
+#: readelf.c:3529
#, c-format
msgid " OS/ABI: %s\n"
msgstr ""
-#: readelf.c:3524
+#: readelf.c:3531
#, c-format
msgid " ABI Version: %d\n"
msgstr ""
-#: readelf.c:3526
+#: readelf.c:3533
#, c-format
msgid " Type: %s\n"
msgstr ""
-#: readelf.c:3528
+#: readelf.c:3535
#, c-format
msgid " Machine: %s\n"
msgstr ""
-#: readelf.c:3530
+#: readelf.c:3537
#, c-format
msgid " Version: 0x%lx\n"
msgstr ""
-#: readelf.c:3533
+#: readelf.c:3540
#, c-format
msgid " Entry point address: "
msgstr ""
-#: readelf.c:3535
+#: readelf.c:3542
#, c-format
msgid ""
"\n"
" Start of program headers: "
msgstr ""
-#: readelf.c:3537
+#: readelf.c:3544
#, c-format
msgid ""
" (bytes into file)\n"
" Start of section headers: "
msgstr ""
-#: readelf.c:3539
+#: readelf.c:3546
#, c-format
msgid " (bytes into file)\n"
msgstr ""
-#: readelf.c:3541
+#: readelf.c:3548
#, c-format
msgid " Flags: 0x%lx%s\n"
msgstr ""
-#: readelf.c:3544
+#: readelf.c:3551
#, c-format
msgid " Size of this header: %ld (bytes)\n"
msgstr ""
-#: readelf.c:3546
+#: readelf.c:3553
#, c-format
msgid " Size of program headers: %ld (bytes)\n"
msgstr ""
-#: readelf.c:3548
+#: readelf.c:3555
#, c-format
msgid " Number of program headers: %ld"
msgstr ""
-#: readelf.c:3555
+#: readelf.c:3562
#, c-format
msgid " Size of section headers: %ld (bytes)\n"
msgstr ""
-#: readelf.c:3557
+#: readelf.c:3564
#, c-format
msgid " Number of section headers: %ld"
msgstr ""
-#: readelf.c:3562
+#: readelf.c:3569
#, c-format
msgid " Section header string table index: %ld"
msgstr ""
-#: readelf.c:3569
+#: readelf.c:3576
#, c-format
msgid " <corrupt: out of range>"
msgstr ""
-#: readelf.c:3603 readelf.c:3637
+#: readelf.c:3610 readelf.c:3644
msgid "program headers"
msgstr ""
-#: readelf.c:3704
+#: readelf.c:3711
msgid ""
"possibly corrupt ELF header - it has a non-zero program header offset, but "
"no program headers"
msgstr ""
-#: readelf.c:3707
+#: readelf.c:3714
#, c-format
msgid ""
"\n"
"There are no program headers in this file.\n"
msgstr ""
-#: readelf.c:3713
+#: readelf.c:3720
#, c-format
msgid ""
"\n"
"Elf file type is %s\n"
msgstr ""
-#: readelf.c:3714
+#: readelf.c:3721
#, c-format
msgid "Entry point "
msgstr ""
-#: readelf.c:3716
+#: readelf.c:3723
#, c-format
msgid ""
"\n"
"There are %d program headers, starting at offset "
msgstr ""
-#: readelf.c:3728 readelf.c:3730
+#: readelf.c:3735 readelf.c:3737
#, c-format
msgid ""
"\n"
"Program Headers:\n"
msgstr ""
-#: readelf.c:3734
+#: readelf.c:3741
#, c-format
msgid ""
" Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align\n"
msgstr ""
-#: readelf.c:3737
+#: readelf.c:3744
#, c-format
msgid ""
" Type Offset VirtAddr PhysAddr FileSiz "
"MemSiz Flg Align\n"
msgstr ""
-#: readelf.c:3741
+#: readelf.c:3748
#, c-format
msgid " Type Offset VirtAddr PhysAddr\n"
msgstr ""
-#: readelf.c:3743
+#: readelf.c:3750
#, c-format
msgid " FileSiz MemSiz Flags Align\n"
msgstr ""
-#: readelf.c:3836
+#: readelf.c:3843
msgid "more than one dynamic segment\n"
msgstr ""
-#: readelf.c:3855
+#: readelf.c:3862
msgid "no .dynamic section in the dynamic segment\n"
msgstr ""
-#: readelf.c:3870
+#: readelf.c:3877
msgid "the .dynamic section is not contained within the dynamic segment\n"
msgstr ""
-#: readelf.c:3873
+#: readelf.c:3880
msgid "the .dynamic section is not the first section in the dynamic segment.\n"
msgstr ""
-#: readelf.c:3881
+#: readelf.c:3888
msgid "Unable to find program interpreter name\n"
msgstr ""
-#: readelf.c:3888
+#: readelf.c:3895
msgid ""
"Internal error: failed to create format string to display program "
"interpreter\n"
msgstr ""
-#: readelf.c:3892
+#: readelf.c:3899
msgid "Unable to read program interpreter name\n"
msgstr ""
-#: readelf.c:3895
+#: readelf.c:3902
#, c-format
msgid ""
"\n"
" [Requesting program interpreter: %s]"
msgstr ""
-#: readelf.c:3907
+#: readelf.c:3914
#, c-format
msgid ""
"\n"
" Section to Segment mapping:\n"
msgstr ""
-#: readelf.c:3908
+#: readelf.c:3915
#, c-format
msgid " Segment Sections...\n"
msgstr ""
-#: readelf.c:3944
+#: readelf.c:3951
msgid "Cannot interpret virtual addresses without program headers.\n"
msgstr ""
-#: readelf.c:3960
+#: readelf.c:3967
#, c-format
msgid "Virtual address 0x%lx not located in any PT_LOAD segment.\n"
msgstr ""
-#: readelf.c:3975 readelf.c:4018
+#: readelf.c:3982 readelf.c:4025
msgid "section headers"
msgstr ""
-#: readelf.c:4067 readelf.c:4147
+#: readelf.c:4074 readelf.c:4154
msgid "sh_entsize is zero\n"
msgstr ""
-#: readelf.c:4075 readelf.c:4155
+#: readelf.c:4082 readelf.c:4162
msgid "Invalid sh_entsize\n"
msgstr ""
-#: readelf.c:4080 readelf.c:4160
+#: readelf.c:4087 readelf.c:4167
msgid "symbols"
msgstr ""
-#: readelf.c:4092 readelf.c:4171
+#: readelf.c:4099 readelf.c:4178
msgid "symbol table section indicies"
msgstr ""
-#: readelf.c:4432
+#: readelf.c:4439
#, c-format
msgid "UNKNOWN (%*.*lx)"
msgstr ""
-#: readelf.c:4454
+#: readelf.c:4461
msgid ""
"possibly corrupt ELF file header - it has a non-zero section header offset, "
"but no section headers\n"
msgstr ""
-#: readelf.c:4457
+#: readelf.c:4464
#, c-format
msgid ""
"\n"
"There are no sections in this file.\n"
msgstr ""
-#: readelf.c:4463
+#: readelf.c:4470
#, c-format
msgid "There are %d section headers, starting at offset 0x%lx:\n"
msgstr ""
-#: readelf.c:4484 readelf.c:5072 readelf.c:5484 readelf.c:5790 readelf.c:6203
-#: readelf.c:7086 readelf.c:9206
+#: readelf.c:4491 readelf.c:5079 readelf.c:5491 readelf.c:5797 readelf.c:6210
+#: readelf.c:7093 readelf.c:9213
msgid "string table"
msgstr ""
-#: readelf.c:4551
+#: readelf.c:4558
#, c-format
msgid "Section %d has invalid sh_entsize %lx (expected %lx)\n"
msgstr ""
-#: readelf.c:4571
+#: readelf.c:4578
msgid "File contains multiple dynamic symbol tables\n"
msgstr ""
-#: readelf.c:4583
+#: readelf.c:4590
msgid "File contains multiple dynamic string tables\n"
msgstr ""
-#: readelf.c:4589
+#: readelf.c:4596
msgid "dynamic strings"
msgstr ""
-#: readelf.c:4596
+#: readelf.c:4603
msgid "File contains multiple symtab shndx tables\n"
msgstr ""
-#: readelf.c:4667
+#: readelf.c:4674
#, c-format
msgid ""
"\n"
"Section Headers:\n"
msgstr ""
-#: readelf.c:4669
+#: readelf.c:4676
#, c-format
msgid ""
"\n"
"Section Header:\n"
msgstr ""
-#: readelf.c:4675 readelf.c:4686 readelf.c:4697
+#: readelf.c:4682 readelf.c:4693 readelf.c:4704
#, c-format
msgid " [Nr] Name\n"
msgstr ""
-#: readelf.c:4676
+#: readelf.c:4683
#, c-format
msgid " Type Addr Off Size ES Lk Inf Al\n"
msgstr ""
-#: readelf.c:4680
+#: readelf.c:4687
#, c-format
msgid ""
" [Nr] Name Type Addr Off Size ES Flg Lk "
"Inf Al\n"
msgstr ""
-#: readelf.c:4687
+#: readelf.c:4694
#, c-format
msgid " Type Address Off Size ES Lk Inf Al\n"
msgstr ""
-#: readelf.c:4691
+#: readelf.c:4698
#, c-format
msgid ""
" [Nr] Name Type Address Off Size ES "
"Flg Lk Inf Al\n"
msgstr ""
-#: readelf.c:4698
+#: readelf.c:4705
#, c-format
msgid " Type Address Offset Link\n"
msgstr ""
-#: readelf.c:4699
+#: readelf.c:4706
#, c-format
msgid " Size EntSize Info Align\n"
msgstr ""
-#: readelf.c:4703
+#: readelf.c:4710
#, c-format
msgid " [Nr] Name Type Address Offset\n"
msgstr ""
-#: readelf.c:4704
+#: readelf.c:4711
#, c-format
msgid " Size EntSize Flags Link Info Align\n"
msgstr ""
-#: readelf.c:4709
+#: readelf.c:4716
#, c-format
msgid " Flags\n"
msgstr ""
-#: readelf.c:4789
+#: readelf.c:4796
#, c-format
msgid "section %u: sh_link value of %u is larger than the number of sections\n"
msgstr ""
-#: readelf.c:4889
+#: readelf.c:4896
#, c-format
msgid ""
"Key to Flags:\n"
" O (extra OS processing required) o (OS specific), p (processor specific)\n"
msgstr ""
-#: readelf.c:4894
+#: readelf.c:4901
#, c-format
msgid ""
"Key to Flags:\n"
" O (extra OS processing required) o (OS specific), p (processor specific)\n"
msgstr ""
-#: readelf.c:4916
+#: readelf.c:4923
#, c-format
msgid "[<unknown>: 0x%x] "
msgstr ""
-#: readelf.c:4942
+#: readelf.c:4949
#, c-format
msgid ""
"\n"
"There are no sections to group in this file.\n"
msgstr ""
-#: readelf.c:4949
+#: readelf.c:4956
msgid "Section headers are not available!\n"
msgstr ""
-#: readelf.c:4973
+#: readelf.c:4980
#, c-format
msgid ""
"\n"
"There are no section groups in this file.\n"
msgstr ""
-#: readelf.c:5011
+#: readelf.c:5018
#, c-format
msgid "Bad sh_link in group section `%s'\n"
msgstr ""
-#: readelf.c:5025
+#: readelf.c:5032
#, c-format
msgid "Corrupt header in group section `%s'\n"
msgstr ""
-#: readelf.c:5031 readelf.c:5042
+#: readelf.c:5038 readelf.c:5049
#, c-format
msgid "Bad sh_info in group section `%s'\n"
msgstr ""
-#: readelf.c:5081
+#: readelf.c:5088
msgid "section data"
msgstr ""
-#: readelf.c:5092
+#: readelf.c:5099
#, c-format
msgid ""
"\n"
"%sgroup section [%5u] `%s' [%s] contains %u sections:\n"
msgstr ""
-#: readelf.c:5095
+#: readelf.c:5102
#, c-format
msgid " [Index] Name\n"
msgstr ""
-#: readelf.c:5109
+#: readelf.c:5116
#, c-format
msgid "section [%5u] in group section [%5u] > maximum section [%5u]\n"
msgstr ""
-#: readelf.c:5118
+#: readelf.c:5125
#, c-format
msgid "section [%5u] in group section [%5u] already in group section [%5u]\n"
msgstr ""
-#: readelf.c:5131
+#: readelf.c:5138
#, c-format
msgid "section 0 in group section [%5u]\n"
msgstr ""
-#: readelf.c:5198
+#: readelf.c:5205
msgid "dynamic section image fixups"
msgstr ""
-#: readelf.c:5210
+#: readelf.c:5217
#, c-format
msgid ""
"\n"
"Image fixups for needed library #%d: %s - ident: %lx\n"
msgstr ""
-#: readelf.c:5213
+#: readelf.c:5220
#, c-format
msgid "Seg Offset Type SymVec DataType\n"
msgstr ""
-#: readelf.c:5245
+#: readelf.c:5252
msgid "dynamic section image relocations"
msgstr ""
-#: readelf.c:5249
+#: readelf.c:5256
#, c-format
msgid ""
"\n"
"Image relocs\n"
msgstr ""
-#: readelf.c:5251
+#: readelf.c:5258
#, c-format
msgid ""
"Seg Offset Type Addend Seg Sym Off\n"
msgstr ""
-#: readelf.c:5306
+#: readelf.c:5313
msgid "dynamic string section"
msgstr ""
-#: readelf.c:5407
+#: readelf.c:5414
#, c-format
msgid ""
"\n"
"'%s' relocation section at offset 0x%lx contains %ld bytes:\n"
msgstr ""
-#: readelf.c:5422
+#: readelf.c:5429
#, c-format
msgid ""
"\n"
"There are no dynamic relocations in this file.\n"
msgstr ""
-#: readelf.c:5446
+#: readelf.c:5453
#, c-format
msgid ""
"\n"
"Relocation section "
msgstr ""
-#: readelf.c:5453 readelf.c:5883 readelf.c:6220
+#: readelf.c:5460 readelf.c:5890 readelf.c:6227
#, c-format
msgid " at offset 0x%lx contains %lu entries:\n"
msgstr ""
-#: readelf.c:5503
+#: readelf.c:5510
#, c-format
msgid ""
"\n"
"There are no relocations in this file.\n"
msgstr ""
-#: readelf.c:5641
+#: readelf.c:5648
#, c-format
msgid "\tUnknown version.\n"
msgstr ""
-#: readelf.c:5694 readelf.c:6067
+#: readelf.c:5701 readelf.c:6074
msgid "unwind table"
msgstr ""
-#: readelf.c:5736 readelf.c:6149 readelf.c:6408
+#: readelf.c:5743 readelf.c:6156 readelf.c:6415
#, c-format
msgid "Skipping unexpected relocation type %s\n"
msgstr ""
-#: readelf.c:5798 readelf.c:6211 readelf.c:7094 readelf.c:7141
+#: readelf.c:5805 readelf.c:6218 readelf.c:7101 readelf.c:7148
#, c-format
msgid ""
"\n"
"There are no unwind sections in this file.\n"
msgstr ""
-#: readelf.c:5861
+#: readelf.c:5868
#, c-format
msgid ""
"\n"
"Could not find unwind info section for "
msgstr ""
-#: readelf.c:5866 readelf.c:5881 readelf.c:6218
+#: readelf.c:5873 readelf.c:5888 readelf.c:6225
#, c-format
msgid "'%s'"
msgstr ""
-#: readelf.c:5873
+#: readelf.c:5880
msgid "unwind info"
msgstr ""
-#: readelf.c:5876 readelf.c:6217
+#: readelf.c:5883 readelf.c:6224
#, c-format
msgid ""
"\n"
"Unwind section "
msgstr ""
-#: readelf.c:6326
+#: readelf.c:6333
msgid "unwind data"
msgstr ""
-#: readelf.c:6379
+#: readelf.c:6386
#, c-format
msgid "Skipping unexpected relocation at offset 0x%lx\n"
msgstr ""
-#: readelf.c:6483
+#: readelf.c:6490
#, c-format
msgid "[Truncated opcode]\n"
msgstr ""
-#: readelf.c:6527 readelf.c:6727
+#: readelf.c:6534 readelf.c:6734
#, c-format
msgid "Refuse to unwind"
msgstr ""
-#: readelf.c:6550
+#: readelf.c:6557
#, c-format
msgid " [Reserved]"
msgstr ""
-#: readelf.c:6578
+#: readelf.c:6585
#, c-format
msgid " finish"
msgstr ""
-#: readelf.c:6583 readelf.c:6669
+#: readelf.c:6590 readelf.c:6676
#, c-format
msgid "[Spare]"
msgstr ""
-#: readelf.c:6690 readelf.c:6824
+#: readelf.c:6697 readelf.c:6831
#, c-format
msgid " [unsupported opcode]"
msgstr ""
-#: readelf.c:6774
+#: readelf.c:6781
#, c-format
msgid "pop frame {"
msgstr ""
-#: readelf.c:6785
+#: readelf.c:6792
msgid "[pad]"
msgstr ""
-#: readelf.c:6813
+#: readelf.c:6820
#, c-format
msgid "sp = sp + %ld"
msgstr ""
-#: readelf.c:6871
+#: readelf.c:6878
#, c-format
msgid " Personality routine: "
msgstr ""
-#: readelf.c:6889
+#: readelf.c:6896
#, c-format
msgid " [Truncated data]\n"
msgstr ""
-#: readelf.c:6904
+#: readelf.c:6911
#, c-format
msgid " Compact model %d\n"
msgstr ""
-#: readelf.c:6940
+#: readelf.c:6947
#, c-format
msgid " Restore stack from frame pointer\n"
msgstr ""
-#: readelf.c:6942
+#: readelf.c:6949
#, c-format
msgid " Stack increment %d\n"
msgstr ""
-#: readelf.c:6943
+#: readelf.c:6950
#, c-format
msgid " Registers restored: "
msgstr ""
-#: readelf.c:6948
+#: readelf.c:6955
#, c-format
msgid " Return register: %s\n"
msgstr ""
-#: readelf.c:7031
+#: readelf.c:7038
#, c-format
msgid "Could not locate .ARM.extab section containing 0x%lx.\n"
msgstr ""
-#: readelf.c:7100
+#: readelf.c:7107
#, c-format
msgid ""
"\n"
"Unwind table index '%s' at offset 0x%lx contains %lu entries:\n"
msgstr ""
-#: readelf.c:7152
+#: readelf.c:7159
#, c-format
msgid "NONE\n"
msgstr ""
-#: readelf.c:7178
+#: readelf.c:7185
#, c-format
msgid "Interface Version: %s\n"
msgstr ""
-#: readelf.c:7180
+#: readelf.c:7187
#, c-format
msgid "<corrupt: %ld>\n"
msgstr ""
-#: readelf.c:7193
+#: readelf.c:7200
#, c-format
msgid "Time Stamp: %s\n"
msgstr ""
-#: readelf.c:7370 readelf.c:7416
+#: readelf.c:7377 readelf.c:7423
msgid "dynamic section"
msgstr ""
-#: readelf.c:7494
+#: readelf.c:7501
#, c-format
msgid ""
"\n"
"There is no dynamic section in this file.\n"
msgstr ""
-#: readelf.c:7532
+#: readelf.c:7539
msgid "Unable to seek to end of file!\n"
msgstr ""
-#: readelf.c:7545
+#: readelf.c:7552
msgid "Unable to determine the number of symbols to load\n"
msgstr ""
-#: readelf.c:7578
+#: readelf.c:7585
msgid "Unable to seek to end of file\n"
msgstr ""
-#: readelf.c:7585
+#: readelf.c:7592
msgid "Unable to determine the length of the dynamic string table\n"
msgstr ""
-#: readelf.c:7591
+#: readelf.c:7598
msgid "dynamic string table"
msgstr ""
-#: readelf.c:7628
+#: readelf.c:7635
msgid "symbol information"
msgstr ""
-#: readelf.c:7653
+#: readelf.c:7660
#, c-format
msgid ""
"\n"
"Dynamic section at offset 0x%lx contains %u entries:\n"
msgstr ""
-#: readelf.c:7656
+#: readelf.c:7663
#, c-format
msgid " Tag Type Name/Value\n"
msgstr ""
-#: readelf.c:7692
+#: readelf.c:7699
#, c-format
msgid "Auxiliary library"
msgstr ""
-#: readelf.c:7696
+#: readelf.c:7703
#, c-format
msgid "Filter library"
msgstr ""
-#: readelf.c:7700
+#: readelf.c:7707
#, c-format
msgid "Configuration file"
msgstr ""
-#: readelf.c:7704
+#: readelf.c:7711
#, c-format
msgid "Dependency audit library"
msgstr ""
-#: readelf.c:7708
+#: readelf.c:7715
#, c-format
msgid "Audit library"
msgstr ""
-#: readelf.c:7726 readelf.c:7754 readelf.c:7782
+#: readelf.c:7733 readelf.c:7761 readelf.c:7789
#, c-format
msgid "Flags:"
msgstr ""
-#: readelf.c:7729 readelf.c:7757 readelf.c:7784
+#: readelf.c:7736 readelf.c:7764 readelf.c:7791
#, c-format
msgid " None\n"
msgstr ""
-#: readelf.c:7905
+#: readelf.c:7912
#, c-format
msgid "Shared library: [%s]"
msgstr ""
-#: readelf.c:7908
+#: readelf.c:7915
#, c-format
msgid " program interpreter"
msgstr ""
-#: readelf.c:7912
+#: readelf.c:7919
#, c-format
msgid "Library soname: [%s]"
msgstr ""
-#: readelf.c:7916
+#: readelf.c:7923
#, c-format
msgid "Library rpath: [%s]"
msgstr ""
-#: readelf.c:7920
+#: readelf.c:7927
#, c-format
msgid "Library runpath: [%s]"
msgstr ""
-#: readelf.c:7953
+#: readelf.c:7960
#, c-format
msgid " (bytes)\n"
msgstr ""
-#: readelf.c:7983
+#: readelf.c:7990
#, c-format
msgid "Not needed object: [%s]\n"
msgstr ""
-#: readelf.c:8083
+#: readelf.c:8090
msgid "| <unknown>"
msgstr ""
-#: readelf.c:8116
+#: readelf.c:8123
#, c-format
msgid ""
"\n"
"Version definition section '%s' contains %u entries:\n"
msgstr ""
-#: readelf.c:8119
+#: readelf.c:8126
#, c-format
msgid " Addr: 0x"
msgstr ""
-#: readelf.c:8121 readelf.c:8239 readelf.c:8383
+#: readelf.c:8128 readelf.c:8246 readelf.c:8390
#, c-format
msgid " Offset: %#08lx Link: %u (%s)\n"
msgstr ""
-#: readelf.c:8129
+#: readelf.c:8136
msgid "version definition section"
msgstr ""
-#: readelf.c:8162
+#: readelf.c:8169
#, c-format
msgid " %#06x: Rev: %d Flags: %s"
msgstr ""
-#: readelf.c:8165
+#: readelf.c:8172
#, c-format
msgid " Index: %d Cnt: %d "
msgstr ""
-#: readelf.c:8181
+#: readelf.c:8188
#, c-format
msgid "Name: %s\n"
msgstr ""
-#: readelf.c:8183
+#: readelf.c:8190
#, c-format
msgid "Name index: %ld\n"
msgstr ""
-#: readelf.c:8205
+#: readelf.c:8212
#, c-format
msgid " %#06x: Parent %d: %s\n"
msgstr ""
-#: readelf.c:8208
+#: readelf.c:8215
#, c-format
msgid " %#06x: Parent %d, name index: %ld\n"
msgstr ""
-#: readelf.c:8213
+#: readelf.c:8220
#, c-format
msgid " Version def aux past end of section\n"
msgstr ""
-#: readelf.c:8219
+#: readelf.c:8226
#, c-format
msgid " Version definition past end of section\n"
msgstr ""
-#: readelf.c:8234
+#: readelf.c:8241
#, c-format
msgid ""
"\n"
"Version needs section '%s' contains %u entries:\n"
msgstr ""
-#: readelf.c:8237
+#: readelf.c:8244
#, c-format
msgid " Addr: 0x"
msgstr ""
-#: readelf.c:8248
+#: readelf.c:8255
msgid "Version Needs section"
msgstr ""
-#: readelf.c:8276
+#: readelf.c:8283
#, c-format
msgid " %#06x: Version: %d"
msgstr ""
-#: readelf.c:8279
+#: readelf.c:8286
#, c-format
msgid " File: %s"
msgstr ""
-#: readelf.c:8281
+#: readelf.c:8288
#, c-format
msgid " File: %lx"
msgstr ""
-#: readelf.c:8283
+#: readelf.c:8290
#, c-format
msgid " Cnt: %d\n"
msgstr ""
-#: readelf.c:8308
+#: readelf.c:8315
#, c-format
msgid " %#06x: Name: %s"
msgstr ""
-#: readelf.c:8311
+#: readelf.c:8318
#, c-format
msgid " %#06x: Name index: %lx"
msgstr ""
-#: readelf.c:8314
+#: readelf.c:8321
#, c-format
msgid " Flags: %s Version: %d\n"
msgstr ""
-#: readelf.c:8327
+#: readelf.c:8334
msgid "Missing Version Needs auxillary information\n"
msgstr ""
-#: readelf.c:8333
+#: readelf.c:8340
msgid "Missing Version Needs information\n"
msgstr ""
-#: readelf.c:8371
+#: readelf.c:8378
msgid "version string table"
msgstr ""
-#: readelf.c:8378
+#: readelf.c:8385
#, c-format
msgid ""
"\n"
"Version symbols section '%s' contains %d entries:\n"
msgstr ""
-#: readelf.c:8381
+#: readelf.c:8388
#, c-format
msgid " Addr: "
msgstr ""
-#: readelf.c:8392
+#: readelf.c:8399
msgid "version symbol data"
msgstr ""
-#: readelf.c:8420
+#: readelf.c:8427
msgid " 0 (*local*) "
msgstr ""
-#: readelf.c:8424
+#: readelf.c:8431
msgid " 1 (*global*) "
msgstr ""
-#: readelf.c:8435
+#: readelf.c:8442
msgid "invalid index into symbol array\n"
msgstr ""
-#: readelf.c:8469 readelf.c:9272
+#: readelf.c:8476 readelf.c:9279
msgid "version need"
msgstr ""
-#: readelf.c:8480
+#: readelf.c:8487
msgid "version need aux (2)"
msgstr ""
-#: readelf.c:8501 readelf.c:8563
+#: readelf.c:8508 readelf.c:8570
msgid "*invalid*"
msgstr ""
-#: readelf.c:8531 readelf.c:9350
+#: readelf.c:8538 readelf.c:9357
msgid "version def"
msgstr ""
-#: readelf.c:8557 readelf.c:9372
+#: readelf.c:8564 readelf.c:9379
msgid "version def aux"
msgstr ""
-#: readelf.c:8592
+#: readelf.c:8599
#, c-format
msgid ""
"\n"
"No version information found in this file.\n"
msgstr ""
-#: readelf.c:8800
+#: readelf.c:8807
#, c-format
msgid "<other>: %x"
msgstr ""
-#: readelf.c:8862
+#: readelf.c:8869
msgid "Unable to read in dynamic data\n"
msgstr ""
-#: readelf.c:8912
+#: readelf.c:8919
#, c-format
msgid " <corrupt: %14ld>"
msgstr ""
-#: readelf.c:8955 readelf.c:9007 readelf.c:9031 readelf.c:9061 readelf.c:9085
+#: readelf.c:8962 readelf.c:9014 readelf.c:9038 readelf.c:9068 readelf.c:9092
msgid "Unable to seek to start of dynamic information\n"
msgstr ""
-#: readelf.c:8961 readelf.c:9013
+#: readelf.c:8968 readelf.c:9020
msgid "Failed to read in number of buckets\n"
msgstr ""
-#: readelf.c:8967
+#: readelf.c:8974
msgid "Failed to read in number of chains\n"
msgstr ""
-#: readelf.c:9069
+#: readelf.c:9076
msgid "Failed to determine last chain length\n"
msgstr ""
-#: readelf.c:9113
+#: readelf.c:9120
#, c-format
msgid ""
"\n"
"Symbol table for image:\n"
msgstr ""
-#: readelf.c:9115 readelf.c:9133
+#: readelf.c:9122 readelf.c:9140
#, c-format
msgid " Num Buc: Value Size Type Bind Vis Ndx Name\n"
msgstr ""
-#: readelf.c:9117 readelf.c:9135
+#: readelf.c:9124 readelf.c:9142
#, c-format
msgid " Num Buc: Value Size Type Bind Vis Ndx Name\n"
msgstr ""
-#: readelf.c:9131
+#: readelf.c:9138
#, c-format
msgid ""
"\n"
"Symbol table of `.gnu.hash' for image:\n"
msgstr ""
-#: readelf.c:9175
+#: readelf.c:9182
#, c-format
msgid ""
"\n"
"Symbol table '%s' has a sh_entsize of zero!\n"
msgstr ""
-#: readelf.c:9180
+#: readelf.c:9187
#, c-format
msgid ""
"\n"
"Symbol table '%s' contains %lu entries:\n"
msgstr ""
-#: readelf.c:9185
+#: readelf.c:9192
#, c-format
msgid " Num: Value Size Type Bind Vis Ndx Name\n"
msgstr ""
-#: readelf.c:9187
+#: readelf.c:9194
#, c-format
msgid " Num: Value Size Type Bind Vis Ndx Name\n"
msgstr ""
-#: readelf.c:9242
+#: readelf.c:9249
msgid "version data"
msgstr ""
-#: readelf.c:9291
+#: readelf.c:9298
msgid "version need aux (3)"
msgstr ""
-#: readelf.c:9325
+#: readelf.c:9332
msgid "bad dynamic symbol\n"
msgstr ""
-#: readelf.c:9397
+#: readelf.c:9404
#, c-format
msgid ""
"\n"
"Dynamic symbol information is not available for displaying symbols.\n"
msgstr ""
-#: readelf.c:9409
+#: readelf.c:9416
#, c-format
msgid ""
"\n"
"Histogram for bucket list length (total of %lu buckets):\n"
msgstr ""
-#: readelf.c:9411 readelf.c:9481
+#: readelf.c:9418 readelf.c:9488
#, c-format
msgid " Length Number %% of total Coverage\n"
msgstr ""
-#: readelf.c:9479
+#: readelf.c:9486
#, c-format
msgid ""
"\n"
"Histogram for `.gnu.hash' bucket list length (total of %lu buckets):\n"
msgstr ""
-#: readelf.c:9545
+#: readelf.c:9552
#, c-format
msgid ""
"\n"
"Dynamic info segment at offset 0x%lx contains %d entries:\n"
msgstr ""
-#: readelf.c:9548
+#: readelf.c:9555
#, c-format
msgid " Num: Name BoundTo Flags\n"
msgstr ""
-#: readelf.c:9557
+#: readelf.c:9564
#, c-format
msgid "<corrupt: %19ld>"
msgstr ""
-#: readelf.c:9639
+#: readelf.c:9646
msgid "Unhandled MN10300 reloc type found after SYM_DIFF reloc"
msgstr ""
-#: readelf.c:9804
+#: readelf.c:9813
#, c-format
msgid ""
"Missing knowledge of 32-bit reloc types used in DWARF sections of machine "
"number %d\n"
msgstr ""
-#: readelf.c:10124
+#: readelf.c:10138
#, c-format
msgid "unable to apply unsupported reloc type %d to section %s\n"
msgstr ""
-#: readelf.c:10132
+#: readelf.c:10146
#, c-format
msgid "skipping invalid relocation offset 0x%lx in section %s\n"
msgstr ""
-#: readelf.c:10141
+#: readelf.c:10155
#, c-format
msgid "skipping invalid relocation symbol index 0x%lx in section %s\n"
msgstr ""
-#: readelf.c:10163
+#: readelf.c:10177
#, c-format
msgid "skipping unexpected symbol type %s in %ld'th relocation in section %s\n"
msgstr ""
-#: readelf.c:10209
+#: readelf.c:10223
#, c-format
msgid ""
"\n"
"Assembly dump of section %s\n"
msgstr ""
-#: readelf.c:10230
+#: readelf.c:10244
#, c-format
msgid ""
"\n"
"Section '%s' has no data to dump.\n"
msgstr ""
-#: readelf.c:10236
+#: readelf.c:10250
msgid "section contents"
msgstr ""
-#: readelf.c:10255
+#: readelf.c:10269
#, c-format
msgid ""
"\n"
"String dump of section '%s':\n"
msgstr ""
-#: readelf.c:10273
+#: readelf.c:10287
#, c-format
msgid ""
" Note: This section has relocations against it, but these have NOT been "
"applied to this dump.\n"
msgstr ""
-#: readelf.c:10304
+#: readelf.c:10318
#, c-format
msgid " No strings found in this section."
msgstr ""
-#: readelf.c:10326
+#: readelf.c:10340
#, c-format
msgid ""
"\n"
"Hex dump of section '%s':\n"
msgstr ""
-#: readelf.c:10350
+#: readelf.c:10364
#, c-format
msgid ""
" NOTE: This section has relocations against it, but these have NOT been "
"applied to this dump.\n"
msgstr ""
-#: readelf.c:10484
+#: readelf.c:10498
#, c-format
msgid "%s section data"
msgstr ""
-#: readelf.c:10554
+#: readelf.c:10568
#, c-format
msgid ""
"\n"
#. which has the NOBITS type - the bits in the file will be random.
#. This can happen when a file containing a .eh_frame section is
#. stripped with the --only-keep-debug command line option.
-#: readelf.c:10563
+#: readelf.c:10577
#, c-format
msgid "section '%s' has the NOBITS type - its contents are unreliable.\n"
msgstr ""
-#: readelf.c:10599
+#: readelf.c:10613
#, c-format
msgid "Unrecognized debug section: %s\n"
msgstr ""
-#: readelf.c:10627
+#: readelf.c:10641
#, c-format
msgid "Section '%s' was not dumped because it does not exist!\n"
msgstr ""
-#: readelf.c:10668
+#: readelf.c:10682
#, c-format
msgid "Section %d was not dumped because it does not exist!\n"
msgstr ""
-#: readelf.c:10846 readelf.c:10860 readelf.c:10879 readelf.c:11279
+#: readelf.c:10860 readelf.c:10874 readelf.c:10893 readelf.c:11293
#, c-format
msgid "None\n"
msgstr ""
-#: readelf.c:10847
+#: readelf.c:10861
#, c-format
msgid "Application\n"
msgstr ""
-#: readelf.c:10848
+#: readelf.c:10862
#, c-format
msgid "Realtime\n"
msgstr ""
-#: readelf.c:10849
+#: readelf.c:10863
#, c-format
msgid "Microcontroller\n"
msgstr ""
-#: readelf.c:10850
+#: readelf.c:10864
#, c-format
msgid "Application or Realtime\n"
msgstr ""
-#: readelf.c:10861 readelf.c:10881 readelf.c:11333 readelf.c:11351
-#: readelf.c:11426 readelf.c:11447
+#: readelf.c:10875 readelf.c:10895 readelf.c:11347 readelf.c:11365
+#: readelf.c:11440 readelf.c:11461
#, c-format
msgid "8-byte\n"
msgstr ""
-#: readelf.c:10862 readelf.c:11429 readelf.c:11450
+#: readelf.c:10876 readelf.c:11443 readelf.c:11464
#, c-format
msgid "4-byte\n"
msgstr ""
-#: readelf.c:10866 readelf.c:10885
+#: readelf.c:10880 readelf.c:10899
#, c-format
msgid "8-byte and up to %d-byte extended\n"
msgstr ""
-#: readelf.c:10880
+#: readelf.c:10894
#, c-format
msgid "8-byte, except leaf SP\n"
msgstr ""
-#: readelf.c:10896 readelf.c:10986 readelf.c:11465
+#: readelf.c:10910 readelf.c:11000 readelf.c:11479
#, c-format
msgid "flag = %d, vendor = %s\n"
msgstr ""
-#: readelf.c:10902
+#: readelf.c:10916
#, c-format
msgid "True\n"
msgstr ""
-#: readelf.c:11031 readelf.c:11217
+#: readelf.c:11045 readelf.c:11231
#, c-format
msgid "Hard or soft float\n"
msgstr ""
-#: readelf.c:11034
+#: readelf.c:11048
#, c-format
msgid "Hard float\n"
msgstr ""
-#: readelf.c:11037 readelf.c:11226
+#: readelf.c:11051 readelf.c:11240
#, c-format
msgid "Soft float\n"
msgstr ""
-#: readelf.c:11040
+#: readelf.c:11054
#, c-format
msgid "Single-precision hard float\n"
msgstr ""
-#: readelf.c:11057 readelf.c:11083
+#: readelf.c:11071 readelf.c:11097
#, c-format
msgid "Any\n"
msgstr ""
-#: readelf.c:11060
+#: readelf.c:11074
#, c-format
msgid "Generic\n"
msgstr ""
-#: readelf.c:11089
+#: readelf.c:11103
#, c-format
msgid "Memory\n"
msgstr ""
-#: readelf.c:11220
+#: readelf.c:11234
#, c-format
msgid "Hard float (double precision)\n"
msgstr ""
-#: readelf.c:11223
+#: readelf.c:11237
#, c-format
msgid "Hard float (single precision)\n"
msgstr ""
-#: readelf.c:11229
+#: readelf.c:11243
#, c-format
msgid "Hard float (MIPS32r2 64-bit FPU)\n"
msgstr ""
-#: readelf.c:11312
+#: readelf.c:11326
#, c-format
msgid "Not used\n"
msgstr ""
-#: readelf.c:11315
+#: readelf.c:11329
#, c-format
msgid "2 bytes\n"
msgstr ""
-#: readelf.c:11318
+#: readelf.c:11332
#, c-format
msgid "4 bytes\n"
msgstr ""
-#: readelf.c:11336 readelf.c:11354 readelf.c:11432 readelf.c:11453
+#: readelf.c:11350 readelf.c:11368 readelf.c:11446 readelf.c:11467
#, c-format
msgid "16-byte\n"
msgstr ""
-#: readelf.c:11369
+#: readelf.c:11383
#, c-format
msgid "DSBT addressing not used\n"
msgstr ""
-#: readelf.c:11372
+#: readelf.c:11386
#, c-format
msgid "DSBT addressing used\n"
msgstr ""
-#: readelf.c:11387
+#: readelf.c:11401
#, c-format
msgid "Data addressing position-dependent\n"
msgstr ""
-#: readelf.c:11390
+#: readelf.c:11404
#, c-format
msgid "Data addressing position-independent, GOT near DP\n"
msgstr ""
-#: readelf.c:11393
+#: readelf.c:11407
#, c-format
msgid "Data addressing position-independent, GOT far from DP\n"
msgstr ""
-#: readelf.c:11408
+#: readelf.c:11422
#, c-format
msgid "Code addressing position-dependent\n"
msgstr ""
-#: readelf.c:11411
+#: readelf.c:11425
#, c-format
msgid "Code addressing position-independent\n"
msgstr ""
-#: readelf.c:11517
+#: readelf.c:11531
msgid "attributes"
msgstr ""
-#: readelf.c:11538
+#: readelf.c:11552
#, c-format
msgid "ERROR: Bad section length (%d > %d)\n"
msgstr ""
-#: readelf.c:11544
+#: readelf.c:11558
#, c-format
msgid "Attribute Section: %s\n"
msgstr ""
-#: readelf.c:11569
+#: readelf.c:11583
#, c-format
msgid "ERROR: Bad subsection length (%d > %d)\n"
msgstr ""
-#: readelf.c:11581
+#: readelf.c:11595
#, c-format
msgid "File Attributes\n"
msgstr ""
-#: readelf.c:11584
+#: readelf.c:11598
#, c-format
msgid "Section Attributes:"
msgstr ""
-#: readelf.c:11587
+#: readelf.c:11601
#, c-format
msgid "Symbol Attributes:"
msgstr ""
-#: readelf.c:11602
+#: readelf.c:11616
#, c-format
msgid "Unknown tag: %d\n"
msgstr ""
#. ??? Do something sensible, like dump hex.
-#: readelf.c:11621
+#: readelf.c:11635
#, c-format
msgid " Unknown section contexts\n"
msgstr ""
-#: readelf.c:11628
+#: readelf.c:11642
#, c-format
msgid "Unknown format '%c'\n"
msgstr ""
-#: readelf.c:11679 readelf.c:11701
+#: readelf.c:11693 readelf.c:11715
msgid "<unknown>"
msgstr ""
-#: readelf.c:11796 readelf.c:12330
+#: readelf.c:11810 readelf.c:12344
msgid "liblist section data"
msgstr ""
-#: readelf.c:11799
+#: readelf.c:11813
#, c-format
msgid ""
"\n"
"Section '.liblist' contains %lu entries:\n"
msgstr ""
-#: readelf.c:11801
+#: readelf.c:11815
msgid ""
" Library Time Stamp Checksum Version Flags\n"
msgstr ""
-#: readelf.c:11827
+#: readelf.c:11841
#, c-format
msgid "<corrupt: %9ld>"
msgstr ""
-#: readelf.c:11832
+#: readelf.c:11846
msgid " NONE"
msgstr ""
-#: readelf.c:11883
+#: readelf.c:11897
msgid "options"
msgstr ""
-#: readelf.c:11914
+#: readelf.c:11928
#, c-format
msgid ""
"\n"
"Section '%s' contains %d entries:\n"
msgstr ""
-#: readelf.c:12075
+#: readelf.c:12089
msgid "conflict list found without a dynamic symbol table\n"
msgstr ""
-#: readelf.c:12092 readelf.c:12107
+#: readelf.c:12106 readelf.c:12121
msgid "conflict"
msgstr ""
-#: readelf.c:12117
+#: readelf.c:12131
#, c-format
msgid ""
"\n"
"Section '.conflict' contains %lu entries:\n"
msgstr ""
-#: readelf.c:12119
+#: readelf.c:12133
msgid " Num: Index Value Name"
msgstr ""
-#: readelf.c:12131 readelf.c:12220 readelf.c:12291
+#: readelf.c:12145 readelf.c:12234 readelf.c:12305
#, c-format
msgid "<corrupt: %14ld>"
msgstr ""
-#: readelf.c:12153
+#: readelf.c:12167
msgid "Global Offset Table data"
msgstr ""
-#: readelf.c:12157
+#: readelf.c:12171
#, c-format
msgid ""
"\n"
"Primary GOT:\n"
msgstr ""
-#: readelf.c:12158
+#: readelf.c:12172
#, c-format
msgid " Canonical gp value: "
msgstr ""
-#: readelf.c:12162 readelf.c:12262
+#: readelf.c:12176 readelf.c:12276
#, c-format
msgid " Reserved entries:\n"
msgstr ""
-#: readelf.c:12163
+#: readelf.c:12177
#, c-format
msgid " %*s %10s %*s Purpose\n"
msgstr ""
-#: readelf.c:12164 readelf.c:12181 readelf.c:12197 readelf.c:12264
-#: readelf.c:12273
+#: readelf.c:12178 readelf.c:12195 readelf.c:12211 readelf.c:12278
+#: readelf.c:12287
msgid "Address"
msgstr ""
-#: readelf.c:12164 readelf.c:12181 readelf.c:12198
+#: readelf.c:12178 readelf.c:12195 readelf.c:12212
msgid "Access"
msgstr ""
-#: readelf.c:12165 readelf.c:12182 readelf.c:12199 readelf.c:12264
-#: readelf.c:12274
+#: readelf.c:12179 readelf.c:12196 readelf.c:12213 readelf.c:12278
+#: readelf.c:12288
msgid "Initial"
msgstr ""
-#: readelf.c:12167
+#: readelf.c:12181
#, c-format
msgid " Lazy resolver\n"
msgstr ""
-#: readelf.c:12173
+#: readelf.c:12187
#, c-format
msgid " Module pointer (GNU extension)\n"
msgstr ""
-#: readelf.c:12179
+#: readelf.c:12193
#, c-format
msgid " Local entries:\n"
msgstr ""
-#: readelf.c:12195
+#: readelf.c:12209
#, c-format
msgid " Global entries:\n"
msgstr ""
-#: readelf.c:12200 readelf.c:12275
+#: readelf.c:12214 readelf.c:12289
msgid "Sym.Val."
msgstr ""
#. Note for translators: "Ndx" = abbreviated form of "Index".
-#: readelf.c:12203 readelf.c:12275
+#: readelf.c:12217 readelf.c:12289
msgid "Ndx"
msgstr ""
-#: readelf.c:12203 readelf.c:12275
+#: readelf.c:12217 readelf.c:12289
msgid "Name"
msgstr ""
-#: readelf.c:12257
+#: readelf.c:12271
msgid "Procedure Linkage Table data"
msgstr ""
-#: readelf.c:12263
+#: readelf.c:12277
#, c-format
msgid " %*s %*s Purpose\n"
msgstr ""
-#: readelf.c:12266
+#: readelf.c:12280
#, c-format
msgid " PLT lazy resolver\n"
msgstr ""
-#: readelf.c:12268
+#: readelf.c:12282
#, c-format
msgid " Module pointer\n"
msgstr ""
-#: readelf.c:12271
+#: readelf.c:12285
#, c-format
msgid " Entries:\n"
msgstr ""
-#: readelf.c:12338
+#: readelf.c:12352
msgid "liblist string table"
msgstr ""
-#: readelf.c:12348
+#: readelf.c:12362
#, c-format
msgid ""
"\n"
"Library list section '%s' contains %lu entries:\n"
msgstr ""
-#: readelf.c:12352
+#: readelf.c:12366
msgid " Library Time Stamp Checksum Version Flags"
msgstr ""
-#: readelf.c:12402
+#: readelf.c:12416
msgid "NT_AUXV (auxiliary vector)"
msgstr ""
-#: readelf.c:12404
+#: readelf.c:12418
msgid "NT_PRSTATUS (prstatus structure)"
msgstr ""
-#: readelf.c:12406
+#: readelf.c:12420
msgid "NT_FPREGSET (floating point registers)"
msgstr ""
-#: readelf.c:12408
+#: readelf.c:12422
msgid "NT_PRPSINFO (prpsinfo structure)"
msgstr ""
-#: readelf.c:12410
+#: readelf.c:12424
msgid "NT_TASKSTRUCT (task structure)"
msgstr ""
-#: readelf.c:12412
+#: readelf.c:12426
msgid "NT_PRXFPREG (user_xfpregs structure)"
msgstr ""
-#: readelf.c:12414
+#: readelf.c:12428
msgid "NT_PPC_VMX (ppc Altivec registers)"
msgstr ""
-#: readelf.c:12416
+#: readelf.c:12430
msgid "NT_PPC_VSX (ppc VSX registers)"
msgstr ""
-#: readelf.c:12418
+#: readelf.c:12432
msgid "NT_X86_XSTATE (x86 XSAVE extended state)"
msgstr ""
-#: readelf.c:12420
+#: readelf.c:12434
msgid "NT_S390_HIGH_GPRS (s390 upper register halves)"
msgstr ""
-#: readelf.c:12422
+#: readelf.c:12436
msgid "NT_S390_TIMER (s390 timer register)"
msgstr ""
-#: readelf.c:12424
+#: readelf.c:12438
msgid "NT_S390_TODCMP (s390 TOD comparator register)"
msgstr ""
-#: readelf.c:12426
+#: readelf.c:12440
msgid "NT_S390_TODPREG (s390 TOD programmable register)"
msgstr ""
-#: readelf.c:12428
+#: readelf.c:12442
msgid "NT_S390_CTRS (s390 control registers)"
msgstr ""
-#: readelf.c:12430
+#: readelf.c:12444
msgid "NT_S390_PREFIX (s390 prefix register)"
msgstr ""
-#: readelf.c:12432
+#: readelf.c:12446
msgid "NT_ARM_VFP (arm VFP registers)"
msgstr ""
-#: readelf.c:12434
+#: readelf.c:12448
msgid "NT_PSTATUS (pstatus structure)"
msgstr ""
-#: readelf.c:12436
+#: readelf.c:12450
msgid "NT_FPREGS (floating point registers)"
msgstr ""
-#: readelf.c:12438
+#: readelf.c:12452
msgid "NT_PSINFO (psinfo structure)"
msgstr ""
-#: readelf.c:12440
+#: readelf.c:12454
msgid "NT_LWPSTATUS (lwpstatus_t structure)"
msgstr ""
-#: readelf.c:12442
+#: readelf.c:12456
msgid "NT_LWPSINFO (lwpsinfo_t structure)"
msgstr ""
-#: readelf.c:12444
+#: readelf.c:12458
msgid "NT_WIN32PSTATUS (win32_pstatus structure)"
msgstr ""
-#: readelf.c:12452
+#: readelf.c:12466
msgid "NT_VERSION (version)"
msgstr ""
-#: readelf.c:12454
+#: readelf.c:12468
msgid "NT_ARCH (architecture)"
msgstr ""
-#: readelf.c:12459 readelf.c:12482 readelf.c:12561 readelf.c:12619
-#: readelf.c:12696
+#: readelf.c:12473 readelf.c:12496 readelf.c:12575 readelf.c:12633
+#: readelf.c:12710
#, c-format
msgid "Unknown note type: (0x%08x)"
msgstr ""
-#: readelf.c:12471
+#: readelf.c:12485
msgid "NT_GNU_ABI_TAG (ABI version tag)"
msgstr ""
-#: readelf.c:12473
+#: readelf.c:12487
msgid "NT_GNU_HWCAP (DSO-supplied software HWCAP info)"
msgstr ""
-#: readelf.c:12475
+#: readelf.c:12489
msgid "NT_GNU_BUILD_ID (unique build ID bitstring)"
msgstr ""
-#: readelf.c:12477
+#: readelf.c:12491
msgid "NT_GNU_GOLD_VERSION (gold version)"
msgstr ""
-#: readelf.c:12495
+#: readelf.c:12509
#, c-format
msgid " Build ID: "
msgstr ""
-#: readelf.c:12534
+#: readelf.c:12548
#, c-format
msgid " OS: %s, ABI: %ld.%ld.%ld\n"
msgstr ""
#. NetBSD core "procinfo" structure.
-#: readelf.c:12551
+#: readelf.c:12565
msgid "NetBSD procinfo structure"
msgstr ""
-#: readelf.c:12578 readelf.c:12592
+#: readelf.c:12592 readelf.c:12606
msgid "PT_GETREGS (reg structure)"
msgstr ""
-#: readelf.c:12580 readelf.c:12594
+#: readelf.c:12594 readelf.c:12608
msgid "PT_GETFPREGS (fpreg structure)"
msgstr ""
-#: readelf.c:12613
+#: readelf.c:12627
msgid "NT_STAPSDT (SystemTap probe descriptors)"
msgstr ""
-#: readelf.c:12646
+#: readelf.c:12660
#, c-format
msgid " Provider: %s\n"
msgstr ""
-#: readelf.c:12647
+#: readelf.c:12661
#, c-format
msgid " Name: %s\n"
msgstr ""
-#: readelf.c:12648
+#: readelf.c:12662
#, c-format
msgid " Location: "
msgstr ""
-#: readelf.c:12650
+#: readelf.c:12664
#, c-format
msgid ", Base: "
msgstr ""
-#: readelf.c:12652
+#: readelf.c:12666
#, c-format
msgid ", Semaphore: "
msgstr ""
-#: readelf.c:12655
+#: readelf.c:12669
#, c-format
msgid " Arguments: %s\n"
msgstr ""
-#: readelf.c:12668
+#: readelf.c:12682
msgid "NT_VMS_MHD (module header)"
msgstr ""
-#: readelf.c:12670
+#: readelf.c:12684
msgid "NT_VMS_LNM (language name)"
msgstr ""
-#: readelf.c:12672
+#: readelf.c:12686
msgid "NT_VMS_SRC (source files)"
msgstr ""
-#: readelf.c:12676
+#: readelf.c:12690
msgid "NT_VMS_EIDC (consistency check)"
msgstr ""
-#: readelf.c:12678
+#: readelf.c:12692
msgid "NT_VMS_FPMODE (FP mode)"
msgstr ""
-#: readelf.c:12682
+#: readelf.c:12696
msgid "NT_VMS_IMGNAM (image name)"
msgstr ""
-#: readelf.c:12684
+#: readelf.c:12698
msgid "NT_VMS_IMGID (image id)"
msgstr ""
-#: readelf.c:12686
+#: readelf.c:12700
msgid "NT_VMS_LINKID (link id)"
msgstr ""
-#: readelf.c:12688
+#: readelf.c:12702
msgid "NT_VMS_IMGBID (build id)"
msgstr ""
-#: readelf.c:12690
+#: readelf.c:12704
msgid "NT_VMS_GSTNAM (sym table name)"
msgstr ""
-#: readelf.c:12710
+#: readelf.c:12724
#, c-format
msgid " Creation date : %.17s\n"
msgstr ""
-#: readelf.c:12711
+#: readelf.c:12725
#, c-format
msgid " Last patch date: %.17s\n"
msgstr ""
-#: readelf.c:12712
+#: readelf.c:12726
#, c-format
msgid " Module name : %s\n"
msgstr ""
-#: readelf.c:12713
+#: readelf.c:12727
#, c-format
msgid " Module version : %s\n"
msgstr ""
-#: readelf.c:12716
+#: readelf.c:12730
#, c-format
msgid " Invalid size\n"
msgstr ""
-#: readelf.c:12719
+#: readelf.c:12733
#, c-format
msgid " Language: %s\n"
msgstr ""
-#: readelf.c:12723
+#: readelf.c:12737
#, c-format
msgid " Floating Point mode: "
msgstr ""
-#: readelf.c:12728
+#: readelf.c:12742
#, c-format
msgid " Link time: "
msgstr ""
-#: readelf.c:12734
+#: readelf.c:12748
#, c-format
msgid " Patch time: "
msgstr ""
-#: readelf.c:12740
+#: readelf.c:12754
#, c-format
msgid " Major id: %u, minor id: %u\n"
msgstr ""
-#: readelf.c:12743
+#: readelf.c:12757
#, c-format
msgid " Last modified : "
msgstr ""
-#: readelf.c:12746
+#: readelf.c:12760
#, c-format
msgid ""
"\n"
" Link flags : "
msgstr ""
-#: readelf.c:12749
+#: readelf.c:12763
#, c-format
msgid " Header flags: 0x%08x\n"
msgstr ""
-#: readelf.c:12751
+#: readelf.c:12765
#, c-format
msgid " Image id : %s\n"
msgstr ""
-#: readelf.c:12755
+#: readelf.c:12769
#, c-format
msgid " Image name: %s\n"
msgstr ""
-#: readelf.c:12758
+#: readelf.c:12772
#, c-format
msgid " Global symbol table name: %s\n"
msgstr ""
-#: readelf.c:12761
+#: readelf.c:12775
#, c-format
msgid " Image id: %s\n"
msgstr ""
-#: readelf.c:12764
+#: readelf.c:12778
#, c-format
msgid " Linker id: %s\n"
msgstr ""
-#: readelf.c:12839
+#: readelf.c:12853
msgid "notes"
msgstr ""
-#: readelf.c:12845
+#: readelf.c:12859
#, c-format
msgid ""
"\n"
"Notes at offset 0x%08lx with length 0x%08lx:\n"
msgstr ""
-#: readelf.c:12847
+#: readelf.c:12861
#, c-format
msgid " %-20s %10s\tDescription\n"
msgstr ""
-#: readelf.c:12847
+#: readelf.c:12861
msgid "Owner"
msgstr ""
-#: readelf.c:12847
+#: readelf.c:12861
msgid "Data size"
msgstr ""
-#: readelf.c:12885 readelf.c:12898
+#: readelf.c:12899 readelf.c:12912
#, c-format
msgid "corrupt note found at offset %lx into core notes\n"
msgstr ""
-#: readelf.c:12887 readelf.c:12900
+#: readelf.c:12901 readelf.c:12914
#, c-format
msgid " type: %lx, namesize: %08lx, descsize: %08lx\n"
msgstr ""
-#: readelf.c:12996
+#: readelf.c:13010
#, c-format
msgid "No note segments present in the core file.\n"
msgstr ""
-#: readelf.c:13088
+#: readelf.c:13102
msgid ""
"This instance of readelf has been built without support for a\n"
"64 bit data type and so it cannot read 64 bit ELF files.\n"
msgstr ""
-#: readelf.c:13135
+#: readelf.c:13149
#, c-format
msgid "%s: Failed to read file header\n"
msgstr ""
-#: readelf.c:13149
+#: readelf.c:13163
#, c-format
msgid ""
"\n"
"File: %s\n"
msgstr ""
-#: readelf.c:13321
+#: readelf.c:13335
#, c-format
msgid "%s: unable to dump the index as none was found\n"
msgstr ""
-#: readelf.c:13327
+#: readelf.c:13341
#, c-format
msgid "Index of archive %s: (%ld entries, 0x%lx bytes in the symbol table)\n"
msgstr ""
-#: readelf.c:13345
+#: readelf.c:13359
#, c-format
msgid "Binary %s contains:\n"
msgstr ""
-#: readelf.c:13353
+#: readelf.c:13367
#, c-format
msgid "%s: end of the symbol table reached before the end of the index\n"
msgstr ""
-#: readelf.c:13364
+#: readelf.c:13378
#, c-format
msgid ""
"%s: symbols remain in the index symbol table, but without corresponding "
"entries in the index table\n"
msgstr ""
-#: readelf.c:13369
+#: readelf.c:13383
#, c-format
msgid "%s: failed to seek back to start of object files in the archive\n"
msgstr ""
-#: readelf.c:13452 readelf.c:13535
+#: readelf.c:13466 readelf.c:13549
#, c-format
msgid "Input file '%s' is not readable.\n"
msgstr ""
-#: readelf.c:13474
+#: readelf.c:13488
#, c-format
msgid "%s: failed to seek to archive member.\n"
msgstr ""
-#: readelf.c:13553
+#: readelf.c:13567
#, c-format
msgid "File %s is not an archive so its index cannot be displayed.\n"
msgstr ""
#include "elf/d10v.h"
#include "elf/d30v.h"
#include "elf/dlx.h"
+#include "elf/epiphany.h"
#include "elf/fr30.h"
#include "elf/frv.h"
#include "elf/h8.h"
/* Targets that use RELA relocations. */
case EM_68K:
case EM_860:
+ case EM_ADAPTEVA_EPIPHANY:
case EM_ALPHA:
case EM_ALTERA_NIOS2:
case EM_AVR:
rtype = elf_vax_reloc_type (type);
break;
+ case EM_ADAPTEVA_EPIPHANY:
+ rtype = elf_epiphany_reloc_type (type);
+ break;
+
case EM_IP2K:
case EM_IP2K_OLD:
rtype = elf_ip2k_reloc_type (type);
case EM_OR32: return "OpenRISC";
case EM_ARC_A5: return "ARC International ARCompact processor";
case EM_CRX: return "National Semiconductor CRX microprocessor";
+ case EM_ADAPTEVA_EPIPHANY: return "Adapteva EPIPHANY";
case EM_DLX: return "OpenDLX";
case EM_IP2K_OLD:
case EM_IP2K: return "Ubicom IP2xxx 8-bit microcontrollers";
case EM_AVR_OLD:
case EM_AVR:
return reloc_type == 1;
+ case EM_ADAPTEVA_EPIPHANY:
+ return reloc_type == 3;
case EM_BLACKFIN:
return reloc_type == 0x12; /* R_byte4_data. */
case EM_CRIS:
return reloc_type == 2; /* R_386_PC32. */
case EM_68K:
return reloc_type == 4; /* R_68K_PC32. */
+ case EM_ADAPTEVA_EPIPHANY:
+ return reloc_type == 6;
case EM_ALPHA:
return reloc_type == 10; /* R_ALPHA_SREL32. */
case EM_ARM:
case EM_AVR_OLD:
case EM_AVR:
return reloc_type == 4; /* R_AVR_16. */
+ case EM_ADAPTEVA_EPIPHANY:
+ return reloc_type == 5;
case EM_CYGNUS_D10V:
case EM_D10V:
return reloc_type == 3; /* R_D10V_16. */
case EM_MIPS: /* R_MIPS_NONE. */
case EM_PARISC: /* R_PARISC_NONE. */
case EM_ALPHA: /* R_ALPHA_NONE. */
+ case EM_ADAPTEVA_EPIPHANY:
case EM_PPC: /* R_PPC_NONE. */
case EM_PPC64: /* R_PPC64_NONE. */
case EM_ARM: /* R_ARM_NONE. */
+2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
+
+ * cpu/epiphany.cpu: New file.
+ * cpu/epiphany.opc: New file.
+
2011-08-22 Nick Clifton <nickc@redhat.com>
* fr30.cpu: Newly contributed file.
--- /dev/null
+; Adapteva EPIPHANY CPU description. -*- Scheme -*-
+; Copyright 2011
+; Free Software Foundation, Inc.
+;
+; Contributed by Embecosm on behalf of Adapteva, Inc.
+; This file is part of the GNU Binutils and of GDB.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+
+(include "simplify.inc")
+ ; define-arch must appear first
+
+(define-arch
+ (name epiphany) ; name of cpu family
+ (comment "Adapteva, Inc. EPIPHANY family")
+ (default-alignment aligned)
+ (insn-lsb0? #t)
+
+ ; - a 16/32 bit instruction machine (the default)
+
+ (machs epiphany32)
+ (isas epiphany)
+ )
+
+ ; Attributes.
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name SHORT-INSN)
+ (comment "instruction is a 16 bit form")
+ )
+
+;; 3 bit add/sub immediate forms - useful for relaxing into 11 bit form
+(define-attr
+ (for insn)
+ (type boolean)
+ (name IMM3)
+ (comment "instruction has a 3 bit immediate form")
+ )
+
+;; 8 bit mov immediate forms - useful for relaxing into 16 bit form
+(define-attr
+ (for insn)
+ (type boolean)
+ (name IMM8)
+ (comment "instruction has a 8 bit immediate form")
+ )
+
+ ; Instruction set parameters.
+
+(define-isa
+ (name epiphany)
+ (comment "Adapteva, Inc. EPIPHANY32 ISA")
+
+ (default-insn-word-bitsize 32)
+ (default-insn-bitsize 32)
+ (base-insn-bitsize 32)
+ (decode-assist (3 2 1 0)) ; CGEN can figure this out
+ (liw-insns 1) ; # instructions fetched at once
+ )
+
+ ; Cpu family definitions.
+
+
+(define-cpu
+ ; cpu names must be distinct from the architecture name and machine names.
+ (name epiphanybf)
+ (comment "Adapteva, Inc. EPIPHANY Family")
+ (endian little)
+ (word-bitsize 32)
+ )
+
+(define-cpu
+ (name epiphanymf)
+ (comment "Adapteva, Inc. EPIPHANY Family")
+ (endian little)
+ (word-bitsize 32)
+ )
+
+
+(define-mach
+ (name epiphany32)
+ (comment "Adapteva EPIPHANY")
+ (cpu epiphanybf)
+ )
+
+
+ ; Model descriptions.
+
+(define-model
+ (name epiphany32) (comment "Adapteva EPIPHANY 32/16") (attrs)
+ (mach epiphany32)
+
+ (unit u-exec "Execution Unit" ()
+ 1 1 ; issue done
+ () ; state
+ () ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ )
+
+
+
+ ; Instruction fields.
+ ;
+ ; Attributes:
+ ; XXX: what EPIPHANY attrs
+ ; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
+ ; ABS-ADDR: absolute address (for reloc and disassembly purposes?)
+ ; RESERVED: bits are not used to decode insn, must be all 0
+ ; RELOC: there is a relocation associated with this field
+
+(define-attr
+ (for ifield operand)
+ (type boolean)
+ (name RELOC)
+ (comment "there is a reloc associated with this field (experiment)")
+ )
+
+;; define the fields of the instruction.
+;; name description ATTR MSB LEN
+(dnf f-opc "primary opcode" () 3 4)
+(dnf f-opc-4-1 "secondary opcode" () 4 1)
+(dnf f-opc-6-3 "secondary opcode" () 6 3) ;;
+(dnf f-opc-8-5 "tertiary opcode" () 8 5) ;;
+(dnf f-opc-19-4 "additional opcode bits" () 19 4)
+(dnf f-condcode "condition codes" () 7 4)
+(dnf f-secondary-ccs "flag for secondary ccs" () 7 1)
+(dnf f-shift "shift amount" () 9 5)
+(dnf f-wordsize "load/store size" () 6 2)
+(dnf f-store "load/store flag" () 4 1) ;; 0==load,1==store
+(dnf f-opc-8-1 "opcode bits" () 8 1)
+(dnf f-opc-31-32 "all opcode set" () 31 32)
+
+(df f-simm8 "branch displacement" (PCREL-ADDR RELOC) 15 8 INT
+ ((value pc) (sra SI (sub SI value pc) 1))
+ ((value pc) (add SI (sll SI value 1) pc)))
+
+(df f-simm24 "branch displacement" (PCREL-ADDR RELOC) 31 24 INT
+ ((value pc) (sra SI (sub SI value pc) 1))
+ ((value pc) (add SI (sll SI value 1) pc)))
+
+(df f-sdisp3 "signed immediate 3 bit" () 9 3 INT #f #f)
+
+(dnf f-disp3 "address offset" () 9 3)
+(dnf f-disp8 "address offset" () 23 8)
+
+(dnf f-imm8 "move/add/sub imm8" () 12 8)
+(dnf f-imm-27-8 "move/add/sub imm16" () 27 8)
+(dnf f-addsubx "+/- index address" () 20 1)
+(dnf f-subd "+/- displ address" () 24 1)
+(dnf f-pm "post-modify immediate" () 25 1)
+
+(dnf f-rm "short rm" () 9 3) ;; RM
+(dnf f-rn "short rn" () 12 3) ;; RN
+(dnf f-rd "short rd" () 15 3) ;; RD
+
+(dnf f-rm-x "extension rm" () 25 3) ;; RM
+(dnf f-rn-x "extension rn" () 28 3) ;; RN
+(dnf f-rd-x "extension rd" () 31 3) ;; RD
+
+(dnf f-dc-9-1 "DC" (RESERVED) 9 1)
+
+(dnf f-sn "short sn" () 12 3) ;; SN
+(dnf f-sd "short sd" () 15 3) ;; SD
+
+(dnf f-sn-x "extension sn" () 28 3) ;; SN
+(dnf f-sd-x "extension sd" () 31 3) ;; SD
+
+
+
+(dnf f-dc-7-4 "movts zeros" () 7 4)
+(dnf f-trap-swi-9-1 "trap or swi" () 9 1)
+(dnf f-gien-gidis-9-1 "gien or gidis" () 9 1)
+
+
+(dnf f-dc-15-3 "DC" (RESERVED) 15 3)
+(dnf f-dc-15-7 "DC" (RESERVED) 15 7)
+(dnf f-dc-15-6 "DC" () 15 6)
+(dnf f-trap-num "trap number" () 15 6)
+
+(dnf f-dc-20-1 "DC" (RESERVED) 20 1)
+
+(dnf f-dc-21-1 "DC" (RESERVED) 21 1)
+(dnf f-dc-21-2 "DC" (RESERVED) 21 2)
+
+(dnf f-dc-22-3 "DC" (RESERVED) 22 3)
+(dnf f-dc-22-2 "DC" (RESERVED) 22 2)
+(dnf f-dc-22-1 "DC" (RESERVED) 22 1)
+
+(dnf f-dc-25-6 "DC" (RESERVED) 25 6)
+(dnf f-dc-25-4 "DC" (RESERVED) 25 4)
+(dnf f-dc-25-2 "DC" (RESERVED) 25 2)
+(dnf f-dc-25-1 "DC" (RESERVED) 25 1)
+
+(dnf f-dc-28-1 "DC" (RESERVED) 28 1)
+(dnf f-dc-31-3 "DC" (RESERVED) 31 3)
+
+(dnmf f-disp11 "Unsigned offset for load/store" () UINT (f-disp3 f-disp8)
+ (sequence ()
+ (set (ifield f-disp8) (and (srl (ifield f-disp11) 3) (const 255)))
+ (set (ifield f-disp3) (and (ifield f-disp11) 7)))
+ (sequence ()
+ (set (ifield f-disp11) (or (sll (ifield f-disp8) 3)
+ (ifield f-disp3)))
+ )
+ )
+
+
+(dnmf f-sdisp11 "Signed offset for load/store" () INT (f-disp3 f-disp8)
+ (sequence () ;encode
+ (set (ifield f-disp8) (and #xff (srl SI (ifield f-sdisp11) 3)))
+ (set (ifield f-disp3) (and SI (ifield f-sdisp11) 7)))
+ (sequence () ;decode
+ (set (ifield f-sdisp11)
+ (sra SI (sll SI (or SI (sll (ifield f-disp8) 3)
+ (ifield f-disp3))
+ 21)
+ 21)))
+ )
+
+(dnmf f-imm16 "Short immediate for move/add/sub" () UINT (f-imm8 f-imm-27-8)
+ (sequence ()
+ (set (ifield f-imm8) (and (ifield f-imm16) #xff))
+ (set (ifield f-imm-27-8) (srl (ifield f-imm16) 8)))
+ (sequence ()
+ (set (ifield f-imm16) (or (sll (ifield f-imm-27-8) 8)
+ (ifield f-imm8))))
+ )
+
+
+;; 32 bit instructions have the register number broken into two non-contiguous fields
+
+(define-pmacro (x-reg-field reg)
+ (define-multi-ifield
+ (name (.sym "f-" reg "6"))
+ (mode UINT)
+ (subfields (.sym "f-" reg "-x") (.sym "f-" reg))
+ (insert (sequence ()
+ (set (ifield (.sym "f-" reg)) (and (ifield (.sym "f-" reg "6"))
+ (const 7)))
+ (set (ifield (.sym "f-" reg "-x")) (srl (ifield (.sym "f-" reg "6"))
+ (const 3)))
+ ))
+ (extract (sequence ()
+ (set (ifield (.sym "f-" reg "6")) (or (sll (ifield (.sym "f-" reg "-x"))
+ (const 3))
+ (ifield (.sym "f-" reg))))
+ ))
+ )
+ )
+
+(x-reg-field rd) ; f-rd6
+(x-reg-field rn) ; f-rn6
+(x-reg-field rm) ; f-rm6
+(x-reg-field sd) ; f-sd6
+(x-reg-field sn) ; f-sn6
+
+
+;;;;;;;;;;
+ ; Enums. ;
+;;;;;;;;;;
+
+ ; insn-opc: bits 3..0 - major family selector
+(define-normal-insn-enum insn-opc "opc enums" () OP4_ f-opc
+ (
+ BRANCH16 ;; 0000
+ LDSTR16X ;; 0001
+ FLOW16 ;; 0010
+ IMM16 ;; 0011
+ LDSTR16D ;; 0100
+ LDSTR16P ;; 0101
+ LSHIFT16 ;; 0110 - logical shift
+ DSP16 ;; 0111 - 3 reg DSP 16 bit insns
+ BRANCH ;; 1000
+ LDSTRX ;; 1001
+ ALU16 ;; 1010 - 3 reg 16 bit
+ IMM32 ;; 1011
+ LDSTRD ;; 1100
+ LDSTRP ;; 1101
+ ASHIFT16 ;; 1110 ASR, BITR
+ MISC ;; 1111 - 32 bit shifts, 3 reg ALU, 3 reg DSP, FLOW, BITR
+ )
+ )
+
+(define-normal-insn-enum insn-wordsize "memory access width" () OPW_ f-wordsize
+ ; specifies the size of a memory load/store operation
+ (BYTE SHORT WORD DOUBLE)
+ )
+
+(define-normal-insn-enum insn-memory-access "memory access direction" () OP_ f-store
+ ; load=0, store=1
+ (LOAD STORE)
+ )
+
+ ; enum for trap codes used by simulator
+(define-normal-insn-enum trap-codes "trap instruction dispatch code" () TRAP_ f-trap-num
+ (write read open exit pass fail close other)
+ )
+
+ ; cond branch: bits 7..4
+ ;
+(define-normal-insn-enum insn-cond "branch conditions" () OPC_ f-condcode
+ (EQ NE GTU GTEU LTEU LTU GT GTE LT LTE BEQ BNE BLT BLTE B BL))
+
+ ; dsp 3 operand opcodes
+(define-normal-insn-enum insn-bop "binary operator subcodes" () OPB_ f-opc-6-3
+ (EOR ADD LSL SUB LSR AND ASR ORR))
+
+ ; dsp 3 operand opcodes
+(define-normal-insn-enum insn-bopext "binary operator subcodes" () OPBE_ f-opc-6-3
+ (FEXT FDEP LFSR - - - - -))
+
+
+(define-normal-insn-enum insn-fop "floating operators" () OPF_ f-opc-6-3
+ (ADD SUB MUL MADD MSUB FLOAT FIX FABS))
+
+(define-normal-insn-enum insn-fopexn "extended floating operators" () OPF_ f-opc-6-3
+ (FRECIP FSQRT - - - - - -))
+
+
+
+
+; Immediate operation secondary opcodes
+(define-normal-insn-enum insn-immop "immediate operators" () OPI_ f-opc-6-3
+ (- ADD - SUB - - - TRAP) ; TRAP is special extension for simulator
+ )
+
+ ; don't care fields
+(define-normal-insn-enum insn-dc-25-2 "don't cares" () OPI_25_2_ f-dc-25-2
+ (MBZ))
+
+; General Register keyword names.
+(define-keyword
+ (name gr-names)
+ (print-name h-registers)
+ (prefix "")
+ (values
+; some preferred aliases
+ (sb 9) (sl 10) (fp 11) (ip 12) (sp 13) (lr 14)
+; the default register names
+ (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
+ (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15)
+ (r16 16) (r17 17) (r18 18) (r19 19) (r20 20) (r21 21) (r22 22) (r23 23)
+ (r24 24) (r25 25) (r26 26) (r27 27) (r28 28) (r29 29) (r30 30) (r31 31)
+ (r32 32) (r33 33) (r34 34) (r35 35) (r36 36) (r37 37) (r38 38) (r39 39)
+ (r40 40) (r41 41) (r42 42) (r43 43) (r44 44) (r45 45) (r46 46) (r47 47)
+ (r48 48) (r49 49) (r50 50) (r51 51) (r52 52) (r53 53) (r54 54) (r55 55)
+ (r56 56) (r57 57) (r58 58) (r59 59) (r60 60) (r61 61) (r62 62) (r63 63)
+; some less popular aliases
+ (a1 0) (a2 1) (a3 2) (a4 3) (v1 4) (v2 5) (v3 6) (v4 7)
+ (v5 8) (v6 9) (v7 10) (v8 11)
+ )
+ )
+
+(define-normal-insn-enum post-index "+/- index register" () DIR_ f-addsubx (POSTINC POSTDEC))
+
+(define-normal-insn-enum disp-post-modify "postmodify displacement" () PMOD_ f-pm (DISP POST))
+\f
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ; Hardware pieces.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;; 64 general-purpose registers
+(define-hardware
+ (name h-registers)
+ (comment "all addressable registers")
+ (type register SI (64))
+ (attrs PROFILE CACHE-ADDR)
+ (indices extern-keyword gr-names)
+ )
+
+
+
+;; Same 64 registers as floating point registers
+(define-hardware
+ (name h-fpregisters)
+ (comment "all GPRs as float values")
+ (type register SF (64))
+ (attrs PROFILE VIRTUAL)
+ (indices extern-keyword gr-names)
+ (get (index) (subword SF (reg h-registers index) 0))
+ (set (index newval) (set (reg h-registers index) (subword SI newval 0)))
+ )
+
+;; define processor status bits as physical hardware
+
+(define-pmacro (psw-h-bit name cmt)
+ (dsh name cmt () (register BI)))
+
+(psw-h-bit h-zbit "integer zero bit")
+(psw-h-bit h-nbit "integer neg bit")
+(psw-h-bit h-cbit "integer carry bit")
+(psw-h-bit h-vbit "integer overflow bit")
+(psw-h-bit h-vsbit "integer overflow sticky")
+
+
+(psw-h-bit h-bzbit "floating point zero bit")
+(psw-h-bit h-bnbit "floating point neg bit")
+(psw-h-bit h-bvbit "floating point ovfl bit")
+(psw-h-bit h-bubit "floating point underfl bit")
+(psw-h-bit h-bibit "floating point invalid bit")
+(psw-h-bit h-bcbit "floating point carry bit")
+
+(psw-h-bit h-bvsbit "floating point overflow sticky")
+(psw-h-bit h-bisbit "floating point invalid sticky")
+(psw-h-bit h-busbit "floating point underflow sticky")
+
+(psw-h-bit h-expcause0bit "exceprion cause bit0")
+(psw-h-bit h-expcause1bit "exceprion cause bit1")
+(psw-h-bit h-expcause2bit "external load stalled bit")
+(psw-h-bit h-extFstallbit "external fetch stalled bit")
+
+(psw-h-bit h-trmbit "0=round to nearest, 1=trunacte select bit")
+(psw-h-bit h-invExcEnbit "invalid exception enable bit")
+(psw-h-bit h-ovfExcEnbit "overflow exception enable bit")
+(psw-h-bit h-unExcEnbit "underflow exception enablebit ")
+
+(psw-h-bit h-timer0bit0 "timer 0 mode selection 0")
+(psw-h-bit h-timer0bit1 "timer 0 mode selection 1")
+(psw-h-bit h-timer0bit2 "timer 0 mode selection 2")
+(psw-h-bit h-timer0bit3 "timer 0 mode selection 3")
+(psw-h-bit h-timer1bit0 "timer 1 mode selection 0")
+(psw-h-bit h-timer1bit1 "timer 1 mode selection 1")
+(psw-h-bit h-timer1bit2 "timer 1 mode selection 2")
+(psw-h-bit h-timer1bit3 "timer 1 mode selection 3")
+
+(psw-h-bit h-mbkptEnbit "multicore bkpt enable")
+(psw-h-bit h-clockGateEnbit "clock gating enable bkpt enable")
+
+
+(psw-h-bit h-coreCfgResBit12 "core config bit 12")
+(psw-h-bit h-coreCfgResBit13 "core config bit 13")
+(psw-h-bit h-coreCfgResBit14 "core config bit 14")
+(psw-h-bit h-coreCfgResBit15 "core config bit 15")
+(psw-h-bit h-coreCfgResBit16 "core config bit 16")
+
+
+(psw-h-bit h-coreCfgResBit20 "core config bit 20")
+(psw-h-bit h-coreCfgResBit21 "core config bit 21")
+
+(psw-h-bit h-coreCfgResBit24 "core config bit 24")
+(psw-h-bit h-coreCfgResBit25 "core config bit 25")
+(psw-h-bit h-coreCfgResBit26 "core config bit 26")
+(psw-h-bit h-coreCfgResBit27 "core config bit 27")
+(psw-h-bit h-coreCfgResBit28 "core config bit 28")
+(psw-h-bit h-coreCfgResBit29 "core config bit 29")
+(psw-h-bit h-coreCfgResBit30 "core config bit 30")
+(psw-h-bit h-coreCfgResBit31 "core config bit 31")
+
+
+(psw-h-bit h-arithmetic-modebit0 "arithmetic mode bit0")
+(psw-h-bit h-arithmetic-modebit1 "arithmetic mode bit1")
+(psw-h-bit h-arithmetic-modebit2 "arithmetic mode bit2")
+
+
+(psw-h-bit h-gidisablebit "global interrupt disable bit")
+(psw-h-bit h-kmbit "kernel mode bit")
+(psw-h-bit h-caibit "core active indicator mode bit")
+(psw-h-bit h-sflagbit "sflag bit")
+
+
+ ; Define operands for each of the physical bits
+(define-pmacro (psw-bit name hname cmt)
+ (dnop name cmt (SEM-ONLY) hname f-nil)
+ )
+
+(psw-bit zbit h-zbit "integer zero bit")
+(psw-bit nbit h-nbit "integer neg bit")
+(psw-bit cbit h-cbit "integer carry bit")
+(psw-bit vbit h-vbit "integer overflow bit")
+
+(psw-bit bzbit h-bzbit "floating point zero bit")
+(psw-bit bnbit h-bnbit "floating point neg bit")
+(psw-bit bvbit h-bvbit "floating point ovfl bit")
+(psw-bit bcbit h-bcbit "floating point carry bit")
+
+(psw-bit bubit h-bubit "floating point underfl bit")
+(psw-bit bibit h-bibit "floating point invalid bit")
+
+
+(psw-bit vsbit h-vsbit "integer overflow sticky")
+(psw-bit bvsbit h-bvsbit "floating point overflow sticky")
+(psw-bit bisbit h-bisbit "floating point invalid sticky")
+(psw-bit busbit h-busbit "floating point underflow sticky")
+(psw-bit expcause0bit h-expcause0bit "exceprion cause bit0")
+(psw-bit expcause1bit h-expcause1bit "exceprion cause bit1")
+
+
+(psw-bit expcause2bit h-expcause2bit "external load stalled bit")
+(psw-bit extFstallbit h-extFstallbit "external fetch stalled bit")
+
+(psw-bit trmbit h-trmbit "0=round to nearest, 1=trunacte selct bit")
+(psw-bit invExcEnbit h-invExcEnbit "invalid exception enable bit")
+(psw-bit ovfExcEnbit h-ovfExcEnbit "overflow exception enable bit")
+(psw-bit unExcEnbit h-unExcEnbit "underflow exception enable bit")
+
+(psw-bit timer0bit0 h-timer0bit0 "timer 0 mode selection 0")
+(psw-bit timer0bit1 h-timer0bit1 "timer 0 mode selection 1")
+(psw-bit timer0bit2 h-timer0bit2 "timer 0 mode selection 2")
+(psw-bit timer0bit3 h-timer0bit3 "timer 0 mode selection 3")
+
+(psw-bit timer1bit0 h-timer1bit0 "timer 1 mode selection 0")
+(psw-bit timer1bit1 h-timer1bit1 "timer 1 mode selection 1")
+(psw-bit timer1bit2 h-timer1bit2 "timer 1 mode selection 2")
+(psw-bit timer1bit3 h-timer1bit3 "timer 1 mode selection 3")
+
+(psw-bit mbkptEnbit h-mbkptEnbit "multicore bkpt enable")
+(psw-bit clockGateEnbit h-clockGateEnbit "clock gate enable enable")
+
+(psw-bit arithmetic-modebit0 h-arithmetic-modebit0 "arithmetic mode bit0")
+(psw-bit arithmetic-modebit1 h-arithmetic-modebit1 "arithmetic mode bit1")
+(psw-bit arithmetic-modebit2 h-arithmetic-modebit2 "arithmetic mode bit2")
+
+(psw-bit coreCfgResBit12 h-coreCfgResBit12 "core config bit 12")
+(psw-bit coreCfgResBit13 h-coreCfgResBit13 "core config bit 13")
+(psw-bit coreCfgResBit14 h-coreCfgResBit14 "core config bit 14")
+(psw-bit coreCfgResBit15 h-coreCfgResBit15 "core config bit 15")
+(psw-bit coreCfgResBit16 h-coreCfgResBit16 "core config bit 16")
+
+(psw-bit coreCfgResBit20 h-coreCfgResBit20 "core config bit 20")
+(psw-bit coreCfgResBit21 h-coreCfgResBit21 "core config bit 21")
+
+(psw-bit coreCfgResBit24 h-coreCfgResBit24 "core config bit 24")
+(psw-bit coreCfgResBit25 h-coreCfgResBit25 "core config bit 25")
+(psw-bit coreCfgResBit26 h-coreCfgResBit26 "core config bit 26")
+(psw-bit coreCfgResBit27 h-coreCfgResBit27 "core config bit 27")
+(psw-bit coreCfgResBit28 h-coreCfgResBit28 "core config bit 28")
+(psw-bit coreCfgResBit29 h-coreCfgResBit29 "core config bit 29")
+(psw-bit coreCfgResBit30 h-coreCfgResBit30 "core config bit 30")
+(psw-bit coreCfgResBit31 h-coreCfgResBit31 "core config bit 31")
+
+
+(psw-bit gidisablebit h-gidisablebit "global interrupt disable bit")
+(psw-bit kmbit h-kmbit "kernel mode bit")
+(psw-bit caibit h-caibit "core actibe indicator bit")
+(psw-bit sflagbit h-sflagbit "sflag bit")
+
+
+
+
+;; Special registers - accessed via MOVTS and MOVFS.
+;;
+;; "Core control and status" in group MR0=0, MR1=0
+
+(define-keyword
+ (name cr-names)
+ (print-name h-core-registers)
+ (prefix "")
+ (values (config 0)
+ (status 1) ; unified condition codes
+ (pc 2) ; virtualized PC
+ (debug 3);
+ (iab 4)
+ (lc 5);loop counter Not impemented
+ (ls 6);loop start address Not impemented
+ (le 7);loop end address Not impemented
+ (iret 8)
+ (imask 9)
+ (ilat 10)
+ (ilatst 11)
+ (ilatcl 12)
+ (ipend 13)
+ (ctimer0 14)
+ (ctimer1 15)
+ (hstatus 16)
+ )
+ )
+;; DMA registers in group MR0=1, MR1=0
+
+(define-keyword
+ (name crdma-names)
+ (print-name h-coredma-registers)
+ (prefix "")
+ (values
+
+
+ (dma0config 0)
+ (dma0stride 1)
+ (dma0count 2)
+
+ (dma0srcaddr 3)
+ (dma0dstaddr 4)
+
+ (dma0auto0 5)
+ (dma0auto1 6)
+
+ (dma0status 7)
+
+ (dma1config 8)
+ (dma1stride 9)
+ (dma1count 10)
+
+ (dma1srcaddr 11)
+ (dma1dstaddr 12)
+
+ (dma1auto0 13)
+ (dma1auto1 14)
+
+ (dma1status 15)
+
+ )
+ )
+;; mem configuration registers in group MR0=0, MR1=1
+
+(define-keyword
+ (name crmem-names)
+ (print-name h-coremem-registers)
+ (prefix "")
+ (values
+ (memconfig 0)
+ (memstatus 1)
+ (memprotect 2)
+ (memreserve 3)
+ )
+ )
+
+;; mesh configuration registers in group MR0=1, MR1=1
+
+(define-keyword
+ (name crmesh-names)
+ (print-name h-coremesh-registers)
+ (prefix "")
+
+ (values
+
+
+ (meshconfig 0)
+ (coreid 1)
+ (meshmulticast 2)
+ (swreset 3)
+ )
+ )
+
+
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ; PC is a byte-addressed register
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ; Memory Effective Address wants to be visible
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(dnh h-memaddr "memory effective address" (PROFILE) (register SI) () () ())
+(dnop memaddr "memory effective address" (SEM-ONLY) h-memaddr f-nil)
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ; Special Core Registers
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; STATUS
+;; [0]=core active indicator
+;; [1]=global interrupt disable
+;; [2]=processor mode(1=user mode, 0=kernel mode)
+;; [3]=wired AND global flag
+
+;; [4]=integer zero zbit
+;; [5]=integer negative nbit
+;; [6]=integer carry cbit
+;; [7]=integer overflow vbit
+
+;; [8]=fpu zero flag bzbit
+;; [9]=fpu negative flag bnbit
+;; [10]=fpu overflow flag bvbit
+;; [11]=fpu carry flag(not used) bcbit
+
+;; [12]=ialu overflow flag(sticky) vsbit
+;; [13]=fpu invalid flag(sticky) bisbit
+;; [14]=fpu overflow flag(sticky) bvsbit
+;; [15]=fpu underflow flag(sticky) busbit
+
+;; [17:16]=exception cause 00=no exception 01=load-store exception 10=fpu exception 11=unimplemented instruction
+;; expcause1bit
+;; expcause0bit
+
+;; [18]=external load stalled expcause2bit
+;; [19]=external fetch stalled extFstallbit
+
+;; [31:20]=RESERVED
+
+
+
+
+
+(define-hardware
+ (name h-core-registers)
+ (comment "Special Core Registers")
+ (type register USI (17))
+ (attrs)
+ (indices extern-keyword cr-names)
+ (get (index)
+ (cond USI
+ ((eq index (const 1)) ; STATUS reg ?
+ (or (or (or (or (sll USI kmbit (const 2))
+ (sll USI gidisablebit (const 1)))
+ (or (or (sll USI expcause1bit (const 17))
+ (sll USI expcause0bit (const 16)))
+ (or (sll USI expcause2bit (const 18))
+ (sll USI extFstallbit (const 19)))))
+ (or (or (or (sll USI busbit (const 15))
+ (sll USI bisbit (const 13)))
+ (or (sll USI bvsbit (const 14))
+ (sll USI vsbit (const 12))))
+ (or (or (sll USI bvbit (const 10))
+ (sll USI bcbit (const 11)))
+ (or (sll USI bnbit (const 9))
+ (sll USI bzbit (const 8))))))
+ (or (or (or (sll USI vbit (const 7))
+ (sll USI cbit (const 6)))
+ (or (sll USI nbit (const 5))
+ (sll USI zbit (const 4))))
+ (or (sll USI sflagbit (const 3))
+ (sll USI (const 1) (const 0)))))) ;caibit
+ ((eq index (const 0)) ; Config reg ?
+ (or (or (or (or (or (or (sll USI timer0bit2 (const 6))
+ (sll USI timer0bit3 (const 7)))
+ (or (or (sll USI coreCfgResBit28 (const 28))
+ (sll USI coreCfgResBit29 (const 29)))
+ (or (sll USI coreCfgResBit30 (const 30))
+ (sll USI coreCfgResBit31 (const 31)))))
+ (or (or (sll USI coreCfgResBit24 (const 24))
+ (sll USI coreCfgResBit25 (const 25)))
+ (or (sll USI coreCfgResBit26 (const 26))
+ (sll USI coreCfgResBit27 (const 27)))))
+ (or (or (sll USI timer0bit0 (const 4))
+ (sll USI timer0bit1 (const 5)))
+ (or (sll USI coreCfgResBit14 (const 14))
+ (sll USI coreCfgResBit15 (const 15)))))
+ (or (or (or (or (sll USI timer1bit2 (const 10))
+ (sll USI timer1bit3 (const 11)))
+ (or (sll USI coreCfgResBit12 (const 12))
+ (sll USI coreCfgResBit13 (const 13))))
+ (or (sll USI clockGateEnbit (const 22))
+ (sll USI mbkptEnbit (const 23))))
+ (or (or (sll USI timer1bit0 (const 8))
+ (sll USI timer1bit1 (const 9)))
+ (or (sll USI coreCfgResBit20 (const 20))
+ (sll USI coreCfgResBit21 (const 21))))))
+ (or (or (sll USI invExcEnbit (const 1))
+ (sll USI ovfExcEnbit (const 2)))
+ (or (or (sll USI trmbit (const 0))
+ (sll USI unExcEnbit (const 3)))
+ (or (or (sll USI arithmetic-modebit0 (const 17))
+ (sll USI arithmetic-modebit1 (const 18)))
+ (or (sll USI arithmetic-modebit2 (const 19))
+ (sll USI coreCfgResBit16 (const 16)))))))) ;config reg
+
+ ((eq index (const 2)) (raw-reg USI h-pc)) ;PC reg
+
+ (else (raw-reg USI h-core-registers index))))
+
+ (set (index val)
+ (cond VOID
+ ((eq index (const 0)) ; CONFIG reg
+ (sequence ()
+ (set trmbit (and (const 1) (srl val (const 0))))
+ (set invExcEnbit (and (const 1) (srl val (const 1))))
+ (set ovfExcEnbit (and (const 1) (srl val (const 2))))
+ (set unExcEnbit (and (const 1) (srl val (const 3))))
+ (set timer0bit0 (and (const 1) (srl val (const 4))))
+ (set timer0bit1 (and (const 1) (srl val (const 5))))
+ (set timer0bit2 (and (const 1) (srl val (const 6))))
+ (set timer0bit3 (and (const 1) (srl val (const 7))))
+ (set timer1bit0 (and (const 1) (srl val (const 8))))
+ (set timer1bit1 (and (const 1) (srl val (const 9))))
+ (set timer1bit2 (and (const 1) (srl val (const 10))))
+ (set timer1bit3 (and (const 1) (srl val (const 11))))
+
+ (set coreCfgResBit12 (and (const 1) (srl val (const 12))))
+ (set coreCfgResBit13 (and (const 1) (srl val (const 13))))
+ (set coreCfgResBit14 (and (const 1) (srl val (const 14))))
+ (set coreCfgResBit15 (and (const 1) (srl val (const 15))))
+ (set coreCfgResBit16 (and (const 1) (srl val (const 16))))
+
+ (set arithmetic-modebit0 (and (const 1) (srl val (const 17))))
+ (set arithmetic-modebit1 (and (const 1) (srl val (const 18))))
+ (set arithmetic-modebit2 (and (const 1) (srl val (const 19))))
+
+ (set coreCfgResBit20 (and (const 1) (srl val (const 20))))
+ (set coreCfgResBit21 (and (const 1) (srl val (const 21))))
+
+ (set clockGateEnbit (and (const 1) (srl val (const 22))))
+ (set mbkptEnbit (and (const 1) (srl val (const 23))))
+
+ (set coreCfgResBit24 (and (const 1) (srl val (const 24))))
+ (set coreCfgResBit25 (and (const 1) (srl val (const 25))))
+ (set coreCfgResBit26 (and (const 1) (srl val (const 26))))
+ (set coreCfgResBit27 (and (const 1) (srl val (const 27))))
+ (set coreCfgResBit28 (and (const 1) (srl val (const 28))))
+ (set coreCfgResBit29 (and (const 1) (srl val (const 29))))
+ (set coreCfgResBit30 (and (const 1) (srl val (const 30))))
+ (set coreCfgResBit31 (and (const 1) (srl val (const 31))))
+
+ (set (raw-reg USI h-core-registers index) val)
+ ;; check LSB of CONFIG for rounding mode
+ (c-call "epiphany_set_rounding_mode" val)
+ )
+ )
+ ((eq index (const 1)) ;STATUS reg ; TODO check which bits can be set or clear
+ (sequence ((USI newval))
+ (set newval (and val (const #xfff2)))
+ (set extFstallbit (and (const 1) (srl newval (const 19))))
+ (set expcause2bit (and (const 1) (srl newval (const 18))))
+ (set expcause1bit (and (const 1) (srl newval (const 17))))
+ (set expcause0bit (and (const 1) (srl newval (const 16))))
+ (set busbit (and (const 1) (srl newval (const 15))))
+ (set bisbit (and (const 1) (srl newval (const 13))))
+ (set bvsbit (and (const 1) (srl newval (const 14))))
+ (set vsbit (and (const 1) (srl newval (const 12))))
+ (set bvbit (and (const 1) (srl newval (const 10))))
+ (set bcbit (and (const 1) (srl newval (const 11))))
+ (set bnbit (and (const 1) (srl newval (const 9))))
+ (set bzbit (and (const 1) (srl newval (const 8))))
+ (set vbit (and (const 1) (srl newval (const 7))))
+ (set cbit (and (const 1) (srl newval (const 6))))
+ (set nbit (and (const 1) (srl newval (const 5))))
+ (set zbit (and (const 1) (srl newval (const 4))))
+ (set sflagbit (and (const 1) (srl newval (const 3))))
+ (set kmbit (and (const 1) (srl newval (const 2))))
+ ;;(set gie (and (const 1) (srl newval (const 1))))
+ (set (raw-reg SI h-core-registers (const 1)) newval)
+ ))
+ ;; causes simulator errors
+ ;; ((eq index (const 2)) ;PC reg
+ ;; (set pc val))
+
+ (else (set (raw-reg USI h-core-registers index) val))
+ ))
+)
+ ; (define-pmacro (hcr-config) (reg h-core-registers 0)) etc.
+(.splice begin (.unsplice (.map
+ (.pmacro (xname xnum)
+ (define-pmacro ((.sym hcr- xname)) (reg h-core-registers xnum)))
+
+ (
+ config
+ status
+ pc
+ debug
+ iab
+ lc
+ ls
+ le
+ iret
+ imask
+ ilat
+ ilatst
+ ilatcl
+ ipend
+ ctimer0
+ ctimer1
+ hstatus
+
+
+
+ )
+
+ (0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
+ )
+ )))
+
+
+
+;; DMA registers in MMR space
+(define-hardware
+ (name h-coredma-registers)
+ (comment "DMA registers in MMR space")
+ (type register USI (16))
+ (attrs)
+ (indices extern-keyword crdma-names)
+ )
+
+;; MEM registers in MMR space
+(define-hardware
+ (name h-coremem-registers)
+ (comment "MEM registers in MMR space")
+ (type register USI (4))
+ (attrs)
+ (indices extern-keyword crmem-names)
+ )
+
+;; MEM registers in MMR space
+(define-hardware
+ (name h-coremesh-registers)
+ (comment "MESH registers in MMR space")
+ (type register USI (4))
+ (attrs)
+ (indices extern-keyword crmesh-names)
+ )
+
+
+
+ ; Operands
+
+ ; Branch displacements
+(define-operand
+ (name simm24)
+ (comment "branch address pc-relative")
+ (attrs RELAX)
+ (type h-iaddr)
+ (index f-simm24)
+ (handlers (parse "branch_addr")))
+
+(define-operand
+ (name simm8)
+ (comment "branch address pc-relative")
+ (attrs RELAX)
+ (type h-iaddr)
+ (index f-simm8)
+ (handlers (parse "branch_addr")))
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ; Register operands
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(define-pmacro (short-regs nm group hw cmt)
+ (define-operand
+ (name nm)
+ (comment cmt)
+ (attrs)
+ (type hw)
+ (index (.sym "f-r" group))
+ (handlers (parse "shortregs") (print "keyword"))
+ )
+ )
+
+(define-pmacro (short-regs-core nm group hw cmt)
+ (define-operand
+ (name nm)
+ (comment cmt)
+ (attrs)
+ (type hw)
+ (index (.sym "f-s" group))
+ (handlers (parse "shortregs") (print "keyword"))
+ )
+ )
+
+
+ ; short regs (0-7)
+(short-regs rd d h-registers "destination register")
+(short-regs rn n h-registers "source register")
+(short-regs rm m h-registers "source register")
+
+(short-regs frd d h-fpregisters "fp destination register")
+(short-regs frn n h-fpregisters "fp source register")
+(short-regs frm m h-fpregisters "fp source register")
+
+ ; long regs (0-63)
+(dnop rd6 "destination register" () h-registers f-rd6)
+(dnop rn6 "source register" () h-registers f-rn6)
+(dnop rm6 "source register" () h-registers f-rm6)
+
+(dnop frd6 "fp destination register" () h-fpregisters f-rd6)
+(dnop frn6 "fp source register" () h-fpregisters f-rn6)
+(dnop frm6 "fp source register" () h-fpregisters f-rm6)
+
+ ; special regs (0-7)
+(short-regs-core sd d h-core-registers "special destination")
+(short-regs-core sn n h-core-registers "special source")
+
+ ; special regs (long form)
+(dnop sd6 "special destination register" () h-core-registers f-sd6)
+(dnop sn6 "special source register" () h-core-registers f-sn6)
+
+(dnop sddma "dma register" () h-coredma-registers f-sd6)
+(dnop sndma "dma register" () h-coredma-registers f-sn6)
+(dnop sdmem "mem register" () h-coremem-registers f-sd6)
+(dnop snmem "mem register" () h-coremem-registers f-sn6)
+(dnop sdmesh "mesh register" () h-coremesh-registers f-sd6)
+(dnop snmesh "mesh register" () h-coremesh-registers f-sn6)
+
+ ; Immediate literals - but don't allow register names!
+(define-pmacro (dimmop nm cmt hwtype idx)
+ (define-operand (name nm) (comment cmt) (type hwtype) (index idx)
+ (attrs RELAX)
+ (handlers (parse "simm_not_reg")
+ (print "simm_not_reg")))
+ )
+
+(dimmop simm3 "signed 3-bit literal" h-sint f-sdisp3)
+(dimmop simm11 "signed 11-bit literal" h-sint f-sdisp11)
+(dnop disp3 "short data displacement" () h-uint f-disp3)
+(dnop trapnum6 "parameter for swi or trap" () h-uint f-trap-num)
+
+(define-pmacro (duimmop nm cmt hwtype idx)
+ (define-operand (name nm) (comment cmt) (type hwtype) (index idx)
+ (attrs)
+ (handlers (parse "uimm_not_reg")
+ (print "uimm_not_reg")))
+ )
+
+(duimmop swi_num "unsigned 6-bit swi#" h-uint f-trap-num)
+(duimmop disp11 "sign-magnitude data displacement" h-uint f-disp11)
+
+(dnop shift "immediate shift amount" () h-uint f-shift)
+
+(define-operand (name imm16) (comment "16-bit unsigned literal") (attrs RELAX)
+ (type h-addr) (index f-imm16) (handlers (parse "imm16")))
+(define-operand (name imm8) (comment "8-bit unsigned literal") (attrs RELAX)
+ (type h-addr) (index f-imm8) (handlers (parse "imm8")))
+
+(define-operand
+ (name direction)
+ (comment "+/- indexing")
+ (attrs)
+ (type h-uint)
+ (index f-addsubx)
+ (handlers (parse "postindex")
+ (print "postindex")))
+
+(define-operand
+ (name dpmi)
+ (comment "+/- magnitude immediate displacement")
+ (attrs)
+ (type h-uint)
+ (index f-subd)
+ (handlers (parse "postindex")
+ (print "postindex")))
+
+
+
+;; call exception macro - no check for imask
+(define-pmacro (call-exception vaddr bit-in-ilat)
+ (if (eq gidisablebit 0)
+ (if (eq (and (hcr-imask) bit-in-ilat) 0)
+ (sequence ()
+ (set kmbit 1)
+ (set gidisablebit 1)
+ (set (hcr-iret) (add pc (const 2)))
+ (set (hcr-ipend) (or (hcr-ipend) (const bit-in-ilat)))
+ (set pc (const vaddr))
+
+ )
+ ;; schedule interrupt
+ (set (hcr-ilat) (or (hcr-ilat) (const bit-in-ilat)))
+ )
+ )
+ )
+
+
+;; (lc 5);loop counter Not impemented
+;; (ls 6);loop start address Not impemented
+;; (le 7);loop end address Not impemented
+
+;;have callback to adjust pc in case od events ( HW loops ... )
+(define-pmacro (dni_wrapper isnid stdrdesc attr_ strassembl iopcode proceed null_b)
+ (begin
+ (dni isnid stdrdesc attr_ strassembl iopcode
+ (sequence () proceed
+ (sequence ((USI tmpPC))
+ ;;(set tmpPC (c-call USI "epiphany_post_isn_callback" pc))
+
+ (if (eq pc (hcr-le))
+ (set (hcr-lc) (sub (hcr-lc) #x1)))
+ (if (and
+ (eq pc (hcr-le))
+ (not (eq (hcr-lc) #x0)))
+ (set pc (hcr-ls)))
+ )
+ )
+ null_b)
+ )
+ )
+
+
+
+
+
+;; Some handy macros
+;;
+
+;; define instructions
+;; Short (16 bit forms) must appear first so that instruction
+;; selection can reject them and match long forms when registers
+;; or immediates exceed the values in the 16 bit instructions
+
+
+;; B<COND> SIMM8
+;; B<COND> SIMM24
+
+(define-pmacro (br-insn name cond g-op)
+ (begin
+ ; the 16-bit versions of branch
+ (dni (.sym "b" name "16")
+ (.str "Conditional Branch - 16 bit" name)
+ (COND-CTI SHORT-INSN)
+ (.str "b" name ".s $simm8")
+ (+ OP4_BRANCH16 (.sym "OPC_" cond) simm8)
+ (if (g-op)
+ (set pc simm8)
+ )
+ ()
+ )
+
+ (dnmi (.sym "b" name "16r") "relaxable conditional branch"
+ (COND-CTI RELAXABLE)
+ (.str "b" name " $simm8")
+ (emit (.sym "b" name "16") simm8)
+ )
+
+ (dni (.sym "b" name)
+ (.str "Conditional Branch " name)
+ (COND-CTI)
+ (.str "b" name ".l $simm24")
+ (+ OP4_BRANCH (.sym "OPC_" cond) simm24)
+ (if (g-op)
+ (set pc simm24)
+ )
+ ()
+ )
+
+ (dnmi (.sym "b" name "32r") "relaxable conditional branch"
+ (COND-CTI RELAXED)
+ (.str "b" name " $simm24")
+ (emit (.sym "b" name) simm24)
+ )
+ )
+ )
+
+
+ ; basic conditional branches for integer arithmetic
+(br-insn "eq" EQ (.pmacro () (eq zbit #x1)))
+(br-insn "ne" NE (.pmacro () (eq zbit #x0)))
+(br-insn "gtu" GTU (.pmacro () (and BI cbit (not BI zbit))))
+(br-insn "gteu" GTEU (.pmacro () (eq cbit #x1)))
+(br-insn "lteu" LTEU (.pmacro () (or BI (not BI cbit) zbit)))
+(br-insn "ltu" LTU (.pmacro () (eq cbit #x0)))
+(br-insn "gt" GT (.pmacro () (and BI (not BI zbit) (eq vbit nbit))))
+(br-insn "gte" GTE (.pmacro () (eq vbit nbit)))
+(br-insn "lt" LT (.pmacro () (xor BI vbit nbit)))
+(br-insn "lte" LTE (.pmacro () (or BI zbit (xor vbit nbit))))
+
+
+ ; floating point condition codes (floating point instructions)
+(br-insn "beq" BEQ (.pmacro () (or BI bzbit bzbit)))
+(br-insn "bne" BNE (.pmacro () (not BI bzbit)))
+(br-insn "blt" BLT (.pmacro () (and BI bnbit (not bzbit))))
+(br-insn "blte" BLTE (.pmacro () (or BI bnbit bzbit)))
+
+ ; unconditional branches
+(dni b16 "short unconditional branch" (UNCOND-CTI SHORT-INSN)
+ "b.s $simm8"
+ (+ OP4_BRANCH16 OPC_B simm8)
+ (set pc simm8)
+ ()
+ )
+
+(dnmi b16r "relaxable b16"
+ (UNCOND-CTI RELAXABLE)
+ "b $simm8"
+ (emit b16 simm8)
+ )
+
+(dni b "long unconditional branch" (UNCOND-CTI)
+ "b.l $simm24"
+ (+ OP4_BRANCH OPC_B simm24)
+ (set pc simm24)
+ ()
+ )
+
+(dnmi b32r "relaxable b"
+ (UNCOND-CTI RELAXED)
+ "b $simm24"
+ (emit b simm24))
+
+;; BL R,ADDR
+
+(dni bl16 "branch and link"
+ (UNCOND-CTI SHORT-INSN)
+ ("bl.s $simm8")
+ (+ OP4_BRANCH16 OPC_BL simm8)
+ (sequence ()
+ (set (reg h-registers 14) (add pc (const 2)))
+ (set pc simm8))
+ ()
+ )
+
+(dnmi bl16r "bl16 relaxable"
+ (UNCOND-CTI RELAXABLE)
+ "bl $simm8"
+ (emit bl16 simm8))
+
+(dni bl "branch and link"
+ (UNCOND-CTI)
+ ("bl.l $simm24")
+ (+ OP4_BRANCH OPC_BL simm24)
+ (sequence ()
+ (set (reg h-registers 14) (add pc (const 4)))
+ (set pc simm24))
+ ()
+ )
+
+(dnmi blr "bl relaxable"
+ (UNCOND-CTI RELAXED)
+ "bl $simm24"
+ (emit bl simm24))
+
+;; JUMP <RN>
+(dni jr16 "unconditional jump 16"
+ (UNCOND-CTI SHORT-INSN)
+ ("jr $rn")
+ (+ OP4_FLOW16 (f-opc-8-5 #x14) (f-dc-15-3 #x0) (f-dc-9-1 #x0) rn)
+ (set pc rn)
+ ()
+ )
+
+;; RTS / JR
+;; ??? Putting a constant into a multi-ifield does not work -
+;; the constant gets inserted in full into each part.
+ ;(dnmi rts "return from subroutine"
+ ; (UNCOND-CTI)
+ ; ("rts")
+ ; (emit jr (rn6 14)) ; jr lr / jr r14
+ ;)
+;; RTS / JR
+(dni rts "return from subroutine"
+ (ALIAS UNCOND-CTI)
+ ("rts")
+ (+ OP4_MISC (f-opc-8-5 #x14) (f-opc-19-4 #x2) (f-rn 6) (f-rn-x 1)
+ (f-dc-9-1 #x0)
+ (f-dc-15-3 #x0)
+ (f-dc-25-6 #x0)
+ (f-dc-31-3 #x0)
+ )
+ (set pc (reg h-registers 14))
+ ()
+ )
+
+(dni jr "unconditional jump"
+ (UNCOND-CTI)
+ ("jr $rn6")
+ (+ OP4_MISC (f-opc-8-5 #x14) (f-opc-19-4 #x2) rn6
+ (f-dc-9-1 #x0)
+ (f-dc-15-3 #x0)
+ (f-dc-25-6 #x0)
+ (f-dc-31-3 #x0)
+ )
+ (set pc rn6)
+ ()
+ )
+
+
+;; JALR <RN>
+(dni jalr16 "jump and link register"
+ (UNCOND-CTI SHORT-INSN)
+ ("jalr $rn")
+ (+ OP4_FLOW16 (f-opc-8-5 #x15) (f-dc-15-3 #x0) (f-dc-9-1 #x0) rn)
+ (sequence ()
+ (set (reg h-registers 14) (add pc (const 2)))
+ (set pc rn)
+ )
+ ()
+ )
+
+(dni jalr "jump and link register"
+ (UNCOND-CTI)
+ ("jalr $rn6")
+ (+ OP4_MISC
+ (f-opc-8-5 #x15)
+ (f-opc-19-4 #x2)
+ rn6
+ (f-dc-9-1 #x0)
+ (f-dc-15-3 #x0)
+ (f-dc-25-6 #x0)
+ (f-dc-31-3 #x0)
+
+ )
+ (sequence ()
+ (set (reg h-registers 14) (add pc (const 4)))
+ (set pc rn6))
+ ()
+ )
+
+\f
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ; Load/Store Memory Instructions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+
+(define-pmacro (callMisaligmentExceptionIfNeeded sel addr isAligmentAccess)
+ (sequence ((BI scale))
+ (set isAligmentAccess
+ (case BI sel
+ ((OPW_BYTE) (eq (and addr #x0) #x0))
+ ((OPW_SHORT) (eq (and addr #x1) #x0))
+ ((OPW_WORD) (eq (and addr #x3) #x0))
+ (else (eq (and addr #x7) #x0))))
+ (if (not BI isAligmentAccess)
+ (call-exception #x4 #x2))
+ )
+)
+
+
+
+;; helper to convert size selector OPW_<mode> into a literal scale factor
+(define-pmacro (ConvertSelectorToShift sel scale)
+ (set scale
+ (case SI sel
+ ((OPW_BYTE) (const 0))
+ ((OPW_SHORT) (const 1))
+ ((OPW_WORD) (const 2))
+ (else (const 3))))
+)
+
+;; common load macros from effective address, handling 8/16/32/64 bits
+(define-pmacro (load-double-from-ea regnum eff-addr mode sel)
+ (sequence ((SI loadaddr) (BI isAligmentAccess))
+ (set loadaddr eff-addr)
+ (callMisaligmentExceptionIfNeeded sel loadaddr isAligmentAccess)
+
+ (if (not (not BI isAligmentAccess))
+ (sequence ()
+ (set memaddr loadaddr)
+ (set regnum (mem SI loadaddr))
+ (set loadaddr (add loadaddr (const 4)))
+ (set memaddr loadaddr)
+ (set (reg h-registers
+ (add (index-of regnum)
+ (const 1)))
+ (mem SI loadaddr))
+
+ )
+ )
+ )
+ )
+
+(define-pmacro (load-from-ea regnum eff-addr mode sel)
+ (sequence ((BI isAligmentAccess))
+
+ (callMisaligmentExceptionIfNeeded sel eff-addr isAligmentAccess)
+ (if (not (not BI isAligmentAccess))
+ (sequence ()
+ (set memaddr eff-addr)
+ (set regnum (zext SI (mem mode eff-addr)))
+ )
+ )
+ )
+ ) ;; 8/16/32 bit cases
+
+
+;; common store to effective address, handling 8/16/32/64 bit data
+(define-pmacro (store-double-to-ea eff-addr regnum mode sel)
+ (sequence ((SI storeaddr) (BI isAligmentAccess))
+ (set storeaddr eff-addr)
+ (callMisaligmentExceptionIfNeeded sel storeaddr isAligmentAccess)
+ (if (not (not BI isAligmentAccess))
+ (sequence ()
+ (set memaddr storeaddr)
+ (set (mem SI storeaddr) regnum)
+ (set storeaddr (add storeaddr (const 4)))
+ (set memaddr storeaddr)
+ (set (mem SI storeaddr)
+ (reg h-registers (add (index-of regnum) (const 1))))
+ )
+ )
+ )
+ )
+
+(define-pmacro (store-to-ea eff-addr regnum mode sel)
+ (sequence ((BI isAligmentAccess))
+ (callMisaligmentExceptionIfNeeded sel eff-addr isAligmentAccess)
+ (if (not (not BI isAligmentAccess))
+ (sequence ()
+ (set memaddr eff-addr)
+ (set (mem mode eff-addr) regnum)
+ )
+ )
+ )
+ ) ;8/16/32 bit cases
+
+
+(define-pmacro (load-insn name mode sel sem-op)
+ (begin
+ (dni_wrapper (.sym name "x16.s")
+ (.str "load " mode " indexed")
+ (SHORT-INSN)
+ (.str name " $rd,[$rn,$rm]")
+ (+ OP4_LDSTR16X sel OP_LOAD rd rn rm)
+ (sequence ()
+ (sem-op rd (add rn rm) mode sel))
+ ()
+ )
+
+
+ (dni_wrapper (.sym name "p16.s")
+ (.str "load " mode " postmodify")
+ (SHORT-INSN)
+ (.str name " $rd,[$rn],$rm")
+ (+ OP4_LDSTR16P sel OP_LOAD rd rn rm)
+ (sequence ((SI tmprm))
+ (set tmprm rm)
+ (sem-op rd rn mode sel)
+ (set rn (add rn tmprm)))
+ ()
+ )
+
+
+ (dni_wrapper (.sym name "x.l")
+ (.str "load " mode " indexed")
+ ()
+ (.str name " $rd6,[$rn6,$direction$rm6]")
+ (+ OP4_LDSTRX sel OP_LOAD (f-opc-19-4 #x0) (f-dc-22-1 #x0) (f-dc-21-1 #x0) rd6 rn6 direction rm6)
+ (sequence ()
+ (if (ifield f-addsubx)
+ (sem-op rd6 (sub rn6 rm6) mode sel)
+ (sem-op rd6 (add rn6 rm6) mode sel)))
+ ()
+ )
+
+ (dnmi (.sym name "x")
+ (.str "load " mode " indexed")
+ ()
+ (.str name ".l $rd6,[$rn6,$direction$rm6]")
+ (emit (.sym name "x.l") rd6 rn6 direction rm6)
+ )
+
+
+
+ (dni_wrapper (.sym name "p.l")
+ (.str "load " mode " postmodify")
+ ()
+ (.str name " $rd6,[$rn6],$direction$rm6")
+ (+ OP4_LDSTRP sel OP_LOAD (f-opc-19-4 #x0) (f-dc-22-2 #x0) rd6 rn6 direction rm6)
+ (sequence ((SI tmprm))
+ (set tmprm rm6)
+ (sem-op rd6 rn6 mode sel)
+ (if (ifield f-addsubx)
+ (set rn6 (sub rn6 tmprm))
+ (set rn6 (add rn6 tmprm)))
+ )
+ ()
+ )
+
+
+ (dnmi (.sym name "p")
+ (.str "load " mode " postmodify")
+ ()
+ (.str name ".l $rd6,[$rn6],$direction$rm6")
+ (emit (.sym name "p.l") rd6 rn6 direction rm6)
+ )
+
+
+ ;;immediate modes last so reg forms found first.
+ (dni_wrapper (.sym name "d16.s")
+ (.str "load " mode " displacement")
+ (SHORT-INSN IMM3)
+ (.str name " $rd,[$rn,$disp3]")
+ (+ OP4_LDSTR16D sel OP_LOAD rd rn disp3) ;; convert size to 'B'
+ (sequence ((SI effa)
+ (SI scale))
+ (ConvertSelectorToShift sel scale)
+ (set effa (add rn (sll disp3 scale)))
+ (sem-op rd effa mode sel)
+ )
+ ()
+ )
+
+
+ (dni_wrapper (.sym name "d.l")
+ (.str "load " mode " displacement")
+ ()
+ (.str name " $rd6,[$rn6,$dpmi$disp11]")
+ (+ OP4_LDSTRD sel OP_LOAD PMOD_DISP rd6 rn6 dpmi disp11)
+ (sequence ((SI effa)
+ (SI scale))
+ (ConvertSelectorToShift sel scale)
+ (if dpmi
+ (set effa (sub rn6 (sll disp11 scale)))
+ (set effa (add rn6 (sll disp11 scale)))
+ )
+ (sem-op rd6 effa mode sel)
+ )
+ ()
+ )
+
+ (dnmi (.sym name "d")
+ (.str "load " mode " displacement")
+ ()
+ (.str name ".l $rd6,[$rn6,$dpmi$disp11]")
+ (emit (.sym name "d.l") rd6 rn6 dpmi disp11)
+ )
+
+
+
+ (dni_wrapper (.sym name "dpm.l")
+ (.str "load " mode " displacement post-modify")
+ ()
+ (.str name " $rd6,[$rn6],$dpmi$disp11")
+ (+ OP4_LDSTRD sel OP_LOAD PMOD_POST rd6 rn6 dpmi disp11)
+ (sequence ((SI scale))
+ (ConvertSelectorToShift sel scale)
+ (sem-op rd6 rn6 mode sel)
+ (if dpmi
+ (set rn6 (sub rn6 (sll disp11 scale)))
+ (set rn6 (add rn6 (sll disp11 scale)))
+ )
+ )
+ ()
+ )
+
+ (dnmi (.sym name "dpm")
+ (.str "load " mode " displacement post-modify")
+ ()
+ (.str name ".l $rd6,[$rn6],$dpmi$disp11")
+ (emit (.sym name "dpm.l") rd6 rn6 dpmi disp11)
+ )
+
+
+ ;; ;; macro form with a zero displacement
+ (dnmi (.sym name "ds0") "load with 0 disp"
+ (SHORT-INSN IMM3)
+ (.str name " $rd,[$rn]")
+ (emit (.sym name "d16.s") rd rn (disp3 0))
+ )
+ (dnmi (.sym name "dl0") "load with 0 disp"
+ ()
+ (.str name " $rd6,[$rn6]")
+ (emit (.sym name "d.l") rd6 rn6 (dpmi 0) (disp11 0))
+ )
+ (dnmi (.sym name "dl0.l") "load with 0 disp"
+ ()
+ (.str name ".l $rd6,[$rn6]")
+ (emit (.sym name "d.l") rd6 rn6 (dpmi 0) (disp11 0))
+ )
+
+
+ )
+ )
+
+(load-insn ldrb QI OPW_BYTE load-from-ea)
+(load-insn ldrh HI OPW_SHORT load-from-ea)
+(load-insn ldr SI OPW_WORD load-from-ea)
+(load-insn ldrd DI OPW_DOUBLE load-double-from-ea)
+
+
+
+
+;; TMP = MEM[RD+RM]; /* Copy content of memory to tmp. */
+;; if (~TMP) /* Check if memory location is zero. */
+;; MEM[RD+RM] = RD; /* If zero, write RD to memory. */
+;; RD = TMP; /* Always write tmp into RD (NOTE it's destructive). */
+
+
+(define-pmacro (testset-insn name mode sel)
+ (begin
+
+
+ (dni_wrapper (.sym name "t")
+ (.str "testset " mode " indexed")
+ ()
+ (.str name " $rd6,[$rn6,$direction$rm6]")
+ (+ OP4_LDSTRX sel OP_LOAD (f-opc-19-4 #x0) (f-dc-22-1 #x0) (f-dc-21-1 #x1)
+ rd6 rn6 direction rm6)
+ (sequence ((SI tmemaddr) (SI tmpValReg))
+
+ ;;back up register
+ (set tmpValReg rd6)
+
+ (if (ifield f-addsubx)
+ (set tmemaddr (sub rn6 rm6))
+ (set tmemaddr (add rn6 rm6))
+ )
+ ;;always update rd
+ (load-from-ea rd6 tmemaddr mode sel)
+ ;;if zero
+ (if rd6
+ (nop)
+ (set (mem mode tmemaddr) tmpValReg)
+ )
+
+ )
+ ()
+ )
+
+
+ (dnmi (.sym name "t.l")
+ (.str "testset " mode ".l indexed")
+ ()
+ (.str name ".l $rd6,[$rn6,$direction$rm6]")
+ (emit (.sym name "t") rd6 rn6 direction rm6)
+ )
+
+
+ )
+ )
+
+(testset-insn testsetb QI OPW_BYTE)
+(testset-insn testseth HI OPW_SHORT)
+(testset-insn testset SI OPW_WORD)
+;;no double mode support, since we have to send the src address, data
+;;(testset-insn testsetd DI OPW_DOUBLE load-double-from-ea)
+
+
+
+;; need 16 bit forms too
+(define-pmacro (store-insn name mode sel sem-op)
+ (begin
+ (dni_wrapper (.sym name "x16")
+ (.str "store" mode " indexed")
+ (SHORT-INSN)
+ (.str name " $rd,[$rn,$rm]")
+ (+ OP4_LDSTR16X sel OP_STORE rd rn rm)
+ (sequence ()
+ (sem-op (add rn rm) rd mode sel)
+ )
+ ()
+ )
+
+ (dni_wrapper (.sym name "x")
+ (.str "store" mode " indexed")
+ ()
+ (.str name " $rd6,[$rn6,$direction$rm6]")
+ (+ OP4_LDSTRX sel OP_STORE (f-opc-19-4 #x0) (f-dc-22-1 #x0) (f-dc-21-1 #x0) rd6 rn6 direction rm6)
+ (sequence ()
+ (if (ifield f-addsubx)
+ (sem-op (sub rn6 rm6) rd6 mode sel)
+ (sem-op (add rn6 rm6) rd6 mode sel)
+ ))
+ ()
+ )
+
+ (dnmi (.sym name "x.l")
+ (.str "store" mode " indexed")
+ ()
+ (.str name ".l $rd6,[$rn6,$direction$rm6]")
+ (emit (.sym name "x") rd6 rn6 direction rm6)
+ )
+
+
+
+
+
+ (dni_wrapper (.sym name "p16")
+ (.str "store " mode " postmodify")
+ (SHORT-INSN)
+ (.str name " $rd,[$rn],$rm")
+ (+ OP4_LDSTR16P sel OP_STORE rd rn rm)
+ (sequence ()
+ (sem-op rn rd mode sel)
+ (set rn (add rn rm))
+ )
+ ()
+ )
+
+ (dni_wrapper (.sym name "p")
+ (.str "store " mode " postmodify")
+ ()
+ (.str name " $rd6,[$rn6],$direction$rm6")
+ (+ OP4_LDSTRP sel OP_STORE (f-opc-19-4 #x0) (f-dc-22-2 #x0) rd6 rn6 direction rm6)
+ (sequence ()
+ (sem-op rn6 rd6 mode sel)
+ (if (ifield f-addsubx)
+ (set rn6 (sub rn6 rm6))
+ (set rn6 (add rn6 rm6)))
+ )
+ ()
+ )
+ (dnmi (.sym name "p.l")
+ (.str "store " mode " postmodify")
+ ()
+ (.str name ".l $rd6,[$rn6],$direction$rm6")
+ (emit (.sym name "p") rd6 rn6 direction rm6)
+ )
+
+ (dni_wrapper (.sym name "d16")
+ (.str "store " mode " displacement")
+ (SHORT-INSN IMM3)
+ (.str name " $rd,[$rn,$disp3]")
+ (+ OP4_LDSTR16D sel OP_STORE rd rn disp3) ;; convert size to 'B'
+ (sequence ((SI effa)
+ (SI scale))
+ (ConvertSelectorToShift sel scale)
+ (set effa (add rn (sll disp3 scale)))
+ (sem-op effa rd mode sel)
+ )
+ ()
+ )
+
+ (dni_wrapper (.sym name "d")
+ (.str "store " mode " displacement")
+ ()
+ (.str name " $rd6,[$rn6,$dpmi$disp11]")
+ (+ OP4_LDSTRD sel OP_STORE PMOD_DISP rd6 rn6 dpmi disp11)
+ (sequence ((SI effa)
+ (SI scale))
+ (ConvertSelectorToShift sel scale)
+ (if dpmi
+ (set effa (sub rn6 (sll disp11 scale)))
+ (set effa (add rn6 (sll disp11 scale)))
+ )
+ (sem-op effa rd6 mode sel)
+ )
+ ()
+ )
+
+ (dnmi (.sym name "d.l")
+ (.str "store " mode " displacement")
+ ()
+ (.str name ".l $rd6,[$rn6,$dpmi$disp11]")
+ (emit (.sym name "d") rd6 rn6 dpmi disp11)
+ )
+
+
+ (dni_wrapper (.sym name "dpm")
+ (.str "store " mode " displacement post-modify")
+ ()
+ (.str name " $rd6,[$rn6],$dpmi$disp11")
+ (+ OP4_LDSTRD sel OP_STORE PMOD_POST rd6 rn6 dpmi disp11) ;; convert size to 'B'
+ (sequence ((SI scale))
+ (ConvertSelectorToShift sel scale)
+ (sem-op rn6 rd6 mode sel)
+ (if dpmi
+ (set rn6 (sub rn6 (sll disp11 scale)))
+ (set rn6 (add rn6 (sll disp11 scale)))
+ )
+ )
+ ()
+ )
+ (dnmi (.sym name "dpm.l")
+ (.str "store " mode " displacement post-modify")
+ ()
+ (.str name ".l $rd6,[$rn6],$dpmi$disp11")
+ (emit (.sym name "dpm") rd6 rn6 dpmi disp11)
+ )
+
+ ;; macro form with a zero displacement
+ (dnmi (.sym name "ds0") "store w 0 disp"
+ (SHORT-INSN IMM3)
+ (.str name " $rd,[$rn]")
+ (emit (.sym name "d16") rd rn (disp3 0))
+ )
+
+ (dnmi (.sym name "dl0") "store w 0 disp"
+ ()
+ (.str name " $rd6,[$rn6]")
+ (emit (.sym name "d") rd6 rn6 (dpmi 0) (disp11 0))
+ )
+
+ (dnmi (.sym name "dl0.l") "store w 0 disp"
+ ()
+ (.str name ".l $rd6,[$rn6]")
+ (emit (.sym name "d") rd6 rn6 (dpmi 0) (disp11 0))
+ )
+
+
+
+ )
+ )
+
+(store-insn strb QI OPW_BYTE store-to-ea)
+(store-insn strh HI OPW_SHORT store-to-ea)
+(store-insn str SI OPW_WORD store-to-ea)
+(store-insn strd DI OPW_DOUBLE store-double-to-ea)
+\f
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; MOV<COND> RD,RN
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(define-pmacro (move-insns name cond g-op)
+ (begin
+ (dni_wrapper (.sym "cmov16" cond)
+ (.str "move register " cond)
+ (SHORT-INSN)
+ (.str "mov" name " $rd,$rn")
+ (+ OP4_FLOW16 (.sym "OPC_" cond) (f-opc-8-1 #x0) (f-dc-9-1 #x0) rd rn)
+ (if (g-op)
+ (set rd rn))
+ ()
+ )
+
+ (dni_wrapper (.sym "cmov" cond)
+ (.str "move register " cond)
+ ()
+ (.str "mov" name " $rd6,$rn6")
+ (+ OP4_MISC (.sym "OPC_" cond) (f-opc-8-1 #x0) (f-dc-9-1 #x0) (f-opc-19-4 #x2) (f-dc-25-6 #x0) rd6 rn6)
+ (if (g-op)
+ (set rd6 rn6))
+ ()
+ )
+ (dnmi (.sym "cmov.l" cond)
+ (.str "move register " cond)
+ ()
+ (.str "mov" name ".l $rd6,$rn6")
+ (emit (.sym "cmov" cond) rd6 rn6)
+ )
+
+
+
+ )
+ )
+
+ ; basic conditional moves
+(move-insns "eq" EQ (.pmacro () (eq zbit #x1)))
+(move-insns "ne" NE (.pmacro () (eq zbit #x0)))
+(move-insns "gtu" GTU (.pmacro () (and BI cbit (not BI zbit))))
+(move-insns "gteu" GTEU (.pmacro () (eq cbit #x1)))
+(move-insns "lteu" LTEU (.pmacro () (or BI (not BI cbit) zbit)))
+(move-insns "ltu" LTU (.pmacro () (eq cbit #x0)))
+(move-insns "gt" GT (.pmacro () (and BI (not BI zbit) (eq vbit nbit))))
+(move-insns "gte" GTE (.pmacro () (eq vbit nbit)))
+(move-insns "lt" LT (.pmacro () (xor BI vbit nbit)))
+(move-insns "lte" LTE (.pmacro () (or BI zbit (xor vbit nbit))))
+
+ ; unconditional move
+(move-insns "" B (.pmacro () #x1))
+
+
+ ; floating point condition codes (floating point instructions)
+(move-insns "beq" BEQ (.pmacro () (or BI bzbit bzbit)))
+(move-insns "bne" BNE (.pmacro () (not BI bzbit)))
+(move-insns "blt" BLT (.pmacro () (and BI bnbit (not bzbit))))
+(move-insns "blte" BLTE (.pmacro () (or BI bnbit bzbit)))
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; MOVTS RD,RN
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;; 16 bits form exists for group zero ( M1 and M0 equals to zero ) only
+
+(dni_wrapper movts16
+ "move to special reg"
+ (SHORT-INSN)
+ "movts $sn,$rd"
+ (+ OP4_FLOW16 (f-opc-8-5 #x10) (f-dc-9-1 #x0) rd sn) ;; rd is source for movts
+ (set sn rd)
+ ()
+ )
+
+(define-pmacro (op-mmr-movts name sdreg code)
+ (begin
+
+ (dni_wrapper (.sym "movts" name)
+ (.str "move to " name)
+ ()
+ (.str "movts $" sdreg ",$rd6")
+ (+ OP4_MISC (f-dc-7-4 #x0) (f-opc-8-1 #x1) (f-dc-9-1 #x0) (f-opc-19-4 #x2) (f-dc-25-4 #x0) (f-dc-21-2 code) sdreg rd6);; rd is source for movts
+ (set sdreg rd6)
+ ()
+ )
+
+ (dnmi (.sym "movts.l" name)
+ (.str "move to " name)
+ ()
+ (.str "movts.l $" sdreg ",$rd6")
+ (emit (.sym "movts" name) sdreg rd6)
+ )
+
+
+
+
+ )
+ )
+
+(op-mmr-movts 6 sn6 #x0)
+(op-mmr-movts dma sndma #x1)
+(op-mmr-movts mem snmem #x2)
+(op-mmr-movts mesh snmesh #x3)
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; MOVFS
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+(dni_wrapper movfs16
+ "move from special register"
+ (SHORT-INSN)
+ "movfs $rd,$sn"
+ (+ OP4_FLOW16 (f-opc-8-5 #x11) (f-dc-9-1 #x0) rd sn)
+ (set rd sn)
+ ()
+ )
+
+
+
+(define-pmacro (op-mmr-movfs name snreg code)
+ (begin
+
+ (dni_wrapper (.sym "movfs" name)
+ (.str "move from " name)
+ ()
+ (.str "movfs $rd6,$" snreg)
+ (+ OP4_MISC (f-dc-7-4 #x1) (f-opc-8-1 #x1) (f-dc-9-1 #x0) (f-opc-19-4 #x2) (f-dc-25-4 #x0) (f-dc-21-2 code) rd6 snreg)
+ (set rd6 snreg)
+ ()
+ )
+
+ (dnmi (.sym "movfs.l" name)
+ (.str "move from " name)
+ ()
+ (.str "movfs.l $rd6,$" snreg)
+ (emit (.sym "movfs" name) rd6 snreg)
+ )
+
+
+
+ )
+ )
+
+(op-mmr-movfs 6 sn6 #x0)
+(op-mmr-movfs dma sndma #x1)
+(op-mmr-movfs mem snmem #x2)
+(op-mmr-movfs mesh snmesh #x3)
+
+
+
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; NOP 0x1a2
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+(dni_wrapper nop
+ "no-operation"
+ (SHORT-INSN)
+ "nop"
+ (+ OP4_FLOW16 (f-opc-8-5 #x1a) (f-dc-15-7 #x0))
+ (nop)
+ ()
+ )
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; SNOP 0x3a2
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+(dni_wrapper snop
+ "no-operation"
+ (SHORT-INSN)
+ "snop"
+ (+ OP4_FLOW16 (f-opc-8-5 #x3a) (f-dc-15-7 #x0))
+ (nop)
+ ()
+ )
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; UNIMPL
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+(dni_wrapper unimpl
+ "not-implemented"
+ ()
+ "unimpl"
+ (+ (f-opc-31-32 #x000F000F))
+ (nop)
+ ()
+ )
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; IDLE
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(dni idle "idle until interrupt" () "idle"
+ (+ OP4_FLOW16 (f-opc-8-5 #x1b) (f-dc-15-7 #x0))
+ ;; (set pc pc) ;; should branch to self until interrupt, but not modeling interrupts
+ (sequence ()
+ (set caibit 0)
+ (c-code "sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, \
+ pc, sim_exited, 0);"))
+ ()
+ )
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; BKPT
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(dni bkpt
+ "breakpoint"
+ (SHORT-INSN)
+ "bkpt"
+ (+ OP4_FLOW16 (f-opc-8-5 #x1c) (f-dc-15-7 #x0))
+ (sequence ()
+ (c-call "epiphany_break" pc)
+ (set pc pc)
+ )
+ ()
+ )
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; MBKPT
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(dni mbkpt
+ "multicorebreakpoint"
+ (SHORT-INSN)
+ "mbkpt"
+ (+ OP4_FLOW16 (f-opc-8-5 #x1c) (f-dc-15-7 #x1))
+ ;;;(c-call "epiphany_break" pc)
+ (nop) ;; ignore the multi core break point in the simulator
+ ()
+ )
+
+;;;;;;;;;;;;;;;;
+;; RTI
+;;;;;;;;;;;;;;;;
+
+(dni rti "return from interrupt" (SHORT-INSN UNCOND-CTI)
+ "rti"
+ (+ OP4_FLOW16 (f-opc-8-5 #x1d) (f-dc-15-7 #x0))
+ (sequence ()
+ ;; (set (hcr-ipend)
+ ;; (xor (hcr-ipend)
+ ;; (sll (const 1)
+ ;; (sub (c-raw-call SI "ffs" (and (hcr-ipend) (not (hcr-imask))))
+ ;; (const 1)))))
+
+ (set (hcr-ipend)
+ (c-call SI "epiphany_rti" (hcr-ipend) (hcr-imask)))
+ (set gidisablebit 0)
+ (set kmbit 0)
+ ;(set caibit 1)
+ (set pc (hcr-iret)))
+ ()
+ )
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; WAND is a wired flag that runs around the chip
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+(dni_wrapper wand "wand"
+ (SHORT-INSN)
+ "wand"
+ (+ OP4_FLOW16 (f-opc-8-5 #x18) (f-dc-15-7 #x0))
+ (set sflagbit 1)
+ ()
+ )
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Sync likes wand, but wired OR
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+(dni_wrapper sync "sync"
+ (SHORT-INSN)
+ "sync"
+ (+ OP4_FLOW16 (f-opc-8-5 #x1f) (f-dc-15-7 #x0))
+ (nop);;TODO
+ ()
+ )
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; GIE
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+(dni_wrapper gien "global interrupt enable"
+ (SHORT-INSN)
+ "gie"
+ (+ OP4_FLOW16 (f-gien-gidis-9-1 #x0) (f-opc-8-5 #x19) (f-dc-15-6 #x0))
+ (set gidisablebit 0)
+ ()
+ )
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; GIDIS
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+(dni_wrapper gidis "global interrupt disable"
+ (SHORT-INSN)
+ "gid"
+ (+ OP4_FLOW16 (f-gien-gidis-9-1 #x1) (f-opc-8-5 #x19) (f-dc-15-6 #x0))
+ (set gidisablebit 1)
+ ()
+ )
+
+
+
+;;;;;;;;;;;;;;;;
+;; SWI
+;;;;;;;;;;;;;;;;
+
+;; Model only immediate 'fire' exception, if gien cleared or masked don't fire and don't check later - no ilat like behavior
+(dni swi_num "software interrupt" (SHORT-INSN UNCOND-CTI)
+ "swi $swi_num"
+ (+ OP4_FLOW16 (f-opc-8-5 #x1e) (f-trap-swi-9-1 #x0) swi_num)
+ (sequence () (call-exception #x24 #x80))
+ ;; (if (eq gie 1)
+ ;; (sequence ()
+ ;; (set kmbit 1)
+ ;; (set gie 0)
+ ;; (set (hcr-iret) (add pc (const 2)))
+ ;; (set (hcr-ipend) (or (hcr-ipend) (const #x80)))
+ ;; (set pc (const #x1c))
+
+ ;; )
+ ;; ;; schedule interrupt
+ ;; (set (hcr-ilat) (or (hcr-ilat) (const #x80)))
+ ;; )
+ ()
+ )
+(dni swi "software interrupt" (ALIAS SHORT-INSN UNCOND-CTI)
+ "swi"
+ (+ OP4_FLOW16 (f-opc-8-5 #x1e) (f-trap-swi-9-1 #x0) (f-dc-15-6 #x0))
+ (sequence () (call-exception #x24 #x80))
+ ()
+ )
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; TRAP #disp3 - simulator only and chip as well - make the same grouop as swi
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;; Only defining 16-bit form of this instruction. It exists to support the
+;; simulator, by giving us a simple input/output mechanism beyond returning values
+;; in registers or memory.
+;; TRAP #N - special sw trap for simulator support; allows simple i/o using fixed arguments
+;; TRAP #0 - write (r0=i/o channel, r1=addr, r2=len) returns status in r0
+;; TRAP #1 - read (r0=i/o channel, r1=addr, r2=len) returns length or -<code> on error
+;; TRAP #2 - open (r0=string path, r1=mode) returns channel# or -<code> on error
+;; TRAP #3 - exit (r0=status code) never returns.
+;; TRAP #4 - print "pass\n" and exit
+;; TRAP #5 - print "fail\n" and exit
+;; TRAP #6 - close (r0=i/o channel)
+
+(dni trap16 "trap to simulator"
+ (SHORT-INSN UNCOND-CTI)
+ "trap $trapnum6"
+ (+ OP4_FLOW16 (f-opc-8-5 #x1e) (f-trap-swi-9-1 #x1) trapnum6) ;; (+ OP4_IMM16 OPI_TRAP (f-rd 0) (f-rn 0) disp3)
+ (set (reg SI h-registers 0) (c-call SI "epiphany_trap" pc trapnum6))
+ ()
+ )
+
+\f
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Integer arithmetic instructions 3 address forms
+;; both 16 and 32 bit forms
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(define-pmacro (op-rrr name sem-op cond-op)
+ (begin
+ (dni_wrapper (.sym name "16")
+ (.str name)
+ (SHORT-INSN)
+ (.str name " $rd,$rn,$rm")
+ (+ OP4_ALU16 (.sym "OPB_" (.upcase (.str name))) rd rn rm)
+ (sequence ()
+ (cond-op rn rm)
+ (set rd (sem-op SI rn rm))
+ (set zbit (zflag rd))
+ (set nbit (nflag rd))
+ )
+ ()
+ )
+
+ (dni_wrapper (.sym name)
+ (.str name)
+ ()
+ (.str name " $rd6,$rn6,$rm6")
+ (+ OP4_MISC (.sym "OPB_" (.upcase (.str name))) (f-opc-19-4 #xa) (f-dc-22-3 #x0) rd6 rn6 rm6)
+ (sequence ()
+ (cond-op rn6 rm6)
+ (set rd6 (sem-op SI rn6 rm6))
+ (set zbit (zflag rd6))
+ (set nbit (nflag rd6))
+ )
+ ()
+ )
+
+ (dnmi (.sym name ".l")
+ (.str name)
+ ()
+ (.str name ".l $rd6,$rn6,$rm6")
+ (emit (.sym name) rd6 rn6 rm6)
+ )
+
+
+
+ )
+ )
+
+;; submacros to set condition codes
+;; NZ are always set to reflect the sign and value of the result
+;; CV are a function of the operator
+(define-pmacro (add-vc a b) (sequence ()
+ (set cbit (add-cflag SI a b 0))
+ (set vbit (add-oflag SI a b 0))
+ (set vsbit (or BI vsbit vbit))
+ ))
+
+(define-pmacro (sub-vc a b) (sequence ()
+ (set cbit (not (sub-cflag SI a b 0)))
+ (set vbit (sub-oflag SI a b 0))
+ (set vsbit (or vsbit vbit))
+ ))
+
+(define-pmacro (logic-vc a b) (sequence ()
+ (set cbit 0)
+ (set vbit 0)
+ ))
+
+(op-rrr add add add-vc)
+(op-rrr sub sub sub-vc)
+(op-rrr and and logic-vc)
+(op-rrr orr or logic-vc)
+(op-rrr eor xor logic-vc)
+
+;; Integer arithmetic immediate forms
+
+(define-pmacro (op-rri name code cond-op)
+ (begin
+ (dni_wrapper (.sym name "i16")
+ (.str name)
+ (SHORT-INSN IMM3)
+ (.str name ".s $rd,$rn,$simm3")
+ (+ OP4_IMM16 code rd rn simm3)
+ (sequence ()
+ (cond-op rn simm3)
+ (set rd (name SI rn simm3))
+ (set zbit (zflag rd))
+ (set nbit (nflag rd))
+ )
+ ()
+ )
+
+
+ (dni_wrapper (.sym name "i")
+ (.str name)
+ ()
+ (.str name ".l $rd6,$rn6,$simm11")
+ (+ OP4_IMM32 code OPI_25_2_MBZ rd6 rn6 simm11)
+ (sequence ()
+ (cond-op rn6 simm11)
+ (set rd6 (name SI rn6 simm11))
+ (set zbit (zflag rd6))
+ (set nbit (nflag rd6))
+ )
+ ()
+ )
+
+ ;; (dnmi (.sym name "ri") "relaxed arithmetic immediate" (RELAXED)
+ ;; (.str name " $rd6,$rn6,$simm11")
+ ;; (emit (.sym name "i") rd6 rn6 simm11))
+ )
+ )
+
+(op-rri add OPI_ADD add-vc)
+(op-rri sub OPI_SUB sub-vc)
+
+(dnmi addir "relaxable short immediate add" (RELAXABLE IMM3)
+ "add $rd,$rn,$simm3"
+ (emit addi16 rd rn simm3))
+
+(dnmi addi32r "relaxed long immediate add" (RELAXED)
+ "add $rd6,$rn6,$simm11"
+ (emit addi rd6 rn6 simm11))
+
+;; Again, but not relaxable so that full sized registers are handled
+(dnmi addi32m "relaxed long immediate add" ()
+ "add $rd6,$rn6,$simm11"
+ (emit addi rd6 rn6 simm11))
+
+
+(dnmi subir "relaxable short immediate sub" (RELAXABLE IMM3)
+ "sub $rd,$rn,$simm3"
+ (emit subi16 rd rn simm3))
+
+(dnmi subi32r "relaxed long immediate sub" (RELAXED)
+ "sub $rd6,$rn6,$simm11"
+ (emit subi rd6 rn6 simm11))
+
+(dnmi subi32m "relaxed long immediate sub" ()
+ "sub $rd6,$rn6,$simm11"
+ (emit subi rd6 rn6 simm11))
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Shift instructions 3 address forms
+;; both 16 and 32 bit forms
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(define-pmacro (shift-rrr name sem-op)
+ (begin
+ (dni_wrapper (.sym name "16")
+ (.str name)
+ (SHORT-INSN)
+ (.str name " $rd,$rn,$rm")
+ (+ OP4_ALU16 (.sym "OPB_" (.upcase (.str name))) rd rn rm)
+ (sequence ()
+ (logic-vc rn rm)
+ (set rd (sem-op SI rn (and rm (const 31))))
+ (set zbit (zflag rd))
+ (set nbit (nflag rd))
+ )
+ ()
+ )
+
+ (dni_wrapper (.sym name)
+ (.str name)
+ ()
+ (.str name " $rd6,$rn6,$rm6")
+ (+ OP4_MISC (.sym "OPB_" (.upcase (.str name))) (f-opc-19-4 #xa) (f-dc-22-3 #x0) rd6 rn6 rm6)
+ (sequence ()
+ (logic-vc rn6 rm6)
+ (set rd6 (sem-op SI rn6 (and rm6 (const 31))))
+ (set zbit (zflag rd6))
+ (set nbit (nflag rd6))
+ )
+ ()
+ )
+
+ (dnmi (.sym name ".l")
+ (.str name)
+ ()
+ (.str name ".l $rd6,$rn6,$rm6")
+ (emit (.sym name) rd6 rn6 rm6)
+ )
+ )
+ )
+
+(shift-rrr asr sra)
+(shift-rrr lsr srl)
+(shift-rrr lsl sll)
+
+(define-pmacro (op-shift-rri name shortcode f5 longcode sem-op)
+ (begin
+ (dni_wrapper (.sym name "i16")
+ (.str name)
+ (SHORT-INSN)
+ (.str name " $rd,$rn,$shift")
+ (+ shortcode (f-opc-4-1 f5) rd rn shift)
+ (sequence ()
+ (logic-vc rn shift)
+ (set rd (sem-op SI rn shift))
+ (set zbit (zflag rd))
+ (set nbit (nflag rd))
+ )
+ ()
+ )
+ (dni_wrapper (.sym name "i32")
+ (.str name)
+ ()
+ (.str name " $rd6,$rn6,$shift")
+ (+ OP4_MISC (f-opc-4-1 f5) (f-opc-19-4 longcode) (f-dc-25-6 0) rd6 rn6 shift)
+ (sequence ()
+ (logic-vc rn6 shift)
+ (set rd6 (sem-op SI rn6 shift))
+ (set zbit (zflag rd6))
+ (set nbit (nflag rd6))
+ )
+ ()
+ )
+
+ (dnmi (.sym name "i32.l")
+ (.str name)
+ ()
+ (.str name ".l $rd6,$rn6,$shift")
+ (emit (.sym name "i32") rd6 rn6 shift)
+ )
+
+
+ )
+ )
+
+(op-shift-rri lsr OP4_LSHIFT16 0 #x6 srl)
+(op-shift-rri lsl OP4_LSHIFT16 1 #x6 sll)
+(op-shift-rri asr OP4_ASHIFT16 0 #xe sra)
+
+;; BITR - bitreversal (FFT)
+;;
+;; From Dr Dobbs et al.
+;;
+;; unsigned int v;
+;; v = ((v >> 1) & 0x55555555) | ((v & 0x55555555) << 1); ;; swap odd-even bits
+;; v = ((v >> 2) & 0x33333333) | ((v & 0x33333333) << 2); ;; swap pairs
+;; v = ((v >> 4) & 0x0f0f0f0f) | ((v & 0x0f0f0f0f) << 4); ;; swap nibbles
+;; v = ((v >> 8) & 0x00ff00ff) | ((v & 0x00ff00ff) << 8); ;; swap bytes
+;; v = (v >> 16) | (v << 16); ;; swap halves
+(define-pmacro (bit-reversal dest src)
+ (sequence ((SI v))
+ (set v src)
+ (set v (or (and (srl v 1) #x55555555) (sll (and v #x55555555) 1)))
+ (set v (or (and (srl v 2) #x33333333) (sll (and v #x33333333) 2)))
+ (set v (or (and (srl v 4) #x0f0f0f0f) (sll (and v #x0f0f0f0f) 4)))
+ (set v (or (and (srl v 8) #x00ff00ff) (sll (and v #x00ff00ff) 8)))
+ (set v (or (srl v 16) (sll v 16)))
+ (set dest v)
+ ))
+
+(dni_wrapper bitr16 "bit reverse short"
+ (SHORT-INSN)
+ ("bitr $rd,$rn")
+ (+ OP4_ASHIFT16 (f-opc-4-1 1) rd rn (f-shift 0))
+ (sequence ()
+ (bit-reversal rd rn)
+ (set zbit (zflag rd))
+ (set nbit (nflag rd))
+ (set cbit 0)
+ (set vbit 0)
+ )
+ ()
+ )
+
+(dni_wrapper bitr "bit reverse"
+ ()
+ ("bitr $rd6,$rn6")
+ (+ OP4_MISC (f-opc-4-1 1) (f-opc-19-4 #xe) (f-dc-25-6 0) rd6 rn6 (f-shift 0))
+ (sequence ()
+ (bit-reversal rd6 rn6)
+ (set zbit (zflag rd6))
+ (set nbit (nflag rd6))
+ (set cbit 0)
+ (set vbit 0)
+ )
+ ()
+ )
+(dnmi bitrl "bit reverse l"
+ ()
+ ("bitr.l $rd6,$rn6")
+ (emit bitr rd6 rn6)
+ )
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Integer arithmetic instructions
+;; Extended operation
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(define-pmacro (op-iextrrr name cond-op)
+ (begin
+
+ (dni_wrapper (.sym name)
+ (.str name)
+ ()
+ (.str name " $rd6,$rn6,$rm6")
+ (+ OP4_MISC (.sym "OPBE_" (.upcase (.str name))) (f-opc-19-4 #xa) (f-dc-22-2 #x0) (f-dc-20-1 #x1)
+ rd6 rn6 rm6)
+ (sequence ()
+ ;; TODO cond operation (cond-op rn6 rm6)
+ ;;(set rd6 (sem-op SI rn6 rm6))
+ (set zbit (zflag rd6))
+ (set nbit (nflag rd6))
+ )
+ ()
+ )
+
+ (dnmi (.sym name ".l")
+ (.str name)
+ ()
+ (.str name ".l $rd6,$rn6,$rm6")
+ (emit (.sym name) rd6 rn6 rm6)
+ )
+ )
+ )
+
+(op-iextrrr fext sub-vc)
+(op-iextrrr fdep sub-vc)
+(op-iextrrr lfsr sub-vc)
+
+
+
+;; Immediate moves. The 8 bit form is relaxed if it doesn't fit or is external
+;; Move RD,#IMM
+(dni_wrapper mov8
+ "mov imm8"
+ (SHORT-INSN)
+ "mov.b $rd,$imm8"
+ (+ OP4_IMM16 (f-opc-4-1 #x0) rd imm8)
+ (set rd (zext SI imm8))
+ ()
+ )
+
+(dnmi mov8r "mov imm8 relaxable"
+ (RELAXABLE)
+ "mov $rd,$imm8"
+ (emit mov8 rd imm8))
+
+(dni_wrapper mov16
+ "mov imm16"
+ ()
+ "mov.l $rd6,$imm16"
+ (+ OP4_IMM32 (f-opc-4-1 #x0) (f-opc-19-4 #x2) (f-dc-28-1 #x0) rd6 imm16)
+ (set rd6 (zext SI imm16))
+ ()
+ )
+
+(dnmi mov16r "mov imm16 relaxable"
+ ()
+ "mov $rd6,$imm16"
+ (emit mov16 rd6 imm16))
+
+;; MOVE TO HIGH WORD
+(dni_wrapper movt
+ "movt imm16"
+ ()
+ "movt $rd6,$imm16"
+ (+ OP4_IMM32 (f-opc-4-1 #x0) (f-opc-19-4 #x2) (f-dc-28-1 #x1) rd6 imm16)
+ (set rd6 (or (and SI rd6 (const #xffff)) ; keep low bits of rd
+ (sll SI imm16 (const 16)))) ; replacing just high bits
+ ()
+ )
+(dnmi movtl
+ "movt imm16"
+ ()
+ "movt.l $rd6,$imm16"
+ (emit movt rd6 imm16)
+ )
+
+
+
+;; FLOATING POINT OPERATIONS
+;; TWO operands
+(define-pmacro (op-two_operands-float name code)
+ (begin
+ (dni_wrapper
+ (.sym "f_" name "f16")
+ (.str "f_" name)
+ (SHORT-INSN)
+ (.str "f" name " $rd,$rn,$rm")
+ (+ OP4_DSP16 code rd rn rm)
+ (sequence ()
+ (if
+ (eq arithmetic-modebit2 0)
+ (sequence ((SF fptemp) (SI sdtmp))
+ (set sdtmp (c-call SI (.str "epiphany_f" name) rd rn rm))
+
+ ;;All bits are calculated in C
+ (set bzbit (c-call BI "get_epiphany_fzeroflag" sdtmp))
+ (set bnbit (c-call BI "get_epiphany_fnegativeflag" sdtmp))
+ (set bvbit (c-call BI "get_epiphany_foverflowflag" sdtmp))
+ (set bubit (c-call BI "get_epiphany_funderflowflag" sdtmp))
+ (set bibit (c-call BI "get_epiphany_finvalidflag" sdtmp))
+ (set bvsbit (or bvsbit bvbit))
+ (set busbit (or busbit bubit))
+ (set bisbit (or bisbit bibit))
+ (set rd sdtmp)
+ (if (or (and invExcEnbit bisbit)
+ (or (and ovfExcEnbit bvsbit) (and unExcEnbit busbit)))
+ (sequence ()
+ (set expcause0bit (const 1))
+ (set expcause1bit (const 1))
+ (call-exception #x4 #x2)))
+ ))
+ (if (eq arithmetic-modebit2 1)
+ (sequence ((SI sdtmp))
+ (set sdtmp (c-call SI (.str "epiphany_i" name) rd rn rm))
+ ;; carry is not connected inb the design (set bcbit bcbit)
+ (set bzbit (zflag sdtmp))
+ (set bnbit (nflag sdtmp))
+ (set rd sdtmp)))
+ )
+
+ ()
+ )
+ (dnmi (.sym "i_" name "f16")
+ (.str "i_" name)
+ (SHORT-INSN NO-DIS)
+ (.str "i" name " $rd,$rn,$rm")
+ (emit (.sym "f_" name "f16") rd rn rm)
+ )
+
+
+ (dni_wrapper
+ (.sym "f_" name "f32")
+ (.str "f_" name)
+ ()
+ (.str "f" name " $rd6,$rn6,$rm6")
+ (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rm6)
+ (sequence ()
+ (if
+ (eq arithmetic-modebit2 0)
+ (sequence ((SF fptemp) (SI sdtmp))
+ (set sdtmp (c-call SI (.str "epiphany_f" name) rd6 rn6 rm6))
+
+ ;;All bits are calculated in C
+ (set bzbit (c-call BI "get_epiphany_fzeroflag" sdtmp))
+ (set bnbit (c-call BI "get_epiphany_fnegativeflag" sdtmp))
+ (set bvbit (c-call BI "get_epiphany_foverflowflag" sdtmp))
+ (set bubit (c-call BI "get_epiphany_funderflowflag" sdtmp))
+ (set bibit (c-call BI "get_epiphany_finvalidflag" sdtmp))
+ (set bvsbit (or bvsbit bvbit))
+ (set busbit (or busbit bubit))
+ (set bisbit (or bisbit bibit))
+
+ (set rd6 sdtmp)
+
+ (if (or (and invExcEnbit bisbit)
+ (or (and ovfExcEnbit bvsbit) (and unExcEnbit busbit)))
+ (sequence ()
+ (set expcause0bit (const 1))
+ (set expcause1bit (const 1))
+ (call-exception #x4 #x2)))
+ )
+ )
+ (if (eq arithmetic-modebit2 1)
+ (sequence ((SI sdtmp))
+ (set sdtmp (c-call SI (.str "epiphany_i" name) rd6 rn6 rm6))
+ ;; carry is not connected inb the design (set bcbit bcbit)
+ (set bzbit (zflag sdtmp))
+ (set bnbit (nflag sdtmp))
+ (set rd6 sdtmp)
+ )
+ )
+ )
+ ()
+ )
+
+ (dnmi (.sym "f_" name "f32.l")
+ (.str "f_" name)
+ ()
+ (.str "f" name ".l $rd6,$rn6,$rm6")
+ (emit (.sym "f_" name "f32") rd6 rn6 rm6)
+ )
+ (dnmi (.sym "i_" name "f32")
+ (.str "i_" name)
+ (NO-DIS)
+ (.str "i" name " $rd6,$rn6,$rm6")
+ (emit (.sym "f_" name "f32") rd6 rn6 rm6)
+ )
+ (dnmi (.sym "i_" name "f32.l")
+ (.str "i_" name)
+ (NO-DIS)
+ (.str "i" name ".l $rd6,$rn6,$rm6")
+ (emit (.sym "f_" name "f32") rd6 rn6 rm6)
+ )
+
+
+
+ )
+ )
+
+(op-two_operands-float add OPF_ADD)
+(op-two_operands-float sub OPF_SUB)
+(op-two_operands-float mul OPF_MUL)
+(op-two_operands-float madd OPF_MADD)
+(op-two_operands-float msub OPF_MSUB)
+
+;; ONE operands
+;; FABS
+(define-pmacro (op-fabs-float name code)
+ (begin
+ (dni_wrapper (.sym "f_" name "f16")
+ (.str "f_" name)
+ (SHORT-INSN)
+ (.str "f" name " rd,rn")
+ (+ OP4_DSP16 code rd rn rn)
+ (sequence ((SF fptemp) (SI sdtmp))
+
+ ;(set sdtmp (and rn #x7fffffff))
+ (set sdtmp (c-call SI (.str "epiphany_fabs") rd rn rn))
+
+
+ (set bnbit (const SI 0))
+ (set bzbit (eq SI sdtmp (const SI 0)))
+
+ ;;TODO subnormal ??
+ (set bvsbit (or bvsbit bvbit))
+ (set busbit (or busbit bubit))
+ (set bisbit (or bisbit bibit))
+
+ (set rd sdtmp)
+ )
+ ()
+ )
+
+ (dni_wrapper (.sym "f_" name "f32")
+ (.str "f_" name)
+ ()
+ (.str "f" name " $rd6,$rn6")
+ (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rn6)
+ (sequence ((SF fptemp) (SI sdtmp))
+
+
+ ;(set sdtmp (and rn6 #x7fffffff))
+
+ (set sdtmp (c-call SI (.str "epiphany_fabs") rd6 rn6 rn6))
+
+
+ (set bnbit (const SI 0))
+ (set bzbit (eq SI sdtmp (const SI 0)))
+
+ (set bvsbit (or bvsbit bvbit))
+ (set busbit (or busbit bubit))
+ (set bisbit (or bisbit bibit))
+
+ (set rd6 sdtmp)
+
+ )
+ ()
+ )
+
+ (dnmi (.sym "f_" name "f32.l")
+ (.str "f_" name)
+ ()
+ (.str "f" name ".l $rd6,$rn6")
+ (emit (.sym "f_" name "f32") rd6 rn6)
+ )
+
+
+ )
+ )
+
+(op-fabs-float abs OPF_FABS)
+
+
+(define-pmacro (op-fix2float-float name code)
+ (begin
+ (dni_wrapper (.sym "f_" name "f16")
+ (.str "f_" name)
+ (SHORT-INSN)
+ (.str "f" name " $rd,$rn")
+ (+ OP4_DSP16 code frd frn frn)
+ (sequence ((SF fptemp) (SI sdtmp))
+
+ (set sdtmp (c-call SI (.str "epiphany_f" name) rd rn rn))
+
+ (set bnbit (lt SI sdtmp (const SI 0)))
+ (set bzbit (eq SI sdtmp (const SI 0)))
+
+ (set bvsbit (or bvsbit bvbit))
+ (set busbit (or busbit bubit))
+ (set bisbit (or bisbit bibit))
+
+ (set rd sdtmp)
+ )
+ ()
+ )
+
+
+ (dni_wrapper (.sym "f_" name "f32")
+ (.str "f_" name)
+ ()
+ (.str "f" name " $rd6,$rn6")
+ (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rn6)
+ (sequence ((SF fptemp) (SI sdtmp))
+
+ (set sdtmp (c-call SI (.str "epiphany_f" name) rd6 rn6 rn6))
+
+ (set bnbit (lt SI sdtmp (const SI 0)))
+ (set bzbit (eq SI sdtmp (const SI 0)))
+
+ (set bvsbit (or bvsbit bvbit))
+ (set busbit (or busbit bubit))
+ (set bisbit (or bisbit bibit))
+
+ (set rd6 sdtmp)
+
+ )
+ ()
+ )
+
+ (dnmi (.sym "f_" name "f32.l")
+ (.str "f_" name)
+ ()
+ (.str "f" name ".l $rd6,$rn6")
+ (emit (.sym "f_" name "f32") rd6 rn6)
+ )
+ )
+ )
+
+(op-fix2float-float loat OPF_FLOAT)
+
+(define-pmacro (op-float2fix-float name code)
+ (begin
+ (dni_wrapper (.sym "f_" name "f16")
+ (.str "f_" name)
+ (SHORT-INSN)
+ (.str "f" name " $rd,$rn")
+ (+ OP4_DSP16 code rd rn rn)
+ (sequence ((SF fptemp) (SI sdtmp))
+
+ (set sdtmp (c-call SI (.str "epiphany_f" name) rd rn rn))
+
+ (set bzbit (zflag sdtmp))
+ (set bnbit (nflag sdtmp))
+
+ (set bvbit (c-call BI "get_epiphany_foverflowflag" sdtmp))
+ (set bubit (c-call BI "get_epiphany_funderflowflag" sdtmp))
+ (set bibit (c-call BI "get_epiphany_finvalidflag" sdtmp))
+
+ (set bvsbit (or bvsbit bvbit))
+ (set busbit (or busbit bubit))
+ (set bisbit (or bisbit bibit))
+
+ (set rd6 sdtmp)
+
+ (if (or (and invExcEnbit bisbit)
+ (or (and ovfExcEnbit busbit)
+ (and unExcEnbit bvsbit)))
+ (sequence ()
+ (set expcause0bit (const 1))
+ (set expcause1bit (const 1))
+ (call-exception #x4 #x2)))
+ (set rd sdtmp)
+ )
+ ()
+ )
+
+
+
+ (dni_wrapper (.sym "f_" name "f32")
+ (.str "f_" name)
+ ()
+ (.str "f" name " $rd6,$rn6")
+ (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rn6)
+ (sequence ((SF fptemp) (SI sdtmp))
+
+ (set sdtmp (c-call SI (.str "epiphany_f" name) rd6 rn6 rm6))
+
+ (set bzbit (zflag sdtmp))
+ (set bnbit (nflag sdtmp))
+
+ (set bvbit (c-call BI "get_epiphany_foverflowflag" sdtmp))
+ (set bubit (c-call BI "get_epiphany_funderflowflag" sdtmp))
+ (set bibit (c-call BI "get_epiphany_finvalidflag" sdtmp))
+
+ (set bvsbit (or bvsbit bvbit))
+ (set busbit (or busbit bubit))
+ (set bisbit (or bisbit bibit))
+
+ (set rd6 sdtmp)
+
+ (if (or (and invExcEnbit bisbit)
+ (or (and ovfExcEnbit busbit)
+ (and unExcEnbit bvsbit)))
+ (sequence ()
+ (set expcause0bit (const 1))
+ (set expcause1bit (const 1))
+ (call-exception #x4 #x2))
+ )
+
+ )
+ ()
+ )
+
+ (dnmi (.sym "f_" name "f32.l")
+ (.str "f_" name)
+ ()
+ (.str "f" name ".l $rd6,$rn6")
+ (emit (.sym "f_" name "f32") rd6 rn6)
+ )
+
+
+ )
+ )
+
+
+
+
+
+(op-float2fix-float ix OPF_FIX)
+
+;; MAC (Multiply and Accumulate Instructions
+;; (define-pmacro (op-mac-float name code)
+;; (begin
+;; (dni_wrapper (.sym "fm" name "f16")
+;; (.str "fm" name)
+;; (SHORT-INSN)
+;; (.str "fm" name " $frd,$frn,$frm")
+;; (+ OP4_DSP16 code frd frn frm)
+;; (sequence ((SF fptemp))
+;; (set bvbit 0)
+;; (set busbit 0)
+;; (set fptemp (c-call SF (.str "epiphany_fm" name) frd frm frn))
+;; (set bnbit (lt SF fptemp (const SF 0)))
+;; (set bzbit (eq SF fptemp (const SF 0)))
+;; (set bvsbit (or bvsbit bvbit))
+;; (set frd fptemp)
+;; ; (set rd (subword SI frd 0))
+;; )
+;; ()
+;; )
+
+;; (dni_wrapper (.sym "fm" name "f32")
+;; (.str "fm" name)
+;; ()
+;; (.str "fm" name " $frd6,$frn6,$frm6")
+;; (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) frd6 frn6 frm6)
+;; (sequence ((SF fptemp))
+;; (set bvbit 0)
+;; (set busbit 0)
+;; (set fptemp (c-call SF (.str "epiphany_fm" name) frd6 frm6 frn6))
+;; (set bnbit (lt SF fptemp (const SF 0)))
+;; (set bzbit (eq SF fptemp (const SF 0)))
+;; (set bvsbit (or bvsbit bvbit))
+;; (set frd6 fptemp)
+;; ; (set rd6 (subword SI frd6 0))
+;; )
+;; ()
+;; )
+;; )
+;; )
+
+
+
+
+
+
+
+ ; extended floating point operation
+
+
+(define-pmacro (op-fextop-float name code)
+ (begin
+
+ (dni_wrapper (.sym "f_" name "f32")
+ (.str "f_" name)
+ ()
+ (.str "f" name " $frd6,$frn6")
+ (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-2 #x0) (f-dc-20-1 #x1) frd6 frn6 frn6)
+ (sequence ((SF fptemp))
+ (set bvbit 0)
+ (set busbit 0)
+ (set fptemp (c-call SF (.str "epiphany_f" name) frn6))
+ (set bnbit (lt SF fptemp (const SF 0)))
+ (set bzbit (eq SF fptemp (const SF 0)))
+ (set bvsbit (or bvsbit bvbit))
+ (set frd6 fptemp)
+
+ )
+ ()
+ )
+
+
+ (dnmi (.sym "f_" name "f32.l")
+ (.str "f_" name)
+ ()
+ (.str "f" name ".l $frd6,$frn6")
+ (emit (.sym "f_" name "f32") frd6 frn6)
+ )
+ )
+ )
+
+(op-fextop-float recip OPF_FRECIP)
+(op-fextop-float sqrt OPF_FSQRT)
+
+
+
+
+
--- /dev/null
+/* Adapteva epiphany opcode support. -*- C -*-
+
+ Copyright 2011 Free Software Foundation, Inc.
+
+ Contributed by Embecosm on behalf of Adapteva, Inc.
+
+ This file is part of the GNU Binutils and of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+/*
+ Each section is delimited with start and end markers.
+
+ <arch>-opc.h additions use: "-- opc.h"
+ <arch>-opc.c additions use: "-- opc.c"
+ <arch>-asm.c additions use: "-- asm.c"
+ <arch>-dis.c additions use: "-- dis.c"
+ <arch>-ibd.h additions use: "-- ibd.h". */
+\f
+/* -- opc.h */
+
+/* enumerate relaxation types for gas. */
+typedef enum epiphany_relax_types
+{
+ EPIPHANY_RELAX_NONE=0,
+ EPIPHANY_RELAX_NEED_RELAXING,
+
+ EPIPHANY_RELAX_BRANCH_SHORT, /* Fits into +127..-128 */
+ EPIPHANY_RELAX_BRANCH_LONG, /* b/bl/b<cond> +-2*16 */
+
+ EPIPHANY_RELAX_ARITH_SIMM3, /* add/sub -7..3 */
+ EPIPHANY_RELAX_ARITH_SIMM11, /* add/sub -2**11-1 .. 2**10-1 */
+
+ EPIPHANY_RELAX_MOV_IMM8, /* mov r,imm8 */
+ EPIPHANY_RELAX_MOV_IMM16, /* mov r,imm16 */
+
+ EPIPHANY_RELAX_LDST_IMM3, /* (ldr|str)* r,[r,disp3] */
+ EPIPHANY_RELAX_LDST_IMM11 /* (ldr|str)* r,[r,disp11] */
+
+} EPIPHANY_RELAX_TYPES;
+
+/* Override disassembly hashing... */
+
+/* Can only depend on instruction having 4 decode bits which gets us to the
+ major groups of 16/32 instructions. */
+#undef CGEN_DIS_HASH_SIZE
+#if 1
+
+/* hash code on the 4 LSBs */
+#define CGEN_DIS_HASH_SIZE 16
+
+#define CGEN_DIS_HASH(buf, value) ((*buf) & 0xf)
+#else
+#define CGEN_DIS_HASH_SIZE 1
+#define CGEN_DIS_HASH(buf, value) 0
+#endif
+
+extern const char * parse_shortregs (CGEN_CPU_DESC cd,
+ const char ** strp,
+ CGEN_KEYWORD * keywords,
+ long * valuep);
+
+extern const char * parse_branch_addr (CGEN_CPU_DESC cd,
+ const char ** strp,
+ int opindex,
+ int opinfo,
+ enum cgen_parse_operand_result * resultp,
+ unsigned long * valuep);
+
+/* Allows reason codes to be output when assembler errors occur. */
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+
+\f
+/* -- opc.c */
+
+
+\f
+/* -- asm.c */
+const char *
+parse_shortregs (CGEN_CPU_DESC cd,
+ const char ** strp,
+ CGEN_KEYWORD * keywords,
+ long * regno)
+{
+ const char * errmsg;
+
+ /* Parse register. */
+ errmsg = cgen_parse_keyword (cd, strp, keywords, regno);
+
+ if (errmsg)
+ return errmsg;
+
+ if (*regno > 7)
+ errmsg = _("register unavailable for short instructions");
+
+ return errmsg;
+}
+
+static const char * parse_simm_not_reg (CGEN_CPU_DESC, const char **, int,
+ long *);
+
+static const char *
+parse_uimm_not_reg (CGEN_CPU_DESC cd,
+ const char ** strp,
+ int opindex,
+ unsigned long * valuep)
+{
+ long * svalp = (void *) valuep;
+ return parse_simm_not_reg (cd, strp, opindex, svalp);
+}
+
+/* Handle simm3/simm11/imm3/imm12. */
+
+static const char *
+parse_simm_not_reg (CGEN_CPU_DESC cd,
+ const char ** strp,
+ int opindex,
+ long * valuep)
+{
+ const char * errmsg;
+
+ int sign = 0;
+ int bits = 0;
+
+ switch (opindex)
+ {
+ case EPIPHANY_OPERAND_SIMM3:
+ sign = 1; bits = 3; break;
+ case EPIPHANY_OPERAND_SIMM11:
+ sign = 1; bits = 11; break;
+ case EPIPHANY_OPERAND_DISP3:
+ sign = 0; bits = 3; break;
+ case EPIPHANY_OPERAND_DISP11:
+ /* Load/store displacement is a sign-magnitude 12 bit value. */
+ sign = 0; bits = 11; break;
+ }
+
+ /* First try to parse as a register name and reject the operand. */
+ errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names,valuep);
+ if (!errmsg)
+ return _("register name used as immediate value");
+
+ errmsg = (sign ? cgen_parse_signed_integer (cd, strp, opindex, valuep)
+ : cgen_parse_unsigned_integer (cd, strp, opindex,
+ (unsigned long *) valuep));
+ if (errmsg)
+ return errmsg;
+
+ if (sign)
+ errmsg = cgen_validate_signed_integer (*valuep,
+ -((1L << bits) - 1), (1 << (bits - 1)) - 1);
+ else
+ errmsg = cgen_validate_unsigned_integer (*valuep, 0, (1L << bits) - 1);
+
+ return errmsg;
+}
+
+static const char *
+parse_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ const char ** strp,
+ int opindex ATTRIBUTE_UNUSED,
+ bfd_vma * valuep)
+{
+ if (**strp == '#')
+ ++*strp; /* Skip leading hashes. */
+
+ if (**strp == '-')
+ {
+ *valuep = 1;
+ ++*strp;
+ }
+ else if (**strp == '+')
+ {
+ *valuep = 0;
+ ++*strp;
+ }
+ else
+ *valuep = 0;
+
+ return NULL;
+}
+
+static const char *
+parse_imm8 (CGEN_CPU_DESC cd,
+ const char ** strp,
+ int opindex,
+ bfd_reloc_code_real_type code,
+ enum cgen_parse_operand_result * result_type,
+ bfd_vma * valuep)
+{
+ const char * errmsg;
+ enum cgen_parse_operand_result rt;
+ long dummyval;
+
+ if (!result_type)
+ result_type = &rt;
+
+ code = BFD_RELOC_NONE;
+
+ if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names, &dummyval)
+ || !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names,
+ &dummyval))
+ /* Don't treat "mov ip,ip" as a move-immediate. */
+ return _("register source in immediate move");
+
+ errmsg = cgen_parse_address (cd, strp, opindex, code, result_type, valuep);
+ if (errmsg)
+ return errmsg;
+
+ if (*result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xff);
+ else
+ errmsg = _("byte relocation unsupported");
+
+ *valuep &= 0xff;
+ return errmsg;
+}
+
+static const char * MISSING_CLOSE_PARENTHESIS = N_("missing `)'");
+
+static const char *
+parse_imm16 (CGEN_CPU_DESC cd,
+ const char ** strp,
+ int opindex,
+ bfd_reloc_code_real_type code ATTRIBUTE_UNUSED,
+ enum cgen_parse_operand_result * result_type,
+ bfd_vma * valuep)
+{
+ const char * errmsg;
+ enum cgen_parse_operand_result rt;
+ long dummyval;
+
+ if (!result_type)
+ result_type = &rt;
+
+ if (strncasecmp (*strp, "%high(", 6) == 0)
+ {
+ *strp += 6;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_HIGH,
+ result_type, valuep);
+ if (**strp != ')')
+ return MISSING_CLOSE_PARENTHESIS;
+ ++*strp;
+ *valuep >>= 16;
+ }
+ else if (strncasecmp (*strp, "%low(", 5) == 0)
+ {
+ *strp += 5;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_LOW,
+ result_type, valuep);
+ if (**strp != ')')
+ return MISSING_CLOSE_PARENTHESIS;
+ ++*strp;
+ }
+ else if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names,
+ &dummyval)
+ || !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names,
+ &dummyval))
+ /* Don't treat "mov ip,ip" as a move-immediate. */
+ return _("register source in immediate move");
+ else
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16,
+ result_type, valuep);
+
+ if (!errmsg && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xffff);
+
+ *valuep &= 0xffff;
+ return errmsg;
+}
+
+const char *
+parse_branch_addr (CGEN_CPU_DESC cd,
+ const char ** strp,
+ int opindex,
+ int opinfo ATTRIBUTE_UNUSED,
+ enum cgen_parse_operand_result * resultp ATTRIBUTE_UNUSED,
+ unsigned long * valuep ATTRIBUTE_UNUSED)
+{
+ const char * errmsg;
+ enum cgen_parse_operand_result result_type;
+ bfd_reloc_code_real_type code = BFD_RELOC_NONE;
+ bfd_vma value;
+
+ switch (opindex)
+ {
+ case EPIPHANY_OPERAND_SIMM24:
+ code = BFD_RELOC_EPIPHANY_SIMM24;
+ break;
+
+ case EPIPHANY_OPERAND_SIMM8:
+ code = BFD_RELOC_EPIPHANY_SIMM8;
+ break;
+
+ default:
+ errmsg = _("ABORT: unknown operand");
+ return errmsg;
+ }
+
+ errmsg = cgen_parse_address (cd, strp, opindex, code,
+ &result_type, &value);
+ if (errmsg == NULL)
+ {
+ if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ {
+ /* Act as if we had done a PC-relative branch, ala .+num. */
+ char buf[20];
+ const char * bufp = (const char *) buf;
+
+ sprintf (buf, ".+%ld", value);
+ errmsg = cgen_parse_address (cd, &bufp, opindex, code, &result_type,
+ &value);
+ }
+
+ if (result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED)
+ {
+ /* This will happen for things like (s2-s1) where s2 and s1
+ are labels. */
+ /* Nothing further to be done. */
+ }
+ else
+ errmsg = _("Not a pc-relative address.");
+ }
+ return errmsg;
+}
+\f
+/* -- dis.c */
+
+#define CGEN_PRINT_INSN epiphany_print_insn
+
+static int
+epiphany_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
+{
+ bfd_byte buf[CGEN_MAX_INSN_SIZE];
+ int buflen;
+ int status;
+
+ info->bytes_per_chunk = 2;
+
+ /* Attempt to read the base part of the insn. */
+ info->bytes_per_line = buflen = cd->base_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+
+ /* Try again with the minimum part, if min < base. */
+ if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
+ {
+ info->bytes_per_line = buflen = cd->min_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+ }
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ return print_insn (cd, pc, info, buf, buflen);
+}
+
+
+static void
+print_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void * dis_info,
+ long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+ (*info->fprintf_func) (info->stream, value ? "-" : "+");
+}
+
+static void
+print_simm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void * dis_info,
+ long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ print_address (cd, dis_info, value, attrs, pc, length);
+}
+
+static void
+print_uimm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void * dis_info,
+ unsigned long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *)dis_info;
+
+ if (value & 0x800)
+ (*info->fprintf_func) (info->stream, "-");
+
+ value &= 0x7ff;
+ print_address (cd, dis_info, value, attrs, pc, length);
+}
+
+\f
+/* -- */
+
+2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
+
+ * NEWS: Mention addition of Adapteva Epiphany support.
+ * config/tc-epiphany.c: New file.
+ * config/tc-epiphany.h: New file.
+ * Makefile.am (TARGET_CPU_CFILES): Add config/tc-epiphany.c .
+ (TARGET_CPU_HFILES): Add config/tc-epiphany.h .
+ * configure.in: Also set using_cgen for epiphany.
+ * configure.tgt: Handle epiphany.
+ * doc/Makefile.am (CPU_DOCS): Add c-epiphany.texi .
+ * doc/all.texi: Set EPIPHANY.
+ * doc/as.texinfo: Add EPIPHANY-specific text.
+ * doc/c-epiphany.texi: New file.
+ * po/gas.pot: Regenerate.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+ * doc/Makefile.in: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
* config/tc-mips.c (move_register): Fix formatting.
config/tc-d10v.c \
config/tc-d30v.c \
config/tc-dlx.c \
+ config/tc-epiphany.c \
config/tc-fr30.c \
config/tc-frv.c \
config/tc-h8300.c \
config/tc-d10v.h \
config/tc-d30v.h \
config/tc-dlx.h \
+ config/tc-epiphany.h \
config/tc-fr30.h \
config/tc-frv.h \
config/tc-h8300.h \
config/tc-d10v.c \
config/tc-d30v.c \
config/tc-dlx.c \
+ config/tc-epiphany.c \
config/tc-fr30.c \
config/tc-frv.c \
config/tc-h8300.c \
config/tc-d10v.h \
config/tc-d30v.h \
config/tc-dlx.h \
+ config/tc-epiphany.h \
config/tc-fr30.h \
config/tc-frv.h \
config/tc-h8300.h \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-d10v.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-d30v.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-dlx.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-epiphany.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-fr30.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-frv.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-h8300.Po@am__quote@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-dlx.obj `if test -f 'config/tc-dlx.c'; then $(CYGPATH_W) 'config/tc-dlx.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-dlx.c'; fi`
+tc-epiphany.o: config/tc-epiphany.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-epiphany.o -MD -MP -MF $(DEPDIR)/tc-epiphany.Tpo -c -o tc-epiphany.o `test -f 'config/tc-epiphany.c' || echo '$(srcdir)/'`config/tc-epiphany.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-epiphany.Tpo $(DEPDIR)/tc-epiphany.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-epiphany.c' object='tc-epiphany.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-epiphany.o `test -f 'config/tc-epiphany.c' || echo '$(srcdir)/'`config/tc-epiphany.c
+
+tc-epiphany.obj: config/tc-epiphany.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-epiphany.obj -MD -MP -MF $(DEPDIR)/tc-epiphany.Tpo -c -o tc-epiphany.obj `if test -f 'config/tc-epiphany.c'; then $(CYGPATH_W) 'config/tc-epiphany.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-epiphany.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-epiphany.Tpo $(DEPDIR)/tc-epiphany.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-epiphany.c' object='tc-epiphany.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-epiphany.obj `if test -f 'config/tc-epiphany.c'; then $(CYGPATH_W) 'config/tc-epiphany.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-epiphany.c'; fi`
+
tc-fr30.o: config/tc-fr30.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-fr30.o -MD -MP -MF $(DEPDIR)/tc-fr30.Tpo -c -o tc-fr30.o `test -f 'config/tc-fr30.c' || echo '$(srcdir)/'`config/tc-fr30.c
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-fr30.Tpo $(DEPDIR)/tc-fr30.Po
-*- text -*-
+* Add support for the Adapteva EPIPHANY architecture.
+
Changes in 2.22:
* Add support for the Tilera TILEPRO and TILE-Gx architectures.
--- /dev/null
+/* tc-epiphany.c -- Assembler for the Adapteva EPIPHANY
+ Copyright 2011 Free Software Foundation, Inc.
+ Contributed by Embecosm on behalf of Adapteva, Inc.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to
+ the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+#include "as.h"
+#include "subsegs.h"
+#include "symcat.h"
+#include "opcodes/epiphany-desc.h"
+#include "opcodes/epiphany-opc.h"
+#include "cgen.h"
+#include "elf/common.h"
+#include "elf/epiphany.h"
+#include "dwarf2dbg.h"
+#include "libbfd.h"
+
+/* Structure to hold all of the different components describing
+ an individual instruction. */
+typedef struct
+{
+ const CGEN_INSN * insn;
+ const CGEN_INSN * orig_insn;
+ CGEN_FIELDS fields;
+#if CGEN_INT_INSN_P
+ CGEN_INSN_INT buffer [1];
+#define INSN_VALUE(buf) (*(buf))
+#else
+ unsigned char buffer [CGEN_MAX_INSN_SIZE];
+#define INSN_VALUE(buf) (buf)
+#endif
+ char * addr;
+ fragS * frag;
+ int num_fixups;
+ fixS * fixups [GAS_CGEN_MAX_FIXUPS];
+ int indices [MAX_OPERAND_INSTANCES];
+}
+epiphany_insn;
+
+const char comment_chars[] = ";";
+const char line_comment_chars[] = "#";
+const char line_separator_chars[] = "`";
+const char EXP_CHARS[] = "eE";
+const char FLT_CHARS[] = "fFdD";
+
+/* Flag to detect when switching to code section where insn alignment is
+ implied. */
+static bfd_boolean force_code_align = FALSE;
+
+static void
+epiphany_elf_section_rtn (int i)
+{
+ obj_elf_section (i);
+
+ if (force_code_align)
+ {
+ /* The s_align_ptwo function expects that we are just after a .align
+ directive and it will either try and read the align value or stop
+ if end of line so we must fake it out so it thinks we are at the
+ end of the line. */
+ char *old_input_line_pointer = input_line_pointer;
+
+ input_line_pointer = "\n";
+ s_align_ptwo (1);
+ force_code_align = FALSE;
+
+ /* Restore. */
+ input_line_pointer = old_input_line_pointer;
+ }
+}
+
+static void
+epiphany_elf_section_text (int i)
+{
+ char *old_input_line_pointer;
+
+ obj_elf_text (i);
+
+ /* The s_align_ptwo function expects that we are just after a .align
+ directive and it will either try and read the align value or stop if
+ end of line so we must fake it out so it thinks we are at the end of
+ the line. */
+ old_input_line_pointer = input_line_pointer;
+ input_line_pointer = "\n";
+ s_align_ptwo (1);
+ force_code_align = FALSE;
+ /* Restore. */
+ input_line_pointer = old_input_line_pointer;
+}
+
+/* The target specific pseudo-ops which we support. */
+const pseudo_typeS md_pseudo_table[] =
+{
+ { "text", epiphany_elf_section_text, 0 },
+ { "sect", epiphany_elf_section_rtn, 0 },
+ /* .word should be 32 bits. */
+ { "word", cons, 4 },
+ { "cpu", s_ignore, 0 },
+ { "thumb_func", s_ignore, 0 },
+ { "code", s_ignore, 0 },
+ { NULL, NULL, 0 }
+};
+
+\f
+
+enum options
+{
+ OPTION_CPU_EPIPHANY = OPTION_MD_BASE,
+ OPTION_CPU_EPIPHANY16
+};
+
+struct option md_longopts[] =
+{
+ { "mepiphany ", no_argument, NULL, OPTION_CPU_EPIPHANY },
+ { "mepiphany16", no_argument, NULL, OPTION_CPU_EPIPHANY16 },
+ { NULL, no_argument, NULL, 0 },
+};
+
+size_t md_longopts_size = sizeof (md_longopts);
+
+const char * md_shortopts = "";
+
+int
+md_parse_option (int c ATTRIBUTE_UNUSED, char * arg ATTRIBUTE_UNUSED)
+{
+ return 0; /* No target-specific options. */
+}
+
+void
+md_show_usage (FILE * stream)
+{
+ fprintf (stream, _("EPIPHANY specific command line options:\n"));
+}
+
+\f
+void
+md_begin (void)
+{
+ /* Initialize the `cgen' interface. */
+
+ /* Set the machine number and endian. */
+ gas_cgen_cpu_desc = epiphany_cgen_cpu_open (CGEN_CPU_OPEN_MACHS,
+ bfd_mach_epiphany32,
+ CGEN_CPU_OPEN_ENDIAN,
+ CGEN_ENDIAN_LITTLE,
+ CGEN_CPU_OPEN_END);
+ epiphany_cgen_init_asm (gas_cgen_cpu_desc);
+
+ /* This is a callback from cgen to gas to parse operands. */
+ cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
+
+ /* Set the machine type. */
+ bfd_default_set_arch_mach (stdoutput, bfd_arch_epiphany, bfd_mach_epiphany32);
+}
+
+valueT
+md_section_align (segT segment, valueT size)
+{
+ int align = bfd_get_section_alignment (stdoutput, segment);
+
+ return ((size + (1 << align) - 1) & (-1 << align));
+}
+
+\f
+/* Functions concerning relocs. */
+
+long
+md_pcrel_from (fixS *fixP ATTRIBUTE_UNUSED)
+{
+ abort ();
+}
+
+/* Write a value out to the object file, using the appropriate endianness. */
+
+void
+md_number_to_chars (char * buf, valueT val, int n)
+{
+ number_to_chars_littleendian (buf, val, n);
+}
+
+int
+epiphany_elf_section_flags (int flags,
+ int attr ATTRIBUTE_UNUSED,
+ int type ATTRIBUTE_UNUSED)
+{
+ /* This is used to detect when the section changes to an executable section.
+ This function is called by the elf section processing. When we note an
+ executable section specifier we set an internal flag to denote when
+ word alignment should be forced. */
+ if (flags & SEC_CODE)
+ force_code_align = TRUE;
+
+ return flags;
+}
+
+/* Non-zero if we are generating PIC code. */
+int pic_code;
+
+/* Epiphany er_flags. */
+static int epiphany_flags = 0;
+
+/* Relocations against symbols are done in two
+ parts, with a HI relocation and a LO relocation. Each relocation
+ has only 16 bits of space to store an addend. This means that in
+ order for the linker to handle carries correctly, it must be able
+ to locate both the HI and the LO relocation. This means that the
+ relocations must appear in order in the relocation table.
+
+ In order to implement this, we keep track of each unmatched HI
+ relocation. We then sort them so that they immediately precede the
+ corresponding LO relocation. */
+
+struct epiphany_hi_fixup
+{
+ /* Next HI fixup. */
+ struct epiphany_hi_fixup *next;
+
+ /* This fixup. */
+ fixS *fixp;
+
+ /* The section this fixup is in. */
+ segT seg;
+};
+
+\f
+#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
+static symbolS * GOT_symbol;
+
+static inline bfd_boolean
+epiphany_PIC_related_p (symbolS *sym)
+{
+ expressionS *exp;
+
+ if (! sym)
+ return FALSE;
+
+ if (sym == GOT_symbol)
+ return TRUE;
+
+ exp = symbol_get_value_expression (sym);
+
+ return (exp->X_op == O_PIC_reloc
+ || exp->X_md == BFD_RELOC_EPIPHANY_SIMM24
+ || exp->X_md == BFD_RELOC_EPIPHANY_SIMM8
+ || epiphany_PIC_related_p (exp->X_add_symbol)
+ || epiphany_PIC_related_p (exp->X_op_symbol));
+}
+
+/* Perform target dependent relocations that are done at compile time.
+ There aren't very many of these. */
+
+void
+epiphany_apply_fix (fixS *fixP, valueT *valP, segT seg)
+{
+ if (fixP->fx_addsy == (symbolS *) NULL)
+ fixP->fx_done = 1;
+
+ if (((int) fixP->fx_r_type < (int) BFD_RELOC_UNUSED)
+ && fixP->fx_done)
+ {
+ /* Install EPIPHANY-dependent relocations HERE because nobody else
+ will. */
+ char *where = fixP->fx_frag->fr_literal + fixP->fx_where;
+ unsigned char *insn = (unsigned char *)where;
+ valueT value = * valP;
+
+ switch (fixP->fx_r_type)
+ {
+ default:
+ break;
+
+ case BFD_RELOC_NONE:
+ return;
+
+ case BFD_RELOC_EPIPHANY_SIMM11:
+ where[0] = where[0] | ((value & 1) << 7);
+ where[1] = where[1] | ((value & 6) >> 1);
+ where[2] = (value >> 3) & 0xff;
+ return;
+
+ case BFD_RELOC_EPIPHANY_IMM11:
+ where[0] = where[0] | ((value & 1) << 7);
+ where[1] = where[1] | ((value & 6) >> 1);
+ where[2] = (value >> 3) & 0xff;
+ return;
+
+ case BFD_RELOC_EPIPHANY_SIMM8:
+ md_number_to_chars (where+1, value>>1, 1);
+ return;
+
+ case BFD_RELOC_EPIPHANY_SIMM24:
+ md_number_to_chars (where+1, value>>1, 3);
+ return;
+
+ case BFD_RELOC_EPIPHANY_HIGH:
+ value >>= 16;
+ /* fall thru */
+ case BFD_RELOC_EPIPHANY_LOW:
+ value = (((value & 0xff) << 5) | insn[0])
+ | (insn[1] << 8)
+ | ((value & 0xff00) << 12)
+ | (insn[2] << 16);
+ md_number_to_chars (where, value, 3);
+ return;
+ }
+ }
+
+ /* Just do the default if we can't special case. */
+ return gas_cgen_md_apply_fix (fixP, valP, seg);
+}
+
+
+/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
+ of an rs_align_code fragment. 0x01a2 is 16-bit pattern for a "nop". */
+
+static const unsigned char nop_pattern[] = { 0xa2, 0x01 };
+
+void
+epiphany_handle_align (fragS *fragp)
+{
+ int bytes, fix;
+ char *p;
+
+ if (fragp->fr_type != rs_align_code)
+ return;
+
+ bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
+ p = fragp->fr_literal + fragp->fr_fix;
+ fix = 0;
+
+ if (bytes & 1)
+ {
+ fix = 1;
+ *p++ = 0;
+ bytes--;
+ }
+
+ if (bytes & 2)
+ {
+ memcpy (p, nop_pattern, 2);
+ p += 2;
+ bytes -= 2;
+ fix += 2;
+ }
+ fragp->fr_fix += fix;
+}
+\f
+/* Read a comma separated incrementing list of register names
+ and form a bit mask of upto 15 registers 0..14. */
+
+static const char *
+parse_reglist (const char * s, int * mask)
+{
+ int regmask = 0;
+
+ while (*s)
+ {
+ long value;
+
+ while (*s == ' ')
+ ++s;
+
+ /* Parse a list with "," or "}" as limiters. */
+ const char *errmsg
+ = cgen_parse_keyword (gas_cgen_cpu_desc, &s,
+ &epiphany_cgen_opval_gr_names, &value);
+ if (errmsg)
+ return errmsg;
+
+ if (value > 15)
+ return _("register number too large for push/pop");
+
+ regmask |= 1 << value;
+ if (regmask < *mask)
+ return _("register is out of order");
+ *mask |= regmask;
+
+ while (*s==' ')
+ ++s;
+
+ if (*s == '}')
+ return NULL;
+ else if (*s++ == ',')
+ continue;
+ else
+ return _("bad register list");
+ }
+
+ return _("malformed reglist in push/pop");
+}
+
+\f
+void
+md_assemble (char *str)
+{
+ epiphany_insn insn;
+ char *errmsg = 0;
+ const char * pperr = 0;
+ int regmask=0, push=0, pop=0;
+
+ memset (&insn, 0, sizeof (insn));
+
+ /* Special-case push/pop instruction macros. */
+ if (0 == strncmp (str, "push {", 6))
+ {
+ char * s = str + 6;
+ push = 1;
+ pperr = parse_reglist (s, ®mask);
+ }
+ else if (0 == strncmp (str, "pop {", 5))
+ {
+ char * s = str + 5;
+ pop = 1;
+ pperr = parse_reglist (s, ®mask);
+ }
+
+ if (pperr)
+ {
+ as_bad ("%s", pperr);
+ return;
+ }
+
+ if (push && regmask)
+ {
+ char buff[20];
+ int i,p ATTRIBUTE_UNUSED;
+
+ md_assemble ("mov r15,4");
+ md_assemble ("sub sp,sp,r15");
+
+ for (i = 0, p = 1; i <= 15; ++i, regmask >>= 1)
+ {
+ if (regmask == 1)
+ sprintf (buff, "str r%d,[sp]", i); /* Last one. */
+ else if (regmask & 1)
+ sprintf (buff, "str r%d,[sp],-r15", i);
+ else
+ continue;
+ md_assemble (buff);
+ }
+ return;
+ }
+ else if (pop && regmask)
+ {
+ char buff[20];
+ int i,p;
+
+ md_assemble ("mov r15,4");
+
+ for (i = 15, p = 1 << 15; i >= 0; --i, p >>= 1)
+ if (regmask & p)
+ {
+ sprintf (buff, "ldr r%d,[sp],+r15", i);
+ md_assemble (buff);
+ }
+ return;
+ }
+
+ /* Initialize GAS's cgen interface for a new instruction. */
+ gas_cgen_init_parse ();
+
+ insn.insn = epiphany_cgen_assemble_insn
+ (gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg);
+
+ if (!insn.insn)
+ {
+ as_bad ("%s", errmsg);
+ return;
+ }
+
+ if (CGEN_INSN_BITSIZE (insn.insn) == 32)
+ {
+ /* Doesn't really matter what we pass for RELAX_P here. */
+ gas_cgen_finish_insn (insn.insn, insn.buffer,
+ CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL);
+ }
+ else
+ {
+ if (CGEN_INSN_BITSIZE (insn.insn) != 16)
+ abort ();
+
+ insn.orig_insn = insn.insn;
+
+ gas_cgen_finish_insn (insn.orig_insn, insn.buffer,
+ CGEN_FIELDS_BITSIZE (&insn.fields),
+ 1 /* relax_p */, NULL);
+ }
+
+ /* Checks for behavioral restrictions on LD/ST instructions. */
+#define DISPMOD _("destination register modified by displacement-post-modified address")
+#define LDSTODD _("ldrd/strd requires even:odd register pair")
+
+ /* Helper macros for spliting apart instruction fields. */
+#define ADDR_POST_MODIFIED(i) (((i) >> 25) & 0x1)
+#define ADDR_SIZE(i) (((i) >> 5) & 3)
+#define ADDR_LOADSTORE(i) (((i) >> 4) & 0x1)
+
+ switch (insn.buffer[0] & 0xf)
+ {
+ /* Post-modify registers cannot be destinations. */
+ case OP4_LDSTR16P:
+ {
+ if (ADDR_LOADSTORE (insn.buffer[0]) == OP_LOAD)
+ if (insn.fields.f_rd == insn.fields.f_rn /* Postmodify dest. */
+ || (insn.fields.f_rd+1 == insn.fields.f_rn
+ && ADDR_SIZE (insn.buffer[0]) == OPW_DOUBLE))
+ {
+ as_bad ("%s", DISPMOD);
+ return;
+ }
+ if ((insn.fields.f_rd & 1) /* Odd-numbered register... */
+ && insn.fields.f_wordsize == OPW_DOUBLE) /* ...and 64 bit transfer. */
+ {
+ as_bad ("%s", LDSTODD);
+ return;
+ }
+ break;
+ }
+
+ case OP4_LDSTRP:
+ {
+ if (ADDR_LOADSTORE (insn.buffer[0]) == OP_LOAD) /* A load. */
+ if (insn.fields.f_rd6 == insn.fields.f_rn6 /* Postmodify dest. */
+ /* Check for regpair postindexed. */
+ || (insn.fields.f_rd6 + 1 == insn.fields.f_rn6
+ && ADDR_SIZE (insn.buffer[0]) == OPW_DOUBLE))
+ {
+ as_bad ("%s", DISPMOD);
+ return;
+ }
+ if ((insn.fields.f_rd6 & 1) && ADDR_SIZE (insn.buffer[0]) == OPW_DOUBLE)
+ /* Lsb of RD odd and 64 bit transfer. */
+ {
+ as_bad ("%s", LDSTODD);
+ return;
+ }
+ break;
+ }
+
+ case OP4_LDSTR16X:
+ case OP4_LDSTR16D:
+ {
+ /* Check for unaligned load/store double. */
+ if ((insn.fields.f_rd & 1) && ADDR_SIZE (insn.buffer[0]) == OPW_DOUBLE)
+ /* Lsb of RD odd and 64 bit transfer. */
+ {
+ as_bad ("%s", LDSTODD);
+ return;
+ }
+ break;
+ }
+
+ case OP4_LDSTRD:
+ {
+ /* Check for load to post-modified register. */
+ if (ADDR_LOADSTORE (insn.buffer[0]) == OP_LOAD /* A load. */
+ && ADDR_POST_MODIFIED (insn.buffer[0]) == PMOD_POST /* Post-mod. */
+ && (insn.fields.f_rd6 == insn.fields.f_rn6
+ || (insn.fields.f_rd6+1 == insn.fields.f_rn6
+ && ADDR_SIZE (insn.buffer[0]) == OPW_DOUBLE)))
+ {
+ as_bad ("%s", DISPMOD);
+ return;
+ }
+ }
+ /* fall-thru. */
+
+ case OP4_LDSTRX:
+ {
+ /* Check for unaligned load/store double. */
+ if ((insn.fields.f_rd6 & 1) && ADDR_SIZE (insn.buffer[0]) == OPW_DOUBLE)
+ {
+ as_bad ("%s", LDSTODD);
+ return;
+ }
+ break;
+ }
+
+ default:
+ break;
+ }
+}
+
+/* The syntax in the manual says constants begin with '#'.
+ We just ignore it. */
+
+void
+md_operand (expressionS *expressionP)
+{
+ if (*input_line_pointer == '#')
+ {
+ input_line_pointer++;
+ expression (expressionP);
+ }
+}
+
+symbolS *
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
+{
+ return NULL;
+}
+\f
+/* Interface to relax_segment. */
+
+/* FIXME: Build table by hand, get it working, then machine generate. */
+
+const relax_typeS md_relax_table[] =
+{
+ /* The fields are:
+ 1) most positive reach of this state,
+ 2) most negative reach of this state,
+ 3) how many bytes this mode will add to the size of the current frag
+ 4) which index into the table to try if we can't fit into this one. */
+
+ /* The first entry must be unused because an `rlx_more' value of zero ends
+ each list. */
+ {1, 1, 0, EPIPHANY_RELAX_NONE},
+ {0, 0, 0, EPIPHANY_RELAX_NONE}, /* Also a dummy entry to indicate we need to expand codes. */
+
+ /* The displacement used by GAS is from the end of the 2 byte insn,
+ so we subtract 2 from the following. */
+ /* 16 bit insn, 8 bit disp -> +127 words, -128 words. */
+ {0x00000100 - 1 - 2, -0x00000100 - 2, 0, EPIPHANY_RELAX_BRANCH_LONG },
+ /* 32 bit insn, 24 bit disp -> 25 bit range. */
+ {0x01000000 - 1 - 2, -0x01000000 - 2, 2, EPIPHANY_RELAX_NONE },
+
+ /* addi/subi 3 bits -4..+3. */
+ { 3, -4,0, EPIPHANY_RELAX_ARITH_SIMM11 },
+ /* addi/subi 11 bits. */
+ { 1023, -1024,2, EPIPHANY_RELAX_NONE },
+
+ /* mov r,imm8. */
+ { 255, 0,0, EPIPHANY_RELAX_MOV_IMM16 },
+ /* mov r,imm16. */
+ { 65535, 0,2, EPIPHANY_RELAX_NONE },
+
+ /* ld/st rd,[rn,imm3]. */
+ { 7, 0,0, EPIPHANY_RELAX_LDST_IMM11},
+ /* ld/st rd,[rn,imm11]. */
+ { 2047, 0,2, EPIPHANY_RELAX_NONE }
+
+};
+
+static const EPIPHANY_RELAX_TYPES relax_insn[] =
+{
+ EPIPHANY_RELAX_BRANCH_SHORT, /* OP4_BRANCH16 */
+ EPIPHANY_RELAX_NONE, /* OP4_LDSTR16X */
+ EPIPHANY_RELAX_NONE, /* OP4_FLOW16 */
+ EPIPHANY_RELAX_ARITH_SIMM3, /* OP4_IMM16 - special */
+ EPIPHANY_RELAX_LDST_IMM3, /* OP4_LDSTR16D */
+ EPIPHANY_RELAX_NONE, /* OP4_LDSTR126P */
+ EPIPHANY_RELAX_NONE, /* OP4_LSHIFT16 */
+ EPIPHANY_RELAX_NONE, /* OP4_DSP16 */
+ EPIPHANY_RELAX_BRANCH_LONG, /* OP4_BRANCH */
+ EPIPHANY_RELAX_NONE, /* OP4_LDSTRX */
+ EPIPHANY_RELAX_NONE, /* OP4_ALU16 */
+ EPIPHANY_RELAX_ARITH_SIMM11, /* OP4_IMM32 - special */
+ EPIPHANY_RELAX_LDST_IMM11, /* OP4_LDSTRD */
+ EPIPHANY_RELAX_NONE, /* OP4_LDSTRP */
+ EPIPHANY_RELAX_NONE, /* OP4_ASHIFT16 */
+ EPIPHANY_RELAX_NONE /* OP4_MISC */
+};
+
+long
+epiphany_relax_frag (segT segment, fragS *fragP, long stretch)
+{
+ /* Address of branch insn. */
+ long address ATTRIBUTE_UNUSED = fragP->fr_address + fragP->fr_fix - 2;
+ long growth = 0;
+
+ if (fragP->fr_subtype == EPIPHANY_RELAX_NEED_RELAXING)
+ {
+ EPIPHANY_RELAX_TYPES subtype = relax_insn [*fragP->fr_opcode & 0xf];
+
+ /* Special cases add/sub vs mov immediates. */
+ if (subtype == EPIPHANY_RELAX_ARITH_SIMM3)
+ {
+ if ((*fragP->fr_opcode & 0x10) == 0)
+ subtype = EPIPHANY_RELAX_MOV_IMM8;
+ }
+ else if (subtype == EPIPHANY_RELAX_ARITH_SIMM11)
+ {
+ if ((*fragP->fr_opcode & 0x10) == 0)
+ subtype = EPIPHANY_RELAX_MOV_IMM16;
+ }
+
+ /* Remember refinements for the future. */
+ fragP->fr_subtype = subtype;
+ }
+
+ growth = relax_frag (segment, fragP, stretch);
+
+ return growth;
+}
+
+/* Return an initial guess of the length by which a fragment must grow to
+ hold a branch to reach its destination.
+ Also updates fr_type/fr_subtype as necessary.
+
+ Called just before doing relaxation.
+ Any symbol that is now undefined will not become defined.
+ The guess for fr_var is ACTUALLY the growth beyond fr_fix.
+ Whatever we do to grow fr_fix or fr_var contributes to our returned value.
+ Although it may not be explicit in the frag, pretend fr_var starts
+ with a 0 value. */
+
+int
+md_estimate_size_before_relax (fragS *fragP, segT segment)
+{
+ /* The only thing we have to handle here are symbols outside of the
+ current segment. They may be undefined or in a different segment in
+ which case linker scripts may place them anywhere.
+ However, we can't finish the fragment here and emit the reloc as insn
+ alignment requirements may move the insn about. */
+ if (S_GET_SEGMENT (fragP->fr_symbol) != segment
+ || S_IS_EXTERNAL (fragP->fr_symbol)
+ || S_IS_WEAK (fragP->fr_symbol))
+ {
+ /* The symbol is undefined in this segment. Change the
+ relaxation subtype to the max allowable and leave all further
+ handling to md_convert_frag. */
+
+ EPIPHANY_RELAX_TYPES subtype;
+ /* We haven't relaxed this at all, so the relaxation type may be
+ completely wrong. Set the subtype correctly. */
+ epiphany_relax_frag (segment, fragP, 0);
+ subtype = fragP->fr_subtype;
+
+ switch (subtype)
+ {
+ case EPIPHANY_RELAX_LDST_IMM3:
+ subtype = EPIPHANY_RELAX_LDST_IMM11;
+ break;
+ case EPIPHANY_RELAX_BRANCH_SHORT:
+ subtype = EPIPHANY_RELAX_BRANCH_LONG;
+ break;
+ case EPIPHANY_RELAX_MOV_IMM8:
+ subtype = EPIPHANY_RELAX_MOV_IMM16;
+ break;
+ case EPIPHANY_RELAX_ARITH_SIMM3:
+ subtype = EPIPHANY_RELAX_ARITH_SIMM11;
+ break;
+
+ default:
+ break;
+ }
+
+ fragP->fr_subtype = subtype;
+
+ {
+ const CGEN_INSN *insn;
+ int i;
+
+ /* Update the recorded insn. */
+
+ for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
+ {
+ if ((strcmp (CGEN_INSN_MNEMONIC (insn),
+ CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
+ == 0)
+ && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED))
+ break;
+ }
+
+ if (i == 4)
+ abort ();
+
+ fragP->fr_cgen.insn = insn;
+ }
+ }
+
+ return md_relax_table[fragP->fr_subtype].rlx_length;
+}
+
+/* *FRAGP has been relaxed to its final size, and now needs to have
+ the bytes inside it modified to conform to the new size.
+
+ Called after relaxation is finished.
+ fragP->fr_type == rs_machine_dependent.
+ fragP->fr_subtype is the subtype of what the address relaxed to. */
+
+void
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+ segT sec,
+ fragS *fragP)
+{
+ char *opcode;
+ char *displacement;
+ int target_address;
+ int opcode_address;
+ int extension;
+ int addend;
+ int opindx = -1;
+
+ opcode = fragP->fr_opcode;
+
+ /* Address opcode resides at in file space. */
+ opcode_address = fragP->fr_address + fragP->fr_fix - 2;
+ extension = 0;
+ displacement = &opcode[1];
+
+ /* Set up any addend necessary for branches. */
+ if (S_GET_SEGMENT (fragP->fr_symbol) != sec
+ || S_IS_EXTERNAL (fragP->fr_symbol)
+ || S_IS_WEAK (fragP->fr_symbol))
+ {
+ /* Symbol must be resolved by linker. */
+ if (fragP->fr_offset & 1)
+ as_warn (_("Addend to unresolved symbol not on word boundary."));
+ addend = 0;
+ }
+ else
+ {
+ /* Address we want to reach in file space. */
+ target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
+ addend = (target_address - (opcode_address & -2));
+ }
+
+ /* Do all the housekeeping for frag conversions. */
+ switch (fragP->fr_subtype)
+ {
+ case EPIPHANY_RELAX_ARITH_SIMM11:
+ *opcode |= OP4_IMM32;
+ displacement = &opcode[0];
+ extension += 3;
+
+ addend
+ = (((addend & 0x7) << 7)
+ | opcode[0]
+ | ((addend & 0x7f8) << 13)
+ | (opcode[1] << 8)
+ | (opcode[2] << 16));
+
+ opindx = EPIPHANY_OPERAND_SIMM11;
+ break;
+
+ case EPIPHANY_RELAX_BRANCH_LONG:
+ /* Branches differ only in low nibble of instruction being 8 not 0.
+ 24 bit displacement goes to bytes 1..3 . */
+ *opcode |= OP4_BRANCH;
+ extension += 2;
+
+ addend >>= 1; /* Convert to word offset. */
+ opindx = EPIPHANY_OPERAND_SIMM24;
+ break;
+
+ case EPIPHANY_RELAX_MOV_IMM16:
+ *opcode |= OP4_IMM32;
+ extension += 3;
+
+ addend
+ = (((addend & 0xff00) << 12)
+ | (opcode[2] << 16)
+ | ((addend & 0x00ff) << 5)
+ | (opcode[1] << 8)
+ | opcode[0]);
+ displacement = &opcode[0];
+ opindx = EPIPHANY_OPERAND_IMM16;
+ break;
+
+ case EPIPHANY_RELAX_LDST_IMM11:
+ *opcode |= OP4_LDSTRD;
+ displacement = &opcode[0];
+ extension += 3;
+
+ if (addend < 0)
+ /* Convert twos-complement address value to sign-magnitude. */
+ addend = (-addend & 0x7ff) | 0x800;
+
+ addend
+ = (((addend & 0x7) << 5)
+ | opcode[0]
+ | ((addend & 0xff8) << 13)
+ | (opcode[1] << 8)
+ | (opcode[2] << 16));
+
+ opindx = EPIPHANY_OPERAND_DISP11;
+ break;
+
+ case EPIPHANY_RELAX_ARITH_SIMM3:
+ addend = ((addend & 7) << 5) | opcode[0];
+ opindx = EPIPHANY_OPERAND_SIMM3;
+ break;
+
+ case EPIPHANY_RELAX_LDST_IMM3:
+ addend = ((addend & 7) << 5) | opcode[0];
+ opindx = EPIPHANY_OPERAND_DISP3;
+
+ case EPIPHANY_RELAX_BRANCH_SHORT:
+ addend >>= 1; /* Convert to a word offset. */
+ displacement = & opcode[1];
+ opindx = EPIPHANY_OPERAND_SIMM8;
+ break;
+
+ case EPIPHANY_RELAX_MOV_IMM8:
+ addend
+ = (((addend & 0xff) << 5)
+ | opcode[0]
+ | (opcode[1] << 8));
+ opindx = EPIPHANY_OPERAND_IMM8;
+ break;
+
+ case EPIPHANY_RELAX_NONE:
+ case EPIPHANY_RELAX_NEED_RELAXING:
+ default: /* Anything else? */
+ as_bad ("unrecognized fragment subtype");
+ break;
+ }
+
+ /* Create a relocation for symbols that must be resolved by the linker.
+ Otherwise output the completed insn. */
+
+ if (S_GET_SEGMENT (fragP->fr_symbol) != sec
+ || S_IS_EXTERNAL (fragP->fr_symbol)
+ || S_IS_WEAK (fragP->fr_symbol))
+ {
+ fixS *fixP;
+ const CGEN_OPERAND *operand
+ = cgen_operand_lookup_by_num (gas_cgen_cpu_desc, opindx);
+ bfd_reloc_code_real_type reloc_type;
+
+ gas_assert (fragP->fr_cgen.insn != 0);
+
+ reloc_type = md_cgen_lookup_reloc (fragP->fr_cgen.insn, operand, NULL);
+
+ fixP = gas_cgen_record_fixup (fragP,
+ /* Offset of insn in frag. */
+ (opcode - fragP->fr_literal),
+ fragP->fr_cgen.insn,
+ CGEN_INSN_BITSIZE (fragP->fr_cgen.insn) / 8,
+ operand,
+ reloc_type,
+ fragP->fr_symbol, fragP->fr_offset);
+ fixP->fx_r_type = fixP->fx_cgen.opinfo;
+ }
+
+ md_number_to_chars (displacement, (valueT) addend, extension + 1);
+
+ fragP->fr_fix += (extension & -2); /* 0,2 or 4 bytes added. */
+}
+
+\f
+/* Functions concerning relocs. */
+
+/* The location from which a PC relative jump should be calculated,
+ given a PC relative reloc. */
+
+long
+md_pcrel_from_section (fixS *fixP, segT sec)
+{
+ if (fixP->fx_addsy != (symbolS *) NULL
+ && (!S_IS_DEFINED (fixP->fx_addsy)
+ || (S_GET_SEGMENT (fixP->fx_addsy) != sec)
+ || S_IS_EXTERNAL (fixP->fx_addsy)
+ || S_IS_WEAK (fixP->fx_addsy)))
+ return 0;
+
+ return fixP->fx_frag->fr_address + fixP->fx_where;
+}
+
+/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
+ Returns BFD_RELOC_NONE if no reloc type can be found.
+ *FIXP may be modified if desired. */
+
+bfd_reloc_code_real_type
+md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
+ const CGEN_OPERAND *operand,
+ fixS *fixP ATTRIBUTE_UNUSED)
+{
+ switch (operand->type)
+ {
+ case EPIPHANY_OPERAND_SIMM11:
+ return BFD_RELOC_EPIPHANY_SIMM11;
+ case EPIPHANY_OPERAND_DISP11:
+ return BFD_RELOC_EPIPHANY_IMM11;
+
+ case EPIPHANY_OPERAND_SIMM8:
+ return BFD_RELOC_EPIPHANY_SIMM8;
+ case EPIPHANY_OPERAND_SIMM24:
+ return BFD_RELOC_EPIPHANY_SIMM24;
+
+ case EPIPHANY_OPERAND_IMM8:
+ return BFD_RELOC_EPIPHANY_IMM8;
+
+ case EPIPHANY_OPERAND_IMM16:
+ if (0 == strcmp ("movt", CGEN_INSN_MNEMONIC (insn)))
+ return BFD_RELOC_EPIPHANY_HIGH;
+ else if (0 == strcmp ("mov", CGEN_INSN_MNEMONIC (insn)))
+ return BFD_RELOC_EPIPHANY_LOW;
+ else
+ as_bad ("unknown imm16 operand");
+ /* fall-thru */
+
+ default:
+ break;
+ }
+ return BFD_RELOC_NONE;
+}
+
+\f
+/* Turn a string in input_line_pointer into a floating point constant
+ of type TYPE, and store the appropriate bytes in *LITP. The number
+ of LITTLENUMS emitted is stored in *SIZEP. An error message is
+ returned, or NULL on OK. */
+
+/* Equal to MAX_PRECISION in atof-ieee.c. */
+#define MAX_LITTLENUMS 6
+
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+ return ieee_md_atof (type, litP, sizeP, FALSE);
+}
+
+/* Return true if can adjust the reloc to be relative to its section
+ (such as .data) instead of relative to some symbol. */
+
+bfd_boolean
+epiphany_fix_adjustable (fixS *fixP)
+{
+ bfd_reloc_code_real_type reloc_type;
+
+ if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
+ {
+ const CGEN_INSN *insn = fixP->fx_cgen.insn;
+ int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
+ const CGEN_OPERAND *operand =
+ cgen_operand_lookup_by_num (gas_cgen_cpu_desc, opindex);
+
+ reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
+ }
+ else
+ reloc_type = fixP->fx_r_type;
+
+ if (fixP->fx_addsy == NULL)
+ return TRUE;
+
+ /* Prevent all adjustments to global symbols. */
+ if (S_IS_EXTERNAL (fixP->fx_addsy))
+ return FALSE;
+
+ if (S_IS_WEAK (fixP->fx_addsy))
+ return FALSE;
+
+ if (pic_code
+ && (reloc_type == BFD_RELOC_EPIPHANY_SIMM24
+ || reloc_type == BFD_RELOC_EPIPHANY_SIMM8
+ || reloc_type == BFD_RELOC_EPIPHANY_HIGH
+ || reloc_type == BFD_RELOC_EPIPHANY_LOW))
+ return FALSE;
+
+ /* Since we don't use partial_inplace, we must not reduce symbols in
+ mergable sections to their section symbol. */
+ if ((S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0)
+ return FALSE;
+
+ return TRUE;
+}
+
+void
+epiphany_elf_final_processing (void)
+{
+ elf_elfheader (stdoutput)->e_flags |= epiphany_flags;
+}
+
+int
+epiphany_cgen_parse_fix_exp (int opinfo, expressionS *exp ATTRIBUTE_UNUSED)
+{
+ LITTLENUM_TYPE words[2];
+
+ switch (opinfo)
+ {
+ case BFD_RELOC_EPIPHANY_LOW:
+ case BFD_RELOC_EPIPHANY_HIGH:
+ break;
+ default:
+ return opinfo;
+ }
+
+ /* Doing a %LOW or %HIGH. */
+ switch (exp->X_op)
+ {
+ default:
+ return opinfo;
+ case O_big: /* Bignum. */
+ if (exp->X_add_number > 0) /* Integer value too large. */
+ return opinfo;
+ }
+
+ /* Convert to SP number. */
+ gen_to_words (words, 2, 8L);
+ exp->X_add_number = words[1] | (words[0] << 16);
+ exp->X_op = O_constant;
+ return opinfo;
+}
--- /dev/null
+/* tc-epiphany.h -- Header file for tc-epiphany.c.
+ Copyright 2011 Free Software Foundation, Inc.
+ Contributed by Embecosm on behalf of Adapteva, Inc.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+#define TC_EPIPHANY
+
+#define LISTING_HEADER "EPIPHANY GAS "
+
+/* The target BFD architecture. */
+#define TARGET_ARCH bfd_arch_epiphany
+
+#define TARGET_FORMAT "elf32-epiphany"
+
+/* Permit temporary numeric labels. */
+#define LOCAL_LABELS_FB 1
+
+/* .-foo gets turned into PC relative relocs. */
+#define DIFF_EXPR_OK
+
+/* We don't need to handle .word strangely. */
+#define WORKING_DOT_WORD
+
+#define LITERAL_PREFIXDOLLAR_HEX
+#define LITERAL_PREFIXPERCENT_BIN
+#define DOUBLESLASH_LINE_COMMENTS
+
+#define GAS_CGEN_PCREL_R_TYPE(R_TYPE) gas_cgen_pcrel_r_type (R_TYPE)
+
+/* Values passed to md_apply_fix don't include the symbol value. */
+#define MD_APPLY_SYM_VALUE(FIX) 0
+
+#define tc_fix_adjustable(FIX) epiphany_fix_adjustable (FIX)
+extern bfd_boolean epiphany_fix_adjustable (struct fix *);
+
+extern long md_pcrel_from_section (struct fix *, segT);
+#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP,SEC)
+
+#define TC_HANDLES_FX_DONE
+
+#define elf_tc_final_processing epiphany_elf_final_processing
+extern void epiphany_elf_final_processing (void);
+
+#define md_elf_section_flags epiphany_elf_section_flags
+extern int epiphany_elf_section_flags (int, int, int);
+
+#define md_operand(x) epiphany_cgen_md_operand (x)
+extern void epiphany_cgen_md_operand (expressionS *);
+
+/* Values passed to md_apply_fix don't include the symbol value. */
+#define MD_APPLY_SYM_VALUE(FIX) 0
+
+#define TC_CGEN_MAX_RELAX(insn, len) 4
+
+#define O_PIC_reloc O_md1
+
+#define TC_CGEN_PARSE_FIX_EXP(opinfo, exp) \
+ epiphany_cgen_parse_fix_exp (opinfo, exp)
+extern int epiphany_cgen_parse_fix_exp (int, expressionS *);
+
+#define HANDLE_ALIGN(f) epiphany_handle_align (f)
+extern void epiphany_handle_align (fragS *);
+
+#define TARGET_FORMAT "elf32-epiphany"
+
+#define md_relax_frag epiphany_relax_frag
+
+extern long epiphany_relax_frag (segT, fragS *, long);
+
+/* If you don't define md_relax_frag, md_cgen_record_fixup_exp
+ but do have TC_GENERIC_RELAX_TABLE gas will do the relaxation for you.
+
+ If we have to add support for %LO and %HI relocations, we probably need
+ to define the fixup_exp function to generate fancier relocations. */
+
+/* For 8 vs 24 bit branch selection. */
+extern const struct relax_type md_relax_table[];
+#define TC_GENERIC_RELAX_TABLE md_relax_table
+
+#define tc_gen_reloc gas_cgen_tc_gen_reloc
+
+
+#define md_apply_fix epiphany_apply_fix
+#include "write.h"
+
+extern void epiphany_apply_fix (fixS *fixP, valueT *valP, segT seg);
fi
;;
- fr30 | ip2k | iq2000 | lm32 | m32r | openrisc)
+ epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | openrisc)
using_cgen=yes
;;
fi
;;
- fr30 | ip2k | iq2000 | lm32 | m32r | openrisc)
+ epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | openrisc)
using_cgen=yes
;;
cr16*) cpu_type=cr16 endian=little ;;
crisv32) cpu_type=cris arch=crisv32 ;;
crx*) cpu_type=crx endian=little ;;
+ epiphany*) cpu_type=epiphany endian=little ;;
fido) cpu_type=m68k ;;
hppa*) cpu_type=hppa ;;
i[3-7]86) cpu_type=i386 arch=i386;;
d30v-*-*) fmt=elf ;;
dlx-*-*) fmt=elf ;;
+ epiphany-*-*) fmt=elf ;;
+
fr30-*-*) fmt=elf ;;
frv-*-*linux*) fmt=elf em=linux;;
frv-*-*) fmt=elf ;;
c-avr.texi \
c-bfin.texi \
c-cr16.texi \
- c-d10v.texi \
c-cris.texi \
+ c-d10v.texi \
+ c-epiphany.texi \
c-h8300.texi \
c-hppa.texi \
c-i370.texi \
c-avr.texi \
c-bfin.texi \
c-cr16.texi \
- c-d10v.texi \
c-cris.texi \
+ c-d10v.texi \
+ c-epiphany.texi \
c-h8300.texi \
c-hppa.texi \
c-i370.texi \
@set CRIS
@set D10V
@set D30V
+@set EPIPHANY
@set H8/300
@set HPPA
@set I370
@emph{Target D30V options:}
[@b{-O}|@b{-n}|@b{-N}]
@end ifset
+@ifset EPIPHANY
+
+@emph{Target EPIPHANY options:}
+ [@b{-mepiphany}|@b{-mepiphany16}]
+@end ifset
@ifset H8
@emph{Target H8/300 options:}
@end ifset
@c man end
+@ifset EPIPHANY
+The following options are available when @value{AS} is configured for the
+Adapteva EPIPHANY series.
+
+@table @gcctabopt
+
+@item -mepiphany
+Specifies that the both 32 and 16 bit instructions are allowed. This is the
+default behavior.
+
+@item -mepiphany16
+Restricts the permitted instructions to just the 16 bit set.
+
+@end table
+@end ifset
+
@ifset I80386
@ifclear man
@ifset D30V
* D30V-Dependent:: D30V Dependent Features
@end ifset
+@ifset EPIPHANY
+* Epiphany-Dependent:: EPIPHANY Dependent Features
+@end ifset
@ifset H8/300
* H8/300-Dependent:: Renesas H8/300 Dependent Features
@end ifset
@include c-d30v.texi
@end ifset
+@ifset EPIPHANY
+@include c-epiphany.texi
+@end ifset
+
@ifset H8/300
@include c-h8300.texi
@end ifset
--- /dev/null
+@c Copyright 2011 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@c man end
+
+@ifset GENERIC
+@page
+@node Epiphany-Dependent
+@chapter Epiphany Dependent Features
+@end ifset
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter Epiphany Dependent Features
+@end ifclear
+
+@cindex Epiphany support
+@menu
+* Epiphany Options:: Options
+* Epiphany Syntax:: Epiphany Syntax
+@end menu
+
+@node Epiphany Options
+@section Options
+
+@cindex Epiphany options
+@cindex options, Epiphany
+@code{@value{AS}} has two additional command-line options for the Epiphany
+architecture.
+
+@c man begin OPTIONS
+@table @gcctabopt
+
+@cindex @code{-mepiphany} command line option, Epiphany
+@item -mepiphany
+Specifies that the both 32 and 16 bit instructions are allowed. This is the
+default behavior.
+
+@cindex @code{-mepiphany16} command line option, Epiphany
+@item -mepiphany16
+Restricts the permitted instructions to just the 16 bit set.
+@end table
+@c man end
+
+@node Epiphany Syntax
+@section Epiphany Syntax
+@menu
+* Epiphany-Chars:: Special Characters
+@end menu
+
+@node Epiphany-Chars
+@subsection Special Characters
+
+@cindex line comment character, Epiphany
+@cindex Epiphany line comment character
+The presence of a @samp{;} on a line indicates the start
+of a comment that extends to the end of the current line.
+
+If a @samp{#} appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line could also be
+a logical line number directive (@pxref{Comments}) or a preprocessor
+control command (@pxref{Preprocessing}).
+
+@cindex line separator, Epiphany
+@cindex statement separator, Epiphany
+@cindex Epiphany line separator
+The @samp{`} character can be used to separate statements on the same
+line.
config/tc-d30v.h
config/tc-dlx.c
config/tc-dlx.h
+config/tc-epiphany.c
+config/tc-epiphany.h
config/tc-fr30.c
config/tc-fr30.h
config/tc-frv.c
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n"
-"POT-Creation-Date: 2011-06-02 14:30+0100\n"
+"POT-Creation-Date: 2011-10-25 12:00+0100\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n"
msgid "%s: data size %ld\n"
msgstr ""
-#: as.c:1289
+#: as.c:1292
#, c-format
msgid "%d warnings, treating warnings as errors"
msgstr ""
msgid "failed sanity check"
msgstr ""
-#: cgen.c:113 config/tc-alpha.c:2104 config/tc-alpha.c:2128
+#: cgen.c:113 config/tc-alpha.c:2101 config/tc-alpha.c:2125
#: config/tc-arc.c:1684 config/tc-d10v.c:552 config/tc-d30v.c:538
-#: config/tc-mn10200.c:1100 config/tc-mn10300.c:1751 config/tc-ppc.c:2617
+#: config/tc-mn10200.c:1101 config/tc-mn10300.c:1751 config/tc-ppc.c:2617
#: config/tc-ppc.c:2768 config/tc-ppc.c:2910 config/tc-ppc.c:2921
#: config/tc-s390.c:1250 config/tc-s390.c:1364 config/tc-s390.c:1493
#: config/tc-v850.c:2229 config/tc-v850.c:2300 config/tc-v850.c:2346
msgstr ""
#: cgen.c:400 cgen.c:420 config/tc-arc.c:1665 config/tc-d10v.c:463
-#: config/tc-d30v.c:454 config/tc-i370.c:2125 config/tc-mn10200.c:1042
+#: config/tc-d30v.c:454 config/tc-i370.c:2125 config/tc-mn10200.c:1043
#: config/tc-mn10300.c:1676 config/tc-ppc.c:2656 config/tc-s390.c:1221
#: config/tc-v850.c:2337 config/tc-v850.c:2371 config/tc-v850.c:2411
#: config/tc-v850.c:2622 config/tc-z80.c:417
#: cgen.c:424 config/tc-arc.c:1667 config/tc-avr.c:632 config/tc-d10v.c:465
#: config/tc-d30v.c:456 config/tc-h8300.c:500 config/tc-i370.c:2127
#: config/tc-mcore.c:662 config/tc-microblaze.c:579 config/tc-mmix.c:488
-#: config/tc-mn10200.c:1045 config/tc-mn10300.c:1679 config/tc-msp430.c:452
+#: config/tc-mn10200.c:1046 config/tc-mn10300.c:1679 config/tc-msp430.c:452
#: config/tc-or32.c:307 config/tc-ppc.c:2658 config/tc-s390.c:1239
#: config/tc-sh.c:1387 config/tc-sh64.c:2213 config/tc-v850.c:2341
#: config/tc-v850.c:2375 config/tc-v850.c:2415 config/tc-v850.c:2625
msgstr ""
#. We can't actually support subtracting a symbol.
-#: cgen.c:886 config/tc-arc.c:1249 config/tc-arm.c:1645 config/tc-arm.c:9058
-#: config/tc-arm.c:9110 config/tc-arm.c:9357 config/tc-arm.c:10157
-#: config/tc-arm.c:11248 config/tc-arm.c:11288 config/tc-arm.c:11616
-#: config/tc-arm.c:11655 config/tc-avr.c:1165 config/tc-cris.c:4047
-#: config/tc-d10v.c:1511 config/tc-d30v.c:1915 config/tc-mips.c:4694
-#: config/tc-msp430.c:1936 config/tc-ppc.c:6102 config/tc-spu.c:957
-#: config/tc-spu.c:981 config/tc-v850.c:3084 config/tc-xstormy16.c:483
-#: config/tc-xtensa.c:5833 config/tc-xtensa.c:11830
+#: cgen.c:886 config/tc-arc.c:1249 config/tc-arm.c:1649 config/tc-arm.c:9195
+#: config/tc-arm.c:9247 config/tc-arm.c:9494 config/tc-arm.c:10301
+#: config/tc-arm.c:11396 config/tc-arm.c:11436 config/tc-arm.c:11776
+#: config/tc-arm.c:11815 config/tc-avr.c:1165 config/tc-cris.c:4047
+#: config/tc-d10v.c:1511 config/tc-d30v.c:1915 config/tc-mips.c:5697
+#: config/tc-msp430.c:1936 config/tc-ppc.c:6072 config/tc-spu.c:957
+#: config/tc-spu.c:981 config/tc-tilegx.c:1421 config/tc-tilepro.c:1268
+#: config/tc-v850.c:3084 config/tc-xstormy16.c:483 config/tc-xtensa.c:5833
+#: config/tc-xtensa.c:11830
msgid "expression too complex"
msgstr ""
-#: cgen.c:982 config/tc-arc.c:1310 config/tc-ppc.c:6227 config/tc-s390.c:2135
+#: cgen.c:982 config/tc-arc.c:1310 config/tc-ppc.c:6197 config/tc-s390.c:2135
#: config/tc-v850.c:3131 config/tc-xstormy16.c:537
msgid "unresolved expression that must be resolved"
msgstr ""
msgid "internal error: can't install fix for reloc type %d (`%s')"
msgstr ""
-#: cgen.c:1037
+#: cgen.c:1060
msgid "relocation is not supported"
msgstr ""
msgid "Infinities are not supported by this target\n"
msgstr ""
-#: config/atof-ieee.c:784 config/atof-vax.c:450 config/tc-arm.c:1036
+#: config/atof-ieee.c:784 config/atof-vax.c:450 config/tc-arm.c:1040
#: config/tc-ia64.c:11435 config/tc-tic30.c:1259 config/tc-tic4x.c:2598
msgid "Unrecognized or unsupported floating point constant"
msgstr ""
msgid "Inserting \"%s\" into structure table failed: %s"
msgstr ""
-#: config/obj-coff.c:219 config/obj-coff.c:1695 config/tc-ppc.c:5147
-#: config/tc-tic54x.c:4008 read.c:2795
+#: config/obj-coff.c:219 config/obj-coff.c:1701 config/obj-macho.c:202
+#: config/tc-ppc.c:5147 config/tc-tic54x.c:4008 read.c:2795
#, c-format
msgid "error setting flags for \"%s\": %s"
msgstr ""
#. STYP_INFO
#. STYP_LIB
#. STYP_OVER
-#: config/obj-coff.c:1661
+#: config/obj-coff.c:1667
#, c-format
msgid "unsupported section attribute '%c'"
msgstr ""
-#: config/obj-coff.c:1665 config/tc-ppc.c:5129
+#: config/obj-coff.c:1671 config/tc-ppc.c:5129
#, c-format
msgid "unknown section attribute '%c'"
msgstr ""
-#: config/obj-coff.c:1707
+#: config/obj-coff.c:1713 config/obj-macho.c:216
#, c-format
msgid "Ignoring changed section attributes for %s"
msgstr ""
-#: config/obj-coff.c:1847
+#: config/obj-coff.c:1853
#, c-format
msgid "0x%lx: \"%s\" type = %ld, class = %d, segment = %d\n"
msgstr ""
msgid "Can't set register masks"
msgstr ""
-#: config/obj-elf.c:334 config/tc-sparc.c:3949 config/tc-v850.c:503
+#: config/obj-elf.c:334 config/tc-sparc.c:4092 config/tc-v850.c:503
#, c-format
msgid "bad .common segment %s"
msgstr ""
msgid "missing name"
msgstr ""
-#: config/obj-elf.c:1032
+#: config/obj-elf.c:1030
msgid "invalid merge entity size"
msgstr ""
-#: config/obj-elf.c:1039
+#: config/obj-elf.c:1037
msgid "entity size for SHF_MERGE not specified"
msgstr ""
-#: config/obj-elf.c:1045
+#: config/obj-elf.c:1043
msgid "? section flag ignored with G present"
msgstr ""
-#: config/obj-elf.c:1064
+#: config/obj-elf.c:1062
msgid "group name for SHF_GROUP not specified"
msgstr ""
-#: config/obj-elf.c:1087
+#: config/obj-elf.c:1085
msgid "character following name is not '#'"
msgstr ""
-#: config/obj-elf.c:1207
+#: config/obj-elf.c:1204
msgid ".previous without corresponding .section; ignored"
msgstr ""
-#: config/obj-elf.c:1233
+#: config/obj-elf.c:1230
msgid ".popsection without corresponding .pushsection; ignored"
msgstr ""
-#: config/obj-elf.c:1279
+#: config/obj-elf.c:1276
msgid "expected comma after name in .symver"
msgstr ""
-#: config/obj-elf.c:1303
+#: config/obj-elf.c:1300
#, c-format
msgid "missing version name in `%s' for symbol `%s'"
msgstr ""
-#: config/obj-elf.c:1314
+#: config/obj-elf.c:1311
#, c-format
msgid "multiple versions [`%s'|`%s'] for symbol `%s'"
msgstr ""
-#: config/obj-elf.c:1351
+#: config/obj-elf.c:1348
#, c-format
msgid "expected `%s' to have already been set for .vtable_inherit"
msgstr ""
-#: config/obj-elf.c:1361
+#: config/obj-elf.c:1358
msgid "expected comma after name in .vtable_inherit"
msgstr ""
-#: config/obj-elf.c:1414
+#: config/obj-elf.c:1411
msgid "expected comma after name in .vtable_entry"
msgstr ""
-#: config/obj-elf.c:1537
+#: config/obj-elf.c:1534
msgid "expected quoted string"
msgstr ""
-#: config/obj-elf.c:1557
+#: config/obj-elf.c:1554
#, c-format
msgid "expected comma after name `%s' in .size directive"
msgstr ""
-#: config/obj-elf.c:1566
+#: config/obj-elf.c:1563
msgid "missing expression in .size directive"
msgstr ""
-#: config/obj-elf.c:1690
+#: config/obj-elf.c:1687
#, c-format
msgid "symbol '%s' is already defined"
msgstr ""
-#: config/obj-elf.c:1710 config/obj-elf.c:1722
+#: config/obj-elf.c:1707 config/obj-elf.c:1719
#, c-format
msgid "symbol type \"%s\" is supported only by GNU targets"
msgstr ""
-#: config/obj-elf.c:1733
+#: config/obj-elf.c:1730
#, c-format
msgid "unrecognized symbol type \"%s\""
msgstr ""
-#: config/obj-elf.c:1903 config/obj-elf.c:1906
+#: config/obj-elf.c:1900 config/obj-elf.c:1903
#, c-format
msgid ".size expression for %s does not evaluate to a constant"
msgstr ""
-#: config/obj-elf.c:1938
+#: config/obj-elf.c:1935
#, c-format
msgid ""
"invalid attempt to declare external version name as default in symbol `%s'"
msgstr ""
-#: config/obj-elf.c:1999 ecoff.c:3608
+#: config/obj-elf.c:1996 ecoff.c:3608
#, c-format
msgid "symbol `%s' can not be both weak and common"
msgstr ""
-#: config/obj-elf.c:2116
+#: config/obj-elf.c:2113
#, c-format
msgid "assuming all members of group `%s' are COMDAT"
msgstr ""
-#: config/obj-elf.c:2128
+#: config/obj-elf.c:2125
#, c-format
msgid "can't create group: %s"
msgstr ""
-#: config/obj-elf.c:2267
+#: config/obj-elf.c:2264
#, c-format
msgid "failed to set up debugging information: %s"
msgstr ""
-#: config/obj-elf.c:2287
+#: config/obj-elf.c:2284
#, c-format
msgid "can't start writing .mdebug section: %s"
msgstr ""
-#: config/obj-elf.c:2295
+#: config/obj-elf.c:2292
#, c-format
msgid "could not write .mdebug section: %s"
msgstr ""
+#: config/obj-evax.c:129
+#, c-format
+msgid "no entry symbol for global function '%s'"
+msgstr ""
+
+#: config/obj-macho.c:77
+msgid "missing segment name"
+msgstr ""
+
+#: config/obj-macho.c:89
+msgid "missing comma after segment name"
+msgstr ""
+
+#: config/obj-macho.c:98
+msgid "missing section name"
+msgstr ""
+
+#: config/obj-macho.c:114
+msgid "missing section type name"
+msgstr ""
+
+#: config/obj-macho.c:124
+#, c-format
+msgid "unknown or invalid section type '%s'"
+msgstr ""
+
+#: config/obj-macho.c:140
+msgid "missing section attribute identifier"
+msgstr ""
+
+#: config/obj-macho.c:149
+#, c-format
+msgid "unknown or invalid section attribute '%s'"
+msgstr ""
+
+#: config/obj-macho.c:161
+msgid "unexpected sizeof_stub expression"
+msgstr ""
+
+#: config/obj-macho.c:166
+msgid "missing sizeof_stub expression"
+msgstr ""
+
#: config/obj-som.c:58
msgid "Only one .compiler pseudo-op per file!"
msgstr ""
msgid "attaching copyright header %s: %s"
msgstr ""
-#: config/tc-alpha.c:656
+#: config/tc-alpha.c:655
#, c-format
msgid "No !literal!%ld was found"
msgstr ""
-#: config/tc-alpha.c:663
+#: config/tc-alpha.c:662
#, c-format
msgid "No !tlsgd!%ld was found"
msgstr ""
-#: config/tc-alpha.c:670
+#: config/tc-alpha.c:669
#, c-format
msgid "No !tlsldm!%ld was found"
msgstr ""
-#: config/tc-alpha.c:679
+#: config/tc-alpha.c:678
#, c-format
msgid "No ldah !gpdisp!%ld was found"
msgstr ""
-#: config/tc-alpha.c:729
+#: config/tc-alpha.c:728
#, c-format
msgid "too many !literal!%ld for %s"
msgstr ""
-#: config/tc-alpha.c:759
+#: config/tc-alpha.c:758
#, c-format
msgid "No lda !gpdisp!%ld was found"
msgstr ""
#. Only support one relocation op per insn.
-#: config/tc-alpha.c:918
+#: config/tc-alpha.c:917
msgid "More than one relocation op per insn"
msgstr ""
-#: config/tc-alpha.c:934
+#: config/tc-alpha.c:933
msgid "No relocation operand"
msgstr ""
-#: config/tc-alpha.c:944
+#: config/tc-alpha.c:943
#, c-format
msgid "Unknown relocation operand: !%s"
msgstr ""
-#: config/tc-alpha.c:954
+#: config/tc-alpha.c:953
#, c-format
msgid "no sequence number after !%s"
msgstr ""
-#: config/tc-alpha.c:964
+#: config/tc-alpha.c:963
#, c-format
msgid "!%s does not use a sequence number"
msgstr ""
-#: config/tc-alpha.c:974
+#: config/tc-alpha.c:973
#, c-format
msgid "Bad sequence number: !%s!%s"
msgstr ""
-#: config/tc-alpha.c:1189 config/tc-alpha.c:3364
+#: config/tc-alpha.c:1188 config/tc-alpha.c:3361
#, c-format
msgid "inappropriate arguments for opcode `%s'"
msgstr ""
-#: config/tc-alpha.c:1191 config/tc-alpha.c:3366
+#: config/tc-alpha.c:1190 config/tc-alpha.c:3363
#, c-format
msgid "opcode `%s' not supported for target %s"
msgstr ""
-#: config/tc-alpha.c:1195 config/tc-alpha.c:3370 config/tc-avr.c:1441
+#: config/tc-alpha.c:1194 config/tc-alpha.c:3367 config/tc-avr.c:1441
#: config/tc-msp430.c:1828
#, c-format
msgid "unknown opcode `%s'"
msgstr ""
-#: config/tc-alpha.c:1276 config/tc-alpha.c:1537
+#: config/tc-alpha.c:1275 config/tc-alpha.c:1534
msgid "overflow in literal (.lita) table"
msgstr ""
-#: config/tc-alpha.c:1283 config/tc-alpha.c:1307 config/tc-alpha.c:1550
-#: config/tc-alpha.c:2237 config/tc-alpha.c:2282 config/tc-alpha.c:2351
-#: config/tc-alpha.c:2434 config/tc-alpha.c:2659 config/tc-alpha.c:2757
+#: config/tc-alpha.c:1282 config/tc-alpha.c:1306 config/tc-alpha.c:1547
+#: config/tc-alpha.c:2234 config/tc-alpha.c:2279 config/tc-alpha.c:2348
+#: config/tc-alpha.c:2431 config/tc-alpha.c:2656 config/tc-alpha.c:2754
msgid "macro requires $at register while noat in effect"
msgstr ""
-#: config/tc-alpha.c:1285 config/tc-alpha.c:1309 config/tc-alpha.c:1552
+#: config/tc-alpha.c:1284 config/tc-alpha.c:1308 config/tc-alpha.c:1549
msgid "macro requires $at while $at in use"
msgstr ""
-#: config/tc-alpha.c:1495
+#: config/tc-alpha.c:1493
msgid "bignum invalid; zero assumed"
msgstr ""
-#: config/tc-alpha.c:1497
+#: config/tc-alpha.c:1495
msgid "floating point number invalid; zero assumed"
msgstr ""
-#: config/tc-alpha.c:1502
+#: config/tc-alpha.c:1500
msgid "can't handle expression"
msgstr ""
-#: config/tc-alpha.c:1543
+#: config/tc-alpha.c:1540
msgid "overflow in literal (.lit8) table"
msgstr ""
-#: config/tc-alpha.c:1840
+#: config/tc-alpha.c:1837
#, c-format
msgid "too many ldah insns for !gpdisp!%ld"
msgstr ""
-#: config/tc-alpha.c:1842 config/tc-alpha.c:1854
+#: config/tc-alpha.c:1839 config/tc-alpha.c:1851
#, c-format
msgid "both insns for !gpdisp!%ld must be in the same section"
msgstr ""
-#: config/tc-alpha.c:1852
+#: config/tc-alpha.c:1849
#, c-format
msgid "too many lda insns for !gpdisp!%ld"
msgstr ""
-#: config/tc-alpha.c:1908
+#: config/tc-alpha.c:1905
#, c-format
msgid "too many lituse insns for !lituse_tlsgd!%ld"
msgstr ""
-#: config/tc-alpha.c:1911
+#: config/tc-alpha.c:1908
#, c-format
msgid "too many lituse insns for !lituse_tlsldm!%ld"
msgstr ""
-#: config/tc-alpha.c:1928
+#: config/tc-alpha.c:1925
#, c-format
msgid "duplicate !tlsgd!%ld"
msgstr ""
-#: config/tc-alpha.c:1930
+#: config/tc-alpha.c:1927
#, c-format
msgid "sequence number in use for !tlsldm!%ld"
msgstr ""
-#: config/tc-alpha.c:1944
+#: config/tc-alpha.c:1941
#, c-format
msgid "duplicate !tlsldm!%ld"
msgstr ""
-#: config/tc-alpha.c:1946
+#: config/tc-alpha.c:1943
#, c-format
msgid "sequence number in use for !tlsgd!%ld"
msgstr ""
-#: config/tc-alpha.c:2001 config/tc-arc.c:292 config/tc-mn10200.c:856
+#: config/tc-alpha.c:1998 config/tc-arc.c:292 config/tc-mn10200.c:857
#: config/tc-mn10300.c:1148 config/tc-ppc.c:1730 config/tc-s390.c:638
+#: config/tc-tilegx.c:408 config/tc-tilegx.c:471 config/tc-tilepro.c:369
msgid "operand"
msgstr ""
-#: config/tc-alpha.c:2140
+#: config/tc-alpha.c:2137
msgid "invalid relocation for instruction"
msgstr ""
-#: config/tc-alpha.c:2154
+#: config/tc-alpha.c:2151
msgid "invalid relocation for field"
msgstr ""
-#: config/tc-alpha.c:2985
+#: config/tc-alpha.c:2982
msgid "can not resolve expression"
msgstr ""
-#: config/tc-alpha.c:3524 config/tc-i370.c:1055 config/tc-microblaze.c:185
+#: config/tc-alpha.c:3516 config/tc-i370.c:1055 config/tc-microblaze.c:185
#: config/tc-ppc.c:2055 config/tc-ppc.c:4892
#, c-format
msgid ".COMMon length (%ld.) <0! Ignored."
msgstr ""
-#: config/tc-alpha.c:3535 config/tc-sparc.c:3820 config/tc-v850.c:298
+#: config/tc-alpha.c:3527 config/tc-sparc.c:3963 config/tc-v850.c:298
msgid "Ignoring attempt to re-define symbol"
msgstr ""
-#: config/tc-alpha.c:3627 config/tc-ppc.c:4929 config/tc-sparc.c:3828
+#: config/tc-alpha.c:3619 config/tc-ppc.c:4929 config/tc-sparc.c:3971
#, c-format
msgid "Length of .comm \"%s\" is already %ld. Not changed to %ld."
msgstr ""
-#: config/tc-alpha.c:3730 ecoff.c:3064
+#: config/tc-alpha.c:3722 ecoff.c:3064
msgid ".ent directive has no name"
msgstr ""
-#: config/tc-alpha.c:3738
+#: config/tc-alpha.c:3730
msgid "nested .ent directives"
msgstr ""
-#: config/tc-alpha.c:3783 ecoff.c:3015
+#: config/tc-alpha.c:3775 ecoff.c:3015
msgid ".end directive has no name"
msgstr ""
-#: config/tc-alpha.c:3792
+#: config/tc-alpha.c:3784
msgid ".end directive without matching .ent"
msgstr ""
-#: config/tc-alpha.c:3794
+#: config/tc-alpha.c:3786
msgid ".end directive names different symbol than .ent"
msgstr ""
-#: config/tc-alpha.c:3837 ecoff.c:3150
+#: config/tc-alpha.c:3829 ecoff.c:3150
msgid ".fmask outside of .ent"
msgstr ""
-#: config/tc-alpha.c:3839 config/tc-score.c:5601 ecoff.c:3214
+#: config/tc-alpha.c:3831 config/tc-score.c:5598 ecoff.c:3214
msgid ".mask outside of .ent"
msgstr ""
-#: config/tc-alpha.c:3847 ecoff.c:3157
+#: config/tc-alpha.c:3839 ecoff.c:3157
msgid "bad .fmask directive"
msgstr ""
-#: config/tc-alpha.c:3849 ecoff.c:3221
+#: config/tc-alpha.c:3841 ecoff.c:3221
msgid "bad .mask directive"
msgstr ""
-#: config/tc-alpha.c:3882 config/tc-mips.c:15469 config/tc-score.c:5743
+#: config/tc-alpha.c:3874 config/tc-mips.c:18816 config/tc-score.c:5740
#: ecoff.c:3178
msgid ".frame outside of .ent"
msgstr ""
-#: config/tc-alpha.c:3893 ecoff.c:3189
+#: config/tc-alpha.c:3885 ecoff.c:3189
msgid "bad .frame directive"
msgstr ""
-#: config/tc-alpha.c:3927
+#: config/tc-alpha.c:3919
msgid ".prologue directive without a preceding .ent directive"
msgstr ""
-#: config/tc-alpha.c:3945
+#: config/tc-alpha.c:3937
#, c-format
msgid "Invalid argument %d to .prologue."
msgstr ""
-#: config/tc-alpha.c:4036
+#: config/tc-alpha.c:4028
msgid "ECOFF debugging is disabled."
msgstr ""
-#: config/tc-alpha.c:4050
+#: config/tc-alpha.c:4042
msgid ".ent directive without matching .end"
msgstr ""
msgid "unknown section attribute %s"
msgstr ""
-#: config/tc-alpha.c:4389
+#: config/tc-alpha.c:4370
+msgid "previous .ent not closed by a .end"
+msgstr ""
+
+#: config/tc-alpha.c:4391
msgid ".ent directive has no symbol"
msgstr ""
-#: config/tc-alpha.c:4418
+#: config/tc-alpha.c:4416
msgid ".handler directive has no name"
msgstr ""
-#: config/tc-alpha.c:4447
+#: config/tc-alpha.c:4445
msgid "Bad .frame directive 1./2. param"
msgstr ""
-#: config/tc-alpha.c:4459
+#: config/tc-alpha.c:4457
msgid "Bad .frame directive 3./4. param"
msgstr ""
-#: config/tc-alpha.c:4497
+#: config/tc-alpha.c:4494
msgid ".pdesc directive not in link (.link) section"
msgstr ""
-#: config/tc-alpha.c:4505
+#: config/tc-alpha.c:4501
msgid ".pdesc directive has no entry symbol"
msgstr ""
+#: config/tc-alpha.c:4512
+msgid ".pdesc has a bad entry symbol"
+msgstr ""
+
#: config/tc-alpha.c:4523
-msgid ".pdesc has no matching .ent"
+msgid ".pdesc doesn't match with last .ent"
msgstr ""
-#: config/tc-alpha.c:4541
+#: config/tc-alpha.c:4538
msgid "No comma after .pdesc <entryname>"
msgstr ""
-#: config/tc-alpha.c:4561
+#: config/tc-alpha.c:4558
msgid "unknown procedure kind"
msgstr ""
-#: config/tc-alpha.c:4673
+#: config/tc-alpha.c:4653
msgid ".name directive not in link (.link) section"
msgstr ""
-#: config/tc-alpha.c:4681
+#: config/tc-alpha.c:4661
msgid ".name directive has no symbol"
msgstr ""
-#: config/tc-alpha.c:4716
+#: config/tc-alpha.c:4695
msgid "No symbol after .linkage"
msgstr ""
-#: config/tc-alpha.c:4769
+#: config/tc-alpha.c:4743
msgid "No symbol after .code_address"
msgstr ""
-#: config/tc-alpha.c:4796 config/tc-score.c:5607
+#: config/tc-alpha.c:4769 config/tc-score.c:5604
msgid "Bad .mask directive"
msgstr ""
-#: config/tc-alpha.c:4814
+#: config/tc-alpha.c:4787
msgid "Bad .fmask directive"
msgstr ""
-#: config/tc-alpha.c:4971
+#: config/tc-alpha.c:4944
#, c-format
msgid "Expected comma after name \"%s\""
msgstr ""
-#: config/tc-alpha.c:4983
+#: config/tc-alpha.c:4956
#, c-format
msgid "unhandled: .proc %s,%d"
msgstr ""
-#: config/tc-alpha.c:5017
+#: config/tc-alpha.c:4990
#, c-format
msgid "Tried to .set unrecognized mode `%s'"
msgstr ""
-#: config/tc-alpha.c:5043
+#: config/tc-alpha.c:5016
#, c-format
msgid "Bad base register, using $%d."
msgstr ""
-#: config/tc-alpha.c:5064
+#: config/tc-alpha.c:5037
#, c-format
msgid "Alignment too large: %d. assumed"
msgstr ""
-#: config/tc-alpha.c:5068 config/tc-d30v.c:2060
+#: config/tc-alpha.c:5041 config/tc-d30v.c:2060
msgid "Alignment negative: 0 assumed"
msgstr ""
-#: config/tc-alpha.c:5163 config/tc-alpha.c:5656
+#: config/tc-alpha.c:5136 config/tc-alpha.c:5628
#, c-format
msgid "Unknown CPU identifier `%s'"
msgstr ""
-#: config/tc-alpha.c:5354
+#: config/tc-alpha.c:5327
#, c-format
msgid "Chose GP value of %lx\n"
msgstr ""
-#: config/tc-alpha.c:5368
+#: config/tc-alpha.c:5341
msgid "bad .section directive: want a,s,w,x,M,S,G,T in string"
msgstr ""
-#: config/tc-alpha.c:5457
+#: config/tc-alpha.c:5430
#, c-format
msgid "internal error: can't hash opcode `%s': %s"
msgstr ""
-#: config/tc-alpha.c:5493
+#: config/tc-alpha.c:5466
#, c-format
msgid "internal error: can't hash macro `%s': %s"
msgstr ""
-#: config/tc-alpha.c:5578 config/tc-arm.c:6746 config/tc-arm.c:6758
+#: config/tc-alpha.c:5550 config/tc-arm.c:6818 config/tc-arm.c:6830
#: config/tc-i960.c:708 config/tc-xtensa.c:5315 config/tc-xtensa.c:5393
#: config/tc-xtensa.c:5510 config/tc-z80.c:1897
msgid "syntax error"
msgstr ""
-#: config/tc-alpha.c:5707
+#: config/tc-alpha.c:5679
msgid ""
"Alpha options:\n"
"-32addr\t\t\ttreat addresses as 32-bit values\n"
"\t\t\tthese variants include PALcode opcodes\n"
msgstr ""
-#: config/tc-alpha.c:5717
+#: config/tc-alpha.c:5689
msgid ""
"VMS options:\n"
"-+\t\t\tencode (don't truncate) names longer than 64 characters\n"
"-replace/-noreplace\tenable or disable the optimization of procedure calls\n"
msgstr ""
-#: config/tc-alpha.c:5968
+#: config/tc-alpha.c:5940
#, c-format
msgid "unhandled relocation type %s"
msgstr ""
-#: config/tc-alpha.c:5981
+#: config/tc-alpha.c:5953
msgid "non-absolute expression in constant field"
msgstr ""
-#: config/tc-alpha.c:5995
+#: config/tc-alpha.c:5967
#, c-format
msgid "type %d reloc done?\n"
msgstr ""
-#: config/tc-alpha.c:6042 config/tc-alpha.c:6049 config/tc-mips.c:9793
+#: config/tc-alpha.c:6014 config/tc-alpha.c:6021 config/tc-mips.c:11711
+#: config/tc-mips.c:12396
msgid "Used $at without \".set noat\""
msgstr ""
-#: config/tc-alpha.c:6218
+#: config/tc-alpha.c:6190
#, c-format
msgid "!samegp reloc against symbol without .prologue: %s"
msgstr ""
-#: config/tc-alpha.c:6262 config/tc-xtensa.c:5999
+#: config/tc-alpha.c:6234 config/tc-tilegx.c:1700 config/tc-tilepro.c:1499
+#: config/tc-xtensa.c:5999
#, c-format
msgid "cannot represent `%s' relocation in object file"
msgstr ""
-#: config/tc-alpha.c:6268
+#: config/tc-alpha.c:6240
#, c-format
msgid "internal error? cannot generate `%s' relocation"
msgstr ""
-#: config/tc-alpha.c:6364
+#: config/tc-alpha.c:6339
#, c-format
msgid "frame reg expected, using $%d."
msgstr ""
msgid "could not set architecture and machine"
msgstr ""
-#: config/tc-arc.c:212 config/tc-arm.c:22240 config/tc-score.c:6303
-#: config/tc-score.c:6532 config/tc-score.c:6537
+#: config/tc-arc.c:212 config/tc-arm.c:22402 config/tc-score.c:6299
+#: config/tc-score.c:6528 config/tc-score.c:6533
msgid "virtual memory exhausted"
msgstr ""
msgstr ""
#: config/tc-arc.c:1364 config/tc-dlx.c:1201 config/tc-i960.c:2639
-#: config/tc-m32r.c:2281 config/tc-sparc.c:3508
+#: config/tc-m32r.c:2281 config/tc-sparc.c:3651
#, c-format
msgid "internal error: can't export reloc type %d (`%s')"
msgstr ""
msgstr ""
#. xgettext:c-format.
-#: config/tc-arc.c:1759 config/tc-i370.c:2207 config/tc-mn10200.c:1141
+#: config/tc-arc.c:1759 config/tc-i370.c:2207 config/tc-mn10200.c:1142
#: config/tc-mn10300.c:1820 config/tc-ppc.c:2970 config/tc-s390.c:1506
#: config/tc-v850.c:2699
#, c-format
msgid "conditional branch follows set of flags"
msgstr ""
-#: config/tc-arc.c:1893 config/tc-arm.c:16170
+#: config/tc-arc.c:1893 config/tc-arm.c:16330
#, c-format
msgid "bad instruction `%s'"
msgstr ""
msgid "iWMMXt data register expected"
msgstr ""
-#: config/tc-arm.c:557 config/tc-arm.c:6525
+#: config/tc-arm.c:557 config/tc-arm.c:6597
msgid "iWMMXt control register expected"
msgstr ""
msgid "cannot use writeback with PC-relative addressing"
msgstr ""
-#: config/tc-arm.c:917
+#: config/tc-arm.c:727
+msgid "branch out of range"
+msgstr ""
+
+#: config/tc-arm.c:921
msgid "immediate expression requires a # prefix"
msgstr ""
-#: config/tc-arm.c:945 read.c:3664
+#: config/tc-arm.c:949 read.c:3663
msgid "missing expression"
msgstr ""
-#: config/tc-arm.c:945 config/tc-score.c:6519 expr.c:1357 read.c:2456
+#: config/tc-arm.c:949 config/tc-score.c:6515 expr.c:1357 read.c:2456
msgid "bad expression"
msgstr ""
-#: config/tc-arm.c:956 config/tc-i860.c:1004 config/tc-sparc.c:2880
+#: config/tc-arm.c:960 config/tc-i860.c:1004 config/tc-sparc.c:3023
msgid "bad segment"
msgstr ""
-#: config/tc-arm.c:975 config/tc-arm.c:4848 config/tc-i960.c:1300
-#: config/tc-score.c:1211
+#: config/tc-arm.c:979 config/tc-arm.c:4883 config/tc-i960.c:1300
+#: config/tc-score.c:1210
msgid "invalid constant"
msgstr ""
-#: config/tc-arm.c:1105
+#: config/tc-arm.c:1109
msgid "expected #constant"
msgstr ""
-#: config/tc-arm.c:1266
+#: config/tc-arm.c:1270
#, c-format
msgid "unexpected character `%c' in type specifier"
msgstr ""
-#: config/tc-arm.c:1283
+#: config/tc-arm.c:1287
#, c-format
msgid "bad size %d in type specifier"
msgstr ""
-#: config/tc-arm.c:1333
+#: config/tc-arm.c:1337
msgid "only one type should be specified for operand"
msgstr ""
-#: config/tc-arm.c:1339
+#: config/tc-arm.c:1343
msgid "vector type expected"
msgstr ""
-#: config/tc-arm.c:1411
+#: config/tc-arm.c:1415
msgid "can't redefine type for operand"
msgstr ""
-#: config/tc-arm.c:1422
+#: config/tc-arm.c:1426
msgid "only D registers may be indexed"
msgstr ""
-#: config/tc-arm.c:1428
+#: config/tc-arm.c:1432
msgid "can't change index for operand"
msgstr ""
-#: config/tc-arm.c:1444 config/tc-arm.c:3332 config/tc-arm.c:4430
+#: config/tc-arm.c:1448 config/tc-arm.c:3367 config/tc-arm.c:4465
msgid "constant expression required"
msgstr ""
-#: config/tc-arm.c:1491
+#: config/tc-arm.c:1495
msgid "register operand expected, but got scalar"
msgstr ""
-#: config/tc-arm.c:1524
+#: config/tc-arm.c:1528
msgid "scalar must have an index"
msgstr ""
-#: config/tc-arm.c:1529 config/tc-arm.c:14756 config/tc-arm.c:14806
-#: config/tc-arm.c:15221
+#: config/tc-arm.c:1533 config/tc-arm.c:14916 config/tc-arm.c:14966
+#: config/tc-arm.c:15381
msgid "scalar index out of range"
msgstr ""
-#: config/tc-arm.c:1577
+#: config/tc-arm.c:1581
msgid "bad range in register list"
msgstr ""
-#: config/tc-arm.c:1585 config/tc-arm.c:1594 config/tc-arm.c:1635
+#: config/tc-arm.c:1589 config/tc-arm.c:1598 config/tc-arm.c:1639
#, c-format
msgid "Warning: duplicated register (r%d) in register list"
msgstr ""
-#: config/tc-arm.c:1597
+#: config/tc-arm.c:1601
msgid "Warning: register range not in ascending order"
msgstr ""
-#: config/tc-arm.c:1608
+#: config/tc-arm.c:1612
msgid "missing `}'"
msgstr ""
-#: config/tc-arm.c:1624
+#: config/tc-arm.c:1628
msgid "invalid register mask"
msgstr ""
-#: config/tc-arm.c:1706
+#: config/tc-arm.c:1710
msgid "expecting {"
msgstr ""
-#: config/tc-arm.c:1761 config/tc-arm.c:1805
+#: config/tc-arm.c:1765 config/tc-arm.c:1809
msgid "register out of range in list"
msgstr ""
-#: config/tc-arm.c:1777 config/tc-arm.c:1822 config/tc-h8300.c:1040
-#: config/tc-mips.c:10894 config/tc-mips.c:10916
+#: config/tc-arm.c:1781 config/tc-arm.c:1826 config/tc-h8300.c:1040
+#: config/tc-mips.c:13602 config/tc-mips.c:13624
msgid "invalid register list"
msgstr ""
-#: config/tc-arm.c:1783 config/tc-arm.c:3846 config/tc-arm.c:3979
+#: config/tc-arm.c:1787 config/tc-arm.c:3881 config/tc-arm.c:4014
msgid "register list not in ascending order"
msgstr ""
-#: config/tc-arm.c:1814
+#: config/tc-arm.c:1818
msgid "register range not in ascending order"
msgstr ""
-#: config/tc-arm.c:1847
+#: config/tc-arm.c:1851
msgid "non-contiguous register range"
msgstr ""
-#: config/tc-arm.c:1906
+#: config/tc-arm.c:1910
msgid "register stride must be 1 or 2"
msgstr ""
-#: config/tc-arm.c:1907
+#: config/tc-arm.c:1911
msgid "mismatched element/structure types in list"
msgstr ""
-#: config/tc-arm.c:1971
+#: config/tc-arm.c:1975
msgid "don't use Rn-Rm syntax with non-unit stride"
msgstr ""
-#: config/tc-arm.c:2026
+#: config/tc-arm.c:2030
msgid "error parsing element/structure list"
msgstr ""
-#: config/tc-arm.c:2032
+#: config/tc-arm.c:2036
msgid "expected }"
msgstr ""
-#: config/tc-arm.c:2089
+#: config/tc-arm.c:2093
#, c-format
msgid "ignoring attempt to redefine built-in register '%s'"
msgstr ""
-#: config/tc-arm.c:2094
+#: config/tc-arm.c:2098
#, c-format
msgid "ignoring redefinition of register alias '%s'"
msgstr ""
-#: config/tc-arm.c:2122
+#: config/tc-arm.c:2126
msgid "attempt to redefine typed alias"
msgstr ""
-#: config/tc-arm.c:2161
+#: config/tc-arm.c:2165
#, c-format
msgid "unknown register '%s' -- .req ignored"
msgstr ""
-#: config/tc-arm.c:2256
+#: config/tc-arm.c:2260
msgid "bad type for register"
msgstr ""
-#: config/tc-arm.c:2267
+#: config/tc-arm.c:2271
msgid "expression must be constant"
msgstr ""
-#: config/tc-arm.c:2284
+#: config/tc-arm.c:2288
msgid "can't redefine the type of a register alias"
msgstr ""
-#: config/tc-arm.c:2291
+#: config/tc-arm.c:2295
msgid "you must specify a single type only"
msgstr ""
-#: config/tc-arm.c:2304
+#: config/tc-arm.c:2308
msgid "can't redefine the index of a scalar alias"
msgstr ""
-#: config/tc-arm.c:2312
+#: config/tc-arm.c:2316
msgid "scalar index must be constant"
msgstr ""
-#: config/tc-arm.c:2321
+#: config/tc-arm.c:2325
msgid "expecting ]"
msgstr ""
-#: config/tc-arm.c:2368
+#: config/tc-arm.c:2372
msgid "invalid syntax for .req directive"
msgstr ""
-#: config/tc-arm.c:2374
+#: config/tc-arm.c:2378
msgid "invalid syntax for .dn directive"
msgstr ""
-#: config/tc-arm.c:2380
+#: config/tc-arm.c:2384
msgid "invalid syntax for .qn directive"
msgstr ""
-#: config/tc-arm.c:2406
+#: config/tc-arm.c:2410
msgid "invalid syntax for .unreq directive"
msgstr ""
-#: config/tc-arm.c:2413
+#: config/tc-arm.c:2417
#, c-format
msgid "unknown register alias '%s'"
msgstr ""
-#: config/tc-arm.c:2415
+#: config/tc-arm.c:2419
#, c-format
msgid "ignoring attempt to use .unreq on fixed register name: '%s'"
msgstr ""
-#: config/tc-arm.c:2666
+#: config/tc-arm.c:2687
#, c-format
msgid "Failed to find real start of function: %s\n"
msgstr ""
-#: config/tc-arm.c:2683
+#: config/tc-arm.c:2704
msgid "selected processor does not support THUMB opcodes"
msgstr ""
-#: config/tc-arm.c:2696
+#: config/tc-arm.c:2717
msgid "selected processor does not support ARM opcodes"
msgstr ""
-#: config/tc-arm.c:2708
+#: config/tc-arm.c:2729
#, c-format
msgid "invalid instruction size selected (%d)"
msgstr ""
-#: config/tc-arm.c:2740
+#: config/tc-arm.c:2761
#, c-format
msgid "invalid operand to .code directive (%d) (expecting 16 or 32)"
msgstr ""
-#: config/tc-arm.c:2796
+#: config/tc-arm.c:2817
#, c-format
msgid "expected comma after name \"%s\""
msgstr ""
-#: config/tc-arm.c:2846 config/tc-m32r.c:588
+#: config/tc-arm.c:2867 config/tc-m32r.c:588
#, c-format
msgid "symbol `%s' already defined"
msgstr ""
-#: config/tc-arm.c:2880
+#: config/tc-arm.c:2901
#, c-format
msgid "unrecognized syntax mode \"%s\""
msgstr ""
-#: config/tc-arm.c:2901
+#: config/tc-arm.c:2922
#, c-format
msgid "alignment too large: %d assumed"
msgstr ""
-#: config/tc-arm.c:2904
+#: config/tc-arm.c:2925
msgid "alignment negative. 0 assumed."
msgstr ""
-#: config/tc-arm.c:3054
+#: config/tc-arm.c:3075
msgid "literal pool overflow"
msgstr ""
-#: config/tc-arm.c:3210 config/tc-arm.c:6460
+#: config/tc-arm.c:3245 config/tc-arm.c:6532
msgid "unrecognized relocation suffix"
msgstr ""
-#: config/tc-arm.c:3225
+#: config/tc-arm.c:3260
msgid "(plt) is only valid on branch targets"
msgstr ""
-#: config/tc-arm.c:3231 config/tc-s390.c:1134 config/tc-s390.c:1771
+#: config/tc-arm.c:3266 config/tc-s390.c:1134 config/tc-s390.c:1771
#: config/tc-xtensa.c:1591
#, c-format
msgid "%s relocations do not fit in %d bytes"
msgstr ""
-#: config/tc-arm.c:3308
+#: config/tc-arm.c:3343
msgid ".inst.n operand too big. Use .inst.w instead"
msgstr ""
-#: config/tc-arm.c:3328
+#: config/tc-arm.c:3363
msgid "cannot determine Thumb instruction size. Use .inst.n/.inst.w instead"
msgstr ""
-#: config/tc-arm.c:3358
+#: config/tc-arm.c:3393
msgid "width suffixes are invalid in ARM mode"
msgstr ""
-#: config/tc-arm.c:3400 dwarf2dbg.c:711
+#: config/tc-arm.c:3435 dwarf2dbg.c:744
msgid "expected 0 or 1"
msgstr ""
-#: config/tc-arm.c:3404
+#: config/tc-arm.c:3439
msgid "missing comma"
msgstr ""
-#: config/tc-arm.c:3437
+#: config/tc-arm.c:3472
msgid "duplicate .fnstart directive"
msgstr ""
-#: config/tc-arm.c:3468 config/tc-tic6x.c:413
+#: config/tc-arm.c:3503 config/tc-tic6x.c:413
msgid "duplicate .handlerdata directive"
msgstr ""
-#: config/tc-arm.c:3487
+#: config/tc-arm.c:3522
msgid ".fnend directive without .fnstart"
msgstr ""
-#: config/tc-arm.c:3553 config/tc-tic6x.c:394
+#: config/tc-arm.c:3588 config/tc-tic6x.c:394
msgid "personality routine specified for cantunwind frame"
msgstr ""
-#: config/tc-arm.c:3570 config/tc-tic6x.c:455
+#: config/tc-arm.c:3605 config/tc-tic6x.c:455
msgid "duplicate .personalityindex directive"
msgstr ""
-#: config/tc-arm.c:3577 config/tc-tic6x.c:462
+#: config/tc-arm.c:3612 config/tc-tic6x.c:462
msgid "bad personality routine number"
msgstr ""
-#: config/tc-arm.c:3599 config/tc-tic6x.c:479
+#: config/tc-arm.c:3634 config/tc-tic6x.c:479
msgid "duplicate .personality directive"
msgstr ""
-#: config/tc-arm.c:3622 config/tc-arm.c:3750 config/tc-arm.c:3798
+#: config/tc-arm.c:3657 config/tc-arm.c:3785 config/tc-arm.c:3833
msgid "expected register list"
msgstr ""
-#: config/tc-arm.c:3704
+#: config/tc-arm.c:3739
msgid "expected , <constant>"
msgstr ""
-#: config/tc-arm.c:3713
+#: config/tc-arm.c:3748
msgid "number of registers must be in the range [1:4]"
msgstr ""
-#: config/tc-arm.c:3860 config/tc-arm.c:3993
+#: config/tc-arm.c:3895 config/tc-arm.c:4028
msgid "bad register range"
msgstr ""
-#: config/tc-arm.c:4050
+#: config/tc-arm.c:4085
msgid "register expected"
msgstr ""
-#: config/tc-arm.c:4060
+#: config/tc-arm.c:4095
msgid "FPA .unwind_save does not take a register list"
msgstr ""
-#: config/tc-arm.c:4079
+#: config/tc-arm.c:4114
msgid ".unwind_save does not support this kind of register"
msgstr ""
-#: config/tc-arm.c:4118
+#: config/tc-arm.c:4153
msgid "SP and PC not permitted in .unwind_movsp directive"
msgstr ""
-#: config/tc-arm.c:4123
+#: config/tc-arm.c:4158
msgid "unexpected .unwind_movsp directive"
msgstr ""
-#: config/tc-arm.c:4150
+#: config/tc-arm.c:4185
msgid "stack increment must be multiple of 4"
msgstr ""
-#: config/tc-arm.c:4182
+#: config/tc-arm.c:4217
msgid "expected <reg>, <reg>"
msgstr ""
-#: config/tc-arm.c:4200
+#: config/tc-arm.c:4235
msgid "register must be either sp or set by a previousunwind_movsp directive"
msgstr ""
-#: config/tc-arm.c:4239
+#: config/tc-arm.c:4274
msgid "expected <offset>, <opcode>"
msgstr ""
-#: config/tc-arm.c:4251
+#: config/tc-arm.c:4286
msgid "unwind opcode too long"
msgstr ""
-#: config/tc-arm.c:4256
+#: config/tc-arm.c:4291
msgid "invalid unwind opcode"
msgstr ""
-#: config/tc-arm.c:4436 config/tc-arm.c:5346 config/tc-arm.c:9360
-#: config/tc-arm.c:9888 config/tc-arm.c:13218 config/tc-arm.c:21248
-#: config/tc-arm.c:21273 config/tc-arm.c:21281 config/tc-z8k.c:1144
+#: config/tc-arm.c:4471 config/tc-arm.c:5410 config/tc-arm.c:9497
+#: config/tc-arm.c:10032 config/tc-arm.c:13378 config/tc-arm.c:21410
+#: config/tc-arm.c:21435 config/tc-arm.c:21443 config/tc-z8k.c:1144
#: config/tc-z8k.c:1154
msgid "immediate value out of range"
msgstr ""
-#: config/tc-arm.c:4601
+#: config/tc-arm.c:4636
msgid "invalid FPA immediate expression"
msgstr ""
-#: config/tc-arm.c:4725 config/tc-arm.c:4734
+#: config/tc-arm.c:4760 config/tc-arm.c:4769
msgid "shift expression expected"
msgstr ""
-#: config/tc-arm.c:4748
+#: config/tc-arm.c:4783
msgid "'LSL' or 'ASR' required"
msgstr ""
-#: config/tc-arm.c:4756
+#: config/tc-arm.c:4791
msgid "'LSL' required"
msgstr ""
-#: config/tc-arm.c:4764
+#: config/tc-arm.c:4799
msgid "'ASR' required"
msgstr ""
-#: config/tc-arm.c:4836 config/tc-arm.c:5340 config/tc-arm.c:7168
+#: config/tc-arm.c:4871 config/tc-arm.c:5404 config/tc-arm.c:7259
msgid "constant expression expected"
msgstr ""
-#: config/tc-arm.c:4843
+#: config/tc-arm.c:4878
msgid "invalid rotation"
msgstr ""
-#: config/tc-arm.c:5003 config/tc-arm.c:5167
+#: config/tc-arm.c:5037 config/tc-arm.c:5201
msgid "unknown group relocation"
msgstr ""
-#: config/tc-arm.c:5039
+#: config/tc-arm.c:5073
msgid "alignment must be constant"
msgstr ""
-#: config/tc-arm.c:5198
+#: config/tc-arm.c:5232
msgid "this group relocation is not allowed on this instruction"
msgstr ""
-#: config/tc-arm.c:5219 config/tc-arm.c:5747
+#: config/tc-arm.c:5269 config/tc-arm.c:5817
msgid "']' expected"
msgstr ""
-#: config/tc-arm.c:5237
+#: config/tc-arm.c:5287
msgid "'}' expected at end of 'option' field"
msgstr ""
-#: config/tc-arm.c:5242
+#: config/tc-arm.c:5292
msgid "cannot combine index with option"
msgstr ""
-#: config/tc-arm.c:5255
+#: config/tc-arm.c:5305
msgid "cannot combine pre- and post-indexing"
msgstr ""
-#: config/tc-arm.c:5478
+#: config/tc-arm.c:5548
msgid "unexpected bit specified after APSR"
msgstr ""
-#: config/tc-arm.c:5490
+#: config/tc-arm.c:5560
msgid "selected processor does not support DSP extension"
msgstr ""
-#: config/tc-arm.c:5502
+#: config/tc-arm.c:5572
msgid "bad bitmask specified after APSR"
msgstr ""
-#: config/tc-arm.c:5526
+#: config/tc-arm.c:5596
msgid "writing to APSR without specifying a bitmask is deprecated"
msgstr ""
-#: config/tc-arm.c:5538 config/tc-arm.c:10977 config/tc-arm.c:11016
-#: config/tc-arm.c:11020
+#: config/tc-arm.c:5608 config/tc-arm.c:11125 config/tc-arm.c:11164
+#: config/tc-arm.c:11168
msgid "selected processor does not support requested special purpose register"
msgstr ""
-#: config/tc-arm.c:5543
+#: config/tc-arm.c:5613
msgid "flag for {c}psr instruction expected"
msgstr ""
-#: config/tc-arm.c:5568
+#: config/tc-arm.c:5638
msgid "unrecognized CPS flag"
msgstr ""
-#: config/tc-arm.c:5575
+#: config/tc-arm.c:5645
msgid "missing CPS flags"
msgstr ""
-#: config/tc-arm.c:5598 config/tc-arm.c:5604
+#: config/tc-arm.c:5668 config/tc-arm.c:5674
msgid "valid endian specifiers are be or le"
msgstr ""
-#: config/tc-arm.c:5626
+#: config/tc-arm.c:5696
msgid "missing rotation field after comma"
msgstr ""
-#: config/tc-arm.c:5641
+#: config/tc-arm.c:5711
msgid "rotation can only be 0, 8, 16, or 24"
msgstr ""
-#: config/tc-arm.c:5670
+#: config/tc-arm.c:5740
msgid "condition required"
msgstr ""
-#: config/tc-arm.c:5709 config/tc-arm.c:7755
+#: config/tc-arm.c:5779 config/tc-arm.c:7846
msgid "'[' expected"
msgstr ""
-#: config/tc-arm.c:5722
+#: config/tc-arm.c:5792
msgid "',' expected"
msgstr ""
-#: config/tc-arm.c:5739
+#: config/tc-arm.c:5809
msgid "invalid shift"
msgstr ""
-#: config/tc-arm.c:5812
+#: config/tc-arm.c:5882
msgid "can't use Neon quad register here"
msgstr ""
-#: config/tc-arm.c:5878
+#: config/tc-arm.c:5948
msgid "expected <Rm> or <Dm> or <Qm> operand"
msgstr ""
-#: config/tc-arm.c:5958
+#: config/tc-arm.c:6028
msgid "parse error"
msgstr ""
-#: config/tc-arm.c:5968 read.c:2127
+#: config/tc-arm.c:6038 read.c:2127
msgid "expected comma"
msgstr ""
#. ISB can only take SY as an option.
-#: config/tc-arm.c:6227
+#: config/tc-arm.c:6298
msgid "invalid barrier type"
msgstr ""
-#: config/tc-arm.c:6364
+#: config/tc-arm.c:6435
msgid "immediate value is out of range"
msgstr ""
-#: config/tc-arm.c:6510
+#: config/tc-arm.c:6582
msgid "iWMMXt data or control register expected"
msgstr ""
-#: config/tc-arm.c:6550
+#: config/tc-arm.c:6622
msgid "Banked registers are not available with this architecture."
msgstr ""
-#: config/tc-arm.c:6675
+#: config/tc-arm.c:6747
#, c-format
msgid "unhandled operand code %d"
msgstr ""
-#: config/tc-arm.c:6772 config/tc-score.c:264
+#: config/tc-arm.c:6844 config/tc-score.c:264
msgid "garbage following instruction"
msgstr ""
#. If REG is R13 (the stack pointer), warn that its use is
#. deprecated.
-#: config/tc-arm.c:6813
+#: config/tc-arm.c:6885
msgid "use of r13 is deprecated"
msgstr ""
-#: config/tc-arm.c:6883
+#: config/tc-arm.c:6955
msgid "D register out of range for selected VFP version"
msgstr ""
-#: config/tc-arm.c:6962
+#: config/tc-arm.c:7038
msgid "instruction does not accept preindexed addressing"
msgstr ""
#. unindexed - only for coprocessor
-#: config/tc-arm.c:6978 config/tc-arm.c:9153
+#: config/tc-arm.c:7054 config/tc-arm.c:9290
msgid "instruction does not accept unindexed addressing"
msgstr ""
-#: config/tc-arm.c:6986
+#: config/tc-arm.c:7062
msgid "destination register same as write-back base"
msgstr ""
-#: config/tc-arm.c:6987
+#: config/tc-arm.c:7063
msgid "source register same as write-back base"
msgstr ""
-#: config/tc-arm.c:7037
+#: config/tc-arm.c:7113
msgid "use of PC in this instruction is deprecated"
msgstr ""
-#: config/tc-arm.c:7055
+#: config/tc-arm.c:7136
msgid "instruction does not accept scaled register index"
msgstr ""
-#: config/tc-arm.c:7101
+#: config/tc-arm.c:7188
msgid "instruction does not support unindexed addressing"
msgstr ""
-#: config/tc-arm.c:7116
+#: config/tc-arm.c:7203
msgid "pc may not be used with write-back"
msgstr ""
-#: config/tc-arm.c:7121
+#: config/tc-arm.c:7208
msgid "instruction does not support writeback"
msgstr ""
-#: config/tc-arm.c:7163
+#: config/tc-arm.c:7254
msgid "invalid pseudo operation"
msgstr ""
-#: config/tc-arm.c:7209
+#: config/tc-arm.c:7300
msgid "literal pool insertion failed"
msgstr ""
-#: config/tc-arm.c:7268
+#: config/tc-arm.c:7359
msgid "Rn must not overlap other operands"
msgstr ""
-#: config/tc-arm.c:7273
+#: config/tc-arm.c:7364
msgid "swp{b} use is deprecated for this architecture"
msgstr ""
-#: config/tc-arm.c:7370 config/tc-arm.c:9720
+#: config/tc-arm.c:7461 config/tc-arm.c:9864
msgid "bad barrier type"
msgstr ""
-#: config/tc-arm.c:7381 config/tc-arm.c:7400 config/tc-arm.c:7413
-#: config/tc-arm.c:9732 config/tc-arm.c:9763 config/tc-arm.c:9785
+#: config/tc-arm.c:7472 config/tc-arm.c:7491 config/tc-arm.c:7504
+#: config/tc-arm.c:9876 config/tc-arm.c:9907 config/tc-arm.c:9929
msgid "bit-field extends past end of register"
msgstr ""
-#: config/tc-arm.c:7443
+#: config/tc-arm.c:7534
msgid "the only valid suffixes here are '(plt)' and '(tlscall)'"
msgstr ""
-#: config/tc-arm.c:7496
+#: config/tc-arm.c:7587
msgid "use of r15 in blx in ARM mode is not really useful"
msgstr ""
-#: config/tc-arm.c:7518
+#: config/tc-arm.c:7609
msgid "use of r15 in bx in ARM mode is not really useful"
msgstr ""
-#: config/tc-arm.c:7543
+#: config/tc-arm.c:7634
msgid "use of r15 in bxj is not really useful"
msgstr ""
-#: config/tc-arm.c:7722 config/tc-arm.c:7731
+#: config/tc-arm.c:7813 config/tc-arm.c:7822
msgid "writeback of base register is UNPREDICTABLE"
msgstr ""
-#: config/tc-arm.c:7725
+#: config/tc-arm.c:7816
msgid "writeback of base register when in register list is UNPREDICTABLE"
msgstr ""
-#: config/tc-arm.c:7735
+#: config/tc-arm.c:7826
msgid "if writeback register is in list, it must be the lowest reg in the list"
msgstr ""
-#: config/tc-arm.c:7750
-msgid "first destination register must be even"
+#: config/tc-arm.c:7841
+msgid "first transfer register must be even"
msgstr ""
-#: config/tc-arm.c:7753 config/tc-arm.c:7822
-msgid "can only load two consecutive registers"
+#: config/tc-arm.c:7844
+msgid "can only transfer two consecutive registers"
msgstr ""
#. If op 1 were present and equal to PC, this function wouldn't
#. have been called in the first place.
#. If op 2 were present and equal to PC, this function wouldn't
#. have been called in the first place.
-#: config/tc-arm.c:7754 config/tc-arm.c:7825 config/tc-arm.c:8423
-#: config/tc-arm.c:10504
+#: config/tc-arm.c:7845 config/tc-arm.c:7915 config/tc-arm.c:8544
+#: config/tc-arm.c:10652
msgid "r14 not allowed here"
msgstr ""
-#: config/tc-arm.c:7768
-msgid "base register written back, and overlaps second destination register"
+#: config/tc-arm.c:7857
+msgid "base register written back, and overlaps second transfer register"
msgstr ""
-#: config/tc-arm.c:7776
-msgid "index register overlaps destination register"
+#: config/tc-arm.c:7867
+msgid "index register overlaps transfer register"
msgstr ""
-#: config/tc-arm.c:7806 config/tc-arm.c:8405
+#: config/tc-arm.c:7896 config/tc-arm.c:8511
msgid "offset must be zero in ARM encoding"
msgstr ""
-#: config/tc-arm.c:7819 config/tc-arm.c:8417
+#: config/tc-arm.c:7909 config/tc-arm.c:8538
msgid "even register required"
msgstr ""
-#: config/tc-arm.c:7850 config/tc-arm.c:7882
+#: config/tc-arm.c:7912
+msgid "can only load two consecutive registers"
+msgstr ""
+
+#: config/tc-arm.c:7930
+msgid "ldr to register 15 must be 4-byte alligned"
+msgstr ""
+
+#: config/tc-arm.c:7953 config/tc-arm.c:7985
msgid "this instruction requires a post-indexed address"
msgstr ""
-#: config/tc-arm.c:7909
+#: config/tc-arm.c:8012
msgid "Rd and Rm should be different in mla"
msgstr ""
-#: config/tc-arm.c:7933 config/tc-arm.c:10848
+#: config/tc-arm.c:8036 config/tc-arm.c:10996
msgid ":lower16: not allowed this instruction"
msgstr ""
-#: config/tc-arm.c:7935
+#: config/tc-arm.c:8038
msgid ":upper16: not allowed instruction"
msgstr ""
-#: config/tc-arm.c:7954 config/tc-arm.c:7997
+#: config/tc-arm.c:8057 config/tc-arm.c:8100
msgid "operand 1 must be FPSCR"
msgstr ""
-#: config/tc-arm.c:8016
+#: config/tc-arm.c:8119
msgid "operand 0 must be FPSCR"
msgstr ""
-#: config/tc-arm.c:8036 config/tc-arm.c:10966
+#: config/tc-arm.c:8139 config/tc-arm.c:11114
msgid "bad register for mrs"
msgstr ""
-#: config/tc-arm.c:8043 config/tc-arm.c:10983
+#: config/tc-arm.c:8146 config/tc-arm.c:11131
msgid "'APSR', 'CPSR' or 'SPSR' expected"
msgstr ""
-#: config/tc-arm.c:8084
+#: config/tc-arm.c:8187
msgid "Rd and Rm should be different in mul"
msgstr ""
-#: config/tc-arm.c:8103 config/tc-arm.c:8350 config/tc-arm.c:11117
+#: config/tc-arm.c:8206 config/tc-arm.c:8456 config/tc-arm.c:11265
msgid "rdhi and rdlo must be different"
msgstr ""
-#: config/tc-arm.c:8109
+#: config/tc-arm.c:8212
msgid "rdhi, rdlo and rm must all be different"
msgstr ""
-#: config/tc-arm.c:8175
+#: config/tc-arm.c:8278
msgid "'[' expected after PLD mnemonic"
msgstr ""
-#: config/tc-arm.c:8177 config/tc-arm.c:8192
+#: config/tc-arm.c:8280 config/tc-arm.c:8295
msgid "post-indexed expression used in preload instruction"
msgstr ""
-#: config/tc-arm.c:8179 config/tc-arm.c:8194
+#: config/tc-arm.c:8282 config/tc-arm.c:8297
msgid "writeback used in preload instruction"
msgstr ""
-#: config/tc-arm.c:8181 config/tc-arm.c:8196
+#: config/tc-arm.c:8284 config/tc-arm.c:8299
msgid "unindexed addressing used in preload instruction"
msgstr ""
-#: config/tc-arm.c:8190
+#: config/tc-arm.c:8293
msgid "'[' expected after PLI mnemonic"
msgstr ""
-#: config/tc-arm.c:8376
+#: config/tc-arm.c:8401 config/tc-arm.c:11639 config/tc-arm.c:11671
+#: config/tc-arm.c:11714
+msgid "extraneous shift as part of operand to shift insn"
+msgstr ""
+
+#: config/tc-arm.c:8482
msgid "SRS base register must be r13"
msgstr ""
-#: config/tc-arm.c:8420
+#: config/tc-arm.c:8541
msgid "can only store two consecutive registers"
msgstr ""
-#: config/tc-arm.c:8515 config/tc-arm.c:8532
+#: config/tc-arm.c:8636 config/tc-arm.c:8653
msgid "only two consecutive VFP SP registers allowed here"
msgstr ""
-#: config/tc-arm.c:8560 config/tc-arm.c:8575
+#: config/tc-arm.c:8681 config/tc-arm.c:8696
msgid "this addressing mode requires base-register writeback"
msgstr ""
-#: config/tc-arm.c:8749
+#. If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
+#. i.e. immbits must be in range 0 - 16.
+#: config/tc-arm.c:8813
+msgid "immediate value out of range, expected range [0, 16]"
+msgstr ""
+
+#. If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
+#. i.e. immbits must be in range 0 - 31.
+#: config/tc-arm.c:8820
+msgid "immediate value out of range, expected range [1, 32]"
+msgstr ""
+
+#: config/tc-arm.c:8886
msgid "this instruction does not support indexing"
msgstr ""
-#: config/tc-arm.c:8772
+#: config/tc-arm.c:8909
msgid "only r15 allowed here"
msgstr ""
-#: config/tc-arm.c:8907
+#: config/tc-arm.c:9044
msgid "immediate operand requires iWMMXt2"
msgstr ""
-#: config/tc-arm.c:9051
+#: config/tc-arm.c:9188
msgid "shift by register not allowed in thumb mode"
msgstr ""
-#: config/tc-arm.c:9063 config/tc-arm.c:11660 config/tc-arm.c:20630
+#: config/tc-arm.c:9200 config/tc-arm.c:11820 config/tc-arm.c:20800
msgid "shift expression is too large"
msgstr ""
-#: config/tc-arm.c:9090
+#: config/tc-arm.c:9227
msgid "Instruction does not support =N addresses"
msgstr ""
-#: config/tc-arm.c:9096
+#: config/tc-arm.c:9233
msgid "cannot use register index with this instruction"
msgstr ""
-#: config/tc-arm.c:9098
+#: config/tc-arm.c:9235
msgid "Thumb does not support negative register indexing"
msgstr ""
-#: config/tc-arm.c:9100
+#: config/tc-arm.c:9237
msgid "Thumb does not support register post-indexing"
msgstr ""
-#: config/tc-arm.c:9102
+#: config/tc-arm.c:9239
msgid "Thumb does not support register indexing with writeback"
msgstr ""
-#: config/tc-arm.c:9104
+#: config/tc-arm.c:9241
msgid "Thumb supports only LSL in shifted register indexing"
msgstr ""
-#: config/tc-arm.c:9113 config/tc-arm.c:14558
+#: config/tc-arm.c:9250 config/tc-arm.c:14718
msgid "shift out of range"
msgstr ""
-#: config/tc-arm.c:9122
+#: config/tc-arm.c:9259
msgid "cannot use writeback with this instruction"
msgstr ""
-#: config/tc-arm.c:9143
+#: config/tc-arm.c:9280
msgid "cannot use post-indexing with PC-relative addressing"
msgstr ""
-#: config/tc-arm.c:9144
+#: config/tc-arm.c:9281
msgid "cannot use post-indexing with this instruction"
msgstr ""
-#: config/tc-arm.c:9355
+#: config/tc-arm.c:9492
msgid "only SUBS PC, LR, #const allowed"
msgstr ""
-#: config/tc-arm.c:9434 config/tc-arm.c:9585 config/tc-arm.c:9682
-#: config/tc-arm.c:10927 config/tc-arm.c:11223
+#: config/tc-arm.c:9574 config/tc-arm.c:9729 config/tc-arm.c:9826
+#: config/tc-arm.c:11075 config/tc-arm.c:11371
msgid "shift must be constant"
msgstr ""
-#: config/tc-arm.c:9461 config/tc-arm.c:9600 config/tc-arm.c:9697
-#: config/tc-arm.c:10940
+#: config/tc-arm.c:9579
+msgid "shift value over 3 not allowed in thumb mode"
+msgstr ""
+
+#: config/tc-arm.c:9581
+msgid "only LSL shift allowed in thumb mode"
+msgstr ""
+
+#: config/tc-arm.c:9605 config/tc-arm.c:9744 config/tc-arm.c:9841
+#: config/tc-arm.c:11088
msgid "unshifted register required"
msgstr ""
-#: config/tc-arm.c:9476 config/tc-arm.c:9708 config/tc-arm.c:11078
+#: config/tc-arm.c:9620 config/tc-arm.c:9852 config/tc-arm.c:11226
msgid "dest must overlap one source register"
msgstr ""
-#: config/tc-arm.c:9603
+#: config/tc-arm.c:9747
msgid "dest and source1 must be the same register"
msgstr ""
-#: config/tc-arm.c:9884
+#: config/tc-arm.c:10028
msgid "instruction is always unconditional"
msgstr ""
-#: config/tc-arm.c:9986
+#: config/tc-arm.c:10130
msgid "selected processor does not support 'A' form of this instruction"
msgstr ""
-#: config/tc-arm.c:9989
+#: config/tc-arm.c:10133
msgid "Thumb does not support the 2-argument form of this instruction"
msgstr ""
-#: config/tc-arm.c:10097
+#: config/tc-arm.c:10241
msgid "SP not allowed in register list"
msgstr ""
-#: config/tc-arm.c:10101 config/tc-arm.c:10207
+#: config/tc-arm.c:10245 config/tc-arm.c:10351
msgid ""
"having the base register in the register list when using write back is "
"UNPREDICTABLE"
msgstr ""
-#: config/tc-arm.c:10109
+#: config/tc-arm.c:10253
msgid "LR and PC should not both be in register list"
msgstr ""
-#: config/tc-arm.c:10117
+#: config/tc-arm.c:10261
msgid "PC not allowed in register list"
msgstr ""
-#: config/tc-arm.c:10159
+#: config/tc-arm.c:10303
msgid "Thumb load/store multiple does not support {reglist}^"
msgstr ""
-#: config/tc-arm.c:10184 config/tc-arm.c:10261
+#: config/tc-arm.c:10328 config/tc-arm.c:10405
#, c-format
msgid "value stored for r%d is UNKNOWN"
msgstr ""
-#: config/tc-arm.c:10254
+#: config/tc-arm.c:10398
msgid "Thumb-2 instruction only valid in unified syntax"
msgstr ""
-#: config/tc-arm.c:10258 config/tc-arm.c:10268
+#: config/tc-arm.c:10402 config/tc-arm.c:10412
msgid "this instruction will write back the base register"
msgstr ""
-#: config/tc-arm.c:10271
+#: config/tc-arm.c:10415
msgid "this instruction will not write back the base register"
msgstr ""
-#: config/tc-arm.c:10302
+#: config/tc-arm.c:10446
msgid "r14 not allowed as first register when second register is omitted"
msgstr ""
-#: config/tc-arm.c:10402
+#: config/tc-arm.c:10546
msgid ""
"This instruction may be unpredictable if executed on M-profile cores with "
"interrupts enabled."
msgstr ""
-#: config/tc-arm.c:10427 config/tc-arm.c:10440 config/tc-arm.c:10476
+#: config/tc-arm.c:10575 config/tc-arm.c:10588 config/tc-arm.c:10624
msgid "Thumb does not support this addressing mode"
msgstr ""
-#: config/tc-arm.c:10444
+#: config/tc-arm.c:10592
msgid "byte or halfword not valid for base register"
msgstr ""
-#: config/tc-arm.c:10447
+#: config/tc-arm.c:10595
msgid "r15 based store not allowed"
msgstr ""
-#: config/tc-arm.c:10449
+#: config/tc-arm.c:10597
msgid "invalid base register for register offset"
msgstr ""
-#: config/tc-arm.c:10631
+#: config/tc-arm.c:10779
#, c-format
msgid ""
"Use of r%u as a source register is deprecated when r%u is the destination "
"register."
msgstr ""
-#: config/tc-arm.c:10804
+#: config/tc-arm.c:10952
msgid "shifts in CMP/MOV instructions are only supported in unified syntax"
msgstr ""
-#: config/tc-arm.c:10832
+#: config/tc-arm.c:10980
msgid "only lo regs allowed with immediate"
msgstr ""
-#: config/tc-arm.c:10853
+#: config/tc-arm.c:11001
msgid ":upper16: not allowed this instruction"
msgstr ""
-#: config/tc-arm.c:11001
+#: config/tc-arm.c:11149
msgid "Thumb encoding does not support an immediate here"
msgstr ""
-#: config/tc-arm.c:11083
+#: config/tc-arm.c:11231
msgid "Thumb-2 MUL must not set flags"
msgstr ""
-#: config/tc-arm.c:11148
+#: config/tc-arm.c:11296
msgid "Thumb does not support NOP with hints"
msgstr ""
-#: config/tc-arm.c:11286
+#: config/tc-arm.c:11434
msgid "push/pop do not support {reglist}^"
msgstr ""
-#: config/tc-arm.c:11309
+#: config/tc-arm.c:11457
msgid "invalid register list to push/pop instruction"
msgstr ""
-#: config/tc-arm.c:11542
+#: config/tc-arm.c:11698
msgid "source1 and dest must be same register"
msgstr ""
-#: config/tc-arm.c:11563
+#: config/tc-arm.c:11723
msgid "ror #imm not supported"
msgstr ""
-#: config/tc-arm.c:11614
+#: config/tc-arm.c:11774
msgid "SMC is not permitted on this architecture"
msgstr ""
-#: config/tc-arm.c:11777
+#: config/tc-arm.c:11937
msgid "Thumb encoding does not support rotation"
msgstr ""
-#: config/tc-arm.c:11792
+#: config/tc-arm.c:11952
msgid "SVC is not permitted on this architecture"
msgstr ""
-#: config/tc-arm.c:11808
+#: config/tc-arm.c:11968
msgid "instruction requires register index"
msgstr ""
-#: config/tc-arm.c:11817
+#: config/tc-arm.c:11977
msgid "instruction does not allow shifted index"
msgstr ""
-#: config/tc-arm.c:11962
+#: config/tc-arm.c:12122
msgid "invalid neon suffix for non neon instruction"
msgstr ""
-#: config/tc-arm.c:12253 config/tc-arm.c:12588
+#: config/tc-arm.c:12413 config/tc-arm.c:12748
msgid "invalid instruction shape"
msgstr ""
-#: config/tc-arm.c:12497
+#: config/tc-arm.c:12657
msgid "types specified in both the mnemonic and operands"
msgstr ""
-#: config/tc-arm.c:12534
+#: config/tc-arm.c:12694
msgid "operand types can't be inferred"
msgstr ""
-#: config/tc-arm.c:12540
+#: config/tc-arm.c:12700
msgid "type specifier has the wrong number of parts"
msgstr ""
-#: config/tc-arm.c:12604 config/tc-arm.c:14299 config/tc-arm.c:14306
+#: config/tc-arm.c:12764 config/tc-arm.c:14459 config/tc-arm.c:14466
msgid "operand size must match register width"
msgstr ""
-#: config/tc-arm.c:12615
+#: config/tc-arm.c:12775
msgid "bad type in Neon instruction"
msgstr ""
-#: config/tc-arm.c:12626
+#: config/tc-arm.c:12786
msgid "inconsistent types in Neon instruction"
msgstr ""
-#: config/tc-arm.c:13443
+#: config/tc-arm.c:13603
msgid "first and second operands shall be the same register"
msgstr ""
-#: config/tc-arm.c:13711
+#: config/tc-arm.c:13871
msgid "scalar out of range for multiply instruction"
msgstr ""
-#: config/tc-arm.c:13887 config/tc-arm.c:13899
+#: config/tc-arm.c:14047 config/tc-arm.c:14059
msgid "immediate out of range for insert"
msgstr ""
-#: config/tc-arm.c:13911 config/tc-arm.c:14906
+#: config/tc-arm.c:14071 config/tc-arm.c:15066
msgid "immediate out of range for shift"
msgstr ""
-#: config/tc-arm.c:13968 config/tc-arm.c:13995 config/tc-arm.c:14404
-#: config/tc-arm.c:14852
+#: config/tc-arm.c:14128 config/tc-arm.c:14155 config/tc-arm.c:14564
+#: config/tc-arm.c:15012
msgid "immediate out of range"
msgstr ""
-#: config/tc-arm.c:14032
+#: config/tc-arm.c:14192
msgid "immediate out of range for narrowing operation"
msgstr ""
-#: config/tc-arm.c:14157
+#: config/tc-arm.c:14317
msgid "operands 0 and 1 must be the same register"
msgstr ""
-#: config/tc-arm.c:14378
+#: config/tc-arm.c:14538
msgid "operand size must be specified for immediate VMOV"
msgstr ""
-#: config/tc-arm.c:14388
+#: config/tc-arm.c:14548
msgid "immediate has bits set outside the operand size"
msgstr ""
-#: config/tc-arm.c:14584
+#: config/tc-arm.c:14744
msgid "elements must be smaller than reversal region"
msgstr ""
-#: config/tc-arm.c:14755 config/tc-arm.c:14805
+#: config/tc-arm.c:14915 config/tc-arm.c:14965
msgid "bad type for scalar"
msgstr ""
-#: config/tc-arm.c:14869 config/tc-arm.c:14877
+#: config/tc-arm.c:15029 config/tc-arm.c:15037
msgid "VFP registers must be adjacent"
msgstr ""
-#: config/tc-arm.c:15018
+#: config/tc-arm.c:15178
msgid "bad list length for table lookup"
msgstr ""
-#: config/tc-arm.c:15048
+#: config/tc-arm.c:15208
msgid "writeback (!) must be used for VLDMDB and VSTMDB"
msgstr ""
-#: config/tc-arm.c:15051
+#: config/tc-arm.c:15211
msgid "register list must contain at least 1 and at most 16 registers"
msgstr ""
-#: config/tc-arm.c:15076
+#: config/tc-arm.c:15236
msgid "Use of PC here is deprecated"
msgstr ""
-#: config/tc-arm.c:15078
+#: config/tc-arm.c:15238
msgid "Use of PC here is UNPREDICTABLE"
msgstr ""
-#: config/tc-arm.c:15141
+#: config/tc-arm.c:15301
msgid "bad alignment"
msgstr ""
-#: config/tc-arm.c:15158
+#: config/tc-arm.c:15318
msgid "bad list type for instruction"
msgstr ""
-#: config/tc-arm.c:15200
+#: config/tc-arm.c:15360
msgid "unsupported alignment for instruction"
msgstr ""
-#: config/tc-arm.c:15219 config/tc-arm.c:15313 config/tc-arm.c:15324
-#: config/tc-arm.c:15334 config/tc-arm.c:15348
+#: config/tc-arm.c:15379 config/tc-arm.c:15473 config/tc-arm.c:15484
+#: config/tc-arm.c:15494 config/tc-arm.c:15508
msgid "bad list length"
msgstr ""
-#: config/tc-arm.c:15224
+#: config/tc-arm.c:15384
msgid "stride of 2 unavailable when element size is 8"
msgstr ""
-#: config/tc-arm.c:15257 config/tc-arm.c:15332
+#: config/tc-arm.c:15417 config/tc-arm.c:15492
msgid "can't use alignment with this instruction"
msgstr ""
-#: config/tc-arm.c:15399
+#: config/tc-arm.c:15559
msgid "post-index must be a register"
msgstr ""
-#: config/tc-arm.c:15401
+#: config/tc-arm.c:15561
msgid "bad register for post-index"
msgstr ""
-#: config/tc-arm.c:15737 config/tc-arm.c:15823
+#: config/tc-arm.c:15897 config/tc-arm.c:15983
msgid "conditional infixes are deprecated in unified syntax"
msgstr ""
-#: config/tc-arm.c:15971
+#: config/tc-arm.c:16131
msgid "Warning: conditional outside an IT block for Thumb."
msgstr ""
-#: config/tc-arm.c:16176
+#: config/tc-arm.c:16336
msgid "s suffix on comparison instruction is deprecated"
msgstr ""
-#: config/tc-arm.c:16195
+#: config/tc-arm.c:16355
#, c-format
msgid "selected processor does not support Thumb mode `%s'"
msgstr ""
-#: config/tc-arm.c:16201
+#: config/tc-arm.c:16361
msgid "Thumb does not support conditional execution"
msgstr ""
-#: config/tc-arm.c:16220
+#: config/tc-arm.c:16380
#, c-format
msgid "selected processor does not support Thumb-2 mode `%s'"
msgstr ""
-#: config/tc-arm.c:16245
+#: config/tc-arm.c:16405
#, c-format
msgid "cannot honor width suffix -- `%s'"
msgstr ""
-#: config/tc-arm.c:16286
+#: config/tc-arm.c:16446
#, c-format
msgid "selected processor does not support ARM mode `%s'"
msgstr ""
-#: config/tc-arm.c:16291
+#: config/tc-arm.c:16451
#, c-format
msgid "width suffixes are invalid in ARM mode -- `%s'"
msgstr ""
-#: config/tc-arm.c:16324
+#: config/tc-arm.c:16484
#, c-format
msgid "attempt to use an ARM instruction on a Thumb-only processor -- `%s'"
msgstr ""
-#: config/tc-arm.c:16341
+#: config/tc-arm.c:16501
#, c-format
msgid "section '%s' finished with an open IT block."
msgstr ""
-#: config/tc-arm.c:16346
+#: config/tc-arm.c:16506
msgid "file finished with an open IT block."
msgstr ""
-#: config/tc-arm.c:19385
+#: config/tc-arm.c:19545
#, c-format
msgid "alignments greater than %d bytes not supported in .text sections."
msgstr ""
-#: config/tc-arm.c:19653 config/tc-ia64.c:3469
+#: config/tc-arm.c:19813 config/tc-ia64.c:3469
#, c-format
msgid "Group section `%s' has no group signature"
msgstr ""
-#: config/tc-arm.c:19698
+#: config/tc-arm.c:19858
msgid "handlerdata in cantunwind frame"
msgstr ""
-#: config/tc-arm.c:19715
+#: config/tc-arm.c:19875
msgid "too many unwind opcodes for personality routine 0"
msgstr ""
-#: config/tc-arm.c:19747
+#: config/tc-arm.c:19907
msgid "too many unwind opcodes"
msgstr ""
-#: config/tc-arm.c:20007
+#: config/tc-arm.c:20167
msgid "GOT already in the symbol table"
msgstr ""
-#: config/tc-arm.c:20345 config/tc-arm.c:20387 config/tc-arm.c:20657
+#: config/tc-arm.c:20505 config/tc-arm.c:20547 config/tc-arm.c:20827
#, c-format
msgid "undefined symbol %s used as an immediate value"
msgstr ""
-#: config/tc-arm.c:20347 config/tc-arm.c:20389
+#: config/tc-arm.c:20507 config/tc-arm.c:20549
#, c-format
msgid "symbol %s is in a different section"
msgstr ""
-#: config/tc-arm.c:20349 config/tc-arm.c:20391
+#: config/tc-arm.c:20509 config/tc-arm.c:20551
#, c-format
msgid "symbol %s is weak and may be overridden later"
msgstr ""
-#: config/tc-arm.c:20368 config/tc-arm.c:20699
+#: config/tc-arm.c:20528 config/tc-arm.c:20869
#, c-format
msgid "invalid constant (%lx) after fixup"
msgstr ""
-#: config/tc-arm.c:20424
+#: config/tc-arm.c:20584
#, c-format
msgid "unable to compute ADRL instructions for PC offset of 0x%lx"
msgstr ""
-#: config/tc-arm.c:20459 config/tc-arm.c:20484
+#: config/tc-arm.c:20619 config/tc-arm.c:20649
msgid "invalid literal constant: pool needs to be closer"
msgstr ""
-#: config/tc-arm.c:20462 config/tc-arm.c:20500
+#: config/tc-arm.c:20622 config/tc-arm.c:20670
#, c-format
msgid "bad immediate value for offset (%ld)"
msgstr ""
-#: config/tc-arm.c:20486
+#: config/tc-arm.c:20651
#, c-format
msgid "bad immediate value for 8-bit offset (%ld)"
msgstr ""
-#: config/tc-arm.c:20541
+#: config/tc-arm.c:20711
msgid "offset not a multiple of 4"
msgstr ""
-#: config/tc-arm.c:20548 config/tc-arm.c:20563 config/tc-arm.c:20578
-#: config/tc-arm.c:20589 config/tc-arm.c:20612 config/tc-arm.c:21332
+#: config/tc-arm.c:20718 config/tc-arm.c:20733 config/tc-arm.c:20748
+#: config/tc-arm.c:20759 config/tc-arm.c:20782 config/tc-arm.c:21494
#: config/tc-moxie.c:662 config/tc-pj.c:448 config/tc-sh.c:4281
msgid "offset out of range"
msgstr ""
-#: config/tc-arm.c:20715
+#: config/tc-arm.c:20885
msgid "invalid smc expression"
msgstr ""
-#: config/tc-arm.c:20724
+#: config/tc-arm.c:20894
msgid "invalid hvc expression"
msgstr ""
-#: config/tc-arm.c:20735 config/tc-arm.c:20744
+#: config/tc-arm.c:20905 config/tc-arm.c:20914
msgid "invalid swi expression"
msgstr ""
-#: config/tc-arm.c:20754
+#: config/tc-arm.c:20924
msgid "invalid expression in load/store multiple"
msgstr ""
-#: config/tc-arm.c:20815
+#: config/tc-arm.c:20985
#, c-format
msgid "blx to '%s' an ARM ISA state function changed to bl"
msgstr ""
-#: config/tc-arm.c:20834
+#: config/tc-arm.c:21004
msgid "misaligned branch destination"
msgstr ""
-#: config/tc-arm.c:20838 config/tc-arm.c:20875 config/tc-arm.c:20889
-#: config/tc-arm.c:20902 config/tc-arm.c:21009 config/tc-arm.c:21027
-msgid "branch out of range"
-msgstr ""
-
-#: config/tc-arm.c:20924
+#: config/tc-arm.c:21090
msgid "conditional branch out of range"
msgstr ""
-#: config/tc-arm.c:20959
+#: config/tc-arm.c:21124
#, c-format
msgid "blx to Thumb func '%s' from Thumb ISA state changed to bl"
msgstr ""
-#: config/tc-arm.c:21015
+#: config/tc-arm.c:21174
msgid "Thumb2 branch out of range"
msgstr ""
-#: config/tc-arm.c:21106
+#: config/tc-arm.c:21263
msgid "rel31 relocation overflow"
msgstr ""
-#: config/tc-arm.c:21118 config/tc-arm.c:21141
+#: config/tc-arm.c:21275 config/tc-arm.c:21303
msgid "co-processor offset out of range"
msgstr ""
-#: config/tc-arm.c:21158
+#: config/tc-arm.c:21320
#, c-format
msgid "invalid offset, target not word aligned (0x%08lX)"
msgstr ""
-#: config/tc-arm.c:21165 config/tc-arm.c:21174 config/tc-arm.c:21182
-#: config/tc-arm.c:21190 config/tc-arm.c:21198
+#: config/tc-arm.c:21327 config/tc-arm.c:21336 config/tc-arm.c:21344
+#: config/tc-arm.c:21352 config/tc-arm.c:21360
#, c-format
msgid "invalid offset, value too big (0x%08lX)"
msgstr ""
-#: config/tc-arm.c:21239
+#: config/tc-arm.c:21401
msgid "invalid Hi register with immediate"
msgstr ""
-#: config/tc-arm.c:21255
+#: config/tc-arm.c:21417
msgid "invalid immediate for stack address calculation"
msgstr ""
-#: config/tc-arm.c:21263
+#: config/tc-arm.c:21425
#, c-format
msgid "invalid immediate for address calculation (value = 0x%08lX)"
msgstr ""
-#: config/tc-arm.c:21293
+#: config/tc-arm.c:21455
#, c-format
msgid "invalid immediate: %ld is out of range"
msgstr ""
-#: config/tc-arm.c:21305
+#: config/tc-arm.c:21467
#, c-format
msgid "invalid shift value: %ld"
msgstr ""
-#: config/tc-arm.c:21384
+#: config/tc-arm.c:21546
#, c-format
msgid "the offset 0x%08lX is not representable"
msgstr ""
-#: config/tc-arm.c:21424
+#: config/tc-arm.c:21586
#, c-format
msgid "bad offset 0x%08lX (only 12 bits available for the magnitude)"
msgstr ""
-#: config/tc-arm.c:21463
+#: config/tc-arm.c:21625
#, c-format
msgid "bad offset 0x%08lX (only 8 bits available for the magnitude)"
msgstr ""
-#: config/tc-arm.c:21503
+#: config/tc-arm.c:21665
#, c-format
msgid "bad offset 0x%08lX (must be word-aligned)"
msgstr ""
-#: config/tc-arm.c:21508
+#: config/tc-arm.c:21670
#, c-format
msgid "bad offset 0x%08lX (must be an 8-bit number of words)"
msgstr ""
-#: config/tc-arm.c:21539 config/tc-score.c:7397
+#: config/tc-arm.c:21701 config/tc-score.c:7392
#, c-format
msgid "bad relocation fixup type (%d)"
msgstr ""
-#: config/tc-arm.c:21650
+#: config/tc-arm.c:21812
msgid "literal referenced across section boundary"
msgstr ""
-#: config/tc-arm.c:21717
+#: config/tc-arm.c:21879
msgid "internal relocation (type: IMMEDIATE) not fixed up"
msgstr ""
-#: config/tc-arm.c:21722
+#: config/tc-arm.c:21884
msgid "ADRL used for a symbol not defined in the same file"
msgstr ""
-#: config/tc-arm.c:21737
+#: config/tc-arm.c:21899
#, c-format
msgid "undefined local label `%s'"
msgstr ""
-#: config/tc-arm.c:21743
+#: config/tc-arm.c:21905
msgid "internal_relocation (type: OFFSET_IMM) not fixed up"
msgstr ""
-#: config/tc-arm.c:21765 config/tc-cris.c:3986 config/tc-mcore.c:1926
+#: config/tc-arm.c:21927 config/tc-cris.c:3986 config/tc-mcore.c:1926
#: config/tc-microblaze.c:1833 config/tc-mmix.c:2867 config/tc-moxie.c:757
-#: config/tc-ns32k.c:2248 config/tc-score.c:7490
+#: config/tc-ns32k.c:2248 config/tc-score.c:7478
msgid "<unknown>"
msgstr ""
-#: config/tc-arm.c:21768 config/tc-arm.c:21789 config/tc-score.c:7492
+#: config/tc-arm.c:21930 config/tc-arm.c:21951 config/tc-score.c:7480
#, c-format
msgid "cannot represent %s relocation in this object file format"
msgstr ""
-#: config/tc-arm.c:22145
+#: config/tc-arm.c:22307
#, c-format
msgid "%s: unexpected function type: %d"
msgstr ""
-#: config/tc-arm.c:22274
+#: config/tc-arm.c:22436
msgid "use of old and new-style options to set CPU type"
msgstr ""
-#: config/tc-arm.c:22284
+#: config/tc-arm.c:22446
msgid "use of old and new-style options to set FPU type"
msgstr ""
-#: config/tc-arm.c:22360
+#: config/tc-arm.c:22522
msgid "hard-float conflicts with specified fpu"
msgstr ""
-#: config/tc-arm.c:22547
+#: config/tc-arm.c:22709
msgid "generate PIC code"
msgstr ""
-#: config/tc-arm.c:22548
+#: config/tc-arm.c:22710
msgid "assemble Thumb code"
msgstr ""
-#: config/tc-arm.c:22549
+#: config/tc-arm.c:22711
msgid "support ARM/Thumb interworking"
msgstr ""
-#: config/tc-arm.c:22551
+#: config/tc-arm.c:22713
msgid "code uses 32-bit program counter"
msgstr ""
-#: config/tc-arm.c:22552
+#: config/tc-arm.c:22714
msgid "code uses 26-bit program counter"
msgstr ""
-#: config/tc-arm.c:22553
+#: config/tc-arm.c:22715
msgid "floating point args are in fp regs"
msgstr ""
-#: config/tc-arm.c:22555
+#: config/tc-arm.c:22717
msgid "re-entrant code"
msgstr ""
-#: config/tc-arm.c:22556
+#: config/tc-arm.c:22718
msgid "code is ATPCS conformant"
msgstr ""
-#: config/tc-arm.c:22557
+#: config/tc-arm.c:22719
msgid "assemble for big-endian"
msgstr ""
-#: config/tc-arm.c:22558
+#: config/tc-arm.c:22720
msgid "assemble for little-endian"
msgstr ""
#. These are recognized by the assembler, but have no affect on code.
-#: config/tc-arm.c:22562
+#: config/tc-arm.c:22724
msgid "use frame pointer"
msgstr ""
-#: config/tc-arm.c:22563
+#: config/tc-arm.c:22725
msgid "use stack size checking"
msgstr ""
-#: config/tc-arm.c:22566
+#: config/tc-arm.c:22728
msgid "do not warn on use of deprecated feature"
msgstr ""
#. DON'T add any new processors to this list -- we want the whole list
#. to go away... Add them to the processors table instead.
-#: config/tc-arm.c:22583 config/tc-arm.c:22584
+#: config/tc-arm.c:22745 config/tc-arm.c:22746
msgid "use -mcpu=arm1"
msgstr ""
-#: config/tc-arm.c:22585 config/tc-arm.c:22586
+#: config/tc-arm.c:22747 config/tc-arm.c:22748
msgid "use -mcpu=arm2"
msgstr ""
-#: config/tc-arm.c:22587 config/tc-arm.c:22588
+#: config/tc-arm.c:22749 config/tc-arm.c:22750
msgid "use -mcpu=arm250"
msgstr ""
-#: config/tc-arm.c:22589 config/tc-arm.c:22590
+#: config/tc-arm.c:22751 config/tc-arm.c:22752
msgid "use -mcpu=arm3"
msgstr ""
-#: config/tc-arm.c:22591 config/tc-arm.c:22592
+#: config/tc-arm.c:22753 config/tc-arm.c:22754
msgid "use -mcpu=arm6"
msgstr ""
-#: config/tc-arm.c:22593 config/tc-arm.c:22594
+#: config/tc-arm.c:22755 config/tc-arm.c:22756
msgid "use -mcpu=arm600"
msgstr ""
-#: config/tc-arm.c:22595 config/tc-arm.c:22596
+#: config/tc-arm.c:22757 config/tc-arm.c:22758
msgid "use -mcpu=arm610"
msgstr ""
-#: config/tc-arm.c:22597 config/tc-arm.c:22598
+#: config/tc-arm.c:22759 config/tc-arm.c:22760
msgid "use -mcpu=arm620"
msgstr ""
-#: config/tc-arm.c:22599 config/tc-arm.c:22600
+#: config/tc-arm.c:22761 config/tc-arm.c:22762
msgid "use -mcpu=arm7"
msgstr ""
-#: config/tc-arm.c:22601 config/tc-arm.c:22602
+#: config/tc-arm.c:22763 config/tc-arm.c:22764
msgid "use -mcpu=arm70"
msgstr ""
-#: config/tc-arm.c:22603 config/tc-arm.c:22604
+#: config/tc-arm.c:22765 config/tc-arm.c:22766
msgid "use -mcpu=arm700"
msgstr ""
-#: config/tc-arm.c:22605 config/tc-arm.c:22606
+#: config/tc-arm.c:22767 config/tc-arm.c:22768
msgid "use -mcpu=arm700i"
msgstr ""
-#: config/tc-arm.c:22607 config/tc-arm.c:22608
+#: config/tc-arm.c:22769 config/tc-arm.c:22770
msgid "use -mcpu=arm710"
msgstr ""
-#: config/tc-arm.c:22609 config/tc-arm.c:22610
+#: config/tc-arm.c:22771 config/tc-arm.c:22772
msgid "use -mcpu=arm710c"
msgstr ""
-#: config/tc-arm.c:22611 config/tc-arm.c:22612
+#: config/tc-arm.c:22773 config/tc-arm.c:22774
msgid "use -mcpu=arm720"
msgstr ""
-#: config/tc-arm.c:22613 config/tc-arm.c:22614
+#: config/tc-arm.c:22775 config/tc-arm.c:22776
msgid "use -mcpu=arm7d"
msgstr ""
-#: config/tc-arm.c:22615 config/tc-arm.c:22616
+#: config/tc-arm.c:22777 config/tc-arm.c:22778
msgid "use -mcpu=arm7di"
msgstr ""
-#: config/tc-arm.c:22617 config/tc-arm.c:22618
+#: config/tc-arm.c:22779 config/tc-arm.c:22780
msgid "use -mcpu=arm7m"
msgstr ""
-#: config/tc-arm.c:22619 config/tc-arm.c:22620
+#: config/tc-arm.c:22781 config/tc-arm.c:22782
msgid "use -mcpu=arm7dm"
msgstr ""
-#: config/tc-arm.c:22621 config/tc-arm.c:22622
+#: config/tc-arm.c:22783 config/tc-arm.c:22784
msgid "use -mcpu=arm7dmi"
msgstr ""
-#: config/tc-arm.c:22623 config/tc-arm.c:22624
+#: config/tc-arm.c:22785 config/tc-arm.c:22786
msgid "use -mcpu=arm7100"
msgstr ""
-#: config/tc-arm.c:22625 config/tc-arm.c:22626
+#: config/tc-arm.c:22787 config/tc-arm.c:22788
msgid "use -mcpu=arm7500"
msgstr ""
-#: config/tc-arm.c:22627 config/tc-arm.c:22628
+#: config/tc-arm.c:22789 config/tc-arm.c:22790
msgid "use -mcpu=arm7500fe"
msgstr ""
-#: config/tc-arm.c:22629 config/tc-arm.c:22630 config/tc-arm.c:22631
-#: config/tc-arm.c:22632
+#: config/tc-arm.c:22791 config/tc-arm.c:22792 config/tc-arm.c:22793
+#: config/tc-arm.c:22794
msgid "use -mcpu=arm7tdmi"
msgstr ""
-#: config/tc-arm.c:22633 config/tc-arm.c:22634
+#: config/tc-arm.c:22795 config/tc-arm.c:22796
msgid "use -mcpu=arm710t"
msgstr ""
-#: config/tc-arm.c:22635 config/tc-arm.c:22636
+#: config/tc-arm.c:22797 config/tc-arm.c:22798
msgid "use -mcpu=arm720t"
msgstr ""
-#: config/tc-arm.c:22637 config/tc-arm.c:22638
+#: config/tc-arm.c:22799 config/tc-arm.c:22800
msgid "use -mcpu=arm740t"
msgstr ""
-#: config/tc-arm.c:22639 config/tc-arm.c:22640
+#: config/tc-arm.c:22801 config/tc-arm.c:22802
msgid "use -mcpu=arm8"
msgstr ""
-#: config/tc-arm.c:22641 config/tc-arm.c:22642
+#: config/tc-arm.c:22803 config/tc-arm.c:22804
msgid "use -mcpu=arm810"
msgstr ""
-#: config/tc-arm.c:22643 config/tc-arm.c:22644
+#: config/tc-arm.c:22805 config/tc-arm.c:22806
msgid "use -mcpu=arm9"
msgstr ""
-#: config/tc-arm.c:22645 config/tc-arm.c:22646
+#: config/tc-arm.c:22807 config/tc-arm.c:22808
msgid "use -mcpu=arm9tdmi"
msgstr ""
-#: config/tc-arm.c:22647 config/tc-arm.c:22648
+#: config/tc-arm.c:22809 config/tc-arm.c:22810
msgid "use -mcpu=arm920"
msgstr ""
-#: config/tc-arm.c:22649 config/tc-arm.c:22650
+#: config/tc-arm.c:22811 config/tc-arm.c:22812
msgid "use -mcpu=arm940"
msgstr ""
-#: config/tc-arm.c:22651
+#: config/tc-arm.c:22813
msgid "use -mcpu=strongarm"
msgstr ""
-#: config/tc-arm.c:22653
+#: config/tc-arm.c:22815
msgid "use -mcpu=strongarm110"
msgstr ""
-#: config/tc-arm.c:22655
+#: config/tc-arm.c:22817
msgid "use -mcpu=strongarm1100"
msgstr ""
-#: config/tc-arm.c:22657
+#: config/tc-arm.c:22819
msgid "use -mcpu=strongarm1110"
msgstr ""
-#: config/tc-arm.c:22658
+#: config/tc-arm.c:22820
msgid "use -mcpu=xscale"
msgstr ""
-#: config/tc-arm.c:22659
+#: config/tc-arm.c:22821
msgid "use -mcpu=iwmmxt"
msgstr ""
-#: config/tc-arm.c:22660
+#: config/tc-arm.c:22822
msgid "use -mcpu=all"
msgstr ""
#. Architecture variants -- don't add any more to this list either.
-#: config/tc-arm.c:22663 config/tc-arm.c:22664
+#: config/tc-arm.c:22825 config/tc-arm.c:22826
msgid "use -march=armv2"
msgstr ""
-#: config/tc-arm.c:22665 config/tc-arm.c:22666
+#: config/tc-arm.c:22827 config/tc-arm.c:22828
msgid "use -march=armv2a"
msgstr ""
-#: config/tc-arm.c:22667 config/tc-arm.c:22668
+#: config/tc-arm.c:22829 config/tc-arm.c:22830
msgid "use -march=armv3"
msgstr ""
-#: config/tc-arm.c:22669 config/tc-arm.c:22670
+#: config/tc-arm.c:22831 config/tc-arm.c:22832
msgid "use -march=armv3m"
msgstr ""
-#: config/tc-arm.c:22671 config/tc-arm.c:22672
+#: config/tc-arm.c:22833 config/tc-arm.c:22834
msgid "use -march=armv4"
msgstr ""
-#: config/tc-arm.c:22673 config/tc-arm.c:22674
+#: config/tc-arm.c:22835 config/tc-arm.c:22836
msgid "use -march=armv4t"
msgstr ""
-#: config/tc-arm.c:22675 config/tc-arm.c:22676
+#: config/tc-arm.c:22837 config/tc-arm.c:22838
msgid "use -march=armv5"
msgstr ""
-#: config/tc-arm.c:22677 config/tc-arm.c:22678
+#: config/tc-arm.c:22839 config/tc-arm.c:22840
msgid "use -march=armv5t"
msgstr ""
-#: config/tc-arm.c:22679 config/tc-arm.c:22680
+#: config/tc-arm.c:22841 config/tc-arm.c:22842
msgid "use -march=armv5te"
msgstr ""
#. Floating point variants -- don't add any more to this list either.
-#: config/tc-arm.c:22683
+#: config/tc-arm.c:22845
msgid "use -mfpu=fpe"
msgstr ""
-#: config/tc-arm.c:22684
+#: config/tc-arm.c:22846
msgid "use -mfpu=fpa10"
msgstr ""
-#: config/tc-arm.c:22685
+#: config/tc-arm.c:22847
msgid "use -mfpu=fpa11"
msgstr ""
-#: config/tc-arm.c:22687
+#: config/tc-arm.c:22849
msgid "use either -mfpu=softfpa or -mfpu=softvfp"
msgstr ""
-#: config/tc-arm.c:23016
+#: config/tc-arm.c:23178
msgid "invalid architectural extension"
msgstr ""
-#: config/tc-arm.c:23049
+#: config/tc-arm.c:23211
msgid "must specify extensions to add before specifying those to remove"
msgstr ""
-#: config/tc-arm.c:23057
+#: config/tc-arm.c:23219
msgid "missing architectural extension"
msgstr ""
-#: config/tc-arm.c:23072
+#: config/tc-arm.c:23234
msgid "extension does not apply to the base architecture"
msgstr ""
-#: config/tc-arm.c:23095
+#: config/tc-arm.c:23257
#, c-format
msgid "unknown architectural extension `%s'"
msgstr ""
-#: config/tc-arm.c:23097
+#: config/tc-arm.c:23259
msgid "architectural extensions must be specified in alphabetical order"
msgstr ""
-#: config/tc-arm.c:23129
+#: config/tc-arm.c:23291
#, c-format
msgid "missing cpu name `%s'"
msgstr ""
-#: config/tc-arm.c:23155 config/tc-arm.c:23651
+#: config/tc-arm.c:23317 config/tc-arm.c:23813
#, c-format
msgid "unknown cpu `%s'"
msgstr ""
-#: config/tc-arm.c:23173
+#: config/tc-arm.c:23335
#, c-format
msgid "missing architecture name `%s'"
msgstr ""
-#: config/tc-arm.c:23190 config/tc-arm.c:23685 config/tc-arm.c:23716
-#: config/tc-arm.c:23767 config/tc-score.c:7727
+#: config/tc-arm.c:23352 config/tc-arm.c:23847 config/tc-arm.c:23878
+#: config/tc-arm.c:23929 config/tc-score.c:7715
#, c-format
msgid "unknown architecture `%s'\n"
msgstr ""
-#: config/tc-arm.c:23206 config/tc-arm.c:23798
+#: config/tc-arm.c:23368 config/tc-arm.c:23960
#, c-format
msgid "unknown floating point format `%s'\n"
msgstr ""
-#: config/tc-arm.c:23222
+#: config/tc-arm.c:23384
#, c-format
msgid "unknown floating point abi `%s'\n"
msgstr ""
-#: config/tc-arm.c:23238
+#: config/tc-arm.c:23400
#, c-format
msgid "unknown EABI `%s'\n"
msgstr ""
-#: config/tc-arm.c:23258
+#: config/tc-arm.c:23420
#, c-format
msgid "unknown implicit IT mode `%s', should be arm, thumb, always, or never."
msgstr ""
-#: config/tc-arm.c:23268
+#: config/tc-arm.c:23430
msgid "<cpu name>\t assemble for CPU <cpu name>"
msgstr ""
-#: config/tc-arm.c:23270
+#: config/tc-arm.c:23432
msgid "<arch name>\t assemble for architecture <arch name>"
msgstr ""
-#: config/tc-arm.c:23272
+#: config/tc-arm.c:23434
msgid "<fpu name>\t assemble for FPU architecture <fpu name>"
msgstr ""
-#: config/tc-arm.c:23274
+#: config/tc-arm.c:23436
msgid "<abi>\t assemble for floating point ABI <abi>"
msgstr ""
-#: config/tc-arm.c:23277
+#: config/tc-arm.c:23439
msgid "<ver>\t\t assemble for eabi version <ver>"
msgstr ""
-#: config/tc-arm.c:23280
+#: config/tc-arm.c:23442
msgid "<mode>\t controls implicit insertion of IT instructions"
msgstr ""
-#: config/tc-arm.c:23324 config/tc-arm.c:23342 config/tc-arm.c:23362
+#: config/tc-arm.c:23486 config/tc-arm.c:23504 config/tc-arm.c:23524
#, c-format
msgid "option `-%c%s' is deprecated: %s"
msgstr ""
-#: config/tc-arm.c:23382
+#: config/tc-arm.c:23544
#, c-format
msgid " ARM-specific assembler options:\n"
msgstr ""
-#: config/tc-arm.c:23393
+#: config/tc-arm.c:23555
#, c-format
msgid " -EB assemble code for a big-endian cpu\n"
msgstr ""
-#: config/tc-arm.c:23398
+#: config/tc-arm.c:23560
#, c-format
msgid " -EL assemble code for a little-endian cpu\n"
msgstr ""
-#: config/tc-arm.c:23402
+#: config/tc-arm.c:23564
#, c-format
msgid " --fix-v4bx Allow BX in ARMv4 code\n"
msgstr ""
-#: config/tc-arm.c:23749
+#: config/tc-arm.c:23911
#, c-format
msgid ""
"architectural extension `%s' is not allowed for the current base architecture"
msgid "constant out of 8-bit range: %d"
msgstr ""
-#: config/tc-avr.c:688 config/tc-score.c:1200 read.c:3662
+#: config/tc-avr.c:688 config/tc-score.c:1199 read.c:3661
msgid "illegal expression"
msgstr ""
#. xgettext:c-format.
#: config/tc-avr.c:1412 config/tc-bfin.c:833 config/tc-d10v.c:1466
-#: config/tc-d30v.c:1774 config/tc-mn10200.c:781 config/tc-mn10300.c:2170
-#: config/tc-msp430.c:2055 config/tc-or32.c:957 config/tc-ppc.c:6611
+#: config/tc-d30v.c:1774 config/tc-mn10200.c:782 config/tc-mn10300.c:2170
+#: config/tc-msp430.c:2055 config/tc-or32.c:957 config/tc-ppc.c:6581
#: config/tc-spu.c:879 config/tc-spu.c:1090 config/tc-v850.c:3000
#: config/tc-z80.c:2021
#, c-format
msgid "rel too far BFD_RELOC_16"
msgstr ""
-#: config/tc-cr16.c:165 read.c:4422
+#: config/tc-cr16.c:165 read.c:4421
msgid "using a bit field width of zero"
msgstr ""
-#: config/tc-cr16.c:173 read.c:4430
+#: config/tc-cr16.c:173 read.c:4429
#, c-format
msgid "field width \"%s\" too complex for a bitfield"
msgstr ""
-#: config/tc-cr16.c:182 read.c:4438
+#: config/tc-cr16.c:182 read.c:4437
#, c-format
msgid "field width %lu too big to fit in %d bytes: truncated to %d bits"
msgstr ""
-#: config/tc-cr16.c:204 read.c:4460
+#: config/tc-cr16.c:204 read.c:4459
#, c-format
msgid "field value \"%s\" too complex for a bitfield"
msgstr ""
msgid "Unknown register pair - index relative mode: `%d'"
msgstr ""
-#: config/tc-cr16.c:571 config/tc-crx.c:345 config/tc-mn10200.c:768
-#: write.c:990
+#: config/tc-cr16.c:570 config/tc-crx.c:345 config/tc-mn10200.c:769
+#: write.c:1003
#, c-format
msgid "can't resolve `%s' {%s section} - `%s' {%s section}"
msgstr ""
-#: config/tc-cr16.c:603 config/tc-crx.c:361
+#: config/tc-cr16.c:600 config/tc-crx.c:361
#, c-format
msgid "internal error: reloc %d (`%s') not supported by object file format"
msgstr ""
-#: config/tc-cr16.c:696 config/tc-i386.c:8723 config/tc-s390.c:1911
+#: config/tc-cr16.c:693 config/tc-i386.c:8839 config/tc-s390.c:1911
msgid "GOT already in symbol table"
msgstr ""
-#: config/tc-cr16.c:805 config/tc-cr16.c:828 config/tc-cris.c:1190
+#: config/tc-cr16.c:802 config/tc-cr16.c:825 config/tc-cris.c:1190
#: config/tc-crx.c:535 config/tc-crx.c:562 config/tc-crx.c:580
#: config/tc-pdp11.c:194
msgid "Virtual memory exhausted"
msgstr ""
-#: config/tc-cr16.c:813 config/tc-crx.c:572 config/tc-crx.c:591
-#: config/tc-m68k.c:4656
+#: config/tc-cr16.c:810 config/tc-crx.c:572 config/tc-crx.c:591
+#: config/tc-m68k.c:4656 config/tc-tilegx.c:300 config/tc-tilepro.c:242
#, c-format
msgid "Internal Error: Can't hash %s: %s"
msgstr ""
-#: config/tc-cr16.c:839 config/tc-cris.c:1224 config/tc-crx.c:545
+#: config/tc-cr16.c:836 config/tc-cris.c:1224 config/tc-crx.c:545
#, c-format
msgid "Can't hash `%s': %s\n"
msgstr ""
-#: config/tc-cr16.c:840 config/tc-cris.c:1225 config/tc-crx.c:546
+#: config/tc-cr16.c:837 config/tc-cris.c:1225 config/tc-crx.c:546
msgid "(unknown reason)"
msgstr ""
#. Missing or bad expr becomes absolute 0.
-#: config/tc-cr16.c:892 config/tc-crx.c:619
+#: config/tc-cr16.c:889 config/tc-crx.c:619
#, c-format
msgid "missing or invalid displacement expression `%s' taken as 0"
msgstr ""
-#: config/tc-cr16.c:942
+#: config/tc-cr16.c:939
#, c-format
msgid "GOT bad expression with %s."
msgstr ""
-#: config/tc-cr16.c:1053
+#: config/tc-cr16.c:1050
#, c-format
msgid "operand %d: illegal use expression: `%s`"
msgstr ""
-#: config/tc-cr16.c:1118 config/tc-crx.c:1127
+#: config/tc-cr16.c:1115 config/tc-crx.c:1127
#, c-format
msgid "Unknown register: `%d'"
msgstr ""
#. Issue a error message when register is illegal.
-#: config/tc-cr16.c:1126 config/tc-crx.c:1135
+#: config/tc-cr16.c:1123 config/tc-crx.c:1135
#, c-format
msgid "Illegal register (`%s') in Instruction: `%s'"
msgstr ""
-#: config/tc-cr16.c:1197 config/tc-cr16.c:1272 config/tc-crx.c:757
+#: config/tc-cr16.c:1194 config/tc-cr16.c:1269 config/tc-crx.c:757
#: config/tc-crx.c:777 config/tc-crx.c:792
#, c-format
msgid "Illegal register `%s' in Instruction `%s'"
msgstr ""
-#: config/tc-cr16.c:1225 config/tc-cr16.c:1236
+#: config/tc-cr16.c:1222 config/tc-cr16.c:1233
#, c-format
msgid "Illegal register pair `%s' in Instruction `%s'"
msgstr ""
-#: config/tc-cr16.c:1261 config/tc-i960.c:835
+#: config/tc-cr16.c:1258 config/tc-i960.c:835
msgid "unmatched '['"
msgstr ""
-#: config/tc-cr16.c:1267 config/tc-i960.c:842
+#: config/tc-cr16.c:1264 config/tc-i960.c:842
msgid "garbage after index spec ignored"
msgstr ""
-#: config/tc-cr16.c:1415 config/tc-crx.c:936
+#: config/tc-cr16.c:1412 config/tc-crx.c:936
#, c-format
msgid "Illegal operands (whitespace): `%s'"
msgstr ""
-#: config/tc-cr16.c:1427 config/tc-cr16.c:1434 config/tc-cr16.c:1451
+#: config/tc-cr16.c:1424 config/tc-cr16.c:1431 config/tc-cr16.c:1448
#: config/tc-crx.c:948 config/tc-crx.c:955 config/tc-crx.c:972
#: config/tc-crx.c:1764
#, c-format
msgid "Missing matching brackets : `%s'"
msgstr ""
-#: config/tc-cr16.c:1483 config/tc-crx.c:998
+#: config/tc-cr16.c:1480 config/tc-crx.c:998
#, c-format
msgid "Unknown exception: `%s'"
msgstr ""
-#: config/tc-cr16.c:1570 config/tc-crx.c:1094
+#: config/tc-cr16.c:1565 config/tc-crx.c:1094
#, c-format
msgid "Illegal `cinv' parameter: `%c'"
msgstr ""
-#: config/tc-cr16.c:1592 config/tc-cr16.c:1631
+#: config/tc-cr16.c:1586 config/tc-cr16.c:1625
#, c-format
msgid "Unknown register pair: `%d'"
msgstr ""
#. Issue a error message when register pair is illegal.
-#: config/tc-cr16.c:1600
+#: config/tc-cr16.c:1594
#, c-format
msgid "Illegal register pair (`%s') in Instruction: `%s'"
msgstr ""
#. Issue a error message when register pair is illegal.
-#: config/tc-cr16.c:1639
+#: config/tc-cr16.c:1633
#, c-format
msgid "Illegal index register pair (`%s') in Instruction: `%s'"
msgstr ""
-#: config/tc-cr16.c:1678
+#: config/tc-cr16.c:1672
#, c-format
msgid "Unknown processor register : `%d'"
msgstr ""
#. Issue a error message when register pair is illegal.
-#: config/tc-cr16.c:1686
+#: config/tc-cr16.c:1680
#, c-format
msgid "Illegal processor register (`%s') in Instruction: `%s'"
msgstr ""
-#: config/tc-cr16.c:1734
+#: config/tc-cr16.c:1728
#, c-format
msgid "Unknown processor register (32 bit) : `%d'"
msgstr ""
#. Issue a error message when register pair is illegal.
-#: config/tc-cr16.c:1742
+#: config/tc-cr16.c:1736
#, c-format
msgid "Illegal 32 bit - processor register (`%s') in Instruction: `%s'"
msgstr ""
-#: config/tc-cr16.c:2106 config/tc-crx.c:1662 config/tc-crx.c:1679
+#: config/tc-cr16.c:2100 config/tc-crx.c:1662 config/tc-crx.c:1679
#, c-format
msgid "Same src/dest register is used (`r%d'), result is undefined"
msgstr ""
-#: config/tc-cr16.c:2127
+#: config/tc-cr16.c:2121
msgid "RA register is saved twice."
msgstr ""
-#: config/tc-cr16.c:2131
+#: config/tc-cr16.c:2125
#, c-format
msgid "`%s' Illegal use of registers."
msgstr ""
-#: config/tc-cr16.c:2145
+#: config/tc-cr16.c:2139
#, c-format
msgid "`%s' Illegal count-register combination."
msgstr ""
-#: config/tc-cr16.c:2151
+#: config/tc-cr16.c:2145
#, c-format
msgid "`%s' Illegal use of register."
msgstr ""
-#: config/tc-cr16.c:2160 config/tc-crx.c:1671
+#: config/tc-cr16.c:2154 config/tc-crx.c:1671
#, c-format
msgid "`%s' has undefined result"
msgstr ""
-#: config/tc-cr16.c:2168
+#: config/tc-cr16.c:2162
#, c-format
msgid "Same src/dest register is used (`r%d'),result is undefined"
msgstr ""
-#: config/tc-cr16.c:2339 config/tc-crx.c:1576
+#: config/tc-cr16.c:2333 config/tc-crx.c:1576
msgid "Incorrect number of operands"
msgstr ""
-#: config/tc-cr16.c:2341 config/tc-crx.c:1578
+#: config/tc-cr16.c:2335 config/tc-crx.c:1578
#, c-format
msgid "Illegal type of operand (arg %d)"
msgstr ""
-#: config/tc-cr16.c:2347 config/tc-crx.c:1584
+#: config/tc-cr16.c:2341 config/tc-crx.c:1584
#, c-format
msgid "Operand out of range (arg %d)"
msgstr ""
-#: config/tc-cr16.c:2350 config/tc-crx.c:1587
+#: config/tc-cr16.c:2344 config/tc-crx.c:1587
#, c-format
msgid "Operand has odd displacement (arg %d)"
msgstr ""
-#: config/tc-cr16.c:2353 config/tc-cr16.c:2384 config/tc-crx.c:1600
+#: config/tc-cr16.c:2347 config/tc-cr16.c:2378 config/tc-crx.c:1600
#: config/tc-crx.c:1631
#, c-format
msgid "Illegal operand (arg %d)"
#. Give an error if a frag containing code is not aligned to a 2-byte
#. boundary.
-#: config/tc-cr16.c:2486 config/tc-cr16.h:73 config/tc-crx.c:1953
+#: config/tc-cr16.c:2480 config/tc-cr16.h:73 config/tc-crx.c:1953
#: config/tc-crx.h:76
msgid "instruction address is not a multiple of 2"
msgstr ""
-#: config/tc-cr16.c:2563 config/tc-cris.c:1538 config/tc-cris.c:1546
+#: config/tc-cr16.c:2555 config/tc-cris.c:1538 config/tc-cris.c:1546
#: config/tc-crx.c:1989 config/tc-dlx.c:685 config/tc-hppa.c:3244
#: config/tc-hppa.c:3251 config/tc-i860.c:491 config/tc-i860.c:508
-#: config/tc-i860.c:988 config/tc-sparc.c:1410 config/tc-sparc.c:1418
+#: config/tc-i860.c:988 config/tc-sparc.c:1518 config/tc-sparc.c:1526
#, c-format
msgid "Unknown opcode: `%s'"
msgstr ""
#. We've come to the end of instructions with this
#. opcode, so it must be an error.
-#: config/tc-cris.c:2079 config/tc-mips.c:10425 config/tc-mips.c:10430
+#: config/tc-cris.c:2079 config/tc-mips.c:13126
msgid "Illegal operands"
msgstr ""
msgid ".endfunc missing for previous .proc"
msgstr ""
-#: config/tc-dlx.c:291 config/tc-i860.c:227 config/tc-mips.c:1927
+#: config/tc-dlx.c:291 config/tc-i860.c:227 config/tc-mips.c:2321
#, c-format
msgid "internal error: can't hash `%s': %s\n"
msgstr ""
#. Probably a memory allocation problem? Give up now.
-#: config/tc-dlx.c:298 config/tc-hppa.c:8354 config/tc-mips.c:1930
-#: config/tc-mips.c:1984 config/tc-or32.c:211 config/tc-sparc.c:860
+#: config/tc-dlx.c:298 config/tc-hppa.c:8354 config/tc-mips.c:2324
+#: config/tc-mips.c:2416 config/tc-or32.c:211 config/tc-sparc.c:888
msgid "Broken assembler. No assembly attempted."
msgstr ""
msgid "Invalid expression after # number\n"
msgstr ""
+#: config/tc-epiphany.c:147
+#, c-format
+msgid "EPIPHANY specific command line options:\n"
+msgstr ""
+
+#: config/tc-epiphany.c:386
+msgid "register number too large for push/pop"
+msgstr ""
+
+#: config/tc-epiphany.c:390
+msgid "register is out of order"
+msgstr ""
+
+#: config/tc-epiphany.c:401 config/tc-m68k.c:6037 config/tc-m68k.c:6066
+msgid "bad register list"
+msgstr ""
+
+#: config/tc-epiphany.c:404
+msgid "malformed reglist in push/pop"
+msgstr ""
+
+#. Checks for behavioral restrictions on LD/ST instructions.
+#: config/tc-epiphany.c:505
+msgid "destination register modified by displacement-post-modified address"
+msgstr ""
+
+#: config/tc-epiphany.c:506
+msgid "ldrd/strd requires even:odd register pair"
+msgstr ""
+
+#: config/tc-epiphany.c:824 config/tc-m32r.c:1789
+msgid "Addend to unresolved symbol not on word boundary."
+msgstr ""
+
#: config/tc-fr30.c:82
#, c-format
msgid " FR30 specific command line options:\n"
msgid "operand/size mis-match"
msgstr ""
-#: config/tc-h8300.c:1952 config/tc-mips.c:10489 config/tc-sh.c:2971
+#: config/tc-h8300.c:1952 config/tc-mips.c:13197 config/tc-sh.c:2971
#: config/tc-sh64.c:2795 config/tc-z8k.c:1226
msgid "unknown opcode"
msgstr ""
msgid "-R option not supported on this target."
msgstr ""
-#: config/tc-hppa.c:8335 config/tc-sparc.c:815 config/tc-sparc.c:852
+#: config/tc-hppa.c:8335 config/tc-sparc.c:843 config/tc-sparc.c:880
#, c-format
msgid "Internal error: can't hash `%s': %s\n"
msgstr ""
msgid "wrong number of operands"
msgstr ""
-#: config/tc-i370.c:1928 config/tc-mn10200.c:898 config/tc-mn10300.c:1251
+#: config/tc-i370.c:1928 config/tc-mn10200.c:899 config/tc-mn10300.c:1251
#: config/tc-ppc.c:2405 config/tc-s390.c:1590 config/tc-v850.c:2024
#, c-format
msgid "Unrecognized opcode: `%s'"
msgid "Internal Error: bad instruction length"
msgstr ""
-#: config/tc-i386.c:1873
+#: config/tc-i386.c:1885
#, c-format
msgid "%s shortened to %s"
msgstr ""
-#: config/tc-i386.c:1959
+#: config/tc-i386.c:1971
msgid "same type of prefix used twice"
msgstr ""
-#: config/tc-i386.c:1986
+#: config/tc-i386.c:1998
#, c-format
msgid "64bit mode not supported on `%s'."
msgstr ""
-#: config/tc-i386.c:1995
+#: config/tc-i386.c:2007
#, c-format
msgid "32bit mode not supported on `%s'."
msgstr ""
-#: config/tc-i386.c:2035
+#: config/tc-i386.c:2047
msgid "bad argument to syntax directive."
msgstr ""
-#: config/tc-i386.c:2084
+#: config/tc-i386.c:2096
msgid "bad argument to sse_check directive."
msgstr ""
-#: config/tc-i386.c:2088
+#: config/tc-i386.c:2100
msgid "missing argument for sse_check directive"
msgstr ""
-#: config/tc-i386.c:2118
+#: config/tc-i386.c:2135
#, c-format
msgid "`%s' is not supported on `%s'"
msgstr ""
-#: config/tc-i386.c:2192
+#: config/tc-i386.c:2209
#, c-format
msgid "no such architecture: `%s'"
msgstr ""
-#: config/tc-i386.c:2197
+#: config/tc-i386.c:2214
msgid "missing cpu architecture"
msgstr ""
-#: config/tc-i386.c:2211
+#: config/tc-i386.c:2228
#, c-format
msgid "no such architecture modifier: `%s'"
msgstr ""
-#: config/tc-i386.c:2226 config/tc-i386.c:2242
+#: config/tc-i386.c:2243 config/tc-i386.c:2266
msgid "Intel L1OM is 64bit ELF only"
msgstr ""
-#: config/tc-i386.c:2253 config/tc-i386.c:8600
+#: config/tc-i386.c:2250 config/tc-i386.c:2273
+msgid "Intel K1OM is 64bit ELF only"
+msgstr ""
+
+#: config/tc-i386.c:2284 config/tc-i386.c:8711
msgid "unknown architecture"
msgstr ""
-#: config/tc-i386.c:2287 config/tc-i386.c:2309
+#: config/tc-i386.c:2318 config/tc-i386.c:2340
#, c-format
msgid "internal Error: Can't hash %s: %s"
msgstr ""
-#: config/tc-i386.c:2604
+#: config/tc-i386.c:2635
#, c-format
msgid "unknown relocation (%u)"
msgstr ""
-#: config/tc-i386.c:2606
+#: config/tc-i386.c:2637
#, c-format
msgid "%u-byte relocation cannot be applied to %u-byte field"
msgstr ""
-#: config/tc-i386.c:2610
+#: config/tc-i386.c:2641
msgid "non-pc-relative relocation for pc-relative field"
msgstr ""
-#: config/tc-i386.c:2615
+#: config/tc-i386.c:2646
msgid "relocated field and relocation type differ in signedness"
msgstr ""
-#: config/tc-i386.c:2624
+#: config/tc-i386.c:2655
msgid "there are no unsigned pc-relative relocations"
msgstr ""
-#: config/tc-i386.c:2632
+#: config/tc-i386.c:2663
#, c-format
msgid "cannot do %u byte pc-relative relocation"
msgstr ""
-#: config/tc-i386.c:2649
+#: config/tc-i386.c:2680
#, c-format
msgid "cannot do %s %u byte relocation"
msgstr ""
-#: config/tc-i386.c:2933
+#: config/tc-i386.c:2964
#, c-format
msgid "can't use register '%s%s' as operand %d in '%s'."
msgstr ""
-#: config/tc-i386.c:3045
+#: config/tc-i386.c:3076
#, c-format
msgid "SSE instruction `%s' is used"
msgstr ""
-#: config/tc-i386.c:3059 config/tc-i386.c:4489
+#: config/tc-i386.c:3090 config/tc-i386.c:4562
#, c-format
msgid "ambiguous operand size for `%s'"
msgstr ""
-#: config/tc-i386.c:3076
+#: config/tc-i386.c:3107
msgid "expecting lockable instruction after `lock'"
msgstr ""
#. UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc.
-#: config/tc-i386.c:3127
+#: config/tc-i386.c:3158
#, c-format
msgid "translating to `%sp'"
msgstr ""
-#: config/tc-i386.c:3182
+#: config/tc-i386.c:3213
#, c-format
msgid "can't encode register '%s%s' in an instruction requiring REX prefix."
msgstr ""
-#: config/tc-i386.c:3225 config/tc-i386.c:3357
+#: config/tc-i386.c:3256 config/tc-i386.c:3388
#, c-format
msgid "no such instruction: `%s'"
msgstr ""
-#: config/tc-i386.c:3236 config/tc-i386.c:3390
+#: config/tc-i386.c:3267 config/tc-i386.c:3421
#, c-format
msgid "invalid character %s in mnemonic"
msgstr ""
-#: config/tc-i386.c:3243
+#: config/tc-i386.c:3274
msgid "expecting prefix; got nothing"
msgstr ""
-#: config/tc-i386.c:3245
+#: config/tc-i386.c:3276
msgid "expecting mnemonic; got nothing"
msgstr ""
-#: config/tc-i386.c:3260 config/tc-i386.c:3408
+#: config/tc-i386.c:3291 config/tc-i386.c:3439
#, c-format
msgid "`%s' is only supported in 64-bit mode"
msgstr ""
-#: config/tc-i386.c:3261 config/tc-i386.c:3407
+#: config/tc-i386.c:3292 config/tc-i386.c:3438
#, c-format
msgid "`%s' is not supported in 64-bit mode"
msgstr ""
-#: config/tc-i386.c:3273
+#: config/tc-i386.c:3304
#, c-format
msgid "redundant %s prefix"
msgstr ""
-#: config/tc-i386.c:3414
+#: config/tc-i386.c:3445
#, c-format
msgid "`%s' is not supported on `%s%s'"
msgstr ""
-#: config/tc-i386.c:3425
+#: config/tc-i386.c:3456
msgid "use .code16 to ensure correct addressing mode"
msgstr ""
-#: config/tc-i386.c:3438
+#: config/tc-i386.c:3469
#, c-format
msgid "expecting string instruction after `%s'"
msgstr ""
-#: config/tc-i386.c:3470
+#: config/tc-i386.c:3501
#, c-format
msgid "invalid character %s before operand %d"
msgstr ""
-#: config/tc-i386.c:3484
+#: config/tc-i386.c:3515
#, c-format
msgid "unbalanced parenthesis in operand %d."
msgstr ""
-#: config/tc-i386.c:3487
+#: config/tc-i386.c:3518
#, c-format
msgid "unbalanced brackets in operand %d."
msgstr ""
-#: config/tc-i386.c:3496
+#: config/tc-i386.c:3527
#, c-format
msgid "invalid character %s in operand %d"
msgstr ""
-#: config/tc-i386.c:3524
+#: config/tc-i386.c:3555
#, c-format
msgid "spurious operands; (%d operands/instruction max)"
msgstr ""
-#: config/tc-i386.c:3547
+#: config/tc-i386.c:3578
msgid "expecting operand after ','; got nothing"
msgstr ""
-#: config/tc-i386.c:3552
+#: config/tc-i386.c:3583
msgid "expecting operand before ','; got nothing"
msgstr ""
-#: config/tc-i386.c:4190
+#: config/tc-i386.c:4257
msgid "operand size mismatch"
msgstr ""
-#: config/tc-i386.c:4193
+#: config/tc-i386.c:4260
msgid "operand type mismatch"
msgstr ""
-#: config/tc-i386.c:4196
+#: config/tc-i386.c:4263
msgid "register type mismatch"
msgstr ""
-#: config/tc-i386.c:4199
+#: config/tc-i386.c:4266
msgid "number of operands mismatch"
msgstr ""
-#: config/tc-i386.c:4202
+#: config/tc-i386.c:4269
msgid "invalid instruction suffix"
msgstr ""
-#: config/tc-i386.c:4205
+#: config/tc-i386.c:4272
msgid "Imm4 isn't the first operand"
msgstr ""
-#: config/tc-i386.c:4208
+#: config/tc-i386.c:4275
msgid "only supported with old gcc"
msgstr ""
-#: config/tc-i386.c:4211
+#: config/tc-i386.c:4278
msgid "unsupported with Intel mnemonic"
msgstr ""
-#: config/tc-i386.c:4214
+#: config/tc-i386.c:4281
msgid "unsupported syntax"
msgstr ""
-#: config/tc-i386.c:4217
+#: config/tc-i386.c:4284
msgid "unsupported"
msgstr ""
-#: config/tc-i386.c:4220
+#: config/tc-i386.c:4287
+msgid "invalid VSIB address"
+msgstr ""
+
+#: config/tc-i386.c:4290
+msgid "unsupported vector index register"
+msgstr ""
+
+#: config/tc-i386.c:4293
#, c-format
msgid "%s for `%s'"
msgstr ""
-#: config/tc-i386.c:4231
+#: config/tc-i386.c:4304
#, c-format
msgid "indirect %s without `*'"
msgstr ""
#. Warn them that a data or address size prefix doesn't
#. affect assembly of the next line of code.
-#: config/tc-i386.c:4239
+#: config/tc-i386.c:4312
#, c-format
msgid "stand-alone `%s' prefix"
msgstr ""
-#: config/tc-i386.c:4273 config/tc-i386.c:4289
+#: config/tc-i386.c:4346 config/tc-i386.c:4362
#, c-format
msgid "`%s' operand %d must use `%ses' segment"
msgstr ""
#. We have to know the operand size for crc32.
-#: config/tc-i386.c:4343
+#: config/tc-i386.c:4416
#, c-format
msgid "ambiguous memory operand size for `%s`"
msgstr ""
-#: config/tc-i386.c:4462
+#: config/tc-i386.c:4535
msgid ""
"no instruction mnemonic suffix given and no register operands; can't size "
"instruction"
msgstr ""
-#: config/tc-i386.c:4599 config/tc-i386.c:4674 config/tc-i386.c:4703
-#: config/tc-i386.c:4749 config/tc-i386.c:4787
+#: config/tc-i386.c:4672 config/tc-i386.c:4747 config/tc-i386.c:4776
+#: config/tc-i386.c:4822 config/tc-i386.c:4860
#, c-format
msgid "incorrect register `%s%s' used with `%c' suffix"
msgstr ""
-#: config/tc-i386.c:4607 config/tc-i386.c:4681 config/tc-i386.c:4794
+#: config/tc-i386.c:4680 config/tc-i386.c:4754 config/tc-i386.c:4867
#, c-format
msgid "using `%s%s' instead of `%s%s' due to `%c' suffix"
msgstr ""
-#: config/tc-i386.c:4633 config/tc-i386.c:4657 config/tc-i386.c:4725
-#: config/tc-i386.c:4770
+#: config/tc-i386.c:4706 config/tc-i386.c:4730 config/tc-i386.c:4798
+#: config/tc-i386.c:4843
#, c-format
msgid "`%s%s' not allowed with `%s%c'"
msgstr ""
-#: config/tc-i386.c:4859
+#: config/tc-i386.c:4932
msgid "no instruction mnemonic suffix given; can't determine immediate size"
msgstr ""
-#: config/tc-i386.c:4895
+#: config/tc-i386.c:4968
#, c-format
msgid "the last operand of `%s' must be `%s%s'"
msgstr ""
-#: config/tc-i386.c:4898
+#: config/tc-i386.c:4971
#, c-format
msgid "the first operand of `%s' must be `%s%s'"
msgstr ""
-#: config/tc-i386.c:5046
+#: config/tc-i386.c:5119
#, c-format
msgid "you can't `pop %scs'"
msgstr ""
#. Reversed arguments on faddp, fsubp, etc.
-#: config/tc-i386.c:5075
+#: config/tc-i386.c:5148
#, c-format
msgid "translating to `%s %s%s,%s%s'"
msgstr ""
#. Extraneous `l' suffix on fp insn.
-#: config/tc-i386.c:5082
+#: config/tc-i386.c:5155
#, c-format
msgid "translating to `%s %s%s'"
msgstr ""
-#: config/tc-i386.c:5110
+#: config/tc-i386.c:5183
#, c-format
msgid "segment override on `%s' is ineffectual"
msgstr ""
-#: config/tc-i386.c:5807 config/tc-i386.c:5901 config/tc-i386.c:5946
+#: config/tc-i386.c:5923 config/tc-i386.c:6017 config/tc-i386.c:6062
msgid "skipping prefixes on this instruction"
msgstr ""
-#: config/tc-i386.c:5966
+#: config/tc-i386.c:6082
msgid "16-bit jump out of range"
msgstr ""
-#: config/tc-i386.c:5975
+#: config/tc-i386.c:6091
#, c-format
msgid "can't handle non absolute segment in `%s'"
msgstr ""
-#: config/tc-i386.c:6555
+#: config/tc-i386.c:6671
#, c-format
msgid "@%s reloc is not supported with %d-bit output format"
msgstr ""
-#: config/tc-i386.c:6603
+#: config/tc-i386.c:6719
#, c-format
msgid "missing or invalid expression `%s'"
msgstr ""
-#: config/tc-i386.c:6661
+#: config/tc-i386.c:6776
#, c-format
msgid "at most %d immediate operands are allowed"
msgstr ""
-#: config/tc-i386.c:6683 config/tc-i386.c:6930
+#: config/tc-i386.c:6798 config/tc-i386.c:7045
#, c-format
msgid "junk `%s' after expression"
msgstr ""
-#: config/tc-i386.c:6704
+#: config/tc-i386.c:6819
#, c-format
msgid "missing or invalid immediate expression `%s'"
msgstr ""
-#: config/tc-i386.c:6727 config/tc-i386.c:7020
+#: config/tc-i386.c:6842 config/tc-i386.c:7135
#, c-format
msgid "unimplemented segment %s in operand"
msgstr ""
-#: config/tc-i386.c:6734
+#: config/tc-i386.c:6849
#, c-format
msgid "illegal immediate register operand %s"
msgstr ""
-#: config/tc-i386.c:6782
+#: config/tc-i386.c:6897
#, c-format
msgid "expecting scale factor of 1, 2, 4, or 8: got `%s'"
msgstr ""
-#: config/tc-i386.c:6791
+#: config/tc-i386.c:6906
#, c-format
msgid "scale factor of %d without an index register"
msgstr ""
-#: config/tc-i386.c:6813
+#: config/tc-i386.c:6928
#, c-format
msgid "at most %d displacement operands are allowed"
msgstr ""
-#: config/tc-i386.c:6986
+#: config/tc-i386.c:7101
#, c-format
msgid "missing or invalid displacement expression `%s'"
msgstr ""
-#: config/tc-i386.c:7003
+#: config/tc-i386.c:7118
#, c-format
msgid "0x%lx out range of signed 32bit displacement"
msgstr ""
-#: config/tc-i386.c:7107
+#: config/tc-i386.c:7222
#, c-format
msgid "`%s' is not valid here (expected `%c%s%s%c')"
msgstr ""
-#: config/tc-i386.c:7187
+#: config/tc-i386.c:7306
#, c-format
msgid "`%s' is not a valid %s expression"
msgstr ""
-#: config/tc-i386.c:7192
+#: config/tc-i386.c:7311
#, c-format
msgid "`%s' is not a valid %s-bit %s expression"
msgstr ""
-#: config/tc-i386.c:7273
+#: config/tc-i386.c:7392
#, c-format
msgid "bad memory operand `%s'"
msgstr ""
-#: config/tc-i386.c:7288
+#: config/tc-i386.c:7407
#, c-format
msgid "junk `%s' after register"
msgstr ""
-#: config/tc-i386.c:7301 config/tc-i386.c:7417 config/tc-i386.c:7458
+#: config/tc-i386.c:7420 config/tc-i386.c:7536 config/tc-i386.c:7577
#, c-format
msgid "bad register name `%s'"
msgstr ""
-#: config/tc-i386.c:7309
+#: config/tc-i386.c:7428
msgid "immediate operand illegal with absolute jump"
msgstr ""
-#: config/tc-i386.c:7331
+#: config/tc-i386.c:7450
#, c-format
msgid "too many memory references for `%s'"
msgstr ""
-#: config/tc-i386.c:7409
+#: config/tc-i386.c:7528
#, c-format
msgid "expecting `,' or `)' after index register in `%s'"
msgstr ""
-#: config/tc-i386.c:7434
+#: config/tc-i386.c:7553
#, c-format
msgid "expecting `)' after scale factor in `%s'"
msgstr ""
-#: config/tc-i386.c:7442
+#: config/tc-i386.c:7561
#, c-format
msgid "expecting index register or scale factor after `,'; got '%c'"
msgstr ""
-#: config/tc-i386.c:7450
+#: config/tc-i386.c:7569
#, c-format
msgid "expecting `,' or `)' after base register in `%s'"
msgstr ""
#. It's not a memory operand; argh!
-#: config/tc-i386.c:7494
+#: config/tc-i386.c:7613
#, c-format
msgid "invalid char %s beginning operand %d `%s'"
msgstr ""
-#: config/tc-i386.c:7676
+#: config/tc-i386.c:7791
msgid "long jump required"
msgstr ""
-#: config/tc-i386.c:7731
+#: config/tc-i386.c:7846
msgid "jump target out of range"
msgstr ""
-#: config/tc-i386.c:8249
+#: config/tc-i386.c:8360
msgid "no compiled in support for x86_64"
msgstr ""
-#: config/tc-i386.c:8269
+#: config/tc-i386.c:8380
msgid "no compiled in support for 32bit x86_64"
msgstr ""
-#: config/tc-i386.c:8273
+#: config/tc-i386.c:8384
msgid "32bit x86_64 is only supported for ELF"
msgstr ""
-#: config/tc-i386.c:8303 config/tc-i386.c:8359
+#: config/tc-i386.c:8414 config/tc-i386.c:8470
#, c-format
msgid "invalid -march= option: `%s'"
msgstr ""
-#: config/tc-i386.c:8368 config/tc-i386.c:8380
+#: config/tc-i386.c:8479 config/tc-i386.c:8491
#, c-format
msgid "invalid -mtune= option: `%s'"
msgstr ""
-#: config/tc-i386.c:8389
+#: config/tc-i386.c:8500
#, c-format
msgid "invalid -mmnemonic= option: `%s'"
msgstr ""
-#: config/tc-i386.c:8398
+#: config/tc-i386.c:8509
#, c-format
msgid "invalid -msyntax= option: `%s'"
msgstr ""
-#: config/tc-i386.c:8425
+#: config/tc-i386.c:8536
#, c-format
msgid "invalid -msse-check= option: `%s'"
msgstr ""
-#: config/tc-i386.c:8434
+#: config/tc-i386.c:8545
#, c-format
msgid "invalid -mavxscalar= option: `%s'"
msgstr ""
-#: config/tc-i386.c:8526
+#: config/tc-i386.c:8637
#, c-format
msgid ""
" -Q ignored\n"
" -k ignored\n"
msgstr ""
-#: config/tc-i386.c:8531
+#: config/tc-i386.c:8642
#, c-format
msgid ""
" -n Do not optimize code alignment\n"
" -q quieten some warnings\n"
msgstr ""
-#: config/tc-i386.c:8535
+#: config/tc-i386.c:8646
#, c-format
msgid " -s ignored\n"
msgstr ""
-#: config/tc-i386.c:8540
+#: config/tc-i386.c:8651
#, c-format
msgid " --32/--64/--x32 generate 32bit/64bit/x32 code\n"
msgstr ""
-#: config/tc-i386.c:8544
+#: config/tc-i386.c:8655
#, c-format
msgid " --divide do not treat `/' as a comment character\n"
msgstr ""
-#: config/tc-i386.c:8547
+#: config/tc-i386.c:8658
#, c-format
msgid " --divide ignored\n"
msgstr ""
-#: config/tc-i386.c:8550
+#: config/tc-i386.c:8661
#, c-format
msgid ""
" -march=CPU[,+EXTENSION...]\n"
"of:\n"
msgstr ""
-#: config/tc-i386.c:8554
+#: config/tc-i386.c:8665
#, c-format
msgid " EXTENSION is combination of:\n"
msgstr ""
-#: config/tc-i386.c:8557
+#: config/tc-i386.c:8668
#, c-format
msgid " -mtune=CPU optimize for CPU, CPU is one of:\n"
msgstr ""
-#: config/tc-i386.c:8560
+#: config/tc-i386.c:8671
#, c-format
msgid " -msse2avx encode SSE instructions with VEX prefix\n"
msgstr ""
-#: config/tc-i386.c:8562
+#: config/tc-i386.c:8673
#, c-format
msgid ""
" -msse-check=[none|error|warning]\n"
" check SSE instructions\n"
msgstr ""
-#: config/tc-i386.c:8565
+#: config/tc-i386.c:8676
#, c-format
msgid ""
" -mavxscalar=[128|256] encode scalar AVX instructions with specific "
" length\n"
msgstr ""
-#: config/tc-i386.c:8568
+#: config/tc-i386.c:8679
#, c-format
msgid " -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"
msgstr ""
-#: config/tc-i386.c:8570
+#: config/tc-i386.c:8681
#, c-format
msgid " -msyntax=[att|intel] use AT&T/Intel syntax\n"
msgstr ""
-#: config/tc-i386.c:8572
+#: config/tc-i386.c:8683
#, c-format
msgid " -mindex-reg support pseudo index registers\n"
msgstr ""
-#: config/tc-i386.c:8574
+#: config/tc-i386.c:8685
#, c-format
msgid " -mnaked-reg don't require `%%' prefix for registers\n"
msgstr ""
-#: config/tc-i386.c:8576
+#: config/tc-i386.c:8687
#, c-format
msgid " -mold-gcc support old (<= 2.8.1) versions of gcc\n"
msgstr ""
-#: config/tc-i386.c:8650
+#: config/tc-i386.c:8761
msgid "Intel L1OM is 64bit only"
msgstr ""
-#: config/tc-i386.c:8872
+#: config/tc-i386.c:8767
+msgid "Intel K1OM is 64bit only"
+msgstr ""
+
+#: config/tc-i386.c:8984
#, c-format
msgid "can not do %d byte pc-relative relocation"
msgstr ""
-#: config/tc-i386.c:8890
+#: config/tc-i386.c:9002
#, c-format
msgid "can not do %d byte relocation"
msgstr ""
-#: config/tc-i386.c:8959
+#: config/tc-i386.c:9070
#, c-format
msgid "cannot represent relocation type %s in x32 mode"
msgstr ""
-#: config/tc-i386.c:8994 config/tc-s390.c:2346
+#: config/tc-i386.c:9105 config/tc-s390.c:2346
#, c-format
msgid "cannot represent relocation type %s"
msgstr ""
-#: config/tc-i386.c:9101
+#: config/tc-i386.c:9222
msgid "bad .section directive: want a,l,w,x,M,S,G,T in string"
msgstr ""
-#: config/tc-i386.c:9104
+#: config/tc-i386.c:9225
msgid "bad .section directive: want a,w,x,M,S,G,T in string"
msgstr ""
-#: config/tc-i386.c:9123
+#: config/tc-i386.c:9244
msgid ".largecomm supported only in 64bit mode, producing .comm"
msgstr ""
-#: config/tc-i386.c:9178 read.c:3859
-msgid "unexpected `\"' in expression"
-msgstr ""
-
#: config/tc-i860.c:122
msgid "Directive .dual available only with -mintel-syntax option"
msgstr ""
msgstr ""
#: config/tc-i860.c:393 config/tc-i860.c:939 config/tc-m68k.c:3914
-#: config/tc-m68k.c:3946 config/tc-sparc.c:2697
+#: config/tc-m68k.c:3946 config/tc-sparc.c:2824
msgid "failed sanity check."
msgstr ""
msgid "Inserting \"%s\" into constant hash table failed: %s"
msgstr ""
-#: config/tc-ia64.c:7332 config/tc-mips.c:1916
+#: config/tc-ia64.c:7332 config/tc-mips.c:2310
msgid "Could not set architecture and machine"
msgstr ""
msgstr ""
#: config/tc-ia64.c:7761 config/tc-pdp11.c:448 config/tc-pdp11.c:512
-#: config/tc-pdp11.c:546 config/tc-xstormy16.c:155
+#: config/tc-pdp11.c:546 config/tc-tilegx.c:991 config/tc-tilepro.c:860
+#: config/tc-xstormy16.c:155
msgid "Missing ')'"
msgstr ""
msgid "Can't add stop bit to mark end of instruction group"
msgstr ""
-#: config/tc-ia64.c:11598 config/tc-score.c:6109 read.c:1448 read.c:2434
-#: read.c:3138 read.c:3476 read.c:3520
+#: config/tc-ia64.c:11598 config/tc-score.c:6105 read.c:1448 read.c:2434
+#: read.c:3137 read.c:3475 read.c:3519
msgid "expected symbol name"
msgstr ""
-#: config/tc-ia64.c:11608 read.c:2444 read.c:3148 read.c:3504 stabs.c:469
+#: config/tc-ia64.c:11608 read.c:2444 read.c:3147 read.c:3503 stabs.c:469
#, c-format
msgid "expected comma after \"%s\""
msgstr ""
msgid "Unmatched high relocation"
msgstr ""
-#: config/tc-iq2000.c:829 config/tc-mips.c:15333 config/tc-score.c:5819
+#: config/tc-iq2000.c:829 config/tc-mips.c:18680 config/tc-score.c:5815
msgid ".end not in text section"
msgstr ""
-#: config/tc-iq2000.c:833 config/tc-mips.c:15337 config/tc-score.c:5822
+#: config/tc-iq2000.c:833 config/tc-mips.c:18684 config/tc-score.c:5818
msgid ".end directive without a preceding .ent directive."
msgstr ""
-#: config/tc-iq2000.c:842 config/tc-mips.c:15346 config/tc-score.c:5830
+#: config/tc-iq2000.c:842 config/tc-mips.c:18693 config/tc-score.c:5826
msgid ".end symbol does not match .ent symbol."
msgstr ""
-#: config/tc-iq2000.c:845 config/tc-mips.c:15353 config/tc-score.c:5835
+#: config/tc-iq2000.c:845 config/tc-mips.c:18700 config/tc-score.c:5831
msgid ".end directive missing or unknown symbol"
msgstr ""
msgid "Expected simple number."
msgstr ""
-#: config/tc-iq2000.c:892 config/tc-mips.c:15258 config/tc-score.c:5670
+#: config/tc-iq2000.c:892 config/tc-mips.c:18605 config/tc-score.c:5667
#, c-format
msgid " *input_line_pointer == '%c' 0x%02x\n"
msgstr ""
msgid "Invalid number"
msgstr ""
-#: config/tc-iq2000.c:928 config/tc-mips.c:15425 config/tc-score.c:5708
+#: config/tc-iq2000.c:928 config/tc-mips.c:18772 config/tc-score.c:5705
msgid ".ent or .aent not in text section."
msgstr ""
msgid "Unrecognised option: -hidden"
msgstr ""
-#: config/tc-m32r.c:358 config/tc-sparc.c:583
+#: config/tc-m32r.c:358 config/tc-sparc.c:610
msgid "Unrecognized option following -K"
msgstr ""
msgid "Length of .scomm \"%s\" is already %ld. Not changed to %ld."
msgstr ""
-#: config/tc-m32r.c:1789
-msgid "Addend to unresolved symbol not on word boundary."
-msgstr ""
-
#: config/tc-m32r.c:1930 config/tc-m32r.c:1983 config/tc-sh.c:775
#: config/tc-sh.c:2456
msgid "Invalid PIC expression."
msgid "missing label"
msgstr ""
-#: config/tc-m68k.c:6037 config/tc-m68k.c:6066
-msgid "bad register list"
-msgstr ""
-
#: config/tc-m68k.c:6039
#, c-format
msgid "bad register list: %s"
msgstr ""
#: config/tc-microblaze.c:2363 config/tc-mn10300.c:1067 config/tc-sh.c:804
-#: config/tc-z80.c:666 read.c:4351
+#: config/tc-z80.c:666 read.c:4350
#, c-format
msgid "unsupported BFD relocation size %u"
msgstr ""
#. Prototypes for static functions.
-#: config/tc-mips.c:1064
+#: config/tc-mips.c:1315
#, c-format
msgid "internal Error, line %d, %s"
msgstr ""
-#: config/tc-mips.c:1825 config/tc-mips.c:13188
+#: config/tc-mips.c:1710
+msgid "48-bit microMIPS instructions are not supported"
+msgstr ""
+
+#: config/tc-mips.c:2119 config/tc-mips.c:16004
#, c-format
msgid "Unrecognized register name `%s'"
msgstr ""
-#: config/tc-mips.c:1911
+#: config/tc-mips.c:2305
msgid "-G may not be used in position-independent code"
msgstr ""
-#: config/tc-mips.c:1960
+#: config/tc-mips.c:2354 config/tc-mips.c:2387
#, c-format
msgid "internal: can't hash `%s': %s"
msgstr ""
-#: config/tc-mips.c:1968
+#: config/tc-mips.c:2362
#, c-format
msgid "internal error: bad mips16 opcode: %s %s\n"
msgstr ""
-#: config/tc-mips.c:2140
+#: config/tc-mips.c:2573
#, c-format
msgid "returned from mips_ip(%s) insn_opcode = 0x%x\n"
msgstr ""
-#: config/tc-mips.c:3074 config/tc-mips.c:3082
+#: config/tc-mips.c:4013
+#, c-format
+msgid "Wrong size instruction in a %u-bit branch delay slot"
+msgstr ""
+
+#: config/tc-mips.c:4061 config/tc-mips.c:4071
#, c-format
msgid "jump to misaligned address (0x%lx)"
msgstr ""
-#: config/tc-mips.c:3093 config/tc-mips.c:4042
+#: config/tc-mips.c:4086 config/tc-mips.c:5016
#, c-format
msgid "branch to misaligned address (0x%lx)"
msgstr ""
-#: config/tc-mips.c:3098 config/tc-mips.c:4045
+#: config/tc-mips.c:4092 config/tc-mips.c:5019
#, c-format
msgid "branch address range overflow (0x%lx)"
msgstr ""
-#: config/tc-mips.c:3253 config/tc-mips.c:14896
+#: config/tc-mips.c:4294 config/tc-mips.c:18182
msgid "extended instruction in delay slot"
msgstr ""
#. To reproduce this failure try assembling gas/testsuites/
#. gas/mips/mips16-intermix.s with a mips-ecoff targeted
#. assembler.
-#: config/tc-mips.c:3299
+#: config/tc-mips.c:4350
#, c-format
msgid "Unsupported MIPS relocation number %d"
msgstr ""
-#: config/tc-mips.c:3779
+#: config/tc-mips.c:4645
msgid ""
"Macro instruction expanded into multiple instructions in a branch delay slot"
msgstr ""
-#: config/tc-mips.c:3782
+#: config/tc-mips.c:4648
msgid "Macro instruction expanded into multiple instructions"
msgstr ""
-#: config/tc-mips.c:4314
+#: config/tc-mips.c:4652
+msgid ""
+"Macro instruction expanded into a wrong size instruction in a 16-bit branch "
+"delay slot"
+msgstr ""
+
+#: config/tc-mips.c:4654
+msgid ""
+"Macro instruction expanded into a wrong size instruction in a 32-bit branch "
+"delay slot"
+msgstr ""
+
+#: config/tc-mips.c:5317
msgid "operand overflow"
msgstr ""
-#: config/tc-mips.c:4333 config/tc-mips.c:4933 config/tc-mips.c:8427
+#: config/tc-mips.c:5336 config/tc-mips.c:5936 config/tc-mips.c:9932
msgid "Macro used $at after \".set noat\""
msgstr ""
-#: config/tc-mips.c:4362
+#: config/tc-mips.c:5365
msgid "unsupported large constant"
msgstr ""
-#: config/tc-mips.c:4364
+#: config/tc-mips.c:5367
#, c-format
msgid "Instruction %s requires absolute expression"
msgstr ""
-#: config/tc-mips.c:4497 config/tc-mips.c:6798 config/tc-mips.c:7390
+#: config/tc-mips.c:5500 config/tc-mips.c:8267 config/tc-mips.c:8900
#, c-format
msgid "Number (0x%s) larger than 32 bits"
msgstr ""
-#: config/tc-mips.c:4517
+#: config/tc-mips.c:5520
msgid "Number larger than 64 bits"
msgstr ""
-#: config/tc-mips.c:4811 config/tc-mips.c:4839 config/tc-mips.c:4877
-#: config/tc-mips.c:4922 config/tc-mips.c:7012 config/tc-mips.c:7051
-#: config/tc-mips.c:7090 config/tc-mips.c:7485 config/tc-mips.c:7537
+#: config/tc-mips.c:5814 config/tc-mips.c:5842 config/tc-mips.c:5880
+#: config/tc-mips.c:5925 config/tc-mips.c:8522 config/tc-mips.c:8561
+#: config/tc-mips.c:8600 config/tc-mips.c:8995 config/tc-mips.c:9047
msgid "PIC code offset overflow (max 16 signed bits)"
msgstr ""
-#: config/tc-mips.c:5244 config/tc-mips.c:5310 config/tc-mips.c:5398
-#: config/tc-mips.c:5445 config/tc-mips.c:5507 config/tc-mips.c:5556
-#: config/tc-mips.c:8521 config/tc-mips.c:8528 config/tc-mips.c:8535
-#: config/tc-mips.c:8642
+#: config/tc-mips.c:6484 config/tc-mips.c:6554 config/tc-mips.c:6640
+#: config/tc-mips.c:6686 config/tc-mips.c:6748 config/tc-mips.c:6797
+#: config/tc-mips.c:10026 config/tc-mips.c:10033 config/tc-mips.c:10040
+#: config/tc-mips.c:10147
msgid "Unsupported large constant"
msgstr ""
#. result is always true
-#: config/tc-mips.c:5276
+#: config/tc-mips.c:6518
#, c-format
msgid "Branch %s is always true"
msgstr ""
-#: config/tc-mips.c:5518 config/tc-mips.c:5567 config/tc-mips.c:9297
-#: config/tc-mips.c:9454
+#: config/tc-mips.c:6759 config/tc-mips.c:6808 config/tc-mips.c:11085
+#: config/tc-mips.c:11249
#, c-format
msgid "Improper position (%lu)"
msgstr ""
-#: config/tc-mips.c:5523 config/tc-mips.c:9364
+#: config/tc-mips.c:6764 config/tc-mips.c:11153
#, c-format
msgid "Improper extract size (%lu, position %lu)"
msgstr ""
-#: config/tc-mips.c:5572 config/tc-mips.c:9328
+#: config/tc-mips.c:6813 config/tc-mips.c:11117
#, c-format
msgid "Improper insert size (%lu, position %lu)"
msgstr ""
-#: config/tc-mips.c:5609 config/tc-mips.c:5706
+#: config/tc-mips.c:6850 config/tc-mips.c:6960
msgid "Divide by zero."
msgstr ""
-#: config/tc-mips.c:5792
+#: config/tc-mips.c:7051
msgid "dla used to load 32-bit register"
msgstr ""
-#: config/tc-mips.c:5795
+#: config/tc-mips.c:7054
msgid "la used to load 64-bit address"
msgstr ""
-#: config/tc-mips.c:5819 config/tc-mips.c:6788 config/tc-mips.c:7380
+#: config/tc-mips.c:7078 config/tc-mips.c:8257 config/tc-mips.c:8890
msgid "Expression too complex"
msgstr ""
-#: config/tc-mips.c:5907
+#: config/tc-mips.c:7166
msgid "Offset too large"
msgstr ""
-#: config/tc-mips.c:6079 config/tc-mips.c:6354
+#: config/tc-mips.c:7338 config/tc-mips.c:7613
msgid "PIC code offset overflow (max 32 signed bits)"
msgstr ""
-#: config/tc-mips.c:6432
+#: config/tc-mips.c:7713
msgid "MIPS PIC call to register other than $25"
msgstr ""
-#: config/tc-mips.c:6438 config/tc-mips.c:6449 config/tc-mips.c:6573
-#: config/tc-mips.c:6584
+#: config/tc-mips.c:7724 config/tc-mips.c:7735 config/tc-mips.c:7863
+#: config/tc-mips.c:7874
msgid "No .cprestore pseudo-op used in PIC code"
msgstr ""
-#: config/tc-mips.c:6443 config/tc-mips.c:6578
+#: config/tc-mips.c:7729 config/tc-mips.c:7868
msgid "No .frame pseudo-op used in PIC code"
msgstr ""
-#: config/tc-mips.c:6599
+#: config/tc-mips.c:7889
msgid "Non-PIC jump used in PIC library"
msgstr ""
-#: config/tc-mips.c:6765
+#: config/tc-mips.c:8249
#, c-format
msgid "Opcode not supported on this processor: %s"
msgstr ""
-#: config/tc-mips.c:7643
+#: config/tc-mips.c:9154
#, c-format
msgid "opcode not supported on this processor: %s"
msgstr ""
-#: config/tc-mips.c:7790 config/tc-mips.c:7821 config/tc-mips.c:7873
-#: config/tc-mips.c:7903
+#: config/tc-mips.c:9311 config/tc-mips.c:9342 config/tc-mips.c:9394
+#: config/tc-mips.c:9424
msgid "Improper rotate count"
msgstr ""
-#: config/tc-mips.c:7942
+#: config/tc-mips.c:9463
#, c-format
msgid "Instruction %s: result is always false"
msgstr ""
-#: config/tc-mips.c:8103
+#: config/tc-mips.c:9624
#, c-format
msgid "Instruction %s: result is always true"
msgstr ""
-#: config/tc-mips.c:8240 config/tc-mips.c:8264 config/tc-mips.c:8337
-#: config/tc-mips.c:8360
+#: config/tc-mips.c:9819
msgid "Operand overflow"
msgstr ""
#. FIXME: Check if this is one of the itbl macros, since they
#. are added dynamically.
-#: config/tc-mips.c:8423
+#: config/tc-mips.c:9928
#, c-format
msgid "Macro %s not implemented yet"
msgstr ""
-#: config/tc-mips.c:8673
+#: config/tc-mips.c:10178
#, c-format
msgid "internal: bad mips opcode (mask error): %s %s"
msgstr ""
-#: config/tc-mips.c:8718
+#: config/tc-mips.c:10223
#, c-format
msgid "internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"
msgstr ""
-#: config/tc-mips.c:8797
+#: config/tc-mips.c:10304
#, c-format
msgid "internal: bad mips opcode (unknown operand type `%c'): %s %s"
msgstr ""
-#: config/tc-mips.c:8804
+#: config/tc-mips.c:10311
#, c-format
msgid "internal: bad mips opcode (bits 0x%lx undefined): %s %s"
msgstr ""
-#: config/tc-mips.c:8927 config/tc-mips.c:8935
+#: config/tc-mips.c:10337
+#, c-format
+msgid "Internal error: bad microMIPS opcode (mask error): %s %s"
+msgstr ""
+
+#: config/tc-mips.c:10344
+#, c-format
+msgid "Internal error: bad microMIPS opcode (incorrect length: %u): %s %s"
+msgstr ""
+
+#: config/tc-mips.c:10352
+#, c-format
+msgid "Internal error: bad microMIPS opcode (opcode/length mismatch): %s %s"
+msgstr ""
+
+#: config/tc-mips.c:10383 config/tc-mips.c:10436
+#, c-format
+msgid ""
+"Internal error: bad mips opcode (unknown extension operand type `%c%c'): %s "
+"%s"
+msgstr ""
+
+#: config/tc-mips.c:10483
+#, c-format
+msgid "Internal error: bad microMIPS opcode (unknown operand type `%c'): %s %s"
+msgstr ""
+
+#: config/tc-mips.c:10492
+#, c-format
+msgid "Internal error: bad microMIPS opcode (bits 0x%lx undefined): %s %s"
+msgstr ""
+
+#: config/tc-mips.c:10496
+#, c-format
+msgid "Internal error: bad microMIPS opcode (bits 0x%lx defined): %s %s"
+msgstr ""
+
+#: config/tc-mips.c:10654
msgid "Unrecognized opcode"
msgstr ""
-#: config/tc-mips.c:8962 config/tc-mips.c:10524
+#: config/tc-mips.c:10703 config/tc-mips.c:13232
#, c-format
msgid "opcode not supported on this processor: %s (%s)"
msgstr ""
-#: config/tc-mips.c:8996
+#: config/tc-mips.c:10707
+#, c-format
+msgid "Unrecognized %u-bit version of microMIPS opcode"
+msgstr ""
+
+#: config/tc-mips.c:10738
#, c-format
msgid "BALIGN immediate not 1 or 3 (%lu)"
msgstr ""
-#: config/tc-mips.c:9009 config/tc-mips.c:9022 config/tc-mips.c:9035
-#: config/tc-mips.c:9048 config/tc-mips.c:9074 config/tc-mips.c:9118
+#: config/tc-mips.c:10752 config/tc-mips.c:10766 config/tc-mips.c:10780
+#: config/tc-mips.c:10794 config/tc-mips.c:10822 config/tc-mips.c:10869
#, c-format
msgid "DSP immediate not in range 0..%d (%lu)"
msgstr ""
-#: config/tc-mips.c:9066 config/tc-mips.c:9093
+#: config/tc-mips.c:10813 config/tc-mips.c:10842
msgid "Invalid dsp acc register"
msgstr ""
-#: config/tc-mips.c:9104 config/tc-mips.c:9135 config/tc-mips.c:9152
+#: config/tc-mips.c:10854 config/tc-mips.c:10887 config/tc-mips.c:10905
#, c-format
msgid "DSP immediate not in range %ld..%ld (%ld)"
msgstr ""
-#: config/tc-mips.c:9165
+#: config/tc-mips.c:10919
#, c-format
msgid "MT usermode bit not 0 or 1 (%lu)"
msgstr ""
-#: config/tc-mips.c:9176
+#: config/tc-mips.c:10931
#, c-format
msgid "MT load high bit not 0 or 1 (%lu)"
msgstr ""
-#: config/tc-mips.c:9193 config/tc-mips.c:9206
+#: config/tc-mips.c:10949 config/tc-mips.c:10963
msgid "Invalid dsp/smartmips acc register"
msgstr ""
-#: config/tc-mips.c:9270
+#: config/tc-mips.c:10975
+#, c-format
+msgid "Bit position for %s not in range 0..%lu (%lu)"
+msgstr ""
+
+#: config/tc-mips.c:11058
#, c-format
msgid "Illegal %s number (%lu, 0x%lx)"
msgstr ""
-#: config/tc-mips.c:9383 config/tc-mips.c:10032
+#: config/tc-mips.c:11173 config/tc-mips.c:11975
msgid "absolute expression required"
msgstr ""
-#: config/tc-mips.c:9406
+#: config/tc-mips.c:11198
#, c-format
msgid "Invalid register number (%d)"
msgstr ""
-#: config/tc-mips.c:9414
+#: config/tc-mips.c:11206
msgid "Invalid coprocessor 0 register number"
msgstr ""
-#: config/tc-mips.c:9424
+#: config/tc-mips.c:11217
#, c-format
msgid "Improper bit index (%lu)"
msgstr ""
-#: config/tc-mips.c:9485 config/tc-mips.c:9502
+#: config/tc-mips.c:11282 config/tc-mips.c:11300
#, c-format
msgid "Improper size (%lu)"
msgstr ""
-#: config/tc-mips.c:9518
+#: config/tc-mips.c:11317
#, c-format
msgid "Improper immediate (%ld)"
msgstr ""
-#: config/tc-mips.c:9535 config/tc-mips.c:9552 config/tc-mips.c:9572
+#: config/tc-mips.c:11335 config/tc-mips.c:11353 config/tc-mips.c:11374
#, c-format
msgid "Offset not in range %ld..%ld (%ld)"
msgstr ""
-#: config/tc-mips.c:9578
+#: config/tc-mips.c:11380
#, c-format
msgid "Offset not 16 bytes alignment (%ld)"
msgstr ""
-#: config/tc-mips.c:9593 config/tc-mips.c:10705
+#: config/tc-mips.c:11397 config/tc-mips.c:13413
msgid "used $at without \".set noat\""
msgstr ""
-#: config/tc-mips.c:9595 config/tc-mips.c:10707
+#: config/tc-mips.c:11399 config/tc-mips.c:13415
#, c-format
msgid "used $%u with \".set at=$%u\""
msgstr ""
-#: config/tc-mips.c:9608
+#: config/tc-mips.c:11413
#, c-format
msgid ""
-"Internal error: bad mips opcode (unknown extension operand type `+%c'): %s %s"
+"Internal error: bad %s opcode (unknown extension operand type `+%c'): %s %s"
msgstr ""
-#: config/tc-mips.c:9626
+#: config/tc-mips.c:11467
#, c-format
msgid "Improper shift amount (%lu)"
msgstr ""
-#: config/tc-mips.c:9650 config/tc-mips.c:10845 config/tc-mips.c:11098
+#: config/tc-mips.c:11493 config/tc-mips.c:13553 config/tc-mips.c:13806
#, c-format
msgid "Invalid value for `%s' (%lu)"
msgstr ""
-#: config/tc-mips.c:9686
-#, c-format
-msgid "Code for %s not in range 0..1023 (%lu)"
-msgstr ""
-
-#: config/tc-mips.c:9698
+#: config/tc-mips.c:11543 config/tc-mips.c:11581
#, c-format
-msgid "Lower code for %s not in range 0..1023 (%lu)"
+msgid "Code for %s not in range 0..%lu (%lu)"
msgstr ""
-#: config/tc-mips.c:9710
+#: config/tc-mips.c:11562
#, c-format
-msgid "Code for %s not in range 0..1048575 (%lu)"
+msgid "Lower code for %s not in range 0..%lu (%lu)"
msgstr ""
-#: config/tc-mips.c:9723
+#: config/tc-mips.c:11602
#, c-format
-msgid "Coproccesor code > 25 bits (%lu)"
+msgid "Coproccesor code > %u bits (%lu)"
msgstr ""
-#: config/tc-mips.c:9737
+#: config/tc-mips.c:11618
#, c-format
msgid "Illegal 19-bit code (%lu)"
msgstr ""
-#: config/tc-mips.c:9750
+#: config/tc-mips.c:11632
#, c-format
msgid "Invalid performance register (%lu)"
msgstr ""
-#: config/tc-mips.c:9795
+#: config/tc-mips.c:11713 config/tc-mips.c:12398
#, c-format
msgid "Used $%u with \".set at=$%u\""
msgstr ""
-#: config/tc-mips.c:9822
+#: config/tc-mips.c:11740 config/tc-mips.c:12424
msgid "Source and destination must be different"
msgstr ""
-#: config/tc-mips.c:9828
+#: config/tc-mips.c:11746 config/tc-mips.c:12430
msgid "A destination register must be supplied"
msgstr ""
-#: config/tc-mips.c:9891
+#: config/tc-mips.c:11828
#, c-format
msgid "Improper align amount (%ld), using low bits"
msgstr ""
-#: config/tc-mips.c:9905
+#: config/tc-mips.c:11843
#, c-format
msgid "Invalid MDMX Immediate (%ld)"
msgstr ""
-#: config/tc-mips.c:9943
+#: config/tc-mips.c:11882
#, c-format
msgid "Float register should be even, was %d"
msgstr ""
-#: config/tc-mips.c:9982
+#: config/tc-mips.c:11923
#, c-format
msgid "Bad element selector %ld"
msgstr ""
-#: config/tc-mips.c:9990
+#: config/tc-mips.c:11931
#, c-format
msgid "Expecting ']' found '%s'"
msgstr ""
-#: config/tc-mips.c:10096
+#: config/tc-mips.c:12039
#, c-format
msgid "Bad floating point constant: %s"
msgstr ""
-#: config/tc-mips.c:10216
+#: config/tc-mips.c:12159
msgid "Can't use floating point insn in this section"
msgstr ""
-#: config/tc-mips.c:10275
+#: config/tc-mips.c:12218
msgid "Expression out of range"
msgstr ""
-#: config/tc-mips.c:10319
+#: config/tc-mips.c:12262
#, c-format
msgid "lui expression (%lu) not in range 0..65535"
msgstr ""
-#: config/tc-mips.c:10341
+#: config/tc-mips.c:12284
#, c-format
msgid "Condition code register should be even for %s, was %d"
msgstr ""
-#: config/tc-mips.c:10347
+#: config/tc-mips.c:12290
#, c-format
msgid "Condition code register should be 0 or 4 for %s, was %d"
msgstr ""
-#: config/tc-mips.c:10374
+#: config/tc-mips.c:12317
msgid "Invalid coprocessor sub-selection value (0-7)"
msgstr ""
-#: config/tc-mips.c:10386 config/tc-mips.c:10403
+#: config/tc-mips.c:12330 config/tc-mips.c:12348
#, c-format
msgid "bad byte vector index (%ld)"
msgstr ""
-#: config/tc-mips.c:10414
+#: config/tc-mips.c:13058
+#, c-format
+msgid ""
+"Internal error: bad microMIPS opcode (unknown extension operand type `m%c'): "
+"%s %s"
+msgstr ""
+
+#: config/tc-mips.c:13110
+#, c-format
+msgid "Trap code (%lu) for %s not in 0..15 range"
+msgstr ""
+
+#: config/tc-mips.c:13119
#, c-format
msgid "Bad char = '%c'\n"
msgstr ""
-#: config/tc-mips.c:10498 config/tc-score.c:2696 config/tc-score.c:2742
+#: config/tc-mips.c:13206 config/tc-score.c:2691 config/tc-score.c:2737
msgid "unrecognized opcode"
msgstr ""
-#: config/tc-mips.c:10881 config/tc-mips.c:10962 config/tc-mips.c:10977
+#: config/tc-mips.c:13589 config/tc-mips.c:13670 config/tc-mips.c:13685
msgid "can't parse register list"
msgstr ""
-#: config/tc-mips.c:10950
+#: config/tc-mips.c:13658
msgid "more than one frame size in list"
msgstr ""
-#: config/tc-mips.c:11005
+#: config/tc-mips.c:13713
msgid "unexpected register in list"
msgstr ""
-#: config/tc-mips.c:11015
+#: config/tc-mips.c:13723
msgid "arg/static registers overlap"
msgstr ""
-#: config/tc-mips.c:11033
+#: config/tc-mips.c:13741
msgid "invalid arg register list"
msgstr ""
-#: config/tc-mips.c:11042 config/tc-mips.c:11065
+#: config/tc-mips.c:13750 config/tc-mips.c:13773
msgid "invalid static register list"
msgstr ""
-#: config/tc-mips.c:11072
+#: config/tc-mips.c:13780
msgid "missing frame size"
msgstr ""
-#: config/tc-mips.c:11075
+#: config/tc-mips.c:13783
msgid "invalid frame size"
msgstr ""
-#: config/tc-mips.c:11123
+#: config/tc-mips.c:13831
msgid "illegal operands"
msgstr ""
-#: config/tc-mips.c:11241
+#: config/tc-mips.c:13949
msgid "extended operand requested but not required"
msgstr ""
-#: config/tc-mips.c:11243
+#: config/tc-mips.c:13951
msgid "invalid unextended operand value"
msgstr ""
-#: config/tc-mips.c:11271
+#: config/tc-mips.c:13979
msgid "operand value out of range for instruction"
msgstr ""
-#: config/tc-mips.c:11376
+#: config/tc-mips.c:14084
#, c-format
msgid "relocation %s isn't supported by the current ABI"
msgstr ""
-#: config/tc-mips.c:11432
+#: config/tc-mips.c:14140
msgid "unclosed '('"
msgstr ""
-#: config/tc-mips.c:11699
+#: config/tc-mips.c:14415
#, c-format
msgid "A different %s was already specified, is now %s"
msgstr ""
-#: config/tc-mips.c:11970
+#: config/tc-mips.c:14592
+msgid "-mmicromips cannot be used with -mips16"
+msgstr ""
+
+#: config/tc-mips.c:14607
+msgid "-mips16 cannot be used with -micromips"
+msgstr ""
+
+#: config/tc-mips.c:14714
msgid "-call_shared is supported only for ELF format"
msgstr ""
-#: config/tc-mips.c:11980
+#: config/tc-mips.c:14724
msgid "-call_nonpic is supported only for ELF format"
msgstr ""
-#: config/tc-mips.c:11990
+#: config/tc-mips.c:14734
msgid "-non_shared is supported only for ELF format"
msgstr ""
-#: config/tc-mips.c:12023
+#: config/tc-mips.c:14767
msgid "-n32 is supported for ELF format only"
msgstr ""
-#: config/tc-mips.c:12032
+#: config/tc-mips.c:14776
msgid "-64 is supported for ELF format only"
msgstr ""
-#: config/tc-mips.c:12037 config/tc-mips.c:12090
+#: config/tc-mips.c:14781 config/tc-mips.c:14834
msgid "No compiled in support for 64 bit object file format"
msgstr ""
-#: config/tc-mips.c:12077
+#: config/tc-mips.c:14821
msgid "-mabi is supported for ELF format only"
msgstr ""
-#: config/tc-mips.c:12097
+#: config/tc-mips.c:14841
#, c-format
msgid "invalid abi -mabi=%s"
msgstr ""
-#: config/tc-mips.c:12177
+#: config/tc-mips.c:14921
msgid "-G not supported in this configuration."
msgstr ""
-#: config/tc-mips.c:12203
+#: config/tc-mips.c:14947
#, c-format
msgid "-%s conflicts with the other architecture options, which imply -%s"
msgstr ""
-#: config/tc-mips.c:12215
+#: config/tc-mips.c:14959
#, c-format
msgid "-march=%s is not compatible with the selected ABI"
msgstr ""
-#: config/tc-mips.c:12234
+#: config/tc-mips.c:14978
msgid "-mgp64 used with a 32-bit processor"
msgstr ""
-#: config/tc-mips.c:12236
+#: config/tc-mips.c:14980
msgid "-mgp32 used with a 64-bit ABI"
msgstr ""
-#: config/tc-mips.c:12238
+#: config/tc-mips.c:14982
msgid "-mgp64 used with a 32-bit ABI"
msgstr ""
-#: config/tc-mips.c:12276
+#: config/tc-mips.c:15020
msgid "-mfp64 used with a 32-bit fpu"
msgstr ""
-#: config/tc-mips.c:12279
+#: config/tc-mips.c:15023
msgid "-mfp64 used with a 32-bit ABI"
msgstr ""
-#: config/tc-mips.c:12283
+#: config/tc-mips.c:15027
msgid "-mfp32 used with a 64-bit ABI"
msgstr ""
-#: config/tc-mips.c:12297
+#: config/tc-mips.c:15041
msgid "trap exception not supported at ISA 1"
msgstr ""
-#: config/tc-mips.c:12307
+#: config/tc-mips.c:15053
msgid "-mfp32 used with -mips3d"
msgstr ""
-#: config/tc-mips.c:12313
+#: config/tc-mips.c:15059
msgid "-mfp32 used with -mdmx"
msgstr ""
-#: config/tc-mips.c:12318
+#: config/tc-mips.c:15064
#, c-format
msgid "%s ISA does not support SmartMIPS"
msgstr ""
-#: config/tc-mips.c:12324 config/tc-mips.c:13280
+#: config/tc-mips.c:15070 config/tc-mips.c:16108
#, c-format
msgid "%s ISA does not support DSP ASE"
msgstr ""
-#: config/tc-mips.c:12333 config/tc-mips.c:13293
+#: config/tc-mips.c:15079 config/tc-mips.c:16121
#, c-format
msgid "%s ISA does not support DSP R2 ASE"
msgstr ""
-#: config/tc-mips.c:12339 config/tc-mips.c:13306
+#: config/tc-mips.c:15085 config/tc-mips.c:16134
#, c-format
msgid "%s ISA does not support MT ASE"
msgstr ""
-#: config/tc-mips.c:12387
+#: config/tc-mips.c:15091
+#, c-format
+msgid "%s ISA does not support MCU ASE"
+msgstr ""
+
+#: config/tc-mips.c:15147
msgid "PC relative MIPS16 instruction references a different section"
msgstr ""
-#: config/tc-mips.c:12685 config/tc-sparc.c:3184 config/tc-sparc.c:3191
-#: config/tc-sparc.c:3198 config/tc-sparc.c:3205 config/tc-sparc.c:3212
-#: config/tc-sparc.c:3221 config/tc-sparc.c:3232 config/tc-sparc.c:3254
-#: config/tc-sparc.c:3278 write.c:1138
+#: config/tc-mips.c:15484 config/tc-sparc.c:3327 config/tc-sparc.c:3334
+#: config/tc-sparc.c:3341 config/tc-sparc.c:3348 config/tc-sparc.c:3355
+#: config/tc-sparc.c:3364 config/tc-sparc.c:3375 config/tc-sparc.c:3397
+#: config/tc-sparc.c:3421 write.c:1151
msgid "relocation overflow"
msgstr ""
-#: config/tc-mips.c:12695
+#: config/tc-mips.c:15497
#, c-format
msgid "Branch to misaligned address (%lx)"
msgstr ""
-#: config/tc-mips.c:12742
+#: config/tc-mips.c:15544
msgid "Branch out of range"
msgstr ""
-#: config/tc-mips.c:12824
+#: config/tc-mips.c:15640
#, c-format
msgid "Alignment too large: %d. assumed."
msgstr ""
-#: config/tc-mips.c:12827
+#: config/tc-mips.c:15643
msgid "Alignment negative: 0 assumed."
msgstr ""
-#: config/tc-mips.c:13085
+#: config/tc-mips.c:15901
#, c-format
msgid "%s: no such section"
msgstr ""
-#: config/tc-mips.c:13134
+#: config/tc-mips.c:15950
#, c-format
msgid ".option pic%d not supported"
msgstr ""
-#: config/tc-mips.c:13139 config/tc-mips.c:13446
+#: config/tc-mips.c:15955 config/tc-mips.c:16278
msgid "-G may not be used with SVR4 PIC code"
msgstr ""
-#: config/tc-mips.c:13145
+#: config/tc-mips.c:15961
#, c-format
msgid "Unrecognized option \"%s\""
msgstr ""
-#: config/tc-mips.c:13205
+#: config/tc-mips.c:16021
msgid "`noreorder' must be set before `nomacro'"
msgstr ""
-#: config/tc-mips.c:13231
+#: config/tc-mips.c:16047
#, c-format
msgid "%s isa does not support 64-bit registers"
msgstr ""
-#: config/tc-mips.c:13242
+#: config/tc-mips.c:16058
#, c-format
msgid "%s isa does not support 64-bit floating point registers"
msgstr ""
-#: config/tc-mips.c:13263
+#: config/tc-mips.c:16074
+msgid "`mips16' cannot be used with `micromips'"
+msgstr ""
+
+#: config/tc-mips.c:16083
+msgid "`micromips' cannot be used with `mips16'"
+msgstr ""
+
+#: config/tc-mips.c:16091
#, c-format
msgid "%s ISA does not support SmartMIPS ASE"
msgstr ""
-#: config/tc-mips.c:13330
+#: config/tc-mips.c:16162
#, c-format
msgid "unknown architecture %s"
msgstr ""
-#: config/tc-mips.c:13343 config/tc-mips.c:13373
+#: config/tc-mips.c:16175 config/tc-mips.c:16205
#, c-format
msgid "unknown ISA level %s"
msgstr ""
-#: config/tc-mips.c:13351
+#: config/tc-mips.c:16183
#, c-format
msgid "unknown ISA or architecture %s"
msgstr ""
-#: config/tc-mips.c:13401
+#: config/tc-mips.c:16233
msgid ".set pop with no .set push"
msgstr ""
-#: config/tc-mips.c:13430
+#: config/tc-mips.c:16262
#, c-format
msgid "Tried to set unrecognized symbol: %s\n"
msgstr ""
-#: config/tc-mips.c:13488
+#: config/tc-mips.c:16320
msgid ".cpload not in noreorder section"
msgstr ""
-#: config/tc-mips.c:13556 config/tc-mips.c:13575
+#: config/tc-mips.c:16388 config/tc-mips.c:16407
msgid "missing argument separator ',' for .cpsetup"
msgstr ""
-#: config/tc-mips.c:13733
+#: config/tc-mips.c:16565
#, c-format
msgid "Unsupported use of %s"
msgstr ""
-#: config/tc-mips.c:13815 config/tc-score.c:6035
+#: config/tc-mips.c:16647 config/tc-score.c:6031
msgid "Unsupported use of .gpword"
msgstr ""
-#: config/tc-mips.c:13855
+#: config/tc-mips.c:16687
msgid "Unsupported use of .gpdword"
msgstr ""
-#: config/tc-mips.c:13949
+#: config/tc-mips.c:16781
#, c-format
msgid "ignoring attempt to redefine symbol %s"
msgstr ""
-#: config/tc-mips.c:13964 ecoff.c:3378
+#: config/tc-mips.c:16796 ecoff.c:3378
msgid "bad .weakext directive"
msgstr ""
-#: config/tc-mips.c:14200
+#: config/tc-mips.c:17032
msgid "unsupported PC relative reference to different section"
msgstr ""
-#: config/tc-mips.c:14313 config/tc-xtensa.c:1583 config/tc-xtensa.c:1859
+#: config/tc-mips.c:17145 config/tc-xtensa.c:1583 config/tc-xtensa.c:1859
msgid "unsupported relocation"
msgstr ""
-#: config/tc-mips.c:14571 config/tc-pdp11.c:1424
+#: config/tc-mips.c:17577 config/tc-pdp11.c:1424
#, c-format
msgid "Can not represent %s relocation in this object file format"
msgstr ""
-#: config/tc-mips.c:14656
+#: config/tc-mips.c:17676 config/tc-mips.c:17970
msgid "Relaxed out-of-range branch into a jump"
msgstr ""
-#: config/tc-mips.c:15217
+#: config/tc-mips.c:18564
msgid "missing .end at end of assembly"
msgstr ""
-#: config/tc-mips.c:15232 config/tc-score.c:5644
+#: config/tc-mips.c:18579 config/tc-score.c:5641
msgid "expected simple number"
msgstr ""
-#: config/tc-mips.c:15260 config/tc-score.c:5671
+#: config/tc-mips.c:18607 config/tc-score.c:5668
msgid "invalid number"
msgstr ""
-#: config/tc-mips.c:15428 config/tc-score.c:5710
+#: config/tc-mips.c:18775 config/tc-score.c:5707
msgid "missing .end"
msgstr ""
-#: config/tc-mips.c:15480
+#: config/tc-mips.c:18827
msgid "Bad .frame directive"
msgstr ""
-#: config/tc-mips.c:15512
+#: config/tc-mips.c:18859
msgid ".mask/.fmask outside of .ent"
msgstr ""
-#: config/tc-mips.c:15519
+#: config/tc-mips.c:18866
msgid "Bad .mask/.fmask directive"
msgstr ""
-#: config/tc-mips.c:15796
+#: config/tc-mips.c:19145
#, c-format
msgid "Bad value (%s) for %s"
msgstr ""
-#: config/tc-mips.c:15860
+#: config/tc-mips.c:19209
#, c-format
msgid ""
"MIPS options:\n"
"\t\t\timplicitly with the gp register [default 8]\n"
msgstr ""
-#: config/tc-mips.c:15867
+#: config/tc-mips.c:19216
#, c-format
msgid ""
"-mips1\t\t\tgenerate MIPS ISA I instructions\n"
"-march=CPU/-mtune=CPU\tgenerate code/schedule for CPU, where CPU is one of:\n"
msgstr ""
-#: config/tc-mips.c:15886
+#: config/tc-mips.c:19235
#, c-format
msgid ""
"-mCPU\t\t\tequivalent to -march=CPU -mtune=CPU. Deprecated.\n"
"\t\t\tFor -mCPU and -no-mCPU, CPU must be one of:\n"
msgstr ""
-#: config/tc-mips.c:15899
+#: config/tc-mips.c:19248
#, c-format
msgid ""
"-mips16\t\t\tgenerate mips16 instructions\n"
"-no-mips16\t\tdo not generate mips16 instructions\n"
msgstr ""
-#: config/tc-mips.c:15902
+#: config/tc-mips.c:19251
+#, c-format
+msgid ""
+"-mmicromips\t\tgenerate microMIPS instructions\n"
+"-mno-micromips\t\tdo not generate microMIPS instructions\n"
+msgstr ""
+
+#: config/tc-mips.c:19254
#, c-format
msgid ""
"-msmartmips\t\tgenerate smartmips instructions\n"
"-mno-smartmips\t\tdo not generate smartmips instructions\n"
msgstr ""
-#: config/tc-mips.c:15905
+#: config/tc-mips.c:19257
#, c-format
msgid ""
"-mdsp\t\t\tgenerate DSP instructions\n"
"-mno-dsp\t\tdo not generate DSP instructions\n"
msgstr ""
-#: config/tc-mips.c:15908
+#: config/tc-mips.c:19260
#, c-format
msgid ""
"-mdspr2\t\t\tgenerate DSP R2 instructions\n"
"-mno-dspr2\t\tdo not generate DSP R2 instructions\n"
msgstr ""
-#: config/tc-mips.c:15911
+#: config/tc-mips.c:19263
#, c-format
msgid ""
"-mmt\t\t\tgenerate MT instructions\n"
"-mno-mt\t\t\tdo not generate MT instructions\n"
msgstr ""
-#: config/tc-mips.c:15914
+#: config/tc-mips.c:19266
+#, c-format
+msgid ""
+"-mmcu\t\t\tgenerate MCU instructions\n"
+"-mno-mcu\t\tdo not generate MCU instructions\n"
+msgstr ""
+
+#: config/tc-mips.c:19269
#, c-format
msgid ""
"-mfix-loongson2f-jump\twork around Loongson2F JUMP instructions\n"
"--break, --no-trap\tbreak exception on div by 0 and mult overflow\n"
msgstr ""
-#: config/tc-mips.c:15928
+#: config/tc-mips.c:19283
#, c-format
msgid ""
"-mhard-float\t\tallow floating-point instructions\n"
"--[no-]construct-floats [dis]allow floating point values to be constructed\n"
msgstr ""
-#: config/tc-mips.c:15936
+#: config/tc-mips.c:19291
#, c-format
msgid ""
"-KPIC, -call_shared\tgenerate SVR4 position independent code\n"
"-mabi=ABI\t\tcreate ABI conformant object file for:\n"
msgstr ""
-#: config/tc-mips.c:15957
+#: config/tc-mips.c:19312
#, c-format
msgid ""
"-32\t\t\tcreate o32 ABI object file (default)\n"
msgid "6-bit displacement out of range"
msgstr ""
-#: config/tc-pdp11.c:974 config/tc-vax.c:1944
+#: config/tc-pdp11.c:974 config/tc-tilegx.c:1160 config/tc-tilepro.c:1023
+#: config/tc-vax.c:1944
msgid "Too many operands"
msgstr ""
msgid "missing rename string"
msgstr ""
-#: config/tc-ppc.c:3864 config/tc-ppc.c:4406 read.c:3364
+#: config/tc-ppc.c:3864 config/tc-ppc.c:4406 read.c:3363
msgid "missing value"
msgstr ""
msgid "Unrecognized symbol suffix"
msgstr ""
-#: config/tc-ppc.c:5424
+#: config/tc-ppc.c:5425
msgid "two .function pseudo-ops with no intervening .ef"
msgstr ""
-#: config/tc-ppc.c:5437
+#: config/tc-ppc.c:5438
msgid ".ef with no preceding .function"
msgstr ""
-#: config/tc-ppc.c:5566
+#: config/tc-ppc.c:5567
#, c-format
msgid "warning: symbol %s has no csect"
msgstr ""
-#: config/tc-ppc.c:5828
+#: config/tc-ppc.c:5829
msgid "symbol in .toc does not match any .tc"
msgstr ""
-#: config/tc-ppc.c:6230
+#: config/tc-ppc.c:6200
#, c-format
msgid "unsupported relocation against %s"
msgstr ""
-#: config/tc-ppc.c:6303
+#: config/tc-ppc.c:6273
#, c-format
msgid "cannot emit PC relative %s relocation against %s"
msgstr ""
-#: config/tc-ppc.c:6308
+#: config/tc-ppc.c:6278
#, c-format
msgid "cannot emit PC relative %s relocation"
msgstr ""
-#: config/tc-ppc.c:6497
+#: config/tc-ppc.c:6467
#, c-format
msgid "Unable to handle reference to symbol %s"
msgstr ""
-#: config/tc-ppc.c:6500
+#: config/tc-ppc.c:6470
msgid "Unable to resolve expression"
msgstr ""
-#: config/tc-ppc.c:6527
+#: config/tc-ppc.c:6497
msgid "must branch to an address a multiple of 4"
msgstr ""
-#: config/tc-ppc.c:6531
+#: config/tc-ppc.c:6501
#, c-format
msgid "@local or @plt branch destination is too far away, %ld bytes"
msgstr ""
-#: config/tc-ppc.c:6562
+#: config/tc-ppc.c:6532
#, c-format
msgid "Gas failure, reloc value %d\n"
msgstr ""
-#: config/tc-rx.c:133
+#: config/tc-rx.c:151
#, c-format
msgid " RX specific command line options:\n"
msgstr ""
-#: config/tc-rx.c:134
+#: config/tc-rx.c:152
#, c-format
msgid " --mbig-endian-data\n"
msgstr ""
-#: config/tc-rx.c:135
+#: config/tc-rx.c:153
#, c-format
msgid " --mlittle-endian-data [default]\n"
msgstr ""
-#: config/tc-rx.c:136
+#: config/tc-rx.c:154
#, c-format
msgid " --m32bit-doubles [default]\n"
msgstr ""
-#: config/tc-rx.c:137
+#: config/tc-rx.c:155
#, c-format
msgid " --m64bit-doubles\n"
msgstr ""
-#: config/tc-rx.c:138
+#: config/tc-rx.c:156
#, c-format
msgid " --muse-conventional-section-names\n"
msgstr ""
-#: config/tc-rx.c:139
+#: config/tc-rx.c:157
#, c-format
msgid " --muse-renesas-section-names [default]\n"
msgstr ""
-#: config/tc-rx.c:140
+#: config/tc-rx.c:158
#, c-format
msgid " --msmall-data-limit\n"
msgstr ""
-#: config/tc-rx.c:220
+#: config/tc-rx.c:159
+#, c-format
+msgid " --mrelax\n"
+msgstr ""
+
+#: config/tc-rx.c:160
+#, c-format
+msgid " --mpid\n"
+msgstr ""
+
+#: config/tc-rx.c:161
+#, c-format
+msgid " --mint-register=<value>\n"
+msgstr ""
+
+#: config/tc-rx.c:241
msgid "no filename following .INCLUDE pseudo-op"
msgstr ""
-#: config/tc-rx.c:323
+#: config/tc-rx.c:344
#, c-format
msgid "unable to locate include file: %s"
msgstr ""
-#: config/tc-rx.c:374
+#: config/tc-rx.c:395
#, c-format
msgid "unrecognised alignment value in .SECTION directive: %s"
msgstr ""
-#: config/tc-rx.c:391
+#: config/tc-rx.c:412
#, c-format
msgid "unknown parameter following .SECTION directive: %s"
msgstr ""
-#: config/tc-rx.c:480
+#: config/tc-rx.c:501
msgid "expecting either ON or OFF after .list"
msgstr ""
-#: config/tc-rx.c:516
+#: config/tc-rx.c:537
#, c-format
msgid "The \".%s\" pseudo-op is not implemented\n"
msgstr ""
-#: config/tc-rx.c:748
+#: config/tc-rx.c:797
#, c-format
msgid "Value %d doesn't fit in unsigned %d-bit field"
msgstr ""
-#: config/tc-rx.c:754
+#: config/tc-rx.c:803
#, c-format
msgid "Value %d doesn't fit in signed %d-bit field"
msgstr ""
-#: config/tc-rx.c:954
+#: config/tc-rx.c:1003
msgid "The .DEFINE pseudo-op is not implemented"
msgstr ""
-#: config/tc-rx.c:956
+#: config/tc-rx.c:1005
msgid "The .MACRO pseudo-op is not implemented"
msgstr ""
-#: config/tc-rx.c:958
+#: config/tc-rx.c:1007
msgid "The .BTEQU pseudo-op is not implemented."
msgstr ""
-#: config/tc-rx.c:1883
+#: config/tc-rx.c:1932
msgid "invalid immediate size"
msgstr ""
-#: config/tc-rx.c:1902
+#: config/tc-rx.c:1951
msgid "invalid immediate field position"
msgstr ""
-#: config/tc-rx.c:1951
+#: config/tc-rx.c:2000
#, c-format
msgid "bad frag at %p : fix %ld addr %ld %ld \n"
msgstr ""
-#: config/tc-rx.c:2018
+#: config/tc-rx.c:2067
#, c-format
msgid "unsupported constant size %d\n"
msgstr ""
-#: config/tc-rx.c:2025
+#: config/tc-rx.c:2074
msgid "difference of two symbols only supported with .long, .short, or .byte"
msgstr ""
-#: config/tc-rx.c:2069
+#: config/tc-rx.c:2118
#, c-format
msgid "jump not 3..10 bytes away (is %d)"
msgstr ""
-#: config/tc-rx.c:2215
+#: config/tc-rx.c:2264
#, c-format
msgid "Unknown reloc in md_apply_fix: %s"
msgstr ""
-#: config/tc-s390.c:332 config/tc-sparc.c:272
+#: config/tc-s390.c:332 config/tc-sparc.c:296
msgid "Invalid default architecture, broken assembler."
msgstr ""
-#: config/tc-s390.c:439 config/tc-sparc.c:475
+#: config/tc-s390.c:439 config/tc-sparc.c:499
#, c-format
msgid "invalid architecture -A%s"
msgstr ""
msgid "S+core co-processor register expected"
msgstr ""
-#: config/tc-score.c:1074 config/tc-score.c:2073
+#: config/tc-score.c:1074 config/tc-score.c:2068
msgid "Using temp register(r1)"
msgstr ""
msgid "register expected, not '%.100s'"
msgstr ""
-#: config/tc-score.c:1149 config/tc-score.c:5488
+#: config/tc-score.c:1149 config/tc-score.c:5485
msgid "rd must be even number."
msgstr ""
-#: config/tc-score.c:1520 config/tc-score.c:1527
+#: config/tc-score.c:1513 config/tc-score.c:1520
#, c-format
msgid "invalid constant: %d bit expression not in range %u..%u"
msgstr ""
-#: config/tc-score.c:1533 config/tc-score.c:1540 config/tc-score.c:2900
-#: config/tc-score.c:2905 config/tc-score.c:3172 config/tc-score.c:3177
-#: config/tc-score.c:3470
+#: config/tc-score.c:1526 config/tc-score.c:1533 config/tc-score.c:2895
+#: config/tc-score.c:2900 config/tc-score.c:3165 config/tc-score.c:3170
+#: config/tc-score.c:3462
#, c-format
msgid "invalid constant: %d bit expression not in range %d..%d"
msgstr ""
-#: config/tc-score.c:1565
+#: config/tc-score.c:1558
msgid "invalid constant: bit expression not defined"
msgstr ""
-#: config/tc-score.c:2087
+#: config/tc-score.c:2082
#, c-format
msgid "low register(r0-r15)expected, not '%.100s'"
msgstr ""
-#: config/tc-score.c:2149 config/tc-score.c:3491 config/tc-score.c:3659
-#: config/tc-score.c:3704
+#: config/tc-score.c:2144 config/tc-score.c:3482 config/tc-score.c:3650
+#: config/tc-score.c:3695
#, c-format
msgid "missing ["
msgstr ""
-#: config/tc-score.c:2163 config/tc-score.c:3110 config/tc-score.c:3312
-#: config/tc-score.c:3328 config/tc-score.c:3399 config/tc-score.c:3455
-#: config/tc-score.c:3680 config/tc-score.c:3725 config/tc-score.c:3874
-#: config/tc-score.c:3928 config/tc-score.c:3974
+#: config/tc-score.c:2158 config/tc-score.c:3103 config/tc-score.c:3305
+#: config/tc-score.c:3321 config/tc-score.c:3392 config/tc-score.c:3447
+#: config/tc-score.c:3671 config/tc-score.c:3716 config/tc-score.c:3865
+#: config/tc-score.c:3919 config/tc-score.c:3965
#, c-format
msgid "missing ]"
msgstr ""
-#: config/tc-score.c:2352
+#: config/tc-score.c:2347
#, c-format
msgid "Fix data dependency: %s %s -- %s %s (insert %d nop!/%d)"
msgstr ""
-#: config/tc-score.c:2371
+#: config/tc-score.c:2366
#, c-format
msgid "Fix data dependency: %s %s -- %s %s (insert 1 pflush/%d)"
msgstr ""
-#: config/tc-score.c:2387 config/tc-score.c:2394
+#: config/tc-score.c:2382 config/tc-score.c:2389
#, c-format
msgid "data dependency: %s %s -- %s %s (%d/%d bubble)"
msgstr ""
-#: config/tc-score.c:2755 config/tc-score.c:6508
+#: config/tc-score.c:2750 config/tc-score.c:6504
#, c-format
msgid "%s -- `%s'"
msgstr ""
-#: config/tc-score.c:2843
+#: config/tc-score.c:2838
msgid "address offset must be half word alignment"
msgstr ""
-#: config/tc-score.c:2851
+#: config/tc-score.c:2846
msgid "address offset must be word alignment"
msgstr ""
-#: config/tc-score.c:2993 config/tc-score.c:3130
+#: config/tc-score.c:2986 config/tc-score.c:3123
msgid "register same as write-back base"
msgstr ""
-#: config/tc-score.c:3100
+#: config/tc-score.c:3093
msgid "pre-indexed expression expected"
msgstr ""
-#: config/tc-score.c:3430
+#: config/tc-score.c:3422
#, c-format
msgid "invalid register number: %d is not in [r0--r7]"
msgstr ""
-#: config/tc-score.c:3447
+#: config/tc-score.c:3439
msgid "comma is expected"
msgstr ""
-#: config/tc-score.c:3478
+#: config/tc-score.c:3470
#, c-format
msgid "invalid constant: %d is not word align integer"
msgstr ""
-#: config/tc-score.c:3518 config/tc-score.c:3561
+#: config/tc-score.c:3509 config/tc-score.c:3552
msgid "invalid constant: 32 bit expression not word align"
msgstr ""
-#: config/tc-score.c:3527 config/tc-score.c:3570
+#: config/tc-score.c:3518 config/tc-score.c:3561
msgid "invalid constant: 32 bit expression not in range [0, 0xffffffff]"
msgstr ""
-#: config/tc-score.c:3603
+#: config/tc-score.c:3594
msgid ""
"invalid constant: 32 bit expression not in range [-0x80000000, 0x7fffffff]"
msgstr ""
-#: config/tc-score.c:3792 config/tc-score.c:3820
+#: config/tc-score.c:3783 config/tc-score.c:3811
msgid "imm5 should >= 2"
msgstr ""
-#: config/tc-score.c:3797 config/tc-score.c:3826
+#: config/tc-score.c:3788 config/tc-score.c:3817
msgid "reg should <= 31"
msgstr ""
-#: config/tc-score.c:3868 config/tc-score.c:3919
+#: config/tc-score.c:3859 config/tc-score.c:3910
msgid "missing +"
msgstr ""
-#: config/tc-score.c:3912
+#: config/tc-score.c:3903
#, c-format
msgid "%s register same as write-back base"
msgstr ""
-#: config/tc-score.c:3914
+#: config/tc-score.c:3905
msgid "destination"
msgstr ""
-#: config/tc-score.c:3914
+#: config/tc-score.c:3905
msgid "source"
msgstr ""
-#: config/tc-score.c:4244 config/tc-score.c:4320 config/tc-score.c:4949
+#: config/tc-score.c:4235 config/tc-score.c:4311 config/tc-score.c:4946
msgid "expression error"
msgstr ""
-#: config/tc-score.c:4250
+#: config/tc-score.c:4241
msgid "value not in range [0, 0xffffffff]"
msgstr ""
-#: config/tc-score.c:4326
+#: config/tc-score.c:4317
msgid "value not in range [-0xffffffff, 0xffffffff]"
msgstr ""
-#: config/tc-score.c:4354
+#: config/tc-score.c:4345
msgid "li rd label isn't correct instruction form"
msgstr ""
-#: config/tc-score.c:4523 config/tc-score.c:4674 config/tc-score.c:5200
-#: config/tc-score.c:5228
+#: config/tc-score.c:4515 config/tc-score.c:4670 config/tc-score.c:5197
+#: config/tc-score.c:5225
msgid "lacking label "
msgstr ""
-#: config/tc-score.c:4899
+#: config/tc-score.c:4896
msgid "s3_PIC code offset overflow (max 16 signed bits)"
msgstr ""
-#: config/tc-score.c:4955
+#: config/tc-score.c:4952
msgid "value not in range [0, 0x7fffffff]"
msgstr ""
-#: config/tc-score.c:4960
+#: config/tc-score.c:4957
msgid "end on line error"
msgstr ""
-#: config/tc-score.c:5207
+#: config/tc-score.c:5204
msgid "invalid constant: 25 bit expression not in range [-16777216, 16777215]"
msgstr ""
-#: config/tc-score.c:5234
+#: config/tc-score.c:5231
msgid "invalid constant: 20 bit expression not in range -2^19..2^19"
msgstr ""
-#: config/tc-score.c:5267
+#: config/tc-score.c:5264
msgid "lacking label"
msgstr ""
-#: config/tc-score.c:5272
+#: config/tc-score.c:5269
msgid "invalid constant: 10 bit expression not in range [-2^9, 2^9-1]"
msgstr ""
-#: config/tc-score.c:5368
+#: config/tc-score.c:5365
msgid "pce instruction error (16 bit || 16 bit)'"
msgstr ""
-#: config/tc-score.c:5386 config/tc-score.c:5410 config/tc-score.c:5437
-#: config/tc-score.c:5466 config/tc-score.c:5515
+#: config/tc-score.c:5383 config/tc-score.c:5407 config/tc-score.c:5434
+#: config/tc-score.c:5463 config/tc-score.c:5512
msgid "score3d instruction."
msgstr ""
-#: config/tc-score.c:6126 read.c:1465
+#: config/tc-score.c:6122 read.c:1465
msgid "missing size expression"
msgstr ""
-#: config/tc-score.c:6132
+#: config/tc-score.c:6128
#, c-format
msgid "BSS length (%d) < 0 ignored"
msgstr ""
-#: config/tc-score.c:6147 read.c:2298
+#: config/tc-score.c:6143 read.c:2298
#, c-format
msgid "error setting flags for \".sbss\": %s"
msgstr ""
-#: config/tc-score.c:6161 config/tc-sparc.c:3695
+#: config/tc-score.c:6157 config/tc-sparc.c:3838
msgid "missing alignment"
msgstr ""
-#: config/tc-score.c:6198
+#: config/tc-score.c:6194
#, c-format
msgid "alignment too large; %d assumed"
msgstr ""
-#: config/tc-score.c:6203 read.c:2359
+#: config/tc-score.c:6199 read.c:2359
msgid "alignment negative; 0 assumed"
msgstr ""
-#: config/tc-score.c:6270 ecoff.c:3365 read.c:1484 read.c:1590 read.c:2476
-#: read.c:3098 read.c:3488 symbols.c:334 symbols.c:430
+#: config/tc-score.c:6266 ecoff.c:3365 read.c:1484 read.c:1590 read.c:2476
+#: read.c:3097 read.c:3487 symbols.c:336 symbols.c:432
#, c-format
msgid "symbol `%s' is already defined"
msgstr ""
#. Error routine.
-#: config/tc-score.c:6612 config/tc-score.c:6636
+#: config/tc-score.c:6608 config/tc-score.c:6632
msgid "size is not 4 or 6"
msgstr ""
-#: config/tc-score.c:6695
+#: config/tc-score.c:6691
msgid "bad call to MD_ATOF()"
msgstr ""
-#: config/tc-score.c:7203
+#: config/tc-score.c:7198
#, c-format
msgid " branch relocation truncate (0x%x) [-2^9 ~ 2^9]"
msgstr ""
-#: config/tc-score.c:7218 config/tc-score.c:7247 config/tc-score.c:7299
+#: config/tc-score.c:7213 config/tc-score.c:7242 config/tc-score.c:7294
#, c-format
msgid " branch relocation truncate (0x%x) [-2^19 ~ 2^19]"
msgstr ""
-#: config/tc-score.c:7269 config/tc-score.c:7324
+#: config/tc-score.c:7264 config/tc-score.c:7319
#, c-format
msgid " branch relocation truncate (0x%x) [-2^9 ~ 2^9]"
msgstr ""
-#: config/tc-score.c:7500
+#: config/tc-score.c:7488
#, c-format
msgid "cannot represent %s relocation in this object file format1"
msgstr ""
-#: config/tc-score.c:7791
+#: config/tc-score.c:7779
#, c-format
msgid "Sunplus-v2-0-0-20060510\n"
msgstr ""
-#: config/tc-score.c:7811
+#: config/tc-score.c:7799
#, c-format
msgid " Score-specific assembler options:\n"
msgstr ""
-#: config/tc-score.c:7813
+#: config/tc-score.c:7801
#, c-format
msgid " -EB\t\tassemble code for a big-endian cpu\n"
msgstr ""
-#: config/tc-score.c:7818
+#: config/tc-score.c:7806
#, c-format
msgid " -EL\t\tassemble code for a little-endian cpu\n"
msgstr ""
-#: config/tc-score.c:7822
+#: config/tc-score.c:7810
#, c-format
msgid " -FIXDD\t\tassemble code for fix data dependency\n"
msgstr ""
-#: config/tc-score.c:7824
+#: config/tc-score.c:7812
#, c-format
msgid ""
" -NWARN\t\tassemble code for no warning message for fix data "
"dependency\n"
msgstr ""
-#: config/tc-score.c:7826
+#: config/tc-score.c:7814
#, c-format
msgid " -SCORE5\t\tassemble code for target is SCORE5\n"
msgstr ""
-#: config/tc-score.c:7828
+#: config/tc-score.c:7816
#, c-format
msgid " -SCORE5U\tassemble code for target is SCORE5U\n"
msgstr ""
-#: config/tc-score.c:7830
+#: config/tc-score.c:7818
#, c-format
msgid ""
" -SCORE7\t\tassemble code for target is SCORE7, this is default "
"setting\n"
msgstr ""
-#: config/tc-score.c:7832
+#: config/tc-score.c:7820
#, c-format
msgid " -SCORE3\t\tassemble code for target is SCORE3\n"
msgstr ""
-#: config/tc-score.c:7834
+#: config/tc-score.c:7822
#, c-format
msgid ""
" -march=score7\tassemble code for target is SCORE7, this is default "
"setting\n"
msgstr ""
-#: config/tc-score.c:7836
+#: config/tc-score.c:7824
#, c-format
msgid " -march=score3\tassemble code for target is SCORE3\n"
msgstr ""
-#: config/tc-score.c:7838
+#: config/tc-score.c:7826
#, c-format
msgid ""
" -USE_R1\t\tassemble code for no warning message when using temp "
"register r1\n"
msgstr ""
-#: config/tc-score.c:7840
+#: config/tc-score.c:7828
#, c-format
msgid " -KPIC\t\tassemble code for PIC\n"
msgstr ""
-#: config/tc-score.c:7842
+#: config/tc-score.c:7830
#, c-format
msgid " -O0\t\tassembler will not perform any optimizations\n"
msgstr ""
-#: config/tc-score.c:7844
+#: config/tc-score.c:7832
#, c-format
msgid ""
" -G gpnum\tassemble code for setting gpsize and default is 8 byte\n"
msgstr ""
-#: config/tc-score.c:7846
+#: config/tc-score.c:7834
#, c-format
msgid " -V \t\tSunplus release version \n"
msgstr ""
msgid "overflow in branch to %s; converted into longer instruction sequence"
msgstr ""
-#: config/tc-sh.c:3749 config/tc-sh.c:3796 config/tc-sparc.c:4202
-#: config/tc-sparc.c:4226
+#: config/tc-sh.c:3749 config/tc-sh.c:3796 config/tc-sparc.c:4345
+#: config/tc-sparc.c:4369
msgid "misaligned data"
msgstr ""
msgid "Invalid DataLabel expression"
msgstr ""
-#: config/tc-sparc.c:276 config/tc-sparc.c:481
+#: config/tc-sparc.c:300 config/tc-sparc.c:505
msgid "Bad opcode table, broken assembler."
msgstr ""
-#: config/tc-sparc.c:473
+#: config/tc-sparc.c:497
#, c-format
msgid "invalid architecture -xarch=%s"
msgstr ""
-#: config/tc-sparc.c:542
+#: config/tc-sparc.c:569
#, c-format
msgid "No compiled in support for %d bit object file format"
msgstr ""
-#: config/tc-sparc.c:623
+#: config/tc-sparc.c:650
#, c-format
msgid "SPARC options:\n"
msgstr ""
-#: config/tc-sparc.c:652
+#: config/tc-sparc.c:679
#, c-format
msgid ""
"\n"
"-no-relax\t\tavoid changing any jumps and branches\n"
msgstr ""
-#: config/tc-sparc.c:660
+#: config/tc-sparc.c:687
#, c-format
msgid "-k\t\t\tgenerate PIC\n"
msgstr ""
-#: config/tc-sparc.c:664
+#: config/tc-sparc.c:691
#, c-format
msgid ""
"-32\t\t\tcreate 32 bit object file\n"
"-64\t\t\tcreate 64 bit object file\n"
msgstr ""
-#: config/tc-sparc.c:667
+#: config/tc-sparc.c:694
#, c-format
msgid "\t\t\t[default is %d]\n"
msgstr ""
-#: config/tc-sparc.c:669
+#: config/tc-sparc.c:696
#, c-format
msgid ""
"-TSO\t\t\tuse Total Store Ordering\n"
"-RMO\t\t\tuse Relaxed Memory Ordering\n"
msgstr ""
-#: config/tc-sparc.c:673
+#: config/tc-sparc.c:700
#, c-format
msgid "\t\t\t[default is %s]\n"
msgstr ""
-#: config/tc-sparc.c:675
+#: config/tc-sparc.c:702
#, c-format
msgid ""
"-KPIC\t\t\tgenerate PIC\n"
"-s\t\t\tignored\n"
msgstr ""
-#: config/tc-sparc.c:687
+#: config/tc-sparc.c:714
#, c-format
msgid ""
"-EL\t\t\tgenerate code for a little endian machine\n"
" instructions and little endian data.\n"
msgstr ""
-#: config/tc-sparc.c:823
+#: config/tc-sparc.c:851
#, c-format
msgid "Internal error: losing opcode: `%s' \"%s\"\n"
msgstr ""
-#: config/tc-sparc.c:842
+#: config/tc-sparc.c:870
#, c-format
msgid "Internal error: can't find opcode `%s' for `%s'\n"
msgstr ""
-#: config/tc-sparc.c:983
+#: config/tc-sparc.c:1053
msgid "Support for 64-bit arithmetic not compiled in."
msgstr ""
-#: config/tc-sparc.c:1029
+#: config/tc-sparc.c:1099
msgid "set: number not in 0..4294967295 range"
msgstr ""
-#: config/tc-sparc.c:1036
+#: config/tc-sparc.c:1106
msgid "set: number not in -2147483648..4294967295 range"
msgstr ""
-#: config/tc-sparc.c:1095
+#: config/tc-sparc.c:1165
msgid "setsw: number not in -2147483648..4294967295 range"
msgstr ""
-#: config/tc-sparc.c:1143
+#: config/tc-sparc.c:1213
msgid "setx: temporary register same as destination register"
msgstr ""
-#: config/tc-sparc.c:1214
+#: config/tc-sparc.c:1284
msgid "setx: illegal temporary register g0"
msgstr ""
-#: config/tc-sparc.c:1311
+#: config/tc-sparc.c:1381
msgid "FP branch in delay slot"
msgstr ""
-#: config/tc-sparc.c:1326
+#: config/tc-sparc.c:1396
msgid "FP branch preceded by FP instruction; NOP inserted"
msgstr ""
-#: config/tc-sparc.c:1366
+#: config/tc-sparc.c:1436
msgid "failed special case insn sanity check"
msgstr ""
-#: config/tc-sparc.c:1454
+#: config/tc-sparc.c:1562
msgid ": invalid membar mask name"
msgstr ""
-#: config/tc-sparc.c:1470
+#: config/tc-sparc.c:1578
msgid ": invalid membar mask expression"
msgstr ""
-#: config/tc-sparc.c:1475
+#: config/tc-sparc.c:1583
msgid ": invalid membar mask number"
msgstr ""
-#: config/tc-sparc.c:1490
+#: config/tc-sparc.c:1598
msgid ": invalid siam mode expression"
msgstr ""
-#: config/tc-sparc.c:1495
+#: config/tc-sparc.c:1603
msgid ": invalid siam mode number"
msgstr ""
-#: config/tc-sparc.c:1511
+#: config/tc-sparc.c:1619
msgid ": invalid prefetch function name"
msgstr ""
-#: config/tc-sparc.c:1519
+#: config/tc-sparc.c:1627
msgid ": invalid prefetch function expression"
msgstr ""
-#: config/tc-sparc.c:1524
+#: config/tc-sparc.c:1632
msgid ": invalid prefetch function number"
msgstr ""
-#: config/tc-sparc.c:1552 config/tc-sparc.c:1564
+#: config/tc-sparc.c:1660 config/tc-sparc.c:1672
msgid ": unrecognizable privileged register"
msgstr ""
-#: config/tc-sparc.c:1588 config/tc-sparc.c:1600
+#: config/tc-sparc.c:1696 config/tc-sparc.c:1708
msgid ": unrecognizable hyperprivileged register"
msgstr ""
-#: config/tc-sparc.c:1624 config/tc-sparc.c:1649
+#: config/tc-sparc.c:1732 config/tc-sparc.c:1757
msgid ": unrecognizable v9a or v9b ancillary state register"
msgstr ""
-#: config/tc-sparc.c:1629
+#: config/tc-sparc.c:1737
msgid ": rd on write only ancillary state register"
msgstr ""
#. %sys_tick and %sys_tick_cmpr are v9bnotv9a
-#: config/tc-sparc.c:1637
+#: config/tc-sparc.c:1745
msgid ": unrecognizable v9a ancillary state register"
msgstr ""
-#: config/tc-sparc.c:1673
+#: config/tc-sparc.c:1781
msgid ": asr number must be between 16 and 31"
msgstr ""
-#: config/tc-sparc.c:1681
+#: config/tc-sparc.c:1789
msgid ": asr number must be between 0 and 31"
msgstr ""
-#: config/tc-sparc.c:1691
+#: config/tc-sparc.c:1799
#, c-format
msgid ": expecting %asrN"
msgstr ""
-#: config/tc-sparc.c:1878 config/tc-sparc.c:1916 config/tc-sparc.c:2329
-#: config/tc-sparc.c:2365
+#: config/tc-sparc.c:1986 config/tc-sparc.c:2024 config/tc-sparc.c:2454
+#: config/tc-sparc.c:2490
#, c-format
msgid "Illegal operands: %%%s requires arguments in ()"
msgstr ""
-#: config/tc-sparc.c:1884
+#: config/tc-sparc.c:1992
#, c-format
msgid ""
"Illegal operands: %%%s cannot be used together with other relocs in the insn "
"()"
msgstr ""
-#: config/tc-sparc.c:1895
+#: config/tc-sparc.c:2003
#, c-format
msgid "Illegal operands: %%%s can be only used with call __tls_get_addr"
msgstr ""
-#: config/tc-sparc.c:2102
+#: config/tc-sparc.c:2210
msgid "detected global register use not covered by .register pseudo-op"
msgstr ""
-#: config/tc-sparc.c:2173
+#: config/tc-sparc.c:2285
msgid ": There are only 64 f registers; [0-63]"
msgstr ""
-#: config/tc-sparc.c:2175 config/tc-sparc.c:2193
+#: config/tc-sparc.c:2287 config/tc-sparc.c:2305
msgid ": There are only 32 f registers; [0-31]"
msgstr ""
-#: config/tc-sparc.c:2185
+#: config/tc-sparc.c:2297
msgid ": There are only 32 single precision f registers; [0-31]"
msgstr ""
-#: config/tc-sparc.c:2377
+#: config/tc-sparc.c:2502
#, c-format
msgid ""
"Illegal operands: Can't do arithmetics other than + and - involving %%%s()"
msgstr ""
-#: config/tc-sparc.c:2487
+#: config/tc-sparc.c:2614
#, c-format
msgid "Illegal operands: Can't add non-constant expression to %%%s()"
msgstr ""
-#: config/tc-sparc.c:2497
+#: config/tc-sparc.c:2624
#, c-format
msgid ""
"Illegal operands: Can't do arithmetics involving %%%s() of a relocatable "
"symbol"
msgstr ""
-#: config/tc-sparc.c:2515
+#: config/tc-sparc.c:2642
msgid ": PC-relative operand can't be a constant"
msgstr ""
-#: config/tc-sparc.c:2522
+#: config/tc-sparc.c:2649
msgid ": TLS operand can't be a constant"
msgstr ""
-#: config/tc-sparc.c:2555
+#: config/tc-sparc.c:2682
msgid ": invalid ASI name"
msgstr ""
-#: config/tc-sparc.c:2563
+#: config/tc-sparc.c:2690
msgid ": invalid ASI expression"
msgstr ""
-#: config/tc-sparc.c:2568
+#: config/tc-sparc.c:2695
msgid ": invalid ASI number"
msgstr ""
-#: config/tc-sparc.c:2665
+#: config/tc-sparc.c:2792
msgid "OPF immediate operand out of range (0-0x1ff)"
msgstr ""
-#: config/tc-sparc.c:2670
+#: config/tc-sparc.c:2797
msgid "non-immediate OPF operand, ignored"
msgstr ""
-#: config/tc-sparc.c:2689
+#: config/tc-sparc.c:2816
msgid ": invalid cpreg name"
msgstr ""
-#: config/tc-sparc.c:2718
+#: config/tc-sparc.c:2845
#, c-format
msgid "Illegal operands%s"
msgstr ""
-#: config/tc-sparc.c:2752
+#: config/tc-sparc.c:2884
#, c-format
msgid "architecture bumped from \"%s\" to \"%s\" on \"%s\""
msgstr ""
-#: config/tc-sparc.c:2788
+#: config/tc-sparc.c:2920
#, c-format
msgid "Architecture mismatch on \"%s\"."
msgstr ""
-#: config/tc-sparc.c:2789
+#: config/tc-sparc.c:2921
#, c-format
msgid " (Requires %s; requested architecture is %s.)"
msgstr ""
-#: config/tc-sparc.c:3324
+#: config/tc-sparc.c:2933
+#, c-format
+msgid "Hardware capability \"%s\" not enabled for \"%s\"."
+msgstr ""
+
+#: config/tc-sparc.c:3467
#, c-format
msgid "bad or unhandled relocation type: 0x%02x"
msgstr ""
-#: config/tc-sparc.c:3657
+#: config/tc-sparc.c:3800
msgid "Expected comma after name"
msgstr ""
-#: config/tc-sparc.c:3666
+#: config/tc-sparc.c:3809
#, c-format
msgid "BSS length (%d.) <0! Ignored."
msgstr ""
-#: config/tc-sparc.c:3678
+#: config/tc-sparc.c:3821
msgid "bad .reserve segment -- expected BSS segment"
msgstr ""
-#: config/tc-sparc.c:3706
+#: config/tc-sparc.c:3849
#, c-format
msgid "alignment too large; assuming %d"
msgstr ""
-#: config/tc-sparc.c:3712 config/tc-sparc.c:3862
+#: config/tc-sparc.c:3855 config/tc-sparc.c:4005
msgid "negative alignment"
msgstr ""
-#: config/tc-sparc.c:3722 config/tc-sparc.c:3884 read.c:1321 read.c:2371
+#: config/tc-sparc.c:3865 config/tc-sparc.c:4027 read.c:1321 read.c:2371
msgid "alignment not a power of 2"
msgstr ""
-#: config/tc-sparc.c:3775
+#: config/tc-sparc.c:3918
#, c-format
msgid "Ignoring attempt to re-define symbol %s"
msgstr ""
-#: config/tc-sparc.c:3799 config/tc-v850.c:275
+#: config/tc-sparc.c:3942 config/tc-v850.c:275
msgid "Expected comma after symbol-name"
msgstr ""
-#: config/tc-sparc.c:3809
+#: config/tc-sparc.c:3952
#, c-format
msgid ".COMMon length (%lu) out of range ignored"
msgstr ""
-#: config/tc-sparc.c:3842
+#: config/tc-sparc.c:3985
msgid "Expected comma after common length"
msgstr ""
-#: config/tc-sparc.c:3856
+#: config/tc-sparc.c:3999
#, c-format
msgid "alignment too large; assuming %ld"
msgstr ""
-#: config/tc-sparc.c:3999
+#: config/tc-sparc.c:4142
msgid "Unknown segment type"
msgstr ""
-#: config/tc-sparc.c:4074 config/tc-sparc.c:4084
+#: config/tc-sparc.c:4217 config/tc-sparc.c:4227
#, c-format
msgid "register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"
msgstr ""
-#: config/tc-sparc.c:4102
+#: config/tc-sparc.c:4245
msgid "redefinition of global register"
msgstr ""
-#: config/tc-sparc.c:4113
+#: config/tc-sparc.c:4256
#, c-format
msgid "Register symbol %s already defined."
msgstr ""
-#: config/tc-sparc.c:4317
+#: config/tc-sparc.c:4460
#, c-format
msgid "Illegal operands: %%r_plt in %d-byte data field"
msgstr ""
-#: config/tc-sparc.c:4327
+#: config/tc-sparc.c:4470
#, c-format
msgid "Illegal operands: %%r_tls_dtpoff in %d-byte data field"
msgstr ""
-#: config/tc-sparc.c:4364 config/tc-vax.c:3312
+#: config/tc-sparc.c:4507 config/tc-vax.c:3312
#, c-format
msgid "Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"
msgstr ""
-#: config/tc-sparc.c:4372 config/tc-sparc.c:4403 config/tc-sparc.c:4412
+#: config/tc-sparc.c:4515 config/tc-sparc.c:4546 config/tc-sparc.c:4555
#: config/tc-vax.c:3320 config/tc-vax.c:3351 config/tc-vax.c:3360
#, c-format
msgid "Illegal operands: %%r_%s%d requires arguments in ()"
msgstr ""
-#: config/tc-sparc.c:4421 config/tc-vax.c:3369
+#: config/tc-sparc.c:4564 config/tc-vax.c:3369
#, c-format
msgid "Illegal operands: garbage after %%r_%s%d()"
msgstr ""
msgid "unwound frame has negative size"
msgstr ""
+#: config/tc-tilegx.c:126
+#, c-format
+msgid ""
+" -Q ignored\n"
+" -V print assembler version number\n"
+" --32/--64 generate 32bit/64bit code\n"
+msgstr ""
+
+#: config/tc-tilegx.c:685 config/tc-tilepro.c:554
+msgid "Invalid operator for operand."
+msgstr ""
+
+#: config/tc-tilegx.c:696 config/tc-tilepro.c:565
+msgid "Operator may only be applied to symbols."
+msgstr ""
+
+#: config/tc-tilegx.c:766 config/tc-tilepro.c:635
+#, c-format
+msgid "Writes to register '%s' are not allowed."
+msgstr ""
+
+#: config/tc-tilegx.c:793 config/tc-tilepro.c:662
+#, c-format
+msgid ""
+"Two instructions in the same bundle both write to register %s, which is not "
+"allowed."
+msgstr ""
+
+#: config/tc-tilegx.c:858 config/tc-tilepro.c:726
+#, c-format
+msgid "'%s' may not be bundled with other instructions."
+msgstr ""
+
+#: config/tc-tilegx.c:888 config/tc-tilepro.c:756
+msgid "Invalid combination of instructions for bundle."
+msgstr ""
+
+#: config/tc-tilegx.c:923 config/tc-tilepro.c:791
+msgid "instruction address is not a multiple of 8"
+msgstr ""
+
+#: config/tc-tilegx.c:1000 config/tc-tilepro.c:869
+msgid "Invalid expression."
+msgstr ""
+
+#: config/tc-tilegx.c:1043 config/tc-tilepro.c:911
+#, c-format
+msgid "Expected register, got '%s'."
+msgstr ""
+
+#: config/tc-tilegx.c:1052 config/tc-tilepro.c:918
+#, c-format
+msgid "Found use of non-canonical register name %s; use %s instead."
+msgstr ""
+
+#: config/tc-tilegx.c:1114 config/tc-tilepro.c:977
+#, c-format
+msgid "Too few operands to '%s'."
+msgstr ""
+
+#: config/tc-tilegx.c:1119 config/tc-tilepro.c:982
+#, c-format
+msgid "Unexpected character '%c' after operand %d to %s."
+msgstr ""
+
+#: config/tc-tilegx.c:1140 config/tc-tilepro.c:1003
+msgid "Expected immediate expression"
+msgstr ""
+
+#: config/tc-tilegx.c:1153 config/tc-tilegx.c:1762 config/tc-tilepro.c:1016
+#: config/tc-tilepro.c:1561
+msgid "Found '}' when not bundling."
+msgstr ""
+
+#: config/tc-tilegx.c:1194 config/tc-tilepro.c:1056
+#, c-format
+msgid "Unknown opcode `%.*s'."
+msgstr ""
+
+#: config/tc-tilegx.c:1205 config/tc-tilepro.c:1067
+msgid "Too many instructions for bundle."
+msgstr ""
+
+#: config/tc-tilegx.c:1291 config/tc-tilepro.c:1152
+msgid "Bad call to md_atof ()"
+msgstr ""
+
+#: config/tc-tilegx.c:1367 config/tc-tilepro.c:1215
+msgid "This operator only produces two byte values."
+msgstr ""
+
+#: config/tc-tilegx.c:1393 config/tc-tilepro.c:1241
+#, c-format
+msgid "unsupported BFD relocation size %d"
+msgstr ""
+
+#: config/tc-tilegx.c:1707 config/tc-tilepro.c:1506
+#, c-format
+msgid "internal error? cannot generate `%s' relocation (%d, %d)"
+msgstr ""
+
+#: config/tc-tilegx.c:1750 config/tc-tilepro.c:1549
+msgid "Found '{' when already bundling."
+msgstr ""
+
+#: config/tc-tilepro.c:99
+#, c-format
+msgid ""
+" -Q ignored\n"
+" -V print assembler version number\n"
+msgstr ""
+
#: config/tc-v850.c:286
#, c-format
msgid ".COMMon length (%d.) < 0! Ignored."
msgid "parentheses ignored"
msgstr ""
-#: config/tc-z80.c:1913 read.c:3603
+#: config/tc-z80.c:1913 read.c:3602
#, c-format
msgid "junk at end of line, first unrecognized character is `%c'"
msgstr ""
msgid "CFI is not supported for this target"
msgstr ""
-#: dwarf2dbg.c:552 dwarf2dbg.c:587
+#: dwarf2dbg.c:585 dwarf2dbg.c:620
msgid "file number less than one"
msgstr ""
-#: dwarf2dbg.c:562
+#: dwarf2dbg.c:595
#, c-format
msgid "file number %ld already allocated"
msgstr ""
-#: dwarf2dbg.c:592 dwarf2dbg.c:1345
+#: dwarf2dbg.c:625 dwarf2dbg.c:1378
#, c-format
msgid "unassigned file number %ld"
msgstr ""
-#: dwarf2dbg.c:661
+#: dwarf2dbg.c:694
msgid "is_stmt value not 0 or 1"
msgstr ""
-#: dwarf2dbg.c:673
+#: dwarf2dbg.c:706
msgid "isa number less than zero"
msgstr ""
-#: dwarf2dbg.c:685
+#: dwarf2dbg.c:718
msgid "discriminator less than zero"
msgstr ""
-#: dwarf2dbg.c:691
+#: dwarf2dbg.c:724
#, c-format
msgid "unknown .loc sub-directive `%s'"
msgstr ""
-#: dwarf2dbg.c:1408
+#: dwarf2dbg.c:1441
msgid "internal error: unknown dwarf2 format"
msgstr ""
msgid "GP prologue size exceeds field size, using 0 instead"
msgstr ""
-#: expr.c:87 read.c:3668
+#: expr.c:87 read.c:3667
msgid "bignum invalid"
msgstr ""
-#: expr.c:89 read.c:3670 read.c:4147 read.c:5031
+#: expr.c:89 read.c:3669 read.c:4146 read.c:5030
msgid "floating point number invalid"
msgstr ""
msgid "missing '%c'"
msgstr ""
-#: expr.c:977 read.c:4513
+#: expr.c:977 read.c:4512
msgid "EBCDIC constants are not supported"
msgstr ""
msgid "right operand is a float; integer 0 assumed"
msgstr ""
-#: expr.c:1879 symbols.c:1379
+#: expr.c:1879 symbols.c:1381
msgid "division by zero"
msgstr ""
msgid "attempt to allocate data in common section"
msgstr ""
-#: frags.c:112 write.c:1379
+#: frags.c:102 write.c:1422
#, c-format
msgid "can't extend frag %u chars"
msgstr ""
msgid "can't read from %s: %s"
msgstr ""
-#: input-file.c:267 listing.c:1397 output-file.c:69
+#: input-file.c:267 listing.c:1397 output-file.c:72
#, c-format
msgid "can't close %s: %s"
msgstr ""
msgid "%s without %s"
msgstr ""
-#: read.c:3247
+#: read.c:3246
msgid "unsupported variable size or fill value"
msgstr ""
-#: read.c:3275
+#: read.c:3274
msgid ".space repeat count is zero, ignored"
msgstr ""
-#: read.c:3277
+#: read.c:3276
msgid ".space repeat count is negative, ignored"
msgstr ""
-#: read.c:3306
+#: read.c:3305
msgid "space allocation too complex in absolute section"
msgstr ""
-#: read.c:3312
+#: read.c:3311
msgid "space allocation too complex in common section"
msgstr ""
-#: read.c:3403 read.c:4759
+#: read.c:3402 read.c:4758
#, c-format
msgid "bad floating literal: %s"
msgstr ""
-#: read.c:3560
+#: read.c:3559
#, c-format
msgid "%s: would close weakref loop: %s"
msgstr ""
-#: read.c:3606
+#: read.c:3605
#, c-format
msgid "junk at end of line, first unrecognized character valued 0x%x"
msgstr ""
-#: read.c:3734
+#: read.c:3733
#, c-format
msgid "`%s' can't be equated to common symbol '%s'"
msgstr ""
-#: read.c:3871
+#: read.c:3858
+msgid "unexpected `\"' in expression"
+msgstr ""
+
+#: read.c:3870
msgid "rva without symbol"
msgstr ""
-#: read.c:3928
+#: read.c:3927
msgid "missing or bad offset expression"
msgstr ""
-#: read.c:3949
+#: read.c:3948
msgid "missing reloc type"
msgstr ""
-#: read.c:3961
+#: read.c:3960
msgid "unrecognized reloc type"
msgstr ""
-#: read.c:3977
+#: read.c:3976
msgid "bad reloc expression"
msgstr ""
-#: read.c:4103
+#: read.c:4102
msgid "attempt to store value in absolute section"
msgstr ""
-#: read.c:4141 read.c:5025
+#: read.c:4140 read.c:5024
msgid "zero assumed for missing expression"
msgstr ""
-#: read.c:4153 read.c:5037 write.c:266 write.c:987
+#: read.c:4152 read.c:5036 write.c:266 write.c:1000
msgid "register value used as expression"
msgstr ""
-#: read.c:4233
+#: read.c:4232
#, c-format
msgid "value 0x%llx truncated to 0x%llx"
msgstr ""
-#: read.c:4236
+#: read.c:4235
msgid "value 0x%I64x truncated to 0x%I64x"
msgstr ""
-#: read.c:4240
+#: read.c:4239
#, c-format
msgid "value 0x%lx truncated to 0x%lx"
msgstr ""
-#: read.c:4267
+#: read.c:4266
#, c-format
msgid "bignum truncated to %d bytes"
msgstr ""
-#: read.c:4586 read.c:4781
+#: read.c:4585 read.c:4780
msgid "unresolvable or nonpositive repeat count; using 1"
msgstr ""
-#: read.c:4635
+#: read.c:4634
#, c-format
msgid "unknown floating type type '%c'"
msgstr ""
-#: read.c:4657
+#: read.c:4656
msgid "floating point constant too large"
msgstr ""
-#: read.c:5193
+#: read.c:5192
msgid "strings must be placed into a section"
msgstr ""
-#: read.c:5241
+#: read.c:5240
msgid "expected <nn>"
msgstr ""
#. To be compatible with BSD 4.2 as: give the luser a linefeed!!
-#: read.c:5274 read.c:5360
+#: read.c:5273 read.c:5359
msgid "unterminated string; newline inserted"
msgstr ""
-#: read.c:5368
+#: read.c:5367
msgid "bad escaped character in string"
msgstr ""
-#: read.c:5393
+#: read.c:5392
msgid "expected address expression"
msgstr ""
-#: read.c:5412
+#: read.c:5411
#, c-format
msgid "symbol \"%s\" undefined; zero assumed"
msgstr ""
-#: read.c:5415
+#: read.c:5414
msgid "some symbol undefined; zero assumed"
msgstr ""
-#: read.c:5450
+#: read.c:5449
msgid "this string may not contain '\\0'"
msgstr ""
-#: read.c:5486
+#: read.c:5485
msgid "missing string"
msgstr ""
-#: read.c:5577
+#: read.c:5576
#, c-format
msgid ".incbin count zero, ignoring `%s'"
msgstr ""
-#: read.c:5603
+#: read.c:5602
#, c-format
msgid "file not found: %s"
msgstr ""
-#: read.c:5617
+#: read.c:5616
#, c-format
msgid "seek to end of .incbin file failed `%s'"
msgstr ""
-#: read.c:5628
+#: read.c:5627
#, c-format
msgid "skip (%ld) or count (%ld) invalid for file size (%ld)"
msgstr ""
-#: read.c:5635
+#: read.c:5634
#, c-format
msgid "could not skip to %ld in file `%s'"
msgstr ""
-#: read.c:5644
+#: read.c:5643
#, c-format
msgid "truncated file `%s', %ld of %ld bytes read"
msgstr ""
-#: read.c:5803
+#: read.c:5802
msgid "missing .func"
msgstr ""
-#: read.c:5820
+#: read.c:5819
msgid ".endfunc missing for previous .func"
msgstr ""
-#: read.c:5957
+#: read.c:5956
#, c-format
msgid "missing closing `%c'"
msgstr ""
-#: read.c:5959
+#: read.c:5958
msgid "stray `\\'"
msgstr ""
msgid "comma missing in .xstabs"
msgstr ""
-#: symbols.c:285
+#: symbols.c:287
#, c-format
msgid "cannot define symbol `%s' in absolute section"
msgstr ""
-#: symbols.c:415
+#: symbols.c:417
#, c-format
msgid "symbol `%s' is already defined as \"%s\"/%s%ld"
msgstr ""
-#: symbols.c:490 symbols.c:497
+#: symbols.c:492 symbols.c:499
#, c-format
msgid "inserting \"%s\" into symbol table failed: %s"
msgstr ""
-#: symbols.c:1008
+#: symbols.c:1010
#, c-format
msgid "invalid operands (%s and %s sections) for `%s'"
msgstr ""
-#: symbols.c:1012
+#: symbols.c:1014
#, c-format
msgid "invalid operand (%s section) for `%s'"
msgstr ""
-#: symbols.c:1020
+#: symbols.c:1022
#, c-format
msgid "invalid operands (%s and %s sections) for `%s' when setting `%s'"
msgstr ""
-#: symbols.c:1023
+#: symbols.c:1025
#, c-format
msgid "invalid operand (%s section) for `%s' when setting `%s'"
msgstr ""
-#: symbols.c:1072
+#: symbols.c:1074
#, c-format
msgid "symbol definition loop encountered at `%s'"
msgstr ""
-#: symbols.c:1099
+#: symbols.c:1101
#, c-format
msgid "cannot convert expression symbol %s to complex relocation"
msgstr ""
-#: symbols.c:1381
+#: symbols.c:1383
#, c-format
msgid "division by zero when setting `%s'"
msgstr ""
-#: symbols.c:1462 write.c:2048
+#: symbols.c:1464 write.c:2091
#, c-format
msgid "can't resolve value for symbol `%s'"
msgstr ""
-#: symbols.c:1909
+#: symbols.c:1911
#, c-format
msgid "\"%d\" (instance number %d of a %s label)"
msgstr ""
-#: symbols.c:1938
+#: symbols.c:1940
#, c-format
msgid "attempt to get value of unresolved symbol `%s'"
msgstr ""
-#: symbols.c:2213
+#: symbols.c:2226
msgid "section symbols are already global"
msgstr ""
-#: symbols.c:2326
+#: symbols.c:2339
#, c-format
msgid "Accessing function `%s' as thread-local object"
msgstr ""
-#: symbols.c:2330
+#: symbols.c:2343
#, c-format
msgid "Accessing `%s' as thread-local object"
msgstr ""
msgid "invalid reloc expression"
msgstr ""
-#: write.c:1072
+#: write.c:1085
#, c-format
msgid "value of %s too large for field of %d bytes at %s"
msgstr ""
-#: write.c:1084
+#: write.c:1097
#, c-format
msgid "signed .word overflow; switch may be too large; %ld at 0x%lx"
msgstr ""
-#: write.c:1128
+#: write.c:1141
msgid "redefined symbol cannot be used on reloc"
msgstr ""
-#: write.c:1141
+#: write.c:1154
msgid "relocation out of range"
msgstr ""
-#: write.c:1144
+#: write.c:1157
#, c-format
msgid "%s:%u: bad return from bfd_install_relocation: %x"
msgstr ""
-#: write.c:1208
-msgid "internal error: fixup not contained within frag"
+#: write.c:1180
+msgid "reloc not within (fixed part of) section"
msgstr ""
-#: write.c:1261
-msgid "reloc not within (fixed part of) section"
+#: write.c:1250
+msgid "internal error: fixup not contained within frag"
msgstr ""
-#: write.c:1325 write.c:1455
+#: write.c:1368 write.c:1498
msgid "can't extend frag"
msgstr ""
-#: write.c:1517 write.c:1538
+#: write.c:1560 write.c:1581
#, c-format
msgid "can't write %s: %s"
msgstr ""
-#: write.c:1568
+#: write.c:1611
#, c-format
msgid "cannot write to output file '%s': %s"
msgstr ""
-#: write.c:1724
+#: write.c:1767
#, c-format
msgid "%d error%s, %d warning%s, generating bad object file"
msgstr ""
-#: write.c:1731
+#: write.c:1774
#, c-format
msgid "%d error%s, %d warning%s, no object file generated"
msgstr ""
-#: write.c:1963
+#: write.c:2006
#, c-format
msgid "%s: global symbols not supported in common sections"
msgstr ""
-#: write.c:1977
+#: write.c:2020
#, c-format
msgid "local label `%s' is not defined"
msgstr ""
-#: write.c:1999
+#: write.c:2042
#, c-format
msgid "Local symbol `%s' can't be equated to common symbol `%s'"
msgstr ""
-#: write.c:2006
+#: write.c:2049
#, c-format
msgid "can't make global register symbol `%s'"
msgstr ""
-#: write.c:2299
+#: write.c:2342
#, c-format
msgid "alignment padding (%lu bytes) not a multiple of %ld"
msgstr ""
-#: write.c:2461
+#: write.c:2504
#, c-format
msgid ".word %s-%s+%s didn't fit"
msgstr ""
-#: write.c:2555
+#: write.c:2598
msgid "padding added"
msgstr ""
-#: write.c:2605
+#: write.c:2648
msgid "attempt to move .org backwards"
msgstr ""
-#: write.c:2629
+#: write.c:2672
msgid ".space specifies non-absolute value"
msgstr ""
-#: write.c:2644
+#: write.c:2687
msgid ".space or .fill with negative value, ignored"
msgstr ""
-#: write.c:2715
+#: write.c:2758
#, c-format
msgid ""
"Infinite loop encountered whilst attempting to compute the addresses of "
+2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
+
+ * gas/epiphany: New directory.
+ * gas/testsuite/gas/epiphany/addr-syntax.d: New file.
+ * gas/testsuite/gas/epiphany/addr-syntax.s: New file.
+ * gas/testsuite/gas/epiphany/allinsn.d: New file.
+ * gas/testsuite/gas/epiphany/allinsn.exp: New file.
+ * gas/testsuite/gas/epiphany/allinsn.s: New file.
+ * gas/testsuite/gas/epiphany/badpostmod.s: New file.
+ * gas/testsuite/gas/epiphany/badrelax.d: New file.
+ * gas/testsuite/gas/epiphany/badrelax.s: New file.
+ * gas/testsuite/gas/epiphany/branch_lit.d: New file.
+ * gas/testsuite/gas/epiphany/branch_lit.s: New file.
+ * gas/testsuite/gas/epiphany/regression.d: New file.
+ * gas/testsuite/gas/epiphany/regression.s: New file.
+ * gas/testsuite/gas/epiphany/sample.d: New file.
+ * gas/testsuite/gas/epiphany/sample.s: New file.
+
2011-10-24 Julian Brown <julian@codesourcery.com>
* gas/m68k/all.exp (movem-offset): Add test.
--- /dev/null
+#as:
+#objdump: -dr
+#name: addr-syntax
+
+.*.o: file format elf32-epiphany
+
+
+Disassembly of section \.text:
+
+00000000 \<\.text\>:
+ 0: 2bcc 01ff ldr.l r1,\[r2,-0x7ff\]
+ 4: 4c4c 0301 ldr.l r2,\[r3\],-0x8
+ 8: 107c 2201 strd.l r8,\[r4\],\+0x8
+ c: 506c 2400 ldrd sl,\[ip\]
+ 10: 587c 2400 strd sl,\[lr\]
--- /dev/null
+; Check that we can do negative displacements
+ ldr r1,[r2,-2047]
+; Check postmodified immediate with positive and negative displacements
+ ldr r2,[r3],-8
+ strd r8,[r4],8
+
+; Check that zero displacements work
+ ldrd r10,[r12]
+ strd r10,[r14]
--- /dev/null
+#as:
+#objdump: -dr
+#name: allinsn
+
+.*\.o: file format elf32-epiphany
+
+Disassembly of section .text:
+
+00000000 \<bgt16\>:
+ 0: 0260 bgt 4 \<bgt16\+0x4\>
+ 2: 0260 bgt 6 \<bgt16\+0x6\>
+ 4: fe60 bgt 0 \<bgt16\>
+ 6: fd60 bgt 0 \<bgt16\>
+ 8: 0068 0000 bgt 8 \<bgt16\+0x8\>
+ 8: R_EPIPHANY_SIMM24 \.data
+ c: 0260 bgt 10 \<bgt16\+0x10\>
+ e: f960 bgt 0 \<bgt16\>
+ 10: f860 bgt 0 \<bgt16\>
+
+00000012 \<bgtu16\>:
+ 12: 0220 bgtu 16 \<bgtu16\+0x4\>
+ 14: fe20 bgtu 10 \<bgt16\+0x10\>
+ 16: f520 bgtu 0 \<bgt16\>
+ 18: 0220 bgtu 1c \<bgtu16\+0xa\>
+ 1a: fe20 bgtu 16 \<bgtu16\+0x4\>
+ 1c: f220 bgtu 0 \<bgt16\>
+ 1e: f120 bgtu 0 \<bgt16\>
+ 20: 0220 bgtu 24 \<bgte16\+0x2\>
+
+00000022 \<bgte16\>:
+ 22: ef70 bgte 0 \<bgt16\>
+ 24: ee70 bgte 0 \<bgt16\>
+ 26: ed70 bgte 0 \<bgt16\>
+ 28: ec70 bgte 0 \<bgt16\>
+ 2a: eb70 bgte 0 \<bgt16\>
+ 2c: fe70 bgte 28 \<bgte16\+0x6\>
+ 2e: 0078 0000 bgte 2e \<bgte16\+0xc\>
+ 2e: R_EPIPHANY_SIMM24 \.data
+ 32: 0078 0000 bgte 32 \<bgte16\+0x10\>
+ 32: R_EPIPHANY_SIMM24 \.data
+
+00000036 \<bgteu16\>:
+ 36: 0230 bgteu 3a \<bgteu16\+0x4\>
+ 38: fe30 bgteu 34 \<bgte16\+0x12\>
+ 3a: 0038 0000 bgteu 3a \<bgteu16\+0x4\>
+ 3a: R_EPIPHANY_SIMM24 \.data
+ 3e: 0230 bgteu 42 \<bgteu16\+0xc\>
+ 40: e030 bgteu 0 \<bgt16\>
+ 42: 0230 bgteu 46 \<bgteu16\+0x10\>
+ 44: 0038 0000 bgteu 44 \<bgteu16\+0xe\>
+ 44: R_EPIPHANY_SIMM24 \.data
+ 48: 0038 0000 bgteu 48 \<bgteu16\+0x12\>
+ 48: R_EPIPHANY_SIMM24 \.data
+
+0000004c \<bgteu\>:
+ 4c: fe80 blt 48 \<bgteu16\+0x12\>
+ 4e: 0280 blt 52 \<bgteu\+0x6\>
+ 50: fe80 blt 4c \<bgteu\>
+ 52: 0280 blt 56 \<bgteu\+0xa\>
+ 54: fe80 blt 50 \<bgteu\+0x4\>
+ 56: 0280 blt 5a \<bgteu\+0xe\>
+ 58: 0088 0000 blt 58 \<bgteu\+0xc\>
+ 58: R_EPIPHANY_SIMM24 \.data
+ 5c: 0088 0000 blt 5c \<bgteu\+0x10\>
+ 5c: R_EPIPHANY_SIMM24 \.data
+
+00000060 \<blt\>:
+ 60: fe50 bltu 5c \<bgteu\+0x10\>
+ 62: 0250 bltu 66 \<blt\+0x6\>
+ 64: fe50 bltu 60 \<blt\>
+ 66: cd50 bltu 0 \<bgt16\>
+ 68: cc50 bltu 0 \<bgt16\>
+ 6a: cb50 bltu 0 \<bgt16\>
+ 6c: 0250 bltu 70 \<blt\+0x10\>
+ 6e: 0058 0000 bltu 6e \<blt\+0xe\>
+ 6e: R_EPIPHANY_SIMM24 \.data
+
+00000072 \<blte16\>:
+ 72: c790 blte 0 \<bgt16\>
+ 74: 0098 0000 blte 74 \<blte16\+0x2\>
+ 74: R_EPIPHANY_SIMM24 \.data
+ 78: 0098 0000 blte 78 \<blte16\+0x6\>
+ 78: R_EPIPHANY_SIMM24 \.data
+ 7c: c290 blte 0 \<bgt16\>
+ 7e: fe90 blte 7a \<blte16\+0x8\>
+ 80: c090 blte 0 \<bgt16\>
+ 82: bf90 blte 0 \<bgt16\>
+ 84: 0290 blte 88 \<blte\+0x2\>
+
+00000086 \<blte\>:
+ 86: bd40 blteu 0 \<bgt16\>
+ 88: 0048 0000 blteu 88 \<blte\+0x2\>
+ 88: R_EPIPHANY_SIMM24 \.data
+ 8c: ba40 blteu 0 \<bgt16\>
+ 8e: 0048 0000 blteu 8e \<blte\+0x8\>
+ 8e: R_EPIPHANY_SIMM24 \.data
+ 92: b740 blteu 0 \<bgt16\>
+ 94: fe40 blteu 90 \<blte\+0xa\>
+ 96: 0048 0000 blteu 96 \<blte\+0x10\>
+ 96: R_EPIPHANY_SIMM24 \.data
+ 9a: 0048 0000 blteu 9a \<blte\+0x14\>
+ 9a: R_EPIPHANY_SIMM24 \.data
+
+0000009e \<bbeq16\>:
+ 9e: b1a0 bbeq 0 \<bgt16\>
+ a0: b0a0 bbeq 0 \<bgt16\>
+ a2: 00a8 0000 bbeq a2 \<bbeq16\+0x4\>
+ a2: R_EPIPHANY_SIMM24 \.data
+ a6: ada0 bbeq 0 \<bgt16\>
+ a8: 02a0 bbeq ac \<bbeq16\+0xe\>
+ aa: 00a8 0000 bbeq aa \<bbeq16\+0xc\>
+ aa: R_EPIPHANY_SIMM24 \.data
+ ae: 00a8 0000 bbeq ae \<bbeq16\+0x10\>
+ ae: R_EPIPHANY_SIMM24 \.data
+ b2: 02a0 bbeq b6 \<bbeq\+0x2\>
+
+000000b4 \<bbeq\>:
+ b4: 00b8 0000 bbne b4 \<bbeq\>
+ b4: R_EPIPHANY_SIMM24 \.data
+ b8: feb0 bbne b4 \<bbeq\>
+ ba: 02b0 bbne be \<bbeq\+0xa\>
+ bc: a2b0 bbne 0 \<bgt16\>
+ be: 02b0 bbne c2 \<bbeq\+0xe\>
+ c0: 02b0 bbne c4 \<bbeq\+0x10\>
+ c2: 9fb0 bbne 0 \<bgt16\>
+ c4: 9eb0 bbne 0 \<bgt16\>
+
+000000c6 \<bblt16\>:
+ c6: 00c8 0000 bblt c6 \<bblt16\>
+ c6: R_EPIPHANY_SIMM24 \.data
+ ca: 02c0 bblt ce \<bblt16\+0x8\>
+ cc: 02c0 bblt d0 \<bblt16\+0xa\>
+ ce: 02c0 bblt d2 \<bblt16\+0xc\>
+ d0: fec0 bblt cc \<bblt16\+0x6\>
+ d2: 02c0 bblt d6 \<bblt16\+0x10\>
+ d4: 96c0 bblt 0 \<bgt16\>
+ d6: fec0 bblt d2 \<bblt16\+0xc\>
+
+000000d8 \<bblt\>:
+ d8: 02d0 bblte dc \<bblt\+0x4\>
+ da: 02d0 bblte de \<bblt\+0x6\>
+ dc: 92d0 bblte 0 \<bgt16\>
+ de: 91d0 bblte 0 \<bgt16\>
+ e0: 02d0 bblte e4 \<bblt\+0xc\>
+ e2: fed0 bblte de \<bblt\+0x6\>
+ e4: 00d8 0000 bblte e4 \<bblt\+0xc\>
+ e4: R_EPIPHANY_SIMM24 \.data
+ e8: 02d0 bblte ec \<b16\+0x2\>
+
+000000ea \<b16\>:
+ ea: 8be0 b 0 \<bgt16\>
+ ec: 8ae0 b 0 \<bgt16\>
+ ee: 02e0 b f2 \<b16\+0x8\>
+ f0: fee0 b ec \<b16\+0x2\>
+ f2: 87e0 b 0 \<bgt16\>
+ f4: 00e8 0000 b f4 \<b16\+0xa\>
+ f4: R_EPIPHANY_SIMM24 \.data
+ f8: 00e8 0000 b f8 \<b16\+0xe\>
+ f8: R_EPIPHANY_SIMM24 \.data
+ fc: fee0 b f8 \<b16\+0xe\>
+
+000000fe \<b\>:
+ fe: fef0 bl fa \<b16\+0x10\>
+ 100: 02f0 bl 104 \<b\+0x6\>
+ 102: 7ff8 ffff bl 0 \<bgt16\>
+ 106: fef0 bl 102 \<b\+0x4\>
+ 108: 7cf8 ffff bl 0 \<bgt16\>
+ 10c: fef0 bl 108 \<b\+0xa\>
+ 10e: fef0 bl 10a \<b\+0xc\>
+ 110: 78f8 ffff bl 0 \<bgt16\>
+
+00000114 \<bl\>:
+ 114: 114f 0402 jr ip
+ 118: 0d42 jr r3
+ 11a: 0142 jr r0
+ 11c: 0d4f 0402 jr fp
+ 120: 154f 0402 jr sp
+ 124: 0142 jr r0
+ 126: 0d42 jr r3
+ 128: 0142 jr r0
+
+0000012a \<jr\>:
+ 12a: 114f 0402 jr ip
+ 12e: 0d4f 1c02 jr r59
+ 132: 114f 0c02 jr r28
+ 136: 0d4f 0c02 jr r27
+ 13a: 154f 0402 jr sp
+ 13e: 0d4f 1802 jr r51
+ 142: 014f 1c02 jr r56
+ 146: 154f 1402 jr r45
+
+0000014a \<jalr16\>:
+ 14a: 115f 0402 jalr ip
+ 14e: 0d52 jalr r3
+ 150: 0152 jalr r0
+ 152: 0d5f 0402 jalr fp
+ 156: 155f 0402 jalr sp
+ 15a: 0d52 jalr r3
+ 15c: 0d5f 0402 jalr fp
+ 160: 115f 0402 jalr ip
+
+00000164 \<jalr\>:
+ 164: 115f 0402 jalr ip
+ 168: 0d5f 1c02 jalr r59
+ 16c: 115f 0c02 jalr r28
+ 170: 0d5f 0c02 jalr r27
+ 174: 155f 0402 jalr sp
+ 178: 0d5f 0402 jalr fp
+ 17c: 115f 0c02 jalr r28
+ 180: 0d5f 1c02 jalr r59
+
+00000184 \<ldrbx16\>:
+ 184: 9209 2480 ldrb.l ip,\[ip,\+ip]
+ 188: 6d81 ldrb r3,\[r3,r3]
+ 18a: 0001 ldrb r0,\[r0,r0]
+ 18c: 6d89 2480 ldrb.l fp,\[fp,\+fp]
+ 190: b689 2480 ldrb.l sp,\[sp,\+sp]
+ 194: 8009 2000 ldrb.l ip,\[r0,\+r0]
+ 198: 6b09 0080 ldrb.l r3,\[r2,\+lr]
+ 19c: 5189 0400 ldrb.l r2,\[ip,\+r3]
+
+000001a0 \<ldrbp16\>:
+ 1a0: a18d 2080 ldrb.l sp,\[r0],\+fp
+ 1a4: c60d 2080 ldrb.l lr,\[r1],\+ip
+ 1a8: 618d 2080 ldrb.l fp,\[r0],\+fp
+
+000001ac \<ldrbx\>:
+ 1ac: 9209 2480 ldrb.l ip,\[ip,\+ip]
+ 1b0: 6d89 ff80 ldrb.l r59,\[r59,\+r59]
+ 1b4: 9209 6d80 ldrb.l r28,\[r28,\+r28]
+ 1b8: 6d89 6d80 ldrb.l r27,\[r27,\+r27]
+ 1bc: b689 2480 ldrb.l sp,\[sp,\+sp]
+ 1c0: 2b89 aa80 ldrb.l r41,\[r18,\+r47]
+ 1c4: 6289 a900 ldrb.l r43,\[r16,\+r21]
+ 1c8: 0009 8480 ldrb.l r32,\[r8,\+r8]
+
+000001cc \<ldrbp\>:
+ 1cc: 850d 9900 ldrb.l r36,\[r49],\+r18
+ 1d0: 0d0d 9f00 ldrb.l r32,\[r59],\+r50
+ 1d4: 4c8d e580 ldrb.l r58,\[fp],\+r25
+
+000001d8 \<ldrbd16\>:
+ 1d8: 900c 2400 ldrb ip,\[ip]
+ 1dc: 6f84 ldrb r3,\[r3,0x7]
+ 1de: 0204 ldrb r0,\[r0,0x4]
+ 1e0: 6d8c 2400 ldrb.l fp,\[fp,\+0x3]
+ 1e4: b48c 2400 ldrb.l sp,\[sp,\+0x1]
+ 1e8: d48c 2400 ldrb.l lr,\[sp,\+0x1]
+ 1ec: 2004 ldrb r1,\[r0]
+ 1ee: 2484 ldrb r1,\[r1,0x1]
+
+000001f0 \<ldrbd\>:
+ 1f0: 900c 2400 ldrb ip,\[ip]
+ 1f4: 6f8c fcff ldrb.l r59,\[r59,\+0x7ff]
+ 1f8: 900c 6c80 ldrb.l r28,\[r28,\+0x400]
+ 1fc: 6f8c 6c7f ldrb.l r27,\[r27,\+0x3ff]
+ 200: b48c 2400 ldrb.l sp,\[sp,\+0x1]
+ 204: e70c 10c4 ldrb.l r7,\[r33,\+0x626]
+ 208: fa8c 60f4 ldrb.l r31,\[r6,\+0x7a5]
+ 20c: 438c 20e4 ldrb.l sl,\[r0,\+0x727]
+
+00000210 \<ldrhx16\>:
+ 210: 9229 2480 ldrh.l ip,\[ip,\+ip]
+ 214: 6da1 ldrh r3,\[r3,r3]
+ 216: 0021 ldrh r0,\[r0,r0]
+ 218: 6da9 2480 ldrh.l fp,\[fp,\+fp]
+ 21c: b6a9 2480 ldrh.l sp,\[sp,\+sp]
+ 220: 0329 0080 ldrh.l r0,\[r0,\+lr]
+ 224: daa9 2480 ldrh.l lr,\[lr,\+sp]
+ 228: 0da9 0480 ldrh.l r0,\[fp,\+fp]
+
+0000022c \<ldrhp16\>:
+ 22c: 55ad 0480 ldrh.l r2,\[sp],\+fp
+ 230: d5ad 4480 ldrh.l r22,\[sp],\+fp
+
+00000234 \<ldrhx\>:
+ 234: 9229 2480 ldrh.l ip,\[ip,\+ip]
+ 238: 6da9 ff80 ldrh.l r59,\[r59,\+r59]
+ 23c: 9229 6d80 ldrh.l r28,\[r28,\+r28]
+ 240: 6da9 6d80 ldrh.l r27,\[r27,\+r27]
+ 244: b6a9 2480 ldrh.l sp,\[sp,\+sp]
+ 248: c6a9 a900 ldrh.l r46,\[r17,\+r21]
+ 24c: c7a9 6280 ldrh.l r30,\[r1,\+r47]
+ 250: 6e29 a900 ldrh.l r43,\[r19,\+r20]
+
+00000254 \<ldrhp\>:
+ 254: 1ead 8d80 ldrh.l r32,\[r31],\+r29
+ 258: 9d2d d480 ldrh.l r52,\[r47],\+sl
+ 25c: e1ad 7400 ldrh.l r31,\[r40],\+r3
+
+00000260 \<ldrhd16\>:
+ 260: 902c 2400 ldrh ip,\[ip]
+ 264: 6fa4 ldrh r3,\[r3,0x7]
+ 266: 0224 ldrh r0,\[r0,0x4]
+ 268: 6dac 2400 ldrh.l fp,\[fp,\+0x3]
+ 26c: b4ac 2400 ldrh.l sp,\[sp,\+0x1]
+ 270: c82c 2000 ldrh lr,\[r2]
+ 274: 63a4 ldrh r3,\[r0,0x7]
+ 276: 0f24 ldrh r0,\[r3,0x6]
+
+00000278 \<ldrhd\>:
+ 278: 902c 2400 ldrh ip,\[ip]
+ 27c: 6fac fcff ldrh.l r59,\[r59,\+0x7ff]
+ 280: 902c 6c80 ldrh.l r28,\[r28,\+0x400]
+ 284: 6fac 6c7f ldrh.l r27,\[r27,\+0x3ff]
+ 288: b4ac 2400 ldrh.l sp,\[sp,\+0x1]
+ 28c: a2ac ac98 ldrh.l r45,\[r24,\+0x4c5]
+ 290: 8d2c 94d9 ldrh.l r36,\[r43,\+0x6ca]
+ 294: 40ac b803 ldrh.l r42,\[r48,\+0x19]
+
+00000298 \<ldrx16\>:
+ 298: 9249 2480 ldr.l ip,\[ip,\+ip]
+ 29c: 6dc1 ldr r3,\[r3,r3]
+ 29e: 0041 ldr r0,\[r0,r0]
+ 2a0: 6dc9 2480 ldr.l fp,\[fp,\+fp]
+ 2a4: b6c9 2480 ldr.l sp,\[sp,\+sp]
+ 2a8: 6f49 0480 ldr.l r3,\[fp,\+lr]
+ 2ac: 9949 2400 ldr.l ip,\[lr,\+r2]
+ 2b0: 6b49 0080 ldr.l r3,\[r2,\+lr]
+
+000002b4 \<ldrp16\>:
+ 2b4: cecd 2480 ldr.l lr,\[fp],\+sp
+ 2b8: 144d 0400 ldr.l r0,\[sp],\+r0
+ 2bc: 68cd 2000 ldr.l fp,\[r2],\+r1
+
+000002c0 \<ldrx\>:
+ 2c0: 9249 2480 ldr.l ip,\[ip,\+ip]
+ 2c4: 6dc9 ff80 ldr.l r59,\[r59,\+r59]
+ 2c8: 9249 6d80 ldr.l r28,\[r28,\+r28]
+ 2cc: 6dc9 6d80 ldr.l r27,\[r27,\+r27]
+ 2d0: b6c9 2480 ldr.l sp,\[sp,\+sp]
+ 2d4: 03c9 6a80 ldr.l r24,\[r16,\+r47]
+ 2d8: c4c9 5700 ldr.l r22,\[r41,\+r49]
+ 2dc: cfc9 2600 ldr.l lr,\[fp,\+r39]
+
+000002e0 \<ldrp\>:
+ 2e0: b74d 4180 ldr.l r21,\[r5],\+r30
+ 2e4: 934d 8480 ldr.l r36,\[ip],\+lr
+ 2e8: 91cd 2080 ldr.l ip,\[r4],\+fp
+
+000002ec \<ldrd16\>:
+ 2ec: 904c 2400 ldr ip,\[ip]
+ 2f0: 6fc4 ldr r3,\[r3,0x7]
+ 2f2: 0244 ldr r0,\[r0,0x4]
+ 2f4: 6dcc 2400 ldr.l fp,\[fp,\+0x3]
+ 2f8: b4cc 2400 ldr.l sp,\[sp,\+0x1]
+ 2fc: 144c 0400 ldr r0,\[sp]
+ 300: 87cc 2000 ldr.l ip,\[r1,\+0x7]
+ 304: 64cc 2000 ldr.l fp,\[r1,\+0x1]
+
+00000308 \<ldrd\>:
+ 308: 904c 2400 ldr ip,\[ip]
+ 30c: 6fcc fcff ldr.l r59,\[r59,\+0x7ff]
+ 310: 904c 6c80 ldr.l r28,\[r28,\+0x400]
+ 314: 6fcc 6c7f ldr.l r27,\[r27,\+0x3ff]
+ 318: b4cc 2400 ldr.l sp,\[sp,\+0x1]
+ 31c: dbcc 4c79 ldr.l r22,\[r30,\+0x3cf]
+ 320: f0cc 14aa ldr.l r7,\[r44,\+0x551]
+ 324: efcc 48e7 ldr.l r23,\[r19,\+0x73f]
+
+00000328 \<ldrdx16\>:
+ 328: 9269 2480 ldrd.l ip,\[ip,\+ip]
+ 32c: 8de1 ldrd r4,\[r3,r3]
+ 32e: 0061 ldrd r0,\[r0,r0]
+ 330: cde9 2480 ldrd.l lr,\[fp,\+fp]
+ 334: 16e9 4480 ldrd.l r16,\[sp,\+sp]
+ 338: ca69 6080 ldrd.l r30,\[r2,\+ip]
+ 33c: 0de9 0400 ldrd.l r0,\[fp,\+r3]
+ 340: 9369 4480 ldrd.l r20,\[ip,\+lr]
+
+00000344 \<ldrdp16\>:
+ 344: 8de5 ldrd r4,\[r3],r3
+ 346: 0ded 4480 ldrd.l r16,\[fp],\+fp
+ 34a: 96ed 4480 ldrd.l r20,\[sp],\+sp
+ 34e: 50ed 2400 ldrd.l sl,\[ip],\+r1
+ 352: cf6d 6480 ldrd.l r30,\[fp],\+lr
+ 356: daed e480 ldrd.l r62,\[lr],\+sp
+
+0000035a \<ldrdx\>:
+ 35a: 9269 2480 ldrd.l ip,\[ip,\+ip]
+ 35e: 4de9 ff80 ldrd.l r58,\[r59,\+r59]
+ 362: 9269 6d80 ldrd.l r28,\[r28,\+r28]
+ 366: 4de9 6d80 ldrd.l r26,\[r27,\+r27]
+ 36a: 96e9 2480 ldrd.l ip,\[sp,\+sp]
+ 36e: 0de9 8780 ldrd.l r32,\[fp,\+r59]
+ 372: 8769 0800 ldrd.l r4,\[r17,\+r6]
+ 376: 00e9 9400 ldrd.l r32,\[r40,\+r1]
+
+0000037a \<ldrdp\>:
+ 37a: 16ed 4480 ldrd.l r16,\[sp],\+sp
+ 37e: c76d b180 ldrd.l r46,\[r33],\+r30
+ 382: 11ed 7380 ldrd.l r24,\[r36],\+r59
+ 386: 41ed f080 ldrd.l r58,\[r32],\+fp
+
+0000038a \<ldrdd16\>:
+ 38a: 906c 2400 ldrd ip,\[ip]
+ 38e: 8fe4 ldrd r4,\[r3,0x7]
+ 390: 0264 ldrd r0,\[r0,0x4]
+ 392: 0dec 4400 ldrd.l r16,\[fp,\+0x3]
+ 396: 54ec 4400 ldrd.l r18,\[sp,\+0x1]
+ 39a: 0dec 0400 ldrd.l r0,\[fp,\+0x3]
+ 39e: cfec 2400 ldrd.l lr,\[fp,\+0x7]
+ 3a2: d0ec 2400 ldrd.l lr,\[ip,\+0x1]
+
+000003a6 \<ldrdd\>:
+ 3a6: 906c 2400 ldrd ip,\[ip]
+ 3aa: 4fec fcff ldrd.l r58,\[r59,\+0x7ff]
+ 3ae: 906c 6c80 ldrd.l r28,\[r28,\+0x400]
+ 3b2: 4fec 0c7f ldrd.l r2,\[r27,\+0x3ff]
+ 3b6: 14ec 4400 ldrd.l r16,\[sp,\+0x1]
+ 3ba: 94ec 085f ldrd.l r4,\[r21,\+0x2f9]
+ 3be: c4ec 34c2 ldrd.l lr,\[r41,\+0x611]
+ 3c2: d96c 04f0 ldrd.l r6,\[lr,\+0x782]
+
+000003c6 \<strbx16\>:
+ 3c6: 9219 2480 strb.l ip,\[ip,\+ip]
+ 3ca: 6d91 strb r3,\[r3,r3]
+ 3cc: 0011 strb r0,\[r0,r0]
+ 3ce: 6d99 2480 strb.l fp,\[fp,\+fp]
+ 3d2: b699 2480 strb.l sp,\[sp,\+sp]
+ 3d6: 3999 0400 strb.l r1,\[lr,\+r3]
+ 3da: 8f19 2080 strb.l ip,\[r3,\+lr]
+ 3de: d219 2480 strb.l lr,\[ip,\+ip]
+
+000003e2 \<strbx\>:
+ 3e2: 9219 2480 strb.l ip,\[ip,\+ip]
+ 3e6: 6d99 ff80 strb.l r59,\[r59,\+r59]
+ 3ea: 9219 6d80 strb.l r28,\[r28,\+r28]
+ 3ee: 6d99 6d80 strb.l r27,\[r27,\+r27]
+ 3f2: b699 2480 strb.l sp,\[sp,\+sp]
+ 3f6: 5e99 c480 strb.l r50,\[r15,\+sp]
+ 3fa: ce19 2700 strb.l lr,\[fp,\+r52]
+ 3fe: c199 2f00 strb.l lr,\[r24,\+r51]
+
+00000402 \<strbp16\>:
+ 402: 921d 2480 strb.l ip,\[ip],\+ip
+ 406: 6d95 strb r3,\[r3],r3
+ 408: 0015 strb r0,\[r0],r0
+ 40a: 6d9d 2480 strb.l fp,\[fp],\+fp
+ 40e: b69d 2480 strb.l sp,\[sp],\+sp
+ 412: 4e1d 0480 strb.l r2,\[fp],\+ip
+ 416: 609d 2000 strb.l fp,\[r0],\+r1
+ 41a: 4995 strb r2,\[r2],r3
+
+0000041c \<strbp\>:
+ 41c: 921d 2480 strb.l ip,\[ip],\+ip
+ 420: 6d9d ff80 strb.l r59,\[r59],\+r59
+ 424: 921d 6d80 strb.l r28,\[r28],\+r28
+ 428: 6d9d 6d80 strb.l r27,\[r27],\+r27
+ 42c: b69d 2480 strb.l sp,\[sp],\+sp
+ 430: cd1d 3800 strb.l lr,\[r51],\+r2
+ 434: d11d 1700 strb.l r6,\[r44],\+r50
+ 438: 849d a700 strb.l r44,\[sb],\+r49
+
+0000043c \<strbd16\>:
+ 43c: 901c 2400 strb ip,\[ip]
+ 440: 6f94 strb r3,\[r3,0x7]
+ 442: 0214 strb r0,\[r0,0x4]
+ 444: 6d9c 2400 strb.l fp,\[fp,\+0x3]
+ 448: b49c 2400 strb.l sp,\[sp,\+0x1]
+ 44c: 0894 strb r0,\[r2,0x1]
+ 44e: a99c 2000 strb.l sp,\[r2,\+0x3]
+ 452: 6a1c 2000 strb.l fp,\[r2,\+0x4]
+
+00000456 \<strbd\>:
+ 456: 901c 2400 strb ip,\[ip]
+ 45a: 6f9c fcff strb.l r59,\[r59,\+0x7ff]
+ 45e: 901c 6c80 strb.l r28,\[r28,\+0x400]
+ 462: 6f9c 6c7f strb.l r27,\[r27,\+0x3ff]
+ 466: b49c 2400 strb.l sp,\[sp,\+0x1]
+ 46a: ea1c 44af strb.l r23,\[sl,\+0x57c]
+ 46e: 8e9c 30b6 strb.l ip,\[r35,\+0x5b5]
+ 472: c91c dc88 strb.l r54,\[r58,\+0x442]
+
+00000476 \<strhx16\>:
+ 476: 9239 2480 strh.l ip,\[ip,\+ip]
+ 47a: 6db1 strh r3,\[r3,r3]
+ 47c: 0031 strh r0,\[r0,r0]
+ 47e: 6db9 2480 strh.l fp,\[fp,\+fp]
+ 482: b6b9 2480 strh.l sp,\[sp,\+sp]
+ 486: 0cb1 strh r0,\[r3,r1]
+ 488: 2d39 0400 strh.l r1,\[fp,\+r2]
+ 48c: 6db9 0080 strh.l r3,\[r3,\+fp]
+
+00000490 \<strhx\>:
+ 490: 9239 2480 strh.l ip,\[ip,\+ip]
+ 494: 6db9 ff80 strh.l r59,\[r59,\+r59]
+ 498: 9239 6d80 strh.l r28,\[r28,\+r28]
+ 49c: 6db9 6d80 strh.l r27,\[r27,\+r27]
+ 4a0: b6b9 2480 strh.l sp,\[sp,\+sp]
+ 4a4: 1bb9 5180 strh.l r16,\[r38,\+r31]
+ 4a8: 1239 8580 strh.l r32,\[ip,\+r28]
+ 4ac: 2cb9 e480 strh.l r57,\[fp,\+sb]
+
+000004b0 \<strhp16\>:
+ 4b0: 923d 2480 strh.l ip,\[ip],\+ip
+ 4b4: 6db5 strh r3,\[r3],r3
+ 4b6: 0035 strh r0,\[r0],r0
+ 4b8: 6dbd 2480 strh.l fp,\[fp],\+fp
+ 4bc: b6bd 2480 strh.l sp,\[sp],\+sp
+ 4c0: 0abd 0080 strh.l r0,\[r2],\+sp
+ 4c4: ac3d 2000 strh.l sp,\[r3],\+r0
+ 4c8: 2035 strh r1,\[r0],r0
+
+000004ca \<strhp\>:
+ 4ca: 923d 2480 strh.l ip,\[ip],\+ip
+ 4ce: 6dbd ff80 strh.l r59,\[r59],\+r59
+ 4d2: 923d 6d80 strh.l r28,\[r28],\+r28
+ 4d6: 6dbd 6d80 strh.l r27,\[r27],\+r27
+ 4da: b6bd 2480 strh.l sp,\[sp],\+sp
+ 4de: 773d 1300 strh.l r3,\[r37],\+r54
+ 4e2: 98bd 1980 strh.l r4,\[r54],\+r25
+ 4e6: a0bd 1180 strh.l r5,\[r32],\+r25
+
+000004ea \<strhd16\>:
+ 4ea: 903c 2400 strh ip,\[ip]
+ 4ee: 6fb4 strh r3,\[r3,0x7]
+ 4f0: 0234 strh r0,\[r0,0x4]
+ 4f2: 6dbc 2400 strh.l fp,\[fp,\+0x3]
+ 4f6: b4bc 2400 strh.l sp,\[sp,\+0x1]
+ 4fa: 61b4 strh r3,\[r0,0x3]
+ 4fc: d3bc 2400 strh.l lr,\[ip,\+0x7]
+ 500: 6bb4 strh r3,\[r2,0x7]
+
+00000502 \<strhd\>:
+ 502: 903c 2400 strh ip,\[ip]
+ 506: 6fbc fcff strh.l r59,\[r59,\+0x7ff]
+ 50a: 903c 6c80 strh.l r28,\[r28,\+0x400]
+ 50e: 6fbc 6c7f strh.l r27,\[r27,\+0x3ff]
+ 512: b4bc 2400 strh.l sp,\[sp,\+0x1]
+ 516: fabc 1093 strh.l r7,\[r38,\+0x49d]
+ 51a: 32bc 6009 strh.l r25,\[r4,\+0x4d]
+ 51e: 6fbc 244e strh.l fp,\[fp,\+0x277]
+
+00000522 \<strx16\>:
+ 522: 9259 2480 str.l ip,\[ip,\+ip]
+ 526: 6dd1 str r3,\[r3,r3]
+ 528: 0051 str r0,\[r0,r0]
+ 52a: 6dd9 2480 str.l fp,\[fp,\+fp]
+ 52e: b6d9 2480 str.l sp,\[sp,\+sp]
+ 532: cdd9 2000 str.l lr,\[r3,\+r3]
+ 536: 6c59 0400 str.l r3,\[fp,\+r0]
+ 53a: 94d9 2400 str.l ip,\[sp,\+r1]
+
+0000053e \<strx\>:
+ 53e: 9259 2480 str.l ip,\[ip,\+ip]
+ 542: 6dd9 ff80 str.l r59,\[r59,\+r59]
+ 546: 9259 6d80 str.l r28,\[r28,\+r28]
+ 54a: 6dd9 6d80 str.l r27,\[r27,\+r27]
+ 54e: b6d9 2480 str.l sp,\[sp,\+sp]
+ 552: b659 cd80 str.l r53,\[r29,\+r28]
+ 556: d959 6a00 str.l r30,\[r22,\+r34]
+ 55a: 9259 6e80 str.l r28,\[r28,\+r44]
+
+0000055e \<strp16\>:
+ 55e: 925d 2480 str.l ip,\[ip],\+ip
+ 562: 6dd5 str r3,\[r3],r3
+ 564: 0055 str r0,\[r0],r0
+ 566: 6ddd 2480 str.l fp,\[fp],\+fp
+ 56a: b6dd 2480 str.l sp,\[sp],\+sp
+ 56e: c05d 2000 str.l lr,\[r0],\+r0
+ 572: 62dd 2080 str.l fp,\[r0],\+sp
+ 576: 6c5d 0400 str.l r3,\[fp],\+r0
+
+0000057a \<strp\>:
+ 57a: 925d 2480 str.l ip,\[ip],\+ip
+ 57e: 6ddd ff80 str.l r59,\[r59],\+r59
+ 582: 925d 6d80 str.l r28,\[r28],\+r28
+ 586: 6ddd 6d80 str.l r27,\[r27],\+r27
+ 58a: b6dd 2480 str.l sp,\[sp],\+sp
+ 58e: d3dd 5080 str.l r22,\[r36],\+r15
+ 592: 97dd a680 str.l r44,\[sp],\+r47
+ 596: 62dd 5880 str.l r19,\[r48],\+sp
+
+0000059a \<strd16\>:
+ 59a: 905c 2400 str ip,\[ip]
+ 59e: 6fd4 str r3,\[r3,0x7]
+ 5a0: 0254 str r0,\[r0,0x4]
+ 5a2: 6ddc 2400 str.l fp,\[fp,\+0x3]
+ 5a6: b4dc 2400 str.l sp,\[sp,\+0x1]
+ 5aa: 6ddc 0400 str.l r3,\[fp,\+0x3]
+ 5ae: b35c 2400 str.l sp,\[ip,\+0x6]
+ 5b2: 39dc 0400 str.l r1,\[lr,\+0x3]
+
+000005b6 \<strd\>:
+ 5b6: 905c 2400 str ip,\[ip]
+ 5ba: 6fdc fcff str.l r59,\[r59,\+0x7ff]
+ 5be: 905c 6c80 str.l r28,\[r28,\+0x400]
+ 5c2: 6fdc 6c7f str.l r27,\[r27,\+0x3ff]
+ 5c6: b4dc 2400 str.l sp,\[sp,\+0x1]
+ 5ca: b15c b409 str.l r45,\[r44,\+0x4a]
+ 5ce: 495c f82e str.l r58,\[r50,\+0x172]
+ 5d2: 0d5c a04e str.l r40,\[r3,\+0x272]
+
+000005d6 \<strdx16\>:
+ 5d6: 9279 2480 strd.l ip,\[ip,\+ip]
+ 5da: 4df1 strd r2,\[r3,r3]
+ 5dc: 0071 strd r0,\[r0,r0]
+ 5de: 0df9 4480 strd.l r16,\[fp,\+fp]
+ 5e2: 56f9 4480 strd.l r18,\[sp,\+sp]
+ 5e6: 8cf9 2000 strd.l ip,\[r3,\+r1]
+ 5ea: 59f9 0480 strd.l r2,\[lr,\+fp]
+ 5ee: 8979 2000 strd.l ip,\[r2,\+r2]
+
+000005f2 \<strdx\>:
+ 5f2: 9279 2480 strd.l ip,\[ip,\+ip]
+ 5f6: 4df9 ff80 strd.l r58,\[r59,\+r59]
+ 5fa: 9279 6d80 strd.l r28,\[r28,\+r28]
+ 5fe: 4df9 6d80 strd.l r26,\[r27,\+r27]
+ 602: d6f9 2480 strd.l lr,\[sp,\+sp]
+ 606: d779 9880 strd.l r38,\[r53,\+lr]
+ 60a: 0df9 6a80 strd.l r24,\[r19,\+r43]
+ 60e: 8b79 2580 strd.l ip,\[sl,\+r30]
+
+00000612 \<strdp16\>:
+ 612: 927d 2480 strd.l ip,\[ip],\+ip
+ 616: 4df5 strd r2,\[r3],r3
+ 618: 0075 strd r0,\[r0],r0
+ 61a: cdfd 0480 strd.l r6,\[fp],\+fp
+ 61e: 96fd 0480 strd.l r4,\[sp],\+sp
+ 622: 4c75 strd r2,\[r3],r0
+ 624: 40f5 strd r2,\[r0],r1
+ 626: 58fd 0400 strd.l r2,\[lr],\+r1
+
+0000062a \<strdp\>:
+ 62a: 927d 2480 strd.l ip,\[ip],\+ip
+ 62e: 4dfd ff80 strd.l r58,\[r59],\+r59
+ 632: 927d 6d80 strd.l r28,\[r28],\+r28
+ 636: 4dfd 6d80 strd.l r26,\[r27],\+r27
+ 63a: d6fd 4480 strd.l r22,\[sp],\+sp
+ 63e: ca7d 0680 strd.l r6,\[sl],\+r44
+ 642: 4efd 3400 strd.l sl,\[r43],\+r5
+ 646: c77d a880 strd.l r46,\[r17],\+lr
+
+0000064a \<strdd16\>:
+ 64a: 107c 0400 strd r0,\[ip]
+ 64e: 4ff4 strd r2,\[r3,0x7]
+ 650: 0274 strd r0,\[r0,0x4]
+ 652: 4dfc 0400 strd.l r2,\[fp,\+0x3]
+ 656: 94fc 0400 strd.l r4,\[sp,\+0x1]
+ 65a: 4af4 strd r2,\[r2,0x5]
+ 65c: cff4 strd r6,\[r3,0x7]
+ 65e: c574 strd r6,\[r1,0x2]
+
+00000660 \<strdd\>:
+ 660: 907c 2400 strd ip,\[ip]
+ 664: 4ffc fcff strd.l r58,\[r59,\+0x7ff]
+ 668: 907c 6c80 strd.l r28,\[r28,\+0x400]
+ 66c: 4ffc 6c7f strd.l r26,\[r27,\+0x3ff]
+ 670: d4fc 2400 strd.l lr,\[sp,\+0x1]
+ 674: 93fc 7859 strd.l r28,\[r52,\+0x2cf]
+ 678: 157c b8f9 strd.l r40,\[r53,\+0x7ca]
+ 67c: 877c bc3d strd.l r44,\[r57,\+0x1ee]
+
+00000680 \<mov16EQ\>:
+ 680: 900f 2402 moveq.l ip,ip
+ 684: 6c02 moveq r3,r3
+ 686: 0002 moveq r0,r0
+ 688: 6c0f 2402 moveq.l fp,fp
+ 68c: b40f 2402 moveq.l sp,sp
+ 690: 880f 2002 moveq.l ip,r2
+ 694: 4c0f 0402 moveq.l r2,fp
+ 698: 740f 2402 moveq.l fp,sp
+
+0000069c \<movEQ\>:
+ 69c: 900f 2402 moveq.l ip,ip
+ 6a0: 6c0f fc02 moveq.l r59,r59
+ 6a4: 900f 6c02 moveq.l r28,r28
+ 6a8: 6c0f 6c02 moveq.l r27,r27
+ 6ac: b40f 2402 moveq.l sp,sp
+ 6b0: 180f 8c02 moveq.l r32,r30
+ 6b4: 7c0f b002 moveq.l r43,r39
+ 6b8: 240f 7002 moveq.l r25,r33
+
+000006bc \<mov16NE\>:
+ 6bc: 901f 2402 movne.l ip,ip
+ 6c0: 6c12 movne r3,r3
+ 6c2: 0012 movne r0,r0
+ 6c4: 6c1f 2402 movne.l fp,fp
+ 6c8: b41f 2402 movne.l sp,sp
+ 6cc: 6c12 movne r3,r3
+ 6ce: 0c1f 0402 movne.l r0,fp
+ 6d2: 6c1f 2402 movne.l fp,fp
+
+000006d6 \<movNE\>:
+ 6d6: 901f 2402 movne.l ip,ip
+ 6da: 6c1f fc02 movne.l r59,r59
+ 6de: 901f 6c02 movne.l r28,r28
+ 6e2: 6c1f 6c02 movne.l r27,r27
+ 6e6: b41f 2402 movne.l sp,sp
+ 6ea: 8c12 movne r4,r3
+ 6ec: 8c1f 6402 movne.l r28,fp
+ 6f0: fc1f 5002 movne.l r23,r39
+
+000006f4 \<mov16GT\>:
+ 6f4: 906f 2402 movgt.l ip,ip
+ 6f8: 6c62 movgt r3,r3
+ 6fa: 0062 movgt r0,r0
+ 6fc: 6c6f 2402 movgt.l fp,fp
+ 700: b46f 2402 movgt.l sp,sp
+ 704: 2c62 movgt r1,r3
+ 706: cc6f 2002 movgt.l lr,r3
+ 70a: 306f 0402 movgt.l r1,ip
+
+0000070e \<movGT\>:
+ 70e: 906f 2402 movgt.l ip,ip
+ 712: 6c6f fc02 movgt.l r59,r59
+ 716: 906f 6c02 movgt.l r28,r28
+ 71a: 6c6f 6c02 movgt.l r27,r27
+ 71e: b46f 2402 movgt.l sp,sp
+ 722: 346f 0802 movgt.l r1,r21
+ 726: ac6f 2002 movgt.l sp,r3
+ 72a: 8c6f 7402 movgt.l r28,r43
+
+0000072e \<mov16GTU\>:
+ 72e: 902f 2402 movgtu.l ip,ip
+ 732: 6c22 movgtu r3,r3
+ 734: 0022 movgtu r0,r0
+ 736: 6c2f 2402 movgtu.l fp,fp
+ 73a: b42f 2402 movgtu.l sp,sp
+ 73e: 982f 2402 movgtu.l ip,lr
+ 742: b02f 2402 movgtu.l sp,ip
+ 746: 942f 2402 movgtu.l ip,sp
+
+0000074a \<movGTU\>:
+ 74a: 902f 2402 movgtu.l ip,ip
+ 74e: 6c2f fc02 movgtu.l r59,r59
+ 752: 902f 6c02 movgtu.l r28,r28
+ 756: 6c2f 6c02 movgtu.l r27,r27
+ 75a: b42f 2402 movgtu.l sp,sp
+ 75e: 442f 9002 movgtu.l r34,r33
+ 762: 202f 5802 movgtu.l r17,r48
+ 766: 602f 8c02 movgtu.l r35,r24
+
+0000076a \<mov16GTE\>:
+ 76a: 907f 2402 movgte.l ip,ip
+ 76e: 6c72 movgte r3,r3
+ 770: 0072 movgte r0,r0
+ 772: 6c7f 2402 movgte.l fp,fp
+ 776: b47f 2402 movgte.l sp,sp
+ 77a: 0072 movgte r0,r0
+ 77c: 547f 0402 movgte.l r2,sp
+ 780: c87f 2002 movgte.l lr,r2
+
+00000784 \<movGTE\>:
+ 784: 907f 2402 movgte.l ip,ip
+ 788: 6c7f fc02 movgte.l r59,r59
+ 78c: 907f 6c02 movgte.l r28,r28
+ 790: 6c7f 6c02 movgte.l r27,r27
+ 794: b47f 2402 movgte.l sp,sp
+ 798: 8c7f 3c02 movgte.l ip,r59
+ 79c: a87f 9402 movgte.l r37,r42
+ 7a0: 887f ac02 movgte.l r44,r26
+
+000007a4 \<mov16GTEU\>:
+ 7a4: 903f 2402 movgteu.l ip,ip
+ 7a8: 6c32 movgteu r3,r3
+ 7aa: 0032 movgteu r0,r0
+ 7ac: 6c3f 2402 movgteu.l fp,fp
+ 7b0: b43f 2402 movgteu.l sp,sp
+ 7b4: d03f 2402 movgteu.l lr,ip
+ 7b8: a43f 2002 movgteu.l sp,r1
+ 7bc: 983f 2402 movgteu.l ip,lr
+
+000007c0 \<movGTEU\>:
+ 7c0: 903f 2402 movgteu.l ip,ip
+ 7c4: 6c3f fc02 movgteu.l r59,r59
+ 7c8: 903f 6c02 movgteu.l r28,r28
+ 7cc: 6c3f 6c02 movgteu.l r27,r27
+ 7d0: b43f 2402 movgteu.l sp,sp
+ 7d4: 5c3f f402 movgteu.l r58,r47
+ 7d8: 143f e002 movgteu.l r56,r5
+ 7dc: 903f 5802 movgteu.l r20,r52
+
+000007e0 \<mov16LT\>:
+ 7e0: 908f 2402 movlt.l ip,ip
+ 7e4: 6c82 movlt r3,r3
+ 7e6: 0082 movlt r0,r0
+ 7e8: 6c8f 2402 movlt.l fp,fp
+ 7ec: b48f 2402 movlt.l sp,sp
+ 7f0: 6c82 movlt r3,r3
+ 7f2: 4882 movlt r2,r2
+ 7f4: 988f 2402 movlt.l ip,lr
+
+000007f8 \<movLT\>:
+ 7f8: 908f 2402 movlt.l ip,ip
+ 7fc: 6c8f fc02 movlt.l r59,r59
+ 800: 908f 6c02 movlt.l r28,r28
+ 804: 6c8f 6c02 movlt.l r27,r27
+ 808: b48f 2402 movlt.l sp,sp
+ 80c: 908f c402 movlt.l r52,ip
+ 810: 388f e802 movlt.l r57,r22
+ 814: 1c8f 2002 movlt.l r8,r7
+
+00000818 \<mov16LTU\>:
+ 818: 905f 2402 movltu.l ip,ip
+ 81c: 6c52 movltu r3,r3
+ 81e: 0052 movltu r0,r0
+ 820: 6c5f 2402 movltu.l fp,fp
+ 824: b45f 2402 movltu.l sp,sp
+ 828: 885f 2002 movltu.l ip,r2
+ 82c: b05f 2402 movltu.l sp,ip
+ 830: 2052 movltu r1,r0
+
+00000832 \<movLTU\>:
+ 832: 905f 2402 movltu.l ip,ip
+ 836: 6c5f fc02 movltu.l r59,r59
+ 83a: 905f 6c02 movltu.l r28,r28
+ 83e: 6c5f 6c02 movltu.l r27,r27
+ 842: b45f 2402 movltu.l sp,sp
+ 846: bc5f 2c02 movltu.l sp,r31
+ 84a: 705f a402 movltu.l r43,ip
+ 84e: e05f 1c02 movltu.l r7,r56
+
+00000852 \<mov16LTE\>:
+ 852: 909f 2402 movlte.l ip,ip
+ 856: 6c92 movlte r3,r3
+ 858: 0092 movlte r0,r0
+ 85a: 6c9f 2402 movlte.l fp,fp
+ 85e: b49f 2402 movlte.l sp,sp
+ 862: 0c92 movlte r0,r3
+ 864: 709f 0402 movlte.l r3,ip
+ 868: 789f 0402 movlte.l r3,lr
+
+0000086c \<movLTE\>:
+ 86c: 909f 2402 movlte.l ip,ip
+ 870: 6c9f fc02 movlte.l r59,r59
+ 874: 909f 6c02 movlte.l r28,r28
+ 878: 6c9f 6c02 movlte.l r27,r27
+ 87c: b49f 2402 movlte.l sp,sp
+ 880: cc9f 6c02 movlte.l r30,r27
+ 884: 709f 9802 movlte.l r35,r52
+ 888: f49f 3802 movlte.l r15,r53
+
+0000088c \<mov16LTEU\>:
+ 88c: 904f 2402 movlteu.l ip,ip
+ 890: 6c42 movlteu r3,r3
+ 892: 0042 movlteu r0,r0
+ 894: 6c4f 2402 movlteu.l fp,fp
+ 898: b44f 2402 movlteu.l sp,sp
+ 89c: 984f 2402 movlteu.l ip,lr
+ 8a0: 4842 movlteu r2,r2
+ 8a2: 4c4f 0402 movlteu.l r2,fp
+
+000008a6 \<movLTEU\>:
+ 8a6: 904f 2402 movlteu.l ip,ip
+ 8aa: 6c4f fc02 movlteu.l r59,r59
+ 8ae: 904f 6c02 movlteu.l r28,r28
+ 8b2: 6c4f 6c02 movlteu.l r27,r27
+ 8b6: b44f 2402 movlteu.l sp,sp
+ 8ba: f04f 7002 movlteu.l r31,r36
+ 8be: 084f 7802 movlteu.l r24,r50
+ 8c2: 984f d802 movlteu.l r52,r54
+
+000008c6 \<mov16B\>:
+ 8c6: 90ef 2402 mov.l ip,ip
+ 8ca: 6ce2 mov r3,r3
+ 8cc: 00e2 mov r0,r0
+ 8ce: 6cef 2402 mov.l fp,fp
+ 8d2: b4ef 2402 mov.l sp,sp
+ 8d6: 84ef 2002 mov.l ip,r1
+ 8da: 80ef 2002 mov.l ip,r0
+ 8de: 10ef 0402 mov.l r0,ip
+
+000008e2 \<movB\>:
+ 8e2: 90ef 2402 mov.l ip,ip
+ 8e6: 6cef fc02 mov.l r59,r59
+ 8ea: 90ef 6c02 mov.l r28,r28
+ 8ee: 6cef 6c02 mov.l r27,r27
+ 8f2: b4ef 2402 mov.l sp,sp
+ 8f6: 2cef 1c02 mov.l r1,r59
+ 8fa: 90ef 6402 mov.l r28,ip
+ 8fe: a8ef 1402 mov.l r5,r42
+
+00000902 \<mov16BEQ\>:
+ 902: 90af 2402 movbeq.l ip,ip
+ 906: 6ca2 movbeq r3,r3
+ 908: 00a2 movbeq r0,r0
+ 90a: 6caf 2402 movbeq.l fp,fp
+ 90e: b4af 2402 movbeq.l sp,sp
+ 912: c8af 2002 movbeq.l lr,r2
+ 916: 68af 2002 movbeq.l fp,r2
+ 91a: 84af 2002 movbeq.l ip,r1
+
+0000091e \<movBEQ\>:
+ 91e: 90af 2402 movbeq.l ip,ip
+ 922: 6caf fc02 movbeq.l r59,r59
+ 926: 90af 6c02 movbeq.l r28,r28
+ 92a: 6caf 6c02 movbeq.l r27,r27
+ 92e: b4af 2402 movbeq.l sp,sp
+ 932: a0af 6802 movbeq.l r29,r16
+ 936: 58af 5402 movbeq.l r18,r46
+ 93a: c4af 2002 movbeq.l lr,r1
+
+0000093e \<mov16BNE\>:
+ 93e: 90bf 2402 movbne.l ip,ip
+ 942: 6cb2 movbne r3,r3
+ 944: 00b2 movbne r0,r0
+ 946: 6cbf 2402 movbne.l fp,fp
+ 94a: b4bf 2402 movbne.l sp,sp
+ 94e: 28b2 movbne r1,r2
+ 950: 84bf 2002 movbne.l ip,r1
+ 954: 8cbf 2002 movbne.l ip,r3
+
+00000958 \<movBNE\>:
+ 958: 90bf 2402 movbne.l ip,ip
+ 95c: 6cbf fc02 movbne.l r59,r59
+ 960: 90bf 6c02 movbne.l r28,r28
+ 964: 6cbf 6c02 movbne.l r27,r27
+ 968: b4bf 2402 movbne.l sp,sp
+ 96c: fcbf 2002 movbne.l r15,r7
+ 970: 0cbf 7402 movbne.l r24,r43
+ 974: f0bf 5802 movbne.l r23,r52
+
+00000978 \<mov16BLT\>:
+ 978: 90cf 2402 movblt.l ip,ip
+ 97c: 6cc2 movblt r3,r3
+ 97e: 00c2 movblt r0,r0
+ 980: 6ccf 2402 movblt.l fp,fp
+ 984: b4cf 2402 movblt.l sp,sp
+ 988: b8cf 2402 movblt.l sp,lr
+ 98c: 98cf 2402 movblt.l ip,lr
+ 990: d4cf 2402 movblt.l lr,sp
+
+00000994 \<movBLT\>:
+ 994: 90cf 2402 movblt.l ip,ip
+ 998: 6ccf fc02 movblt.l r59,r59
+ 99c: 90cf 6c02 movblt.l r28,r28
+ 9a0: 6ccf 6c02 movblt.l r27,r27
+ 9a4: b4cf 2402 movblt.l sp,sp
+ 9a8: 90cf d402 movblt.l r52,r44
+ 9ac: 2ccf f002 movblt.l r57,r35
+ 9b0: a4cf d002 movblt.l r53,r33
+
+000009b4 \<mov16BLTE\>:
+ 9b4: 90df 2402 movblte.l ip,ip
+ 9b8: 6cd2 movblte r3,r3
+ 9ba: 00d2 movblte r0,r0
+ 9bc: 6cdf 2402 movblte.l fp,fp
+ 9c0: b4df 2402 movblte.l sp,sp
+ 9c4: b0df 2402 movblte.l sp,ip
+ 9c8: 0cdf 0402 movblte.l r0,fp
+ 9cc: 14df 0402 movblte.l r0,sp
+
+000009d0 \<movBLTE\>:
+ 9d0: 90df 2402 movblte.l ip,ip
+ 9d4: 6cdf fc02 movblte.l r59,r59
+ 9d8: 90df 6c02 movblte.l r28,r28
+ 9dc: 6cdf 6c02 movblte.l r27,r27
+ 9e0: b4df 2402 movblte.l sp,sp
+ 9e4: 50df f402 movblte.l r58,r44
+ 9e8: 78df 8802 movblte.l r35,r22
+ 9ec: 08df 2002 movblte.l r8,r2
+
+000009f0 \<movts16\>:
+ 9f0: 810f 2002 movts.l config,ip
+ 9f4: 750f 0402 movts.l ipend,r3
+ 9f8: 010f 0402 movts.l iret,r0
+ 9fc: 6d0f 2002 movts.l debug,fp
+ a00: a50f 2002 movts.l status,sp
+ a04: 650f 2002 movts.l status,fp
+ a08: 690f 2002 movts.l pc,fp
+ a0c: 050f 0402 movts.l imask,r0
+
+00000a10 \<movts\>:
+ a10: 810f 2002 movts.l config,ip
+ a14: 750f e402 movts.l ipend,r59
+ a18: 810f 6402 movts.l iret,r28
+ a1c: 6d0f 6002 movts.l debug,r27
+ a20: a50f 2002 movts.l status,sp
+ a24: 4d0f c002 movts.l debug,r50
+ a28: 350f 8402 movts.l ipend,r33
+ a2c: 850f 2002 movts.l status,ip
+
+00000a30 \<movfs16\>:
+ a30: 811f 2002 movfs.l ip,config
+ a34: 751f 0402 movfs.l r3,ipend
+ a38: 011f 0402 movfs.l r0,iret
+ a3c: 6d1f 2002 movfs.l fp,debug
+ a40: a51f 2002 movfs.l sp,status
+ a44: 211f 0402 movfs.l r1,iret
+ a48: 4512 movfs r2,status
+ a4a: cd1f 2002 movfs.l lr,debug
+
+00000a4e \<movfs\>:
+ a4e: 811f 2002 movfs.l ip,config
+ a52: 751f e402 movfs.l r59,ipend
+ a56: 811f 6402 movfs.l r28,iret
+ a5a: 6d1f 6002 movfs.l r27,debug
+ a5e: a51f 2002 movfs.l sp,status
+ a62: ad1f 2002 movfs.l sp,debug
+ a66: e51f 2002 movfs.l r15,status
+ a6a: 051f 4402 movfs.l r16,imask
+
+00000a6e \<nop\>:
+ a6e: 01a2 nop
+
+00000a70 \<idle\>:
+ a70: 01b2 idle
+
+00000a72 \<bkpt\>:
+ a72: 01c2 bkpt
+
+00000a74 \<rti\>:
+ a74: 01d2 rti
+
+00000a76 \<trap16\>:
+ a76: 03e2 trap 0x0
+ a78: 1fe2 trap 0x7
+ a7a: 13e2 trap 0x4
+ a7c: 0fe2 trap 0x3
+ a7e: 07e2 trap 0x1
+ a80: 1be2 trap 0x6
+ a82: 0fe2 trap 0x3
+ a84: 17e2 trap 0x5
+
+00000a86 \<add16\>:
+ a86: 921f 248a add.l ip,ip,ip
+ a8a: 6d9a add r3,r3,r3
+ a8c: 001a add r0,r0,r0
+ a8e: 6d9f 248a add.l fp,fp,fp
+ a92: b69f 248a add.l sp,sp,sp
+ a96: ab1f 208a add.l sp,r2,lr
+ a9a: 089a add r0,r2,r1
+ a9c: 8d9f 248a add.l ip,fp,fp
+
+00000aa0 \<add\>:
+ aa0: 921f 248a add.l ip,ip,ip
+ aa4: 6d9f ff8a add.l r59,r59,r59
+ aa8: 921f 6d8a add.l r28,r28,r28
+ aac: 6d9f 6d8a add.l r27,r27,r27
+ ab0: b69f 248a add.l sp,sp,sp
+ ab4: 081f e50a add.l r56,sl,r16
+ ab8: 851f 8e0a add.l r36,r25,r34
+ abc: 449f 190a add.l r2,r49,r17
+
+00000ac0 \<sub16\>:
+ ac0: 923f 248a sub.l ip,ip,ip
+ ac4: 6dba sub r3,r3,r3
+ ac6: 003a sub r0,r0,r0
+ ac8: 6dbf 248a sub.l fp,fp,fp
+ acc: b6bf 248a sub.l sp,sp,sp
+ ad0: 533f 048a sub.l r2,ip,lr
+ ad4: d83f 240a sub.l lr,lr,r0
+ ad8: 6dba sub r3,r3,r3
+
+00000ada \<sub\>:
+ ada: 923f 248a sub.l ip,ip,ip
+ ade: 6dbf ff8a sub.l r59,r59,r59
+ ae2: 923f 6d8a sub.l r28,r28,r28
+ ae6: 6dbf 6d8a sub.l r27,r27,r27
+ aea: b6bf 248a sub.l sp,sp,sp
+ aee: 9a3f 250a sub.l ip,lr,r20
+ af2: 1bbf ca8a sub.l r48,r22,r47
+ af6: 62bf 588a sub.l r19,r48,sp
+
+00000afa \<and16\>:
+ afa: 925f 248a and.l ip,ip,ip
+ afe: 6dda and r3,r3,r3
+ b00: 005a and r0,r0,r0
+ b02: 6ddf 248a and.l fp,fp,fp
+ b06: b6df 248a and.l sp,sp,sp
+ b0a: 75df 240a and.l fp,sp,r3
+ b0e: 6dda and r3,r3,r3
+ b10: 96df 248a and.l ip,sp,sp
+
+00000b14 \<and\>:
+ b14: 925f 248a and.l ip,ip,ip
+ b18: 6ddf ff8a and.l r59,r59,r59
+ b1c: 925f 6d8a and.l r28,r28,r28
+ b20: 6ddf 6d8a and.l r27,r27,r27
+ b24: b6df 248a and.l sp,sp,sp
+ b28: 935f c68a and.l r52,ip,r46
+ b2c: 825f b68a and.l r44,r40,r44
+ b30: 0bdf 7d8a and.l r24,r58,r31
+
+00000b34 \<orr16\>:
+ b34: 927f 248a orr.l ip,ip,ip
+ b38: 6dfa orr r3,r3,r3
+ b3a: 007a orr r0,r0,r0
+ b3c: 6dff 248a orr.l fp,fp,fp
+ b40: b6ff 248a orr.l sp,sp,sp
+ b44: c6ff 208a orr.l lr,r1,sp
+ b48: 7b7f 048a orr.l r3,lr,lr
+ b4c: 4d7a orr r2,r3,r2
+
+00000b4e \<orr\>:
+ b4e: 927f 248a orr.l ip,ip,ip
+ b52: 6dff ff8a orr.l r59,r59,r59
+ b56: 927f 6d8a orr.l r28,r28,r28
+ b5a: 6dff 6d8a orr.l r27,r27,r27
+ b5e: b6ff 248a orr.l sp,sp,sp
+ b62: 95ff c38a orr.l r52,r5,r59
+ b66: e1ff 328a orr.l r15,r32,r43
+ b6a: 167f ee8a orr.l r56,r29,r44
+
+00000b6e \<eor16\>:
+ b6e: 920f 248a eor.l ip,ip,ip
+ b72: 6d8a eor r3,r3,r3
+ b74: 000a eor r0,r0,r0
+ b76: 6d8f 248a eor.l fp,fp,fp
+ b7a: b68f 248a eor.l sp,sp,sp
+ b7e: 8d0f 200a eor.l ip,r3,r2
+ b82: 750f 040a eor.l r3,sp,r2
+ b86: 750f 240a eor.l fp,sp,r2
+
+00000b8a \<eor\>:
+ b8a: 920f 248a eor.l ip,ip,ip
+ b8e: 6d8f ff8a eor.l r59,r59,r59
+ b92: 920f 6d8a eor.l r28,r28,r28
+ b96: 6d8f 6d8a eor.l r27,r27,r27
+ b9a: b68f 248a eor.l sp,sp,sp
+ b9e: 228f 5d8a eor.l r17,r56,r29
+ ba2: a58f 358a eor.l sp,r41,r27
+ ba6: 698f 268a eor.l fp,sl,r43
+
+00000baa \<asr16\>:
+ baa: 926f 248a asr.l ip,ip,ip
+ bae: 6dea asr r3,r3,r3
+ bb0: 006a asr r0,r0,r0
+ bb2: 6def 248a asr.l fp,fp,fp
+ bb6: b6ef 248a asr.l sp,sp,sp
+ bba: 61ea asr r3,r0,r3
+ bbc: 676f 008a asr.l r3,r1,lr
+ bc0: 0eef 048a asr.l r0,fp,sp
+
+00000bc4 \<asr\>:
+ bc4: 926f 248a asr.l ip,ip,ip
+ bc8: 6def ff8a asr.l r59,r59,r59
+ bcc: 926f 6d8a asr.l r28,r28,r28
+ bd0: 6def 6d8a asr.l r27,r27,r27
+ bd4: b6ef 248a asr.l sp,sp,sp
+ bd8: 44ef 858a asr.l r34,sb,r25
+ bdc: 64ef ca0a asr.l r51,r17,r33
+ be0: 9def 208a asr.l ip,r7,fp
+
+00000be4 \<lsr16\>:
+ be4: 924f 248a lsr.l ip,ip,ip
+ be8: 6dca lsr r3,r3,r3
+ bea: 004a lsr r0,r0,r0
+ bec: 6dcf 248a lsr.l fp,fp,fp
+ bf0: b6cf 248a lsr.l sp,sp,sp
+ bf4: adcf 208a lsr.l sp,r3,fp
+ bf8: 674f 208a lsr.l fp,r1,lr
+ bfc: c94f 200a lsr.l lr,r2,r2
+
+00000c00 \<lsr\>:
+ c00: 924f 248a lsr.l ip,ip,ip
+ c04: 6dcf ff8a lsr.l r59,r59,r59
+ c08: 924f 6d8a lsr.l r28,r28,r28
+ c0c: 6dcf 6d8a lsr.l r27,r27,r27
+ c10: b6cf 248a lsr.l sp,sp,sp
+ c14: c5cf 0d0a lsr.l r6,r25,r19
+ c18: 984f 3a0a lsr.l ip,r54,r32
+ c1c: b64f 248a lsr.l sp,sp,ip
+
+00000c20 \<lsl16\>:
+ c20: 922f 248a lsl.l ip,ip,ip
+ c24: 6daa lsl r3,r3,r3
+ c26: 002a lsl r0,r0,r0
+ c28: 6daf 248a lsl.l fp,fp,fp
+ c2c: b6af 248a lsl.l sp,sp,sp
+ c30: 922f 248a lsl.l ip,ip,ip
+ c34: c62f 208a lsl.l lr,r1,ip
+ c38: d5af 240a lsl.l lr,sp,r3
+
+00000c3c \<lsl\>:
+ c3c: 922f 248a lsl.l ip,ip,ip
+ c40: 6daf ff8a lsl.l r59,r59,r59
+ c44: 922f 6d8a lsl.l r28,r28,r28
+ c48: 6daf 6d8a lsl.l r27,r27,r27
+ c4c: b6af 248a lsl.l sp,sp,sp
+ c50: 8faf 948a lsl.l r36,r43,r15
+ c54: 5eaf 920a lsl.l r34,r39,r37
+ c58: e6af 518a lsl.l r23,r33,r29
+
+00000c5c \<addi16\>:
+ c5c: 901b 2400 add ip,ip,0
+ c60: 6f9b 0000 add r3,r3,7
+ c64: 021b 0000 add r0,r0,4
+ c68: 6d9b 2400 add fp,fp,3
+ c6c: b49b 2400 add sp,sp,1
+ c70: 6493 add r3,r1,1
+ c72: 2d9b 0400 add r1,fp,3
+ c76: 0f9b 0400 add r0,fp,7
+
+00000c7a \<addi\>:
+ c7a: 901b 2400 add ip,ip,0
+ c7e: 6f9b fc7f add r59,r59,1023
+ c82: 939b 6c04 add r28,r28,39
+ c86: 6f9b 6c7f add r27,r27,1023
+ c8a: b49b 2400 add sp,sp,1
+ c8e: 329b cc14 add r49,r28,165
+ c92: eb9b 604d add r31,r2,623
+ c96: 049b 4476 add r16,sb,945
+
+00000c9a \<subi16\>:
+ c9a: 903b 2400 sub ip,ip,0
+ c9e: 6fbb 0000 sub r3,r3,7
+ ca2: 023b 0000 sub r0,r0,4
+ ca6: 6dbb 2400 sub fp,fp,3
+ caa: b4bb 2400 sub sp,sp,1
+ cae: 8d3b 2000 sub ip,r3,2
+ cb2: ce3b 2000 sub lr,r3,4
+ cb6: 88bb 2000 sub ip,r2,1
+
+00000cba \<subi\>:
+ cba: 903b 2400 sub ip,ip,0
+ cbe: 6cbb fc00 sub r59,r59,1
+ cc2: 93bb 6c7f sub r28,r28,1023
+ cc6: 6f3b 6c7f sub r27,r27,1022
+ cca: b4bb 2400 sub sp,sp,1
+ cce: 7a3b c068 sub r51,r6,836
+ cd2: e23b b460 sub r47,r40,772
+ cd6: f03b c03d sub r55,r4,488
+
+00000cda \<lsri16\>:
+ cda: 900f 2406 lsr.l ip,ip,0x0
+ cde: 6fe6 lsr r3,r3,0x1f
+ ce0: 0206 lsr r0,r0,0x10
+ ce2: 6def 2406 lsr.l fp,fp,0xf
+ ce6: b42f 2406 lsr.l sp,sp,0x1
+ cea: 0cc6 lsr r0,r3,0x6
+ cec: 2906 lsr r1,r2,0x8
+ cee: 79cf 2406 lsr.l fp,lr,0xe
+
+00000cf2 \<lsri32\>:
+ cf2: 900f 2406 lsr.l ip,ip,0x0
+ cf6: 6fef fc06 lsr.l r59,r59,0x1f
+ cfa: 920f 6c06 lsr.l r28,r28,0x10
+ cfe: 6def 6c06 lsr.l r27,r27,0xf
+ d02: b42f 2406 lsr.l sp,sp,0x1
+ d06: c26f 7806 lsr.l r30,r48,0x13
+ d0a: 7eef a006 lsr.l r43,r7,0x17
+ d0e: 8b8f 6006 lsr.l r28,r2,0x1c
+
+00000d12 \<lsli16\>:
+ d12: 901f 2406 lsl.l ip,ip,0x0
+ d16: 6ff6 lsl r3,r3,0x1f
+ d18: 0216 lsl r0,r0,0x10
+ d1a: 6dff 2406 lsl.l fp,fp,0xf
+ d1e: b43f 2406 lsl.l sp,sp,0x1
+ d22: 4d76 lsl r2,r3,0xb
+ d24: c8df 2006 lsl.l lr,r2,0x6
+ d28: 0a16 lsl r0,r2,0x10
+
+00000d2a \<lsli32\>:
+ d2a: 901f 2406 lsl.l ip,ip,0x0
+ d2e: 6fff fc06 lsl.l r59,r59,0x1f
+ d32: 921f 6c06 lsl.l r28,r28,0x10
+ d36: 6dff 6c06 lsl.l r27,r27,0xf
+ d3a: b43f 2406 lsl.l sp,sp,0x1
+ d3e: 0e7f f806 lsl.l r56,r51,0x13
+ d42: 3e7f 5006 lsl.l r17,r39,0x13
+ d46: 519f 0406 lsl.l r2,ip,0xc
+
+00000d4a \<asri16\>:
+ d4a: 900f 240e asr.l ip,ip,0x0
+ d4e: 6fee asr r3,r3,0x1f
+ d50: 020e asr r0,r0,0x10
+ d52: 6def 240e asr.l fp,fp,0xf
+ d56: b42f 240e asr.l sp,sp,0x1
+ d5a: d2af 240e asr.l lr,ip,0x15
+ d5e: 6ece asr r3,r3,0x16
+ d60: 6d2e asr r3,r3,0x9
+
+00000d62 \<asri32\>:
+ d62: 900f 240e asr.l ip,ip,0x0
+ d66: 6fef fc0e asr.l r59,r59,0x1f
+ d6a: 920f 6c0e asr.l r28,r28,0x10
+ d6e: 6def 6c0e asr.l r27,r27,0xf
+ d72: b42f 240e asr.l sp,sp,0x1
+ d76: 9a2f d40e asr.l r52,r46,0x11
+ d7a: e2cf 5c0e asr.l r23,r56,0x16
+ d7e: bb8f 540e asr.l r21,r46,0x1c
+
+00000d82 \<mov8\>:
+ d82: 800b 2002 mov ip,0x0
+ d86: 7fe3 mov r3,0xff
+ d88: 1003 mov r0,0x80
+ d8a: 6feb 2002 mov fp,0x7f
+ d8e: a02b 2002 mov sp,0x1
+ d92: cb6b 2002 mov lr,0x5b
+ d96: 09a3 mov r0,0x4d
+ d98: 614b 2002 mov fp,0xa
+
+00000d9c \<mov16\>:
+ d9c: 800b 2002 mov ip,0x0
+ da0: 7feb eff2 mov r59,0xffff
+ da4: 800b 6802 mov r28,0x8000
+ da8: 7feb 67f2 mov r27,0x7fff
+ dac: a02b 2002 mov sp,0x1
+ db0: be2b cee2 mov r53,0xeef1
+ db4: 5deb 4cb2 mov r18,0xcbef
+ db8: 044b 48e2 mov r16,0x8e22
+
+00000dbc \<faddf16\>:
+ dbc: 920f 2487 fadd.l ip,ip,ip
+ dc0: 6d87 fadd r3,r3,r3
+ dc2: 0007 fadd r0,r0,r0
+ dc4: 6d8f 2487 fadd.l fp,fp,fp
+ dc8: b68f 2487 fadd.l sp,sp,sp
+ dcc: b10f 2407 fadd.l sp,ip,r2
+ dd0: a90f 2007 fadd.l sp,r2,r2
+ dd4: b98f 2487 fadd.l sp,lr,fp
+
+00000dd8 \<faddf32\>:
+ dd8: 920f 2487 fadd.l ip,ip,ip
+ ddc: 6d8f ff87 fadd.l r59,r59,r59
+ de0: 920f 6d87 fadd.l r28,r28,r28
+ de4: 6d8f 6d87 fadd.l r27,r27,r27
+ de8: b68f 2487 fadd.l sp,sp,sp
+ dec: b78f 2e07 fadd.l sp,r29,r39
+ df0: 018f 9407 fadd.l r32,r40,r3
+ df4: 170f ac87 fadd.l r40,r29,lr
+
+00000df8 \<fsubf16\>:
+ df8: 921f 2487 fsub.l ip,ip,ip
+ dfc: 6d97 fsub r3,r3,r3
+ dfe: 0017 fsub r0,r0,r0
+ e00: 6d9f 2487 fsub.l fp,fp,fp
+ e04: b69f 2487 fsub.l sp,sp,sp
+ e08: 5a9f 0487 fsub.l r2,lr,sp
+ e0c: 661f 0087 fsub.l r3,r1,ip
+ e10: 711f 0407 fsub.l r3,ip,r2
+
+00000e14 \<fsubf32\>:
+ e14: 921f 2487 fsub.l ip,ip,ip
+ e18: 6d9f ff87 fsub.l r59,r59,r59
+ e1c: 921f 6d87 fsub.l r28,r28,r28
+ e20: 6d9f 6d87 fsub.l r27,r27,r27
+ e24: b69f 2487 fsub.l sp,sp,sp
+ e28: 219f 1c87 fsub.l r1,r56,fp
+ e2c: 7b9f 0887 fsub.l r3,r22,r15
+ e30: c29f 1a87 fsub.l r6,r48,r45
+
+00000e34 \<fmulf16\>:
+ e34: 922f 2487 fmul.l ip,ip,ip
+ e38: 6da7 fmul r3,r3,r3
+ e3a: 0027 fmul r0,r0,r0
+ e3c: 6daf 2487 fmul.l fp,fp,fp
+ e40: b6af 2487 fmul.l sp,sp,sp
+ e44: 71af 0487 fmul.l r3,ip,fp
+ e48: c52f 2007 fmul.l lr,r1,r2
+ e4c: bb2f 2487 fmul.l sp,lr,lr
+
+00000e50 \<fmulf32\>:
+ e50: 922f 2487 fmul.l ip,ip,ip
+ e54: 6daf ff87 fmul.l r59,r59,r59
+ e58: 922f 6d87 fmul.l r28,r28,r28
+ e5c: 6daf 6d87 fmul.l r27,r27,r27
+ e60: b6af 2487 fmul.l sp,sp,sp
+ e64: 5daf eb07 fmul.l r58,r23,r51
+ e68: cbaf 4287 fmul.l r22,r2,r47
+ e6c: d92f a487 fmul.l r46,lr,sl
+
+00000e70 \<fmaddf16\>:
+ e70: 923f 2487 fmadd.l ip,ip,ip
+ e74: 6db7 fmadd r3,r3,r3
+ e76: 0037 fmadd r0,r0,r0
+ e78: 6dbf 2487 fmadd.l fp,fp,fp
+ e7c: b6bf 2487 fmadd.l sp,sp,sp
+ e80: a5bf 2007 fmadd.l sp,r1,r3
+ e84: 6c37 fmadd r3,r3,r0
+ e86: 523f 0487 fmadd.l r2,ip,ip
+
+00000e8a \<fmaddf32\>:
+ e8a: 923f 2487 fmadd.l ip,ip,ip
+ e8e: 6dbf ff87 fmadd.l r59,r59,r59
+ e92: 923f 6d87 fmadd.l r28,r28,r28
+ e96: 6dbf 6d87 fmadd.l r27,r27,r27
+ e9a: b6bf 2487 fmadd.l sp,sp,sp
+ e9e: 983f 7a07 fmadd.l r28,r54,r32
+ ea2: 89bf 2087 fmadd.l ip,r2,fp
+ ea6: 633f 3507 fmadd.l fp,r40,r22
+
+00000eaa \<fmsubf16\>:
+ eaa: 924f 2487 fmsub.l ip,ip,ip
+ eae: 6dc7 fmsub r3,r3,r3
+ eb0: 0047 fmsub r0,r0,r0
+ eb2: 6dcf 2487 fmsub.l fp,fp,fp
+ eb6: b6cf 2487 fmsub.l sp,sp,sp
+ eba: accf 2407 fmsub.l sp,fp,r1
+ ebe: 2ecf 0487 fmsub.l r1,fp,sp
+ ec2: 0c47 fmsub r0,r3,r0
+
+00000ec4 \<fmsubf32\>:
+ ec4: 924f 2487 fmsub.l ip,ip,ip
+ ec8: 6dcf ff87 fmsub.l r59,r59,r59
+ ecc: 924f 6d87 fmsub.l r28,r28,r28
+ ed0: 6dcf 6d87 fmsub.l r27,r27,r27
+ ed4: b6cf 2487 fmsub.l sp,sp,sp
+ ed8: 50cf a887 fmsub.l r42,r20,sb
+ edc: c14f 4e87 fmsub.l r22,r24,r42
+ ee0: f9cf 2907 fmsub.l r15,r22,r19
+ ee4: 2a4c 0101 ldr.l r1,\[r2,-0xc]
+ ee8: dbbc 4dff strh.l r22,\[r30,-0x7ff]
+ eec: 9bec 24ff ldrd.l ip,\[lr,\+0x7ff]
+ ef0: 201e bitr r1,r0
+ ef2: fc1f 640e bitr.l r31,r15
--- /dev/null
+# EPIPHANY assembler testsuite. -*- Tcl -*-
+
+if [istarget epiphany*-*-*] {
+ run_dump_test "allinsn"
+ run_dump_test "regression"
+ run_dump_test "sample"
+ run_dump_test "branch_lit"
+ run_dump_test "badrelax"
+ gas_test_error "badpostmod" "" "destination register modified by displacement-post-modified address"
+ run_dump_test "addr-syntax"
+}
--- /dev/null
+ .data
+foodata: .hword 42
+ .text
+footext:
+ .text
+ .global beq16
+
+ .text
+ .global beq
+bgt16:
+ bgt 4
+ bgt 4
+ bgt -4
+ bgt footext
+ bgt foodata
+ bgt 4
+ bgt footext
+ bgt footext
+ .text
+ .global bgt
+
+bgtu16:
+ bgtu 4
+ bgtu -4
+ bgtu footext
+ bgtu 4
+ bgtu -4
+ bgtu footext
+ bgtu footext
+ bgtu 4
+ .text
+ .global bgtu
+
+bgte16:
+ bgte footext
+ bgte footext
+ bgte footext
+ bgte footext
+ bgte footext
+ bgte -4
+ bgte foodata
+ bgte foodata
+
+ .text
+ .global bgteu16
+bgteu16:
+ bgteu 4
+ bgteu -4
+ bgteu foodata
+ bgteu 4
+ bgteu footext
+ bgteu 4
+ bgteu foodata
+ bgteu foodata
+ .text
+ .global bgteu
+bgteu:
+ .text
+ .global blt16
+blt16:
+ blt -4
+ blt 4
+ blt -4
+ blt 4
+ blt -4
+ blt 4
+ blt foodata
+ blt foodata
+ .text
+ .global blt
+blt:
+ .text
+ .global bltu16
+bltu16:
+ bltu -4
+ bltu 4
+ bltu -4
+ bltu footext
+ bltu footext
+ bltu footext
+ bltu 4
+ bltu foodata
+ .text
+ .global bltu
+bltu:
+ .text
+ .global blte16
+blte16:
+ blte footext
+ blte foodata
+ blte foodata
+ blte footext
+ blte -4
+ blte footext
+ blte footext
+ blte 4
+ .text
+ .global blte
+blte:
+ .text
+ .global blteu16
+blteu16:
+ blteu footext
+ blteu foodata
+ blteu footext
+ blteu foodata
+ blteu footext
+ blteu -4
+ blteu foodata
+ blteu foodata
+ .text
+ .global blteu
+blteu:
+ .text
+ .global bbeq16
+bbeq16:
+ bbeq footext
+ bbeq footext
+ bbeq foodata
+ bbeq footext
+ bbeq 4
+ bbeq foodata
+ bbeq foodata
+ bbeq 4
+ .text
+ .global bbeq
+bbeq:
+ .text
+ .global bbne16
+bbne16:
+ bbne foodata
+ bbne -4
+ bbne 4
+ bbne footext
+ bbne 4
+ bbne 4
+ bbne footext
+ bbne footext
+ .text
+ .global bbne
+bbne:
+ .text
+ .global bblt16
+bblt16:
+ bblt foodata
+ bblt 4
+ bblt 4
+ bblt 4
+ bblt -4
+ bblt 4
+ bblt footext
+ bblt -4
+ .text
+ .global bblt
+bblt:
+ .text
+ .global bblte16
+bblte16:
+ bblte 4
+ bblte 4
+ bblte footext
+ bblte footext
+ bblte 4
+ bblte -4
+ bblte foodata
+ bblte 4
+ .text
+ .global bblte
+bblte:
+ .text
+ .global b16
+b16:
+ b footext
+ b footext
+ b 4
+ b -4
+ b footext
+ b foodata
+ b foodata
+ b -4
+ .text
+ .global b
+b:
+ .text
+ .global bl16
+bl16:
+ bl -4
+ bl 4
+ bl footext
+ bl -4
+ bl footext
+ bl -4
+ bl -4
+ bl footext
+ .text
+ .global bl
+bl:
+ .text
+ .global jr16
+jr16:
+ jr ip
+ jr r3
+ jr r0
+ jr fp
+ jr sp
+ jr r0
+ jr r3
+ jr r0
+ .text
+ .global jr
+jr:
+ jr ip
+ jr r59
+ jr r28
+ jr r27
+ jr sp
+ jr r51
+ jr r56
+ jr r45
+ .text
+ .global jalr16
+jalr16:
+ jalr ip
+ jalr r3
+ jalr r0
+ jalr fp
+ jalr sp
+ jalr r3
+ jalr fp
+ jalr ip
+ .text
+ .global jalr
+jalr:
+ jalr ip
+ jalr r59
+ jalr r28
+ jalr r27
+ jalr sp
+ jalr r11
+ jalr r28
+ jalr r59
+ .text
+ .global ldrbx16
+ldrbx16:
+ ldrb ip,[ip,ip]
+ ldrb r3,[r3,r3]
+ ldrb r0,[r0,r0]
+ ldrb fp,[fp,fp]
+ ldrb sp,[sp,sp]
+ ldrb ip,[r0,r0]
+ ldrb r3,[r2,lr]
+ ldrb r2,[ip,r3]
+ .text
+ .global ldrbp16
+ldrbp16:
+ ldrb sp,[r0],fp
+ ldrb lr,[r1],ip
+ ldrb fp,[r0],fp
+ .text
+ .global ldrbx
+ldrbx:
+ ldrb ip,[ip,ip]
+ ldrb r59,[r59,r59]
+ ldrb r28,[r28,r28]
+ ldrb r27,[r27,r27]
+ ldrb sp,[sp,sp]
+ ldrb r41,[r18,r47]
+ ldrb r43,[r16,r21]
+ ldrb r32,[r8,r8]
+ .text
+ .global ldrbp
+ldrbp:
+ ldrb r36,[r49],r18
+ ldrb r32,[r59],r50
+ ldrb r58,[r11],r25
+ .text
+ .global ldrbd16
+ldrbd16:
+ ldrb ip,[ip,0]
+ ldrb r3,[r3,7]
+ ldrb r0,[r0,4]
+ ldrb fp,[fp,3]
+ ldrb sp,[sp,1]
+ ldrb lr,[sp,1]
+ ldrb r1,[r0,0]
+ ldrb r1,[r1,1]
+ .text
+ .global ldrbd
+ldrbd:
+ ldrb ip,[ip,0]
+ ldrb r59,[r59,2047]
+ ldrb r28,[r28,1024]
+ ldrb r27,[r27,1023]
+ ldrb sp,[sp,1]
+ ldrb r7,[r33,1574]
+ ldrb r31,[r6,1957]
+ ldrb r10,[r0,1831]
+ .text
+ .global ldrhx16
+ldrhx16:
+ ldrh ip,[ip,ip]
+ ldrh r3,[r3,r3]
+ ldrh r0,[r0,r0]
+ ldrh fp,[fp,fp]
+ ldrh sp,[sp,sp]
+ ldrh r0,[r0,lr]
+ ldrh lr,[lr,sp]
+ ldrh r0,[fp,fp]
+ .text
+ .global ldrhp16
+ldrhp16:
+ ldrh r2,[sp],fp
+ ldrh r22,[sp],fp
+ .text
+ .global ldrhx
+ldrhx:
+ ldrh ip,[ip,ip]
+ ldrh r59,[r59,r59]
+ ldrh r28,[r28,r28]
+ ldrh r27,[r27,r27]
+ ldrh sp,[sp,sp]
+ ldrh r46,[r17,r21]
+ ldrh r30,[r1,r47]
+ ldrh r43,[r19,r20]
+ .text
+ .global ldrhp
+ldrhp:
+
+
+
+ ldrh r32,[r31],r29
+ ldrh r52,[r47],r10
+ ldrh r31,[r40],r3
+ .text
+ .global ldrhd16
+ldrhd16:
+ ldrh ip,[ip,0]
+ ldrh r3,[r3,7]
+ ldrh r0,[r0,4]
+ ldrh fp,[fp,3]
+ ldrh sp,[sp,1]
+ ldrh lr,[r2,0]
+ ldrh r3,[r0,7]
+ ldrh r0,[r3,6]
+ .text
+ .global ldrhd
+ldrhd:
+ ldrh ip,[ip,0]
+ ldrh r59,[r59,2047]
+ ldrh r28,[r28,1024]
+ ldrh r27,[r27,1023]
+ ldrh sp,[sp,1]
+ ldrh r45,[r24,1221]
+ ldrh r36,[r43,1738]
+ ldrh r42,[r48,25]
+ .text
+ .global ldrx16
+ldrx16:
+ ldr ip,[ip,ip]
+ ldr r3,[r3,r3]
+ ldr r0,[r0,r0]
+ ldr fp,[fp,fp]
+ ldr sp,[sp,sp]
+ ldr r3,[fp,lr]
+ ldr ip,[lr,r2]
+ ldr r3,[r2,lr]
+ .text
+ .global ldrp16
+ldrp16:
+ ldr lr,[fp],sp
+ ldr r0,[sp],r0
+ ldr fp,[r2],r1
+ .text
+ .global ldrx
+ldrx:
+ ldr ip,[ip,ip]
+ ldr r59,[r59,r59]
+ ldr r28,[r28,r28]
+ ldr r27,[r27,r27]
+ ldr sp,[sp,sp]
+ ldr r24,[r16,r47]
+ ldr r22,[r41,r49]
+ ldr r14,[fp,r39]
+ .text
+ .global ldrp
+ldrp:
+ ldr r21,[r5],r30
+ ldr r36,[r12],r14
+ ldr r12,[r4],r11
+ .text
+ .global ldrd16
+ldrd16:
+ ldr ip,[ip,0]
+ ldr r3,[r3,7]
+ ldr r0,[r0,4]
+ ldr fp,[fp,3]
+ ldr sp,[sp,1]
+ ldr r0,[sp,0]
+ ldr ip,[r1,7]
+ ldr fp,[r1,1]
+ .text
+ .global ldrd
+ldrd:
+ ldr ip,[ip,0]
+ ldr r59,[r59,2047]
+ ldr r28,[r28,1024]
+ ldr r27,[r27,1023]
+ ldr sp,[sp,1]
+ ldr r22,[r30,975]
+ ldr r7,[r44,1361]
+ ldr r23,[r19,1855]
+ .text
+ .global ldrdx16
+ldrdx16:
+ ldrd ip,[ip,ip]
+ ldrd r4,[r3,r3]
+ ldrd r0,[r0,r0]
+ ldrd r14,[fp,fp]
+ ldrd r16,[sp,sp]
+ ldrd r30,[r2,ip]
+ ldrd r0,[fp,r3]
+ ldrd r20,[ip,lr]
+ .text
+ .global ldrdp16
+ldrdp16:
+ ldrd r4,[r3],r3
+ ldrd r16,[fp],fp
+ ldrd r20,[sp],sp
+ ldrd r10,[ip],r1
+ ldrd r30,[fp],lr
+ ldrd r62,[lr],sp
+ .text
+ .global ldrdx
+ldrdx:
+ ldrd ip,[ip,ip]
+ ldrd r58,[r59,r59]
+ ldrd r28,[r28,r28]
+ ldrd r26,[r27,r27]
+ ldrd r12,[sp,sp]
+ ldrd r32,[fp,r59]
+ ldrd r4,[r17,r6]
+ ldrd r32,[r40,r1]
+ .text
+ .global ldrdp
+ldrdp:
+ ldrd r16,[sp],sp
+ ldrd r46,[r33],r30
+ ldrd r24,[r36],r59
+ ldrd r58,[r32],r11
+ .text
+ .global ldrdd16
+ldrdd16:
+ ldrd ip,[ip,0]
+ ldrd r4,[r3,7]
+ ldrd r0,[r0,4]
+ ldrd r16,[fp,3]
+ ldrd r18,[sp,1]
+ ldrd r0,[fp,3]
+ ldrd lr,[fp,7]
+ ldrd lr,[ip,1]
+ .text
+ .global ldrdd
+ldrdd:
+ ldrd ip,[ip,0]
+ ldrd r58,[r59,2047]
+ ldrd r28,[r28,1024]
+ ldrd r2,[r27,1023]
+ ldrd r16,[sp,1]
+ ldrd r4,[r21,761]
+ ldrd lr,[r41,1553]
+ ldrd r6,[r14,1922]
+ .text
+ .global strbx16
+strbx16:
+ strb ip,[ip,ip]
+ strb r3,[r3,r3]
+ strb r0,[r0,r0]
+ strb fp,[fp,fp]
+ strb sp,[sp,sp]
+ strb r1,[lr,r3]
+ strb ip,[r3,lr]
+ strb lr,[ip,ip]
+ .text
+ .global strbx
+strbx:
+ strb ip,[ip,ip]
+ strb r59,[r59,r59]
+ strb r28,[r28,r28]
+ strb r27,[r27,r27]
+ strb sp,[sp,sp]
+ strb r50,[r15,sp]
+ strb lr,[fp,r52]
+ strb r14,[r24,r51]
+ .text
+ .global strbp16
+strbp16:
+ strb ip,[ip],ip
+ strb r3,[r3],r3
+ strb r0,[r0],r0
+ strb fp,[fp],fp
+ strb sp,[sp],sp
+ strb r2,[fp],ip
+ strb fp,[r0],r1
+ strb r2,[r2],r3
+ .text
+ .global strbp
+strbp:
+ strb ip,[ip],ip
+ strb r59,[r59],r59
+ strb r28,[r28],r28
+ strb r27,[r27],r27
+ strb sp,[sp],sp
+ strb r14,[r51],r2
+ strb r6,[r44],r50
+ strb r44,[r9],r49
+ .text
+ .global strbd16
+strbd16:
+ strb ip,[ip,0]
+ strb r3,[r3,7]
+ strb r0,[r0,4]
+ strb fp,[fp,3]
+ strb sp,[sp,1]
+ strb r0,[r2,1]
+ strb sp,[r2,3]
+ strb fp,[r2,4]
+ .text
+ .global strbd
+strbd:
+ strb ip,[ip,0]
+ strb r59,[r59,2047]
+ strb r28,[r28,1024]
+ strb r27,[r27,1023]
+ strb sp,[sp,1]
+ strb r23,[r10,1404]
+ strb r12,[r35,1461]
+ strb r54,[r58,1090]
+ .text
+ .global strhx16
+strhx16:
+ strh ip,[ip,ip]
+ strh r3,[r3,r3]
+ strh r0,[r0,r0]
+ strh fp,[fp,fp]
+ strh sp,[sp,sp]
+ strh r0,[r3,r1]
+ strh r1,[fp,r2]
+ strh r3,[r3,fp]
+ .text
+ .global strhx
+strhx:
+ strh ip,[ip,ip]
+ strh r59,[r59,r59]
+ strh r28,[r28,r28]
+ strh r27,[r27,r27]
+ strh sp,[sp,sp]
+ strh r16,[r38,r31]
+ strh r32,[r12,r28]
+ strh r57,[r11,r9]
+ .text
+ .global strhp16
+strhp16:
+ strh ip,[ip],ip
+ strh r3,[r3],r3
+ strh r0,[r0],r0
+ strh fp,[fp],fp
+ strh sp,[sp],sp
+ strh r0,[r2],sp
+ strh sp,[r3],r0
+ strh r1,[r0],r0
+ .text
+ .global strhp
+strhp:
+ strh ip,[ip],ip
+ strh r59,[r59],r59
+ strh r28,[r28],r28
+ strh r27,[r27],r27
+ strh sp,[sp],sp
+ strh r3,[r37],r54
+ strh r4,[r54],r25
+ strh r5,[r32],r25
+ .text
+ .global strhd16
+strhd16:
+ strh ip,[ip,0]
+ strh r3,[r3,7]
+ strh r0,[r0,4]
+ strh fp,[fp,3]
+ strh sp,[sp,1]
+ strh r3,[r0,3]
+ strh lr,[ip,7]
+ strh r3,[r2,7]
+ .text
+ .global strhd
+strhd:
+ strh ip,[ip,0]
+ strh r59,[r59,2047]
+ strh r28,[r28,1024]
+ strh r27,[r27,1023]
+ strh sp,[sp,1]
+ strh r7,[r38,1181]
+ strh r25,[r4,77]
+ strh r11,[fp,631]
+ .text
+ .global strx16
+strx16:
+ str ip,[ip,ip]
+ str r3,[r3,r3]
+ str r0,[r0,r0]
+ str fp,[fp,fp]
+ str sp,[sp,sp]
+ str lr,[r3,r3]
+ str r3,[fp,r0]
+ str ip,[sp,r1]
+ .text
+ .global strx
+strx:
+ str ip,[ip,ip]
+ str r59,[r59,r59]
+ str r28,[r28,r28]
+ str r27,[r27,r27]
+ str sp,[sp,sp]
+ str r53,[r29,r28]
+ str r30,[r22,r34]
+ str r28,[r28,r44]
+ .text
+ .global strp16
+strp16:
+ str ip,[ip],ip
+ str r3,[r3],r3
+ str r0,[r0],r0
+ str fp,[fp],fp
+ str sp,[sp],sp
+ str lr,[r0],r0
+ str fp,[r0],sp
+ str r3,[fp],r0
+ .text
+ .global strp
+strp:
+ str ip,[ip],ip
+ str r59,[r59],r59
+ str r28,[r28],r28
+ str r27,[r27],r27
+ str sp,[sp],sp
+ str r22,[r36],r15
+ str r44,[r13],r47
+ str r19,[r48],sp
+ .text
+ .global strd16
+strd16:
+ str ip,[ip,0]
+ str r3,[r3,7]
+ str r0,[r0,4]
+ str fp,[fp,3]
+ str sp,[sp,1]
+ str r3,[fp,3]
+ str sp,[ip,6]
+ str r1,[lr,3]
+ .text
+ .global strd
+strd:
+ str ip,[ip,0]
+ str r59,[r59,2047]
+ str r28,[r28,1024]
+ str r27,[r27,1023]
+ str sp,[sp,1]
+ str r45,[r44,74]
+ str r58,[r50,370]
+ str r40,[r3,626]
+ .text
+ .global strdx16
+strdx16:
+ strd ip,[ip,ip]
+ strd r2,[r3,r3]
+ strd r0,[r0,r0]
+ strd r16,[fp,fp]
+ strd r18,[sp,sp]
+ strd ip,[r3,r1]
+ strd r2,[lr,fp]
+ strd ip,[r2,r2]
+ .text
+ .global strdx
+strdx:
+ strd ip,[ip,ip]
+ strd r58,[r59,r59]
+ strd r28,[r28,r28]
+ strd r26,[r27,r27]
+ strd r14,[sp,sp]
+ strd r38,[r53,lr]
+ strd r24,[r19,r43]
+ strd r12,[r10,r30]
+ .text
+ .global strdp16
+strdp16:
+ strd ip,[ip],ip
+ strd r2,[r3],r3
+ strd r0,[r0],r0
+ strd r6,[fp],fp
+ strd r4,[sp],sp
+ strd r2,[r3],r0
+ strd r2,[r0],r1
+ strd r2,[lr],r1
+ .text
+ .global strdp
+strdp:
+ strd ip,[ip],ip
+ strd r58,[r59],r59
+ strd r28,[r28],r28
+ strd r26,[r27],r27
+ strd r22,[sp],sp
+ strd r6,[r10],r44
+ strd r10,[r43],r5
+ strd r46,[r17],lr
+ .text
+ .global strdd16
+strdd16:
+ strd r0,[ip,0]
+ strd r2,[r3,7]
+ strd r0,[r0,4]
+ strd r2,[fp,3]
+ strd r4,[sp,1]
+ strd r2,[r2,5]
+ strd r6,[r3,7]
+ strd r6,[r1,2]
+ .text
+ .global strdd
+strdd:
+ strd ip,[ip,0]
+ strd r58,[r59,2047]
+ strd r28,[r28,1024]
+ strd r26,[r27,1023]
+ strd r14,[sp,1]
+ strd r28,[r52,719]
+ strd r40,[r53,1994]
+ strd r44,[r57,494]
+ .text
+ .global mov16EQ
+mov16EQ:
+ moveq ip,ip
+ moveq r3,r3
+ moveq r0,r0
+ moveq fp,fp
+ moveq sp,sp
+ moveq ip,r2
+ moveq r2,fp
+ moveq fp,sp
+ .text
+ .global movEQ
+movEQ:
+ moveq ip,ip
+ moveq r59,r59
+ moveq r28,r28
+ moveq r27,r27
+ moveq sp,sp
+ moveq r32,r30
+ moveq r43,r39
+ moveq r25,r33
+ .text
+ .global mov16NE
+mov16NE:
+ movne ip,ip
+ movne r3,r3
+ movne r0,r0
+ movne fp,fp
+ movne sp,sp
+ movne r3,r3
+ movne r0,fp
+ movne fp,fp
+ .text
+ .global movNE
+movNE:
+ movne ip,ip
+ movne r59,r59
+ movne r28,r28
+ movne r27,r27
+ movne sp,sp
+ movne r4,r3
+ movne r28,fp
+ movne r23,r39
+ .text
+ .global mov16GT
+mov16GT:
+ movgt ip,ip
+ movgt r3,r3
+ movgt r0,r0
+ movgt fp,fp
+ movgt sp,sp
+ movgt r1,r3
+ movgt lr,r3
+ movgt r1,ip
+ .text
+ .global movGT
+movGT:
+ movgt ip,ip
+ movgt r59,r59
+ movgt r28,r28
+ movgt r27,r27
+ movgt sp,sp
+ movgt r1,r21
+ movgt r13,r3
+ movgt r28,r43
+ .text
+ .global mov16GTU
+mov16GTU:
+ movgtu ip,ip
+ movgtu r3,r3
+ movgtu r0,r0
+ movgtu fp,fp
+ movgtu sp,sp
+ movgtu ip,lr
+ movgtu sp,ip
+ movgtu ip,sp
+ .text
+ .global movGTU
+movGTU:
+ movgtu ip,ip
+ movgtu r59,r59
+ movgtu r28,r28
+ movgtu r27,r27
+ movgtu sp,sp
+ movgtu r34,r33
+ movgtu r17,r48
+ movgtu r35,r24
+ .text
+ .global mov16GTE
+mov16GTE:
+ movgte ip,ip
+ movgte r3,r3
+ movgte r0,r0
+ movgte fp,fp
+ movgte sp,sp
+ movgte r0,r0
+ movgte r2,sp
+ movgte lr,r2
+ .text
+ .global movGTE
+movGTE:
+ movgte ip,ip
+ movgte r59,r59
+ movgte r28,r28
+ movgte r27,r27
+ movgte sp,sp
+ movgte ip,r59
+ movgte r37,r42
+ movgte r44,r26
+ .text
+ .global mov16GTEU
+mov16GTEU:
+ movgteu ip,ip
+ movgteu r3,r3
+ movgteu r0,r0
+ movgteu fp,fp
+ movgteu sp,sp
+ movgteu lr,ip
+ movgteu sp,r1
+ movgteu ip,lr
+ .text
+ .global movGTEU
+movGTEU:
+ movgteu ip,ip
+ movgteu r59,r59
+ movgteu r28,r28
+ movgteu r27,r27
+ movgteu sp,sp
+ movgteu r58,r47
+ movgteu r56,r5
+ movgteu r20,r52
+ .text
+ .global mov16LT
+mov16LT:
+ movlt ip,ip
+ movlt r3,r3
+ movlt r0,r0
+ movlt fp,fp
+ movlt sp,sp
+ movlt r3,r3
+ movlt r2,r2
+ movlt ip,lr
+ .text
+ .global movLT
+movLT:
+ movlt ip,ip
+ movlt r59,r59
+ movlt r28,r28
+ movlt r27,r27
+ movlt sp,sp
+ movlt r52,r12
+ movlt r57,r22
+ movlt r8,r7
+ .text
+ .global mov16LTU
+mov16LTU:
+ movltu ip,ip
+ movltu r3,r3
+ movltu r0,r0
+ movltu fp,fp
+ movltu sp,sp
+ movltu ip,r2
+ movltu sp,ip
+ movltu r1,r0
+ .text
+ .global movLTU
+movLTU:
+ movltu ip,ip
+ movltu r59,r59
+ movltu r28,r28
+ movltu r27,r27
+ movltu sp,sp
+ movltu r13,r31
+ movltu r43,ip
+ movltu r7,r56
+ .text
+ .global mov16LTE
+mov16LTE:
+ movlte ip,ip
+ movlte r3,r3
+ movlte r0,r0
+ movlte fp,fp
+ movlte sp,sp
+ movlte r0,r3
+ movlte r3,ip
+ movlte r3,lr
+ .text
+ .global movLTE
+movLTE:
+ movlte ip,ip
+ movlte r59,r59
+ movlte r28,r28
+ movlte r27,r27
+ movlte sp,sp
+ movlte r30,r27
+ movlte r35,r52
+ movlte r15,r53
+ .text
+ .global mov16LTEU
+mov16LTEU:
+ movlteu ip,ip
+ movlteu r3,r3
+ movlteu r0,r0
+ movlteu fp,fp
+ movlteu sp,sp
+ movlteu ip,lr
+ movlteu r2,r2
+ movlteu r2,fp
+ .text
+ .global movLTEU
+movLTEU:
+ movlteu ip,ip
+ movlteu r59,r59
+ movlteu r28,r28
+ movlteu r27,r27
+ movlteu sp,sp
+ movlteu r31,r36
+ movlteu r24,r50
+ movlteu r52,r54
+ .text
+ .global mov16B
+mov16B:
+ mov ip,ip
+ mov r3,r3
+ mov r0,r0
+ mov fp,fp
+ mov sp,sp
+ mov ip,r1
+ mov ip,r0
+ mov r0,ip
+ .text
+ .global movB
+movB:
+ mov ip,ip
+ mov r59,r59
+ mov r28,r28
+ mov r27,r27
+ mov sp,sp
+ mov r1,r59
+ mov r28,r12
+ mov r5,r42
+ .text
+ .global mov16BEQ
+mov16BEQ:
+ movbeq ip,ip
+ movbeq r3,r3
+ movbeq r0,r0
+ movbeq fp,fp
+ movbeq sp,sp
+ movbeq lr,r2
+ movbeq fp,r2
+ movbeq ip,r1
+ .text
+ .global movBEQ
+movBEQ:
+ movbeq ip,ip
+ movbeq r59,r59
+ movbeq r28,r28
+ movbeq r27,r27
+ movbeq sp,sp
+ movbeq r29,r16
+ movbeq r18,r46
+ movbeq lr,r1
+ .text
+ .global mov16BNE
+mov16BNE:
+ movbne ip,ip
+ movbne r3,r3
+ movbne r0,r0
+ movbne fp,fp
+ movbne sp,sp
+ movbne r1,r2
+ movbne ip,r1
+ movbne ip,r3
+ .text
+ .global movBNE
+movBNE:
+ movbne ip,ip
+ movbne r59,r59
+ movbne r28,r28
+ movbne r27,r27
+ movbne sp,sp
+ movbne r15,r7
+ movbne r24,r43
+ movbne r23,r52
+ .text
+ .global mov16BLT
+mov16BLT:
+ movblt ip,ip
+ movblt r3,r3
+ movblt r0,r0
+ movblt fp,fp
+ movblt sp,sp
+ movblt sp,lr
+ movblt ip,lr
+ movblt lr,sp
+ .text
+ .global movBLT
+movBLT:
+ movblt ip,ip
+ movblt r59,r59
+ movblt r28,r28
+ movblt r27,r27
+ movblt sp,sp
+ movblt r52,r44
+ movblt r57,r35
+ movblt r53,r33
+ .text
+ .global mov16BLTE
+mov16BLTE:
+ movblte ip,ip
+ movblte r3,r3
+ movblte r0,r0
+ movblte fp,fp
+ movblte sp,sp
+ movblte sp,ip
+ movblte r0,fp
+ movblte r0,sp
+ .text
+ .global movBLTE
+movBLTE:
+ movblte ip,ip
+ movblte r59,r59
+ movblte r28,r28
+ movblte r27,r27
+ movblte sp,sp
+ movblte r58,r44
+ movblte r35,r22
+ movblte r8,r2
+ .text
+ .global movts16
+movts16:
+ movts config,ip
+ movts ipend,r3
+ movts iret,r0
+ movts debug,fp
+ movts status,sp
+ movts status,fp
+ movts pc,fp
+ movts imask,r0
+ .text
+ .global movts
+movts:
+ movts config,ip
+ movts ipend,r59
+ movts iret,r28
+ movts debug,r27
+ movts status,sp
+ movts debug,r50
+ movts ipend,r33
+ movts status,ip
+ .text
+ .global movfs16
+movfs16:
+ movfs ip,config
+ movfs r3,ipend
+ movfs r0,iret
+ movfs fp,debug
+ movfs sp,status
+ movfs r1,iret
+ movfs r2,status
+ movfs lr,debug
+ .text
+ .global movfs
+movfs:
+ movfs ip,config
+ movfs r59,ipend
+ movfs r28,iret
+ movfs r27,debug
+ movfs sp,status
+ movfs r13,debug
+ movfs r15,status
+ movfs r16,imask
+ .text
+ .global nop
+nop:
+ nop
+ .text
+ .global idle
+idle:
+ idle
+ .text
+ .global bkpt
+bkpt:
+ bkpt
+ .text
+ .global rti
+rti:
+ rti
+ .text
+ .global trap16
+trap16:
+ trap 0
+ trap 7
+ trap 4
+ trap 3
+ trap 1
+ trap 6
+ trap 3
+ trap 5
+ .text
+ .global add16
+add16:
+ add ip,ip,ip
+ add r3,r3,r3
+ add r0,r0,r0
+ add fp,fp,fp
+ add sp,sp,sp
+ add sp,r2,lr
+ add r0,r2,r1
+ add ip,fp,fp
+ .text
+ .global add
+add:
+ add ip,ip,ip
+ add r59,r59,r59
+ add r28,r28,r28
+ add r27,r27,r27
+ add sp,sp,sp
+ add r56,r10,r16
+ add r36,r25,r34
+ add r2,r49,r17
+ .text
+ .global sub16
+sub16:
+ sub ip,ip,ip
+ sub r3,r3,r3
+ sub r0,r0,r0
+ sub fp,fp,fp
+ sub sp,sp,sp
+ sub r2,ip,lr
+ sub lr,lr,r0
+ sub r3,r3,r3
+ .text
+ .global sub
+sub:
+ sub ip,ip,ip
+ sub r59,r59,r59
+ sub r28,r28,r28
+ sub r27,r27,r27
+ sub sp,sp,sp
+ sub ip,lr,r20
+ sub r48,r22,r47
+ sub r19,r48,r13
+ .text
+ .global and16
+and16:
+ and ip,ip,ip
+ and r3,r3,r3
+ and r0,r0,r0
+ and fp,fp,fp
+ and sp,sp,sp
+ and fp,sp,r3
+ and r3,r3,r3
+ and ip,sp,sp
+ .text
+ .global and
+and:
+ and ip,ip,ip
+ and r59,r59,r59
+ and r28,r28,r28
+ and r27,r27,r27
+ and sp,sp,sp
+ and r52,ip,r46
+ and r44,r40,r44
+ and r24,r58,r31
+ .text
+ .global orr16
+orr16:
+ orr ip,ip,ip
+ orr r3,r3,r3
+ orr r0,r0,r0
+ orr fp,fp,fp
+ orr sp,sp,sp
+ orr lr,r1,sp
+ orr r3,lr,lr
+ orr r2,r3,r2
+ .text
+ .global orr
+orr:
+ orr ip,ip,ip
+ orr r59,r59,r59
+ orr r28,r28,r28
+ orr r27,r27,r27
+ orr sp,sp,sp
+ orr r52,r5,r59
+ orr r15,r32,r43
+ orr r56,r29,r44
+ .text
+ .global eor16
+eor16:
+ eor ip,ip,ip
+ eor r3,r3,r3
+ eor r0,r0,r0
+ eor fp,fp,fp
+ eor sp,sp,sp
+ eor ip,r3,r2
+ eor r3,sp,r2
+ eor fp,sp,r2
+ .text
+ .global eor
+eor:
+ eor ip,ip,ip
+ eor r59,r59,r59
+ eor r28,r28,r28
+ eor r27,r27,r27
+ eor sp,sp,sp
+ eor r17,r56,r29
+ eor sp,r41,r27
+ eor r11,r10,r43
+ .text
+ .global asr16
+asr16:
+ asr ip,ip,ip
+ asr r3,r3,r3
+ asr r0,r0,r0
+ asr fp,fp,fp
+ asr sp,sp,sp
+ asr r3,r0,r3
+ asr r3,r1,lr
+ asr r0,fp,sp
+ .text
+ .global asr
+asr:
+ asr ip,ip,ip
+ asr r59,r59,r59
+ asr r28,r28,r28
+ asr r27,r27,r27
+ asr sp,sp,sp
+ asr r34,r9,r25
+ asr r51,r17,r33
+ asr ip,r7,r11
+ .text
+ .global lsr16
+lsr16:
+ lsr ip,ip,ip
+ lsr r3,r3,r3
+ lsr r0,r0,r0
+ lsr fp,fp,fp
+ lsr sp,sp,sp
+ lsr sp,r3,fp
+ lsr fp,r1,lr
+ lsr lr,r2,r2
+ .text
+ .global lsr
+lsr:
+ lsr ip,ip,ip
+ lsr r59,r59,r59
+ lsr r28,r28,r28
+ lsr r27,r27,r27
+ lsr sp,sp,sp
+ lsr r6,r25,r19
+ lsr r12,r54,r32
+ lsr r13,sp,ip
+ .text
+ .global lsl16
+lsl16:
+ lsl ip,ip,ip
+ lsl r3,r3,r3
+ lsl r0,r0,r0
+ lsl fp,fp,fp
+ lsl sp,sp,sp
+ lsl ip,ip,ip
+ lsl lr,r1,ip
+ lsl lr,sp,r3
+ .text
+ .global lsl
+lsl:
+ lsl ip,ip,ip
+ lsl r59,r59,r59
+ lsl r28,r28,r28
+ lsl r27,r27,r27
+ lsl sp,sp,sp
+ lsl r36,r43,r15
+ lsl r34,r39,r37
+ lsl r23,r33,r29
+ .text
+ .global addi16
+addi16:
+ add ip,ip,0
+ add r3,r3,7
+ add r0,r0,4
+ add fp,fp,3
+ add sp,sp,1
+ add r3,r1,1
+ add r1,fp,3
+ add r0,fp,7
+ .text
+ .global addi
+addi:
+ add ip,ip,0
+ add r59,r59,1023
+ add r28,r28,047
+ add r27,r27,1023
+ add sp,sp,1
+ add r49,r28,165
+ add r31,r2,623
+ add r16,r9,945
+ .text
+ .global subi16
+subi16:
+ sub ip,ip,0
+ sub r3,r3,7
+ sub r0,r0,4
+ sub fp,fp,3
+ sub sp,sp,1
+ sub ip,r3,2
+ sub lr,r3,4
+ sub ip,r2,1
+ .text
+ .global subi
+subi:
+ sub ip,ip,0
+ sub r59,r59,-2047
+ sub r28,r28,1023
+ sub r27,r27,1022
+ sub sp,sp,1
+ sub r51,r6,836
+ sub r47,r40,772
+ sub r55,r4,488
+ .text
+ .global lsri16
+lsri16:
+ lsr ip,ip,0
+ lsr r3,r3,31
+ lsr r0,r0,16
+ lsr fp,fp,15
+ lsr sp,sp,1
+ lsr r0,r3,6
+ lsr r1,r2,8
+ lsr fp,lr,14
+ .text
+ .global lsri32
+lsri32:
+ lsr ip,ip,0
+ lsr r59,r59,31
+ lsr r28,r28,16
+ lsr r27,r27,15
+ lsr sp,sp,1
+ lsr r30,r48,19
+ lsr r43,r7,23
+ lsr r28,r2,28
+ .text
+ .global lsli16
+lsli16:
+ lsl ip,ip,0
+ lsl r3,r3,31
+ lsl r0,r0,16
+ lsl fp,fp,15
+ lsl sp,sp,1
+ lsl r2,r3,11
+ lsl lr,r2,6
+ lsl r0,r2,16
+ .text
+ .global lsli32
+lsli32:
+ lsl ip,ip,0
+ lsl r59,r59,31
+ lsl r28,r28,16
+ lsl r27,r27,15
+ lsl sp,sp,1
+ lsl r56,r51,19
+ lsl r17,r39,19
+ lsl r2,r12,12
+ .text
+ .global asri16
+asri16:
+ asr ip,ip,0
+ asr r3,r3,31
+ asr r0,r0,16
+ asr fp,fp,15
+ asr sp,sp,1
+ asr lr,ip,21
+ asr r3,r3,22
+ asr r3,r3,9
+ .text
+ .global asri32
+asri32:
+ asr ip,ip,0
+ asr r59,r59,31
+ asr r28,r28,16
+ asr r27,r27,15
+ asr sp,sp,1
+ asr r52,r46,17
+ asr r23,r56,22
+ asr r21,r46,28
+ .text
+ .global mov8
+mov8:
+ mov ip,0
+ mov r3,255
+ mov r0,128
+ mov fp,127
+ mov sp,1
+ mov lr,91
+ mov r0,77
+ mov fp,10
+ .text
+ .global mov16
+mov16:
+ mov ip,0
+ mov r59,65535
+ mov r28,32768
+ mov r27,32767
+ mov sp,1
+ mov r53,61169
+ mov r18,52207
+ mov r16,36386
+ .text
+ .global faddf16
+faddf16:
+ fadd ip,ip,ip
+ fadd r3,r3,r3
+ fadd r0,r0,r0
+ fadd fp,fp,fp
+ fadd sp,sp,sp
+ fadd sp,ip,r2
+ fadd sp,r2,r2
+ fadd sp,lr,fp
+ .text
+ .global faddf32
+faddf32:
+ fadd ip,ip,ip
+ fadd r59,r59,r59
+ fadd r28,r28,r28
+ fadd r27,r27,r27
+ fadd sp,sp,sp
+ fadd r13,r29,r39
+ fadd r32,r40,r3
+ fadd r40,r29,lr
+ .text
+ .global fsubf16
+fsubf16:
+ fsub ip,ip,ip
+ fsub r3,r3,r3
+ fsub r0,r0,r0
+ fsub fp,fp,fp
+ fsub sp,sp,sp
+ fsub r2,lr,sp
+ fsub r3,r1,ip
+ fsub r3,ip,r2
+ .text
+ .global fsubf32
+fsubf32:
+ fsub ip,ip,ip
+ fsub r59,r59,r59
+ fsub r28,r28,r28
+ fsub r27,r27,r27
+ fsub sp,sp,sp
+ fsub r1,r56,r11
+ fsub r3,r22,r15
+ fsub r6,r48,r45
+ .text
+ .global fmulf16
+fmulf16:
+ fmul ip,ip,ip
+ fmul r3,r3,r3
+ fmul r0,r0,r0
+ fmul fp,fp,fp
+ fmul sp,sp,sp
+ fmul r3,ip,fp
+ fmul lr,r1,r2
+ fmul sp,lr,lr
+ .text
+ .global fmulf32
+fmulf32:
+ fmul ip,ip,ip
+ fmul r59,r59,r59
+ fmul r28,r28,r28
+ fmul r27,r27,r27
+ fmul sp,sp,sp
+ fmul r58,r23,r51
+ fmul r22,r2,r47
+ fmul r46,r14,r10
+ .text
+ .global fmaddf16
+fmaddf16:
+ fmadd ip,ip,ip
+ fmadd r3,r3,r3
+ fmadd r0,r0,r0
+ fmadd fp,fp,fp
+ fmadd sp,sp,sp
+ fmadd sp,r1,r3
+ fmadd r3,r3,r0
+ fmadd r2,ip,ip
+ .text
+ .global fmaddf32
+fmaddf32:
+ fmadd ip,ip,ip
+ fmadd r59,r59,r59
+ fmadd r28,r28,r28
+ fmadd r27,r27,r27
+ fmadd sp,sp,sp
+ fmadd r28,r54,r32
+ fmadd r12,r2,fp
+ fmadd fp,r40,r22
+ .text
+ .global fmsubf16
+fmsubf16:
+ fmsub ip,ip,ip
+ fmsub r3,r3,r3
+ fmsub r0,r0,r0
+ fmsub fp,fp,fp
+ fmsub sp,sp,sp
+ fmsub sp,fp,r1
+ fmsub r1,fp,sp
+ fmsub r0,r3,r0
+ .text
+ .global fmsubf32
+fmsubf32:
+ fmsub ip,ip,ip
+ fmsub r59,r59,r59
+ fmsub r28,r28,r28
+ fmsub r27,r27,r27
+ fmsub sp,sp,sp
+ fmsub r42,r20,r9
+ fmsub r22,r24,r42
+ fmsub r15,r22,r19
+
+;; add some negative displacement ld/store
+ ldr r1,[r2,-12]
+ strh r22,[r30,-2047]
+ ldrd r12,[r14,2047]
+
+;; add bitr
+ bitr r1,r0
+ bitr r31,r15
--- /dev/null
+ .text
+ .global postmod
+postmod:
+ ldrd r0,[r1],r2 ; tricky because r1 is implied as destination
+
+ strb r12,[r12],r3 ; stores are okay
+ strd r12,[r13],r3
+
+ ldr r0,[r0],r0 ; ERROR
+
+ ldr r0,[r0,+128] ; ok
+ ldrd r12,[r13],-256 ; ERROR
+ ldrb r12,[r12],20 ; ERROR
+ strd r12,[r13],-256 ; ok
--- /dev/null
+#as:
+#objdump: -dr
+#name: badrelax
+
+.*\.o: file format elf32-epiphany
+
+
+Disassembly of section \.text:
+
+00000000 \<xxx\>:
+ 0: 01f0 bl 2 \<xxx\+0x2\>
+ 2: 013b 0000 sub r0,r0,2
--- /dev/null
+ .text
+ .global xxx
+xxx:
+ bl 1f
+1: sub r0,r0,1b-xxx
--- /dev/null
+#as:
+#objdump: -dr
+#name: branch_lit
+
+.*.o: file format elf32-epiphany
+
+
+Disassembly of section \.text:
+
+00000000 \<\.text\>:
+ 0: 8008 0000 beq 0x100
--- /dev/null
+#as:
+#objdump: -dr
+#name: regression
+
+.*\.o: file format elf32-epiphany
+
+
+Disassembly of section \.text:
+
+00000000 \<START\>:
+ 0: 000b 0802 mov r0,0x8000
+ 4: 0056 lsl r0,r0,0x2
+ 6: c0c3 mov r6,0x6
+ 8: 6063 mov r3,0x3
+ a: ff1f fc0a add.l r63,r63,r6
+ e: fd1f fc0a add.l r63,r63,r2
+ 12: dc0b e072 mov r62,0x7e0
+ 16: ff3f ff8a sub.l r63,r63,r62
+ 1a: 0300 beq 20 \<BRANCH1\>
+ 1c: 0023 mov r0,0x1
+ 1e: 0fe2 trap 0x3
+
+00000020 \<BRANCH1\>:
+ 20: 0900 beq 32 \<BRANCH2\>
+ 22: 0023 mov r0,0x1
+ 24: 0fe2 trap 0x3
+ 26: 0023 mov r0,0x1
+ 28: 0fe2 trap 0x3
+ 2a: 0023 mov r0,0x1
+ 2c: 0fe2 trap 0x3
+ 2e: 0023 mov r0,0x1
+ 30: 0fe2 trap 0x3
+
+00000032 \<BRANCH2\>:
+ 32: 1c10 bne 6a \<FAIL_BRANCH\>
+
+00000034 \<BRANCH3\>:
+ 34: 1b60 bgt 6a \<FAIL_BRANCH\>
+
+00000036 \<BRANCH4\>:
+ 36: 0370 bgte 3c \<BRANCH5\>
+ 38: 0023 mov r0,0x1
+ 3a: 0fe2 trap 0x3
+
+0000003c \<BRANCH5\>:
+ 3c: 0390 blte 42 \<BRANCH6\>
+ 3e: 0023 mov r0,0x1
+ 40: 0fe2 trap 0x3
+
+00000042 \<BRANCH6\>:
+ 42: 1480 blt 6a \<FAIL_BRANCH\>
+
+00000044 \<BRANCH8\>:
+ 44: efe8 0000 b 222 \<LONGJUMP\>
+ 48: 0023 mov r0,0x1
+ 4a: 0fe2 trap 0x3
+
+0000004c \<RETURN\>:
+ 4c: edf8 0000 bl 226 \<FUNCTION\>
+ 50: e00b e002 mov r63,0x0
+ 50: R_EPIPHANY_LOW \.text\+0x5c
+ 54: 1d4f 1c02 jr r63
+ 58: 0023 mov r0,0x1
+ 5a: 0fe2 trap 0x3
+
+0000005c \<JARLAB\>:
+ 5c: e00b e002 mov r63,0x0
+ 5c: R_EPIPHANY_LOW \.text\+0x226
+ 60: 1d5f 1c02 jalr r63
+ 64: 05e0 b 6e \<NEXT\>
+ 66: 0023 mov r0,0x1
+ 68: 0fe2 trap 0x3
+
+0000006a \<FAIL_BRANCH\>:
+ 6a: 0023 mov r0,0x1
+ 6c: 0fe2 trap 0x3
+
+0000006e \<NEXT\>:
+ 6e: 8014 strb r4,\[r0\]
+ 70: e00c e000 ldrb r63,\[r0\]
+ 74: fe3f fc0a sub.l r63,r63,r4
+ 78: 0300 beq 7e \<STOREB\>
+ 7a: 0023 mov r0,0x1
+ 7c: 0fe2 trap 0x3
+
+0000007e \<STOREB\>:
+ 7e: a39c 0001 strb.l r5,\[r0,\+0xf\]
+ 82: e38c e001 ldrb.l r63,\[r0,\+0xf\]
+ 86: febf fc0a sub.l r63,r63,r5
+ 8a: 0300 beq 90 \<STORES\>
+ 8c: 0023 mov r0,0x1
+ 8e: 0fe2 trap 0x3
+
+00000090 \<STORES\>:
+ 90: 8034 strh r4,\[r0\]
+ 92: e02c e000 ldrh r63,\[r0\]
+ 96: fe3f fc0a sub.l r63,r63,r4
+ 9a: 0300 beq a0 \<STORES2\>
+ 9c: 0023 mov r0,0x1
+ 9e: 0fe2 trap 0x3
+
+000000a0 \<STORES2\>:
+ a0: a33c 0001 strh.l r5,\[r0,\+0xe\]
+ a4: e32c e001 ldrh.l r63,\[r0,\+0xe\]
+ a8: febf fc0a sub.l r63,r63,r5
+ ac: 0300 beq b2 \<STORE\>
+ ae: 0023 mov r0,0x1
+ b0: 0fe2 trap 0x3
+
+000000b2 \<STORE\>:
+ b2: 8054 str r4,\[r0\]
+ b4: e04c e000 ldr r63,\[r0\]
+ b8: fe3f fc0a sub.l r63,r63,r4
+ bc: 0300 beq c2 \<STORE2\>
+ be: 0023 mov r0,0x1
+ c0: 0fe2 trap 0x3
+
+000000c2 \<STORE2\>:
+ c2: a25c 0001 str.l r5,\[r0,\+0xc\]
+ c6: e24c e001 ldr.l r63,\[r0,\+0xc\]
+ ca: febf fc0a sub.l r63,r63,r5
+ ce: 0300 beq d4 \<STOREBI\>
+ d0: 0023 mov r0,0x1
+ d2: 0fe2 trap 0x3
+
+000000d4 \<STOREBI\>:
+ d4: 8211 strb r4,\[r0,r4\]
+ d6: e209 e000 ldrb.l r63,\[r0,\+r4\]
+ da: fe3f fc0a sub.l r63,r63,r4
+ de: 0300 beq e4 \<STORESI\>
+ e0: 0023 mov r0,0x1
+ e2: 0fe2 trap 0x3
+
+000000e4 \<STORESI\>:
+ e4: a231 strh r5,\[r0,r4\]
+ e6: e229 e000 ldrh.l r63,\[r0,\+r4\]
+ ea: febf fc0a sub.l r63,r63,r5
+ ee: 0300 beq f4 \<STOREI\>
+ f0: 0023 mov r0,0x1
+ f2: 0fe2 trap 0x3
+
+000000f4 \<STOREI\>:
+ f4: c251 str r6,\[r0,r4\]
+ f6: e249 e000 ldr.l r63,\[r0,\+r4\]
+ fa: ff3f fc0a sub.l r63,r63,r6
+ fe: 0300 beq 104 \<PMB\>
+ 100: 0023 mov r0,0x1
+ 102: 0fe2 trap 0x3
+
+00000104 \<PMB\>:
+ 104: 8215 strb r4,\[r0\],r4
+ 106: 023b 0000 sub r0,r0,4
+ 10a: e20d e000 ldrb.l r63,\[r0\],\+r4
+ 10e: 023b 0000 sub r0,r0,4
+ 112: fe3f fc0a sub.l r63,r63,r4
+ 116: 0300 beq 11c \<PMS\>
+ 118: 0023 mov r0,0x1
+ 11a: 0fe2 trap 0x3
+
+0000011c \<PMS\>:
+ 11c: a235 strh r5,\[r0\],r4
+ 11e: 023b 0000 sub r0,r0,4
+ 122: e22d e000 ldrh.l r63,\[r0\],\+r4
+ 126: febf fc0a sub.l r63,r63,r5
+ 12a: 0300 beq 130 \<PM\>
+ 12c: 0023 mov r0,0x1
+ 12e: 0fe2 trap 0x3
+
+00000130 \<PM\>:
+ 130: 023b 0000 sub r0,r0,4
+ 134: c255 str r6,\[r0\],r4
+ 136: 023b 0000 sub r0,r0,4
+ 13a: e24d e000 ldr.l r63,\[r0\],\+r4
+ 13e: 023b 0000 sub r0,r0,4
+ 142: ff3f fc0a sub.l r63,r63,r6
+ 146: 0300 beq 14c \<MOVLAB\>
+ 148: 0023 mov r0,0x1
+ 14a: 0fe2 trap 0x3
+
+0000014c \<MOVLAB\>:
+ 14c: ffeb e002 mov r63,0xff
+ 150: 3fe3 mov r1,0xff
+ 152: fcbf fc0a sub.l r63,r63,r1
+ 156: 0300 beq 15c \<ADDLAB\>
+ 158: 0023 mov r0,0x1
+ 15a: 0fe2 trap 0x3
+
+0000015c \<ADDLAB\>:
+ 15c: e99b e000 add r63,r2,3
+ 160: febb fc00 sub r63,r63,5
+ 164: 0300 beq 16a \<SUBLAB\>
+ 166: 0023 mov r0,0x1
+ 168: 0fe2 trap 0x3
+
+0000016a \<SUBLAB\>:
+ 16a: e8bb e000 sub r63,r2,1
+ 16e: fcbb fc00 sub r63,r63,1
+ 172: 0300 beq 178 \<LSRLAB\>
+ 174: 0023 mov r0,0x1
+ 176: 0fe2 trap 0x3
+
+00000178 \<LSRLAB\>:
+ 178: f84f e006 lsr.l r63,r6,0x2
+ 17c: fcbb fc00 sub r63,r63,1
+ 180: 0300 beq 186 \<LSLLAB\>
+ 182: 0023 mov r0,0x1
+ 184: 0fe2 trap 0x3
+
+00000186 \<LSLLAB\>:
+ 186: ec5f e006 lsl.l r63,r3,0x2
+ 18a: fe3b fc01 sub r63,r63,12
+ 18e: 0300 beq 194 \<LSRILAB\>
+ 190: 0023 mov r0,0x1
+ 192: 0fe2 trap 0x3
+
+00000194 \<LSRILAB\>:
+ 194: f94f e00a lsr.l r63,r6,r2
+ 198: fcbb fc00 sub r63,r63,1
+ 19c: 0300 beq 1a2 \<LSLILAB\>
+ 19e: 0023 mov r0,0x1
+ 1a0: 0fe2 trap 0x3
+
+000001a2 \<LSLILAB\>:
+ 1a2: ed2f e00a lsl.l r63,r3,r2
+ 1a6: fe3b fc01 sub r63,r63,12
+ 1aa: 0300 beq 1b0 \<ORRLAB\>
+ 1ac: 0023 mov r0,0x1
+ 1ae: 0fe2 trap 0x3
+
+000001b0 \<ORRLAB\>:
+ 1b0: ae7a orr r5,r3,r4
+ 1b2: f7bb e000 sub r63,r5,7
+ 1b6: 0300 beq 1bc \<ANDLAB\>
+ 1b8: 0023 mov r0,0x1
+ 1ba: 0fe2 trap 0x3
+
+000001bc \<ANDLAB\>:
+ 1bc: ae5a and r5,r3,r4
+ 1be: f43b e000 sub r63,r5,0
+ 1c2: 0300 beq 1c8 \<EORLAB\>
+ 1c4: 0023 mov r0,0x1
+ 1c6: 0fe2 trap 0x3
+
+000001c8 \<EORLAB\>:
+ 1c8: ad0a eor r5,r3,r2
+ 1ca: f4bb e000 sub r63,r5,1
+ 1ce: 0300 beq 1d4 \<ADD3LAB\>
+ 1d0: 0023 mov r0,0x1
+ 1d2: 0fe2 trap 0x3
+
+000001d4 \<ADD3LAB\>:
+ 1d4: e99f e00a add.l r63,r2,r3
+ 1d8: febb fc00 sub r63,r63,5
+ 1dc: 0300 beq 1e2 \<SUB3LAB\>
+ 1de: 0023 mov r0,0x1
+ 1e0: 0fe2 trap 0x3
+
+000001e2 \<SUB3LAB\>:
+ 1e2: fa3f e00a sub.l r63,r6,r4
+ 1e6: fd3b fc00 sub r63,r63,2
+ 1ea: 0300 beq 1f0 \<MOVRLAB\>
+ 1ec: 0023 mov r0,0x1
+ 1ee: 0fe2 trap 0x3
+
+000001f0 \<MOVRLAB\>:
+ 1f0: e8ef e002 mov.l r63,r2
+ 1f4: fd3b fc00 sub r63,r63,2
+ 1f8: 0b00 beq 20e \<NOPLAB\>
+ 1fa: 0023 mov r0,0x1
+ 1fc: 0fe2 trap 0x3
+
+000001fe \<MOVTFLAB\>:
+ 1fe: 0502 movts status,r0
+ 200: e51f e002 movfs.l r63,status
+ 204: fc3f fc0a sub.l r63,r63,r0
+ 208: fb00 beq 1fe \<MOVTFLAB\>
+ 20a: 0023 mov r0,0x1
+ 20c: 0fe2 trap 0x3
+
+0000020e \<NOPLAB\>:
+ 20e: 01a2 nop
+ 210: 01a2 nop
+ 212: 01a2 nop
+ 214: 01a2 nop
+
+00000216 \<PASSED\>:
+ 216: 0003 mov r0,0x0
+ 218: 0fe2 trap 0x3
+ 21a: 01b2 idle
+
+0000021c \<FAILED\>:
+ 21c: 0023 mov r0,0x1
+ 21e: 0fe2 trap 0x3
+ 220: 01b2 idle
+
+00000222 \<LONGJUMP\>:
+ 222: 15e8 ffff b 4c \<RETURN\>
+
+00000226 \<FUNCTION\>:
+ 226: 194f 0402 rts
--- /dev/null
+;; -*-asm-*-
+
+ TABLE=0x8000
+ RZ=r63
+
+ .macro FAIL
+ mov r0,#1
+ trap 3
+ .endm
+
+ .macro PASS
+ mov r0,#0
+ trap 3
+ .endm
+
+
+ .macro VERIFY ra,rb,ref,label
+ sub \ra,\rb,\ref
+ beq \label
+ FAIL
+ .endm
+
+
+/*****************************************/
+/*INITIALIZING REGISTERS */
+/*****************************************/
+/*Check that sum is correct*/
+START: MOV R0, #TABLE ; //Setting R0 to TABLE
+ LSL R0,R0,#2 ; //Create 00020000
+
+ ;; Load r1.63 with 1..63
+ .irpc num,63
+ mov r\num,#\num
+ .endr
+
+
+ ;; Sum the registers
+ .irpc num,62
+ add r63,r63,r\num
+ .endr
+
+ mov r62,#2016 ;//Correct sum of 1..63 = 63*32 + 63
+ VERIFY r63,r63,R62,BRANCH1;//CHECK SUM
+
+
+/*****************************************/
+/*BRANCHING */
+/*****************************************/
+//Check that all condition codes work
+BRANCH1: BEQ BRANCH2 ; //taken
+ FAIL ;
+ FAIL ;
+ FAIL ;
+ FAIL ;
+BRANCH2: BNE FAIL_BRANCH ; //not taken
+BRANCH3: BGT FAIL_BRANCH ; //not taken
+BRANCH4: BGTE BRANCH5 ; //taken
+ FAIL ;
+BRANCH5: BLTE BRANCH6 ; //taken
+ FAIL ;
+BRANCH6: BLT FAIL_BRANCH ; //not taken
+BRANCH8: B LONGJUMP ; //taken
+ FAIL ;
+RETURN: bl FUNCTION ; //jump to subroutine
+ MOV R63,JARLAB ;//REGISTER JUMP
+ JR R63 ;
+ FAIL ;
+JARLAB: MOV R63,FUNCTION ; //REGISTER CALL
+ JALR R63 ; //16 bit
+ B NEXT ; //jump over fail
+ FAIL ;
+
+FAIL_BRANCH: FAIL ; //fail branch
+
+/*****************************************/
+/*LOAD-STORE DISPLACEMENT */
+/*****************************************/
+//Check max displacement value(0xf)
+//Check that offset is correct
+//all load/stores are aligned
+//this gives greater range(2 more bits)
+//offset is shifted by 2x bits
+
+NEXT: STRB R4,[R0,#0x0] ;//Store Byte
+ LDRB R63,[R0,#0x0] ;//Load Byte
+ VERIFY R63,R63,R4,STOREB ;
+
+STOREB: STRB R5,[R0,#0xf] ;//Store Byte
+ LDRB R63,[R0,#0xf] ;//Load Byte
+ VERIFY R63,R63,R5,STORES ;
+
+STORES: STRH R4,[R0,#0x0] ;//Store Short
+ LDRH R63,[R0,#0x0] ;//Load Short
+ VERIFY R63,R63,R4,STORES2 ;
+
+STORES2: STRH R5,[R0,#0xe] ;//Store Short
+ LDRH R63,[R0,#0xe] ;//Load Short
+ VERIFY R63,R63,R5,STORE ;
+
+STORE: STR R4,[R0,#0x0] ;//Store Word
+ LDR R63,[R0,#0x0] ;//Load Word
+ VERIFY R63,R63,R4,STORE2 ;
+
+STORE2: STR R5,[R0,#0xc] ;//Store Word
+ LDR R63,[R0,#0xc] ;//Load Word
+ VERIFY R63,R63,R5,STOREBI ;
+
+
+/*****************************************/
+/*LOAD-STORE INDEX */
+/*****************************************/
+
+STOREBI: STRB R4,[R0,R4] ;//Store Word
+ LDRB R63,[R0,R4] ;//Load Word
+ VERIFY R63,R63,R4,STORESI ;
+
+STORESI: STRH R5,[R0,R4] ;//Store Word
+ LDRH R63,[R0,R4] ;//Load Word
+ VERIFY R63,R63,R5,STOREI ;
+
+STOREI: STR R6,[R0,R4] ;//Store Word
+ LDR R63,[R0,R4] ;//Load Word
+ VERIFY R63,R63,R6,PMB ;
+
+/*****************************************/
+/*LOAD-STORE POSTMODIFY */
+/*****************************************/
+
+PMB: STRB R4,[R0],R4 ;//Store Word
+ SUB R0,R0,#0x4 ;//restoring R0
+ LDRB R63,[R0],R4 ;//Load Word
+ SUB R0,R0,#0x4 ;//restoring R0
+ VERIFY R63,R63,R4,PMS ;
+
+PMS: STRH R5,[R0],R4 ;//Store Word
+ SUB R0,R0,#0x4 ;//restoring R0
+ LDRH R63,[R0],R4 ;//Load Word
+ VERIFY R63,R63,R5,PM ;
+
+PM: SUB R0,R0,#0x4 ;//restoring R0
+ STR R6,[R0],R4 ;//Store Word
+ SUB R0,R0,#0x4 ;//restoring R0
+ LDR R63,[R0],R4 ;//Load Word
+ SUB R0,R0,#0x4 ;//restoring R0
+ VERIFY R63,R63,R6,MOVLAB ;
+
+
+
+/*****************************************/
+/*IMMEDIATE LOAD */
+/*****************************************/
+MOVLAB: MOV R63,#0xFF;
+ MOV R1,#0xFF;
+ VERIFY R63,R63,R1,ADDLAB ;
+
+/*****************************************/
+/*2 REG ADD/SUB PROCESSING */
+/*****************************************/
+ADDLAB: ADD R63,R2,#3; //2+3=5
+ VERIFY R63,R63,#5,SUBLAB ;
+SUBLAB: SUB R63,R2,#1; //2+1=1
+ VERIFY R63,R63,#1,LSRLAB ;
+
+/*****************************************/
+/*SHIFTS */
+/*****************************************/
+//Note ASR does not work
+
+ //Immediates
+LSRLAB: LSR R63,R6,#0x2 ; //6>>2=1
+ VERIFY R63,R63,#1,LSLLAB ;
+LSLLAB: LSL R63,R3,#0x2 ; //3<<2=12
+ VERIFY R63,R63,#12,LSRILAB ;
+ //Registers
+LSRILAB: LSR R63,R6,R2 ; //6>>2=1
+ VERIFY R63,R63,#1,LSLILAB ;
+LSLILAB: LSL R63,R3,R2 ; //3<<2=12
+ VERIFY R63,R63,#12,ORRLAB ;
+
+
+/*****************************************/
+/*LOGICAL */
+/*****************************************/
+ORRLAB: ORR R5,R3,R4 ; //0x3 | 0x4 -->0x7
+ VERIFY R63,R5,#7,ANDLAB ;
+ANDLAB: AND R5,R3,R4 ; //0x3 & 0x4 -->0
+ VERIFY R63,R5,#0,EORLAB ;
+EORLAB: EOR R5,R3,R2 ; //0x3 ^ 0x2 -->1
+ VERIFY R63,R5,#1,ADD3LAB ;
+
+
+/****************************************/
+/*3-REGISTER ADD/SUB */
+/*****************************************/
+ADD3LAB: ADD R63,R2,R3 ; //3+2=5
+ VERIFY R63,R63,#5,SUB3LAB ;
+SUB3LAB: SUB R63,R6,R4 ; //6-4=2
+ VERIFY R63,R63,#2,MOVRLAB ;
+
+/*****************************************/
+/*MOVE REGISTER */
+/*****************************************/
+MOVRLAB: MOV R63,R2 ;
+ VERIFY R63,R63,#2,NOPLAB ;
+
+/*****************************************/
+/*MOVE TO/FROM SPECIAL REGISTER */
+/*****************************************/
+MOVTFLAB: MOVTS status,R0 ;
+ MOVFS R63,status ;
+ VERIFY R63,R63,R0,MOVTFLAB ;
+
+
+/*****************************************/
+/*NOP */
+/*****************************************/
+NOPLAB: NOP ;
+ NOP ;
+ NOP ;
+ NOP ;
+
+/*****************************************/
+/*PASS INDICATOR */
+/*****************************************/
+PASSED: PASS;
+ IDLE;
+/*****************************************/
+/*FAIL INDICATOR */
+/*****************************************/
+FAILED: FAIL;
+ IDLE;
+
+/*****************************************/
+/*LONG JUMP INDICATOR */
+/*****************************************/
+LONGJUMP: B RETURN; //jump back to next
+/*****************************************/
+/*SUBROUTINE */
+/*****************************************/
+FUNCTION: RTS; //return from subroutine
--- /dev/null
+#as:
+#objdump: -dr
+#name: sample
+.*\.o: file format elf32-epiphany
+
+Disassembly of section \.text:
+
+00000000 \<beq\>:
+ \.\.\.
+
+00000002 \<bne\>:
+ 2: ff10 bne 0 \<beq\>
+
+00000004 \<bgtu\>:
+ 4: fe20 bgtu 0 \<beq\>
+
+00000006 \<bgteu\>:
+ 6: fd30 bgteu 0 \<beq\>
+
+00000008 \<blteu\>:
+ 8: fc40 blteu 0 \<beq\>
+
+0000000a \<bltu\>:
+ a: fb50 bltu 0 \<beq\>
+
+0000000c \<bgt\>:
+ c: fa60 bgt 0 \<beq\>
+
+0000000e \<bgte\>:
+ e: f970 bgte 0 \<beq\>
+
+00000010 \<blt\>:
+ 10: f880 blt 0 \<beq\>
+
+00000012 \<blte\>:
+ 12: f790 blte 0 \<beq\>
+
+00000014 \<bbeq\>:
+ 14: f6a0 bbeq 0 \<beq\>
+
+00000016 \<bbne\>:
+ 16: f5b0 bbne 0 \<beq\>
+
+00000018 \<bblt\>:
+ 18: f4c0 bblt 0 \<beq\>
+
+0000001a \<b\>:
+ 1a: f3e0 b 0 \<beq\>
+
+0000001c \<bl\>:
+ 1c: f2f0 bl 0 \<beq\>
+
+0000001e \<jr\>:
+ 1e: 0542 jr r1
+ 20: 1d4f 0c02 jr r31
+
+00000024 \<jalr\>:
+ 24: 0552 jalr r1
+ 26: 1d5f 0c02 jalr r31
+
+0000002a \<add\>:
+ 2a: 299a add r1,r2,r3
+ 2c: 051f 920a add.l r32,r33,r34
+ 30: 2993 add r1,r2,3
+ 32: 681b 2002 add fp,r2,16
+
+00000036 \<sub\>:
+ 36: 29ba sub r1,r2,r3
+ 38: 053f 920a sub.l r32,r33,r34
+ 3c: 29b3 sub r1,r2,3
+ 3e: 683b 2002 sub fp,r2,16
+
+00000042 \<asr\>:
+ 42: 29ea asr r1,r2,r3
+ 44: 056f 920a asr.l r32,r33,r34
+ 48: 286e asr r1,r2,0x3
+ 4a: 6a0f 200e asr.l fp,r2,0x10
+
+0000004e \<lsr\>:
+ 4e: 29ca lsr r1,r2,r3
+ 50: 054f 920a lsr.l r32,r33,r34
+ 54: 2866 lsr r1,r2,0x3
+ 56: 6a0f 2006 lsr.l fp,r2,0x10
+
+0000005a \<lsl\>:
+ 5a: 29aa lsl r1,r2,r3
+ 5c: 052f 920a lsl.l r32,r33,r34
+ 60: 2876 lsl r1,r2,0x3
+ 62: 6a1f 2006 lsl.l fp,r2,0x10
+
+00000066 \<orr\>:
+ 66: 29fa orr r1,r2,r3
+ 68: 72ff 248a orr.l fp,ip,sp
+
+0000006c \<and\>:
+ 6c: 29da and r1,r2,r3
+ 6e: 72df 248a and.l fp,ip,sp
+
+00000072 \<eor\>:
+ 72: 298a eor r1,r2,r3
+ 74: 728f 248a eor.l fp,ip,sp
+ 78: 0584 ldrb r0,\[r1,0x3\]
+ 7a: 478c 201f ldrb.l sl,\[r1,\+0xff\]
+ 7e: 0501 ldrb r0,\[r1,r2\]
+ 80: 0589 0080 ldrb.l r0,\[r1,\+fp\]
+ 84: 0d05 ldrb r0,\[r3\],r2
+ 86: 528d 2480 ldrb.l sl,\[ip\],\+sp
+ 8a: 05a4 ldrh r0,\[r1,0x3\]
+ 8c: 47ac 201f ldrh.l sl,\[r1,\+0xff\]
+ 90: 0521 ldrh r0,\[r1,r2\]
+ 92: 05a9 0080 ldrh.l r0,\[r1,\+fp\]
+ 96: 0d25 ldrh r0,\[r3\],r2
+ 98: 52ad 2480 ldrh.l sl,\[ip\],\+sp
+ 9c: 05c4 ldr r0,\[r1,0x3\]
+ 9e: 47cc 201f ldr.l sl,\[r1,\+0xff\]
+ a2: 0541 ldr r0,\[r1,r2\]
+ a4: 05c9 0080 ldr.l r0,\[r1,\+fp\]
+ a8: 0d45 ldr r0,\[r3\],r2
+ aa: 52cd 2480 ldr.l sl,\[ip\],\+sp
+ ae: 05e4 ldrd r0,\[r1,0x3\]
+ b0: 47ec 201f ldrd.l sl,\[r1,\+0xff\]
+ b4: 0561 ldrd r0,\[r1,r2\]
+ b6: 05e9 0080 ldrd.l r0,\[r1,\+fp\]
+ ba: 0d65 ldrd r0,\[r3\],r2
+ bc: 52ed 2480 ldrd.l sl,\[ip\],\+sp
+ c0: 0594 strb r0,\[r1,0x3\]
+ c2: 479c 201f strb.l sl,\[r1,\+0xff\]
+ c6: 0511 strb r0,\[r1,r2\]
+ c8: 0599 0080 strb.l r0,\[r1,\+fp\]
+ cc: 0d15 strb r0,\[r3\],r2
+ ce: 529d 2480 strb.l sl,\[ip\],\+sp
+ d2: 05b4 strh r0,\[r1,0x3\]
+ d4: 47bc 201f strh.l sl,\[r1,\+0xff\]
+ d8: 0531 strh r0,\[r1,r2\]
+ da: 05b9 0080 strh.l r0,\[r1,\+fp\]
+ de: 0d35 strh r0,\[r3\],r2
+ e0: 52bd 2480 strh.l sl,\[ip\],\+sp
+ e4: 05d4 str r0,\[r1,0x3\]
+ e6: 47dc 201f str.l sl,\[r1,\+0xff\]
+ ea: 0551 str r0,\[r1,r2\]
+ ec: 05d9 0080 str.l r0,\[r1,\+fp\]
+ f0: 0d55 str r0,\[r3\],r2
+ f2: 52dd 2480 str.l sl,\[ip\],\+sp
+ f6: 05f4 strd r0,\[r1,0x3\]
+ f8: 47fc 201f strd.l sl,\[r1,\+0xff\]
+ fc: 0571 strd r0,\[r1,r2\]
+ fe: 05f9 0080 strd.l r0,\[r1,\+fp\]
+ 102: 0d75 strd r0,\[r3\],r2
+ 104: 52fd 2480 strd.l sl,\[ip\],\+sp
+
+00000108 \<mov\>:
+ 108: dfe3 mov r6,0xff
+ 10a: ffeb 6ff2 mov r31,0xffff
+ 10e: 004b 0102 mov r0,0x1002
+ 112: 2802 moveq r1,r2
+ 114: 700f 2402 moveq.l fp,ip
+ 118: 2812 movne r1,r2
+ 11a: 701f 2402 movne.l fp,ip
+ 11e: 2822 movgtu r1,r2
+ 120: 702f 2402 movgtu.l fp,ip
+ 124: 2832 movgteu r1,r2
+ 126: 703f 2402 movgteu.l fp,ip
+ 12a: 2842 movlteu r1,r2
+ 12c: 704f 2402 movlteu.l fp,ip
+ 130: 2852 movltu r1,r2
+ 132: 705f 2402 movltu.l fp,ip
+ 136: 2862 movgt r1,r2
+ 138: 706f 2402 movgt.l fp,ip
+ 13c: 2872 movgte r1,r2
+ 13e: 707f 2402 movgte.l fp,ip
+ 142: 2882 movlt r1,r2
+ 144: 708f 2402 movlt.l fp,ip
+ 148: 2892 movlte r1,r2
+ 14a: 709f 2402 movlte.l fp,ip
+ 14e: 28a2 movbeq r1,r2
+ 150: 70af 2402 movbeq.l fp,ip
+ 154: 28b2 movbne r1,r2
+ 156: 70bf 2402 movbne.l fp,ip
+ 15a: 28c2 movblt r1,r2
+ 15c: 70cf 2402 movblt.l fp,ip
+ 160: 28d2 movblte r1,r2
+ 162: 70df 2402 movblte.l fp,ip
+ 166: 28e2 mov r1,r2
+ 168: 70ef 2402 mov.l fp,ip
+
+0000016c \<nop\>:
+ 16c: 01a2 nop
+
+0000016e \<idle\>:
+ 16e: 01b2 idle
+
+00000170 \<bkpt\>:
+ 170: 01c2 bkpt
+
+00000172 \<fadd\>:
+ 172: 2987 fadd r1,r2,r3
+ 174: 728f 2487 fadd.l fp,ip,sp
+
+00000178 \<fsub\>:
+ 178: 2997 fsub r1,r2,r3
+ 17a: 729f 2487 fsub.l fp,ip,sp
+
+0000017e \<fmul\>:
+ 17e: 29a7 fmul r1,r2,r3
+ 180: 72af 2487 fmul.l fp,ip,sp
+
+00000184 \<fmadd\>:
+ 184: 29b7 fmadd r1,r2,r3
+ 186: 72bf 2487 fmadd.l fp,ip,sp
+
+0000018a \<fmsub\>:
+ 18a: 29c7 fmsub r1,r2,r3
+ 18c: 72cf 2487 fmsub.l fp,ip,sp
+ 190: 2102 movts config,r1
+ 192: e50f 6002 movts.l status,r31
+ 196: 251f 0402 movfs.l r1,imask
+ 19a: e91f 6002 movfs.l r31,pc
+
+0000019e \<trap\>:
+ 19e: 03e2 trap 0x0
+ 1a0: 01d2 rti
--- /dev/null
+ .data
+foodata: .hword 42
+ .text
+footext:
+ .text
+
+ .macro test nm:req, args:vararg
+\nm: \nm \args
+ .global \nm
+ .endm
+
+;;; Basic Instruction Tests
+1: ; All branches
+ test beq,1b
+ test bne,1b
+ test bgtu,1b
+ test bgteu,1b
+ test blteu,1b
+ test bltu,1b
+ test bgt,1b
+ test bgte,1b
+ test blt,1b
+ test blte,1b
+
+ test bbeq,1b
+ test bbne,1b
+ test bblt,1b
+ test b,1b
+ test bl,1b
+
+;;; jumps
+ test jr,r1
+ jr r31
+
+ test jalr,r1
+ jalr r31
+
+
+ .macro test3i nm:req
+ test \nm,r1,r2,r3
+ \nm r32,r33,r34
+ \nm r1,r2,#3
+ \nm r11,r2,#16
+ .endm
+ test3i add
+ test3i sub
+ test3i asr
+ test3i lsr
+ test3i lsl
+
+ .macro test3 nm:req
+ test \nm,r1,r2,r3
+ \nm r11,r12,r13
+ .endm
+
+ test3 orr
+ test3 and
+ test3 eor
+
+ .macro testmem nm:req
+ \nm r0,[r1,#3]
+ \nm r10,[r1,#255]
+ \nm r0,[r1,r2]
+ \nm r0,[r1,r11]
+ \nm r0,[r3],r2
+ \nm r10,[r12],r13
+ .endm
+
+ testmem ldrb
+ testmem ldrh
+ testmem ldr
+ testmem ldrd
+
+
+ testmem strb
+ testmem strh
+ testmem str
+ testmem strd
+
+ test mov,r6,#255
+ mov r31,#65535
+ mov r0,#4098
+
+ .macro testmov cond:req
+ mov\cond r1,r2
+ mov\cond r11,r12
+ .endm
+
+ testmov eq
+ testmov ne
+ testmov gtu
+ testmov gteu
+ testmov lteu
+ testmov ltu
+ testmov gt
+ testmov gte
+ testmov lt
+ testmov lte
+ testmov beq
+ testmov bne
+ testmov blt
+ testmov blte
+ mov r1,r2
+ mov r11,r12
+
+ test nop
+ test idle
+ test bkpt
+
+ test3 fadd
+ test3 fsub
+ test3 fmul
+ test3 fmadd
+ test3 fmsub
+
+ movts config,r1
+ movts status,r31
+
+ movfs r1,imask
+ movfs r31,pc
+
+ test trap,#0 ; write syscall for simulator.
+ rti ; dummy instruction
+2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
+
+ * dis-asm.h (print_insn_epiphany): Declare.
+
2011-10-21 Ulrich Drepper <drepper@gmail.com>
* obstack.h [!GNUC] (obstack_free): Avoid cast to int.
extern int print_insn_d10v (bfd_vma, disassemble_info *);
extern int print_insn_d30v (bfd_vma, disassemble_info *);
extern int print_insn_dlx (bfd_vma, disassemble_info *);
+extern int print_insn_epiphany (bfd_vma, disassemble_info *);
extern int print_insn_fr30 (bfd_vma, disassemble_info *);
extern int print_insn_frv (bfd_vma, disassemble_info *);
extern int print_insn_h8300 (bfd_vma, disassemble_info *);
+2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
+
+ * epiphany.h: New file.
+ * common.h (EM_ADAPTEVA_EPIPHANY): Define.
+
2011-10-10 Alan Modra <amodra@gmail.com>
* ppc64.h (R_PPC64_TOCSAVE): Add.
#define EM_MICROBLAZE_OLD 0xbaab /* Old MicroBlaze */
+#define EM_ADAPTEVA_EPIPHANY 0x1223 /* Adapteva's Epiphany architecture. */
+
/* See the above comment before you add a new EM_* value here. */
/* Values for e_version. */
--- /dev/null
+/* Adapteva EPIPHANY ELF support for BFD.
+ Copyright (C) 2011 Free Software Foundation, Inc.
+ Contributed by Embecosm on behalf of Adapteva, Inc.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+#ifndef _ELF_EPIPHANY_H
+#define _ELF_EPIPHANY_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations. */
+START_RELOC_NUMBERS (elf_epiphany_reloc_type)
+ RELOC_NUMBER (R_EPIPHANY_NONE, 0)
+
+ /* Absolute address relocations. */
+ RELOC_NUMBER (R_EPIPHANY_8, 1)
+ RELOC_NUMBER (R_EPIPHANY_16, 2)
+ RELOC_NUMBER (R_EPIPHANY_32, 3)
+
+ /* PC-relative relocations. */
+ RELOC_NUMBER (R_EPIPHANY_8_PCREL, 4)
+ RELOC_NUMBER (R_EPIPHANY_16_PCREL,5)
+ RELOC_NUMBER (R_EPIPHANY_32_PCREL,6)
+
+ /* special forms for 8/24 bit branch displacements. */
+ RELOC_NUMBER (R_EPIPHANY_SIMM8, 7)
+ RELOC_NUMBER (R_EPIPHANY_SIMM24, 8)
+
+ /* HIGH and LOW relocations taking part of a 32 bit address and
+ depositing it into the IMM16 field of a destination. */
+ RELOC_NUMBER (R_EPIPHANY_HIGH, 9)
+ RELOC_NUMBER (R_EPIPHANY_LOW,10)
+
+ /* 11 bit signed immediate value. */
+ RELOC_NUMBER (R_EPIPHANY_SIMM11, 11)
+ /* 11 bit magnitude addressing displacement. */
+ RELOC_NUMBER (R_EPIPHANY_IMM11, 12)
+
+ /* 8 bit immediate for MOV.S R,IMM8. */
+ RELOC_NUMBER (R_EPIPHANY_IMM8, 13)
+
+END_RELOC_NUMBERS(R_EPIPHANY_max)
+
+#endif /* _ELF_EPIPHANY_H */
+2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
+
+ * NEWS: Mention addition of Adapteva Epiphany support.
+ * Makefile.am (ALL_EMULATION_SOURCES): Add eelf32epiphany.c .
+ (eelf32epiphany.c): New rule.
+ * configure.tgt: Handle epiphany-*-elf.
+ * emulparams/elf32epiphany.sh: New file.
+ * Makefile.in: Regenerate.
+ * po/ld.pot: Regenerate.
+
2011-10-24 Nick Clifton <nickc@redhat.com>
* po/ja.po: Updated Japanese translation.
eelf32ebmipvxworks.c \
eelf32elmip.c \
eelf32elmipvxworks.c \
+ eelf32epiphany.c \
eelf32fr30.c \
eelf32frv.c \
eelf32frvfd.c \
$(ELF_DEPS) $(srcdir)/emultempl/generic.em $(srcdir)/emultempl/mipself.em \
$(srcdir)/emultempl/vxworks.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32elmipvxworks "$(tdir_elf32elmipvxworks)"
+eelf32epiphany.c: $(srcdir)/emulparams/elf32epiphany.sh \
+ $(ELF_DEPS) ${GEN_DEPENDS}
+ ${GENSCRIPTS} elf32epiphany "$(tdir_epiphany)"
eelf32fr30.c: $(srcdir)/emulparams/elf32fr30.sh \
$(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32fr30 "$(tdir_fr30)"
eelf32ebmipvxworks.c \
eelf32elmip.c \
eelf32elmipvxworks.c \
+ eelf32epiphany.c \
eelf32fr30.c \
eelf32frv.c \
eelf32frvfd.c \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ebmipvxworks.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32elmip.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32elmipvxworks.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32epiphany.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32fr30.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32frv.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32frvfd.Po@am__quote@
$(ELF_DEPS) $(srcdir)/emultempl/generic.em $(srcdir)/emultempl/mipself.em \
$(srcdir)/emultempl/vxworks.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32elmipvxworks "$(tdir_elf32elmipvxworks)"
+eelf32epiphany.c: $(srcdir)/emulparams/elf32epiphany.sh \
+ $(ELF_DEPS) ${GEN_DEPENDS}
+ ${GENSCRIPTS} elf32epiphany "$(tdir_epiphany)"
eelf32fr30.c: $(srcdir)/emulparams/elf32fr30.sh \
$(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32fr30 "$(tdir_fr30)"
-*- text -*-
+* Add support for the Adapteva EPIPHANY architecture.
+
Changes in 2.22:
* --copy-dt-needed-entries is no longer enabled by default. Instead
--no-copy-dt-needed-entries is the default.
* INPUT_SECTION_FLAGS has been added to the linker script language
-to allow selection of input sections by section header section flags.
+ to allow selection of input sections by section header section flags.
* Add support for the Tilera TILEPRO and TILE-Gx architectures.
* Added SORT_BY_INIT_PRIORITY to the linker script language to permit
-sorting sections by numerical value of the GCC init_priority attribute
-encoded in the section name.
+ sorting sections by numerical value of the GCC init_priority attribute
+ encoded in the section name.
Changes in 2.21:
;;
dlx-*-elf*) targ_emul=elf32_dlx
;;
+epiphany-*-elf) targ_emul=elf32epiphany
+ ;;
fido*-*-elf*) targ_emul=m68kelf ;;
fr30-*-*) targ_emul=elf32fr30
;;
--- /dev/null
+TEMPLATE_NAME=elf32
+MACHINE=
+SCRIPT_NAME=elf
+OUTPUT_FORMAT="elf32-epiphany"
+NO_REL_RELOCS=yes
+# See also `include/elf/epiphany.h'
+
+MMR_ADDR=0x00000000
+MMR_LEN=0x100
+
+#RESERVED_ADDR=0x00000100
+#RESERVED_LEN=8128
+
+IVT_ADDR=0x00000000
+IVT_LEN=0x040
+
+# ??? This fails: 'Not enough room for program headers, try linking with -N'
+#TEXT_START_ADDR=0x00000040
+
+#The following two lines would allow small to medium sized programs
+#to run in the first 1 MB.
+#TEXT_START_ADDR=0x00000060
+#EXECUTABLE_SYMBOLS='PROVIDE (___bss_start = __bss_start); PROVIDE (___heap_start = end); PROVIDE (___heap_end = (0x0c0000)); PROVIDE (___stack = (0x0ffff0));'
+
+TEXT_START_ADDR='DEFINED (___text_start) ? ___text_start : 0x80000000'
+EXECUTABLE_SYMBOLS='PROVIDE (___bss_start = __bss_start); PROVIDE (___heap_start = end); PROVIDE (___heap_end = (0x81800000)); PROVIDE (___stack = (0x81fffff0));'
+
+#Smuggle an alignemnt directive in here so that .bss is aligned.
+OTHER_SDATA_SECTIONS='. = ALIGN(8);'
+
+
+ARCH=epiphany
+ENTRY=_start
+EMBEDDED=yes
+ELFSIZE=32
+ALIGNMENT=8
+#MAXPAGESIZE=8192
+MAXPAGESIZE=1
+WRITABLE_RODATA=
+#OTHER_RELOCATING_SECTIONS=
+#OTHER_READONLY_SECTIONS=
+#OTHER_READWRITE_SECTIONS=
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n"
-"POT-Creation-Date: 2011-06-02 14:30+0100\n"
+"POT-Creation-Date: 2011-10-25 11:20+0100\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n"
msgid "Errors encountered processing file %s"
msgstr ""
-#: emultempl/armcoff.em:192 emultempl/pe.em:1813
+#: emultempl/armcoff.em:192 emultempl/pe.em:1812
msgid "%P: warning: '--thumb-entry %s' is overriding '-e %s'\n"
msgstr ""
-#: emultempl/armcoff.em:197 emultempl/pe.em:1818
+#: emultempl/armcoff.em:197 emultempl/pe.em:1817
msgid "%P: warning: cannot find thumb start symbol %s\n"
msgstr ""
"symbols from auto-imported DLLs.\n"
msgstr ""
-#: emultempl/pe.em:1160 emultempl/pe.em:1367 emultempl/pe.em:1574 ldcref.c:490
-#: ldcref.c:588 ldmain.c:1215 ldmisc.c:290 pe-dll.c:706 pe-dll.c:1257
-#: pe-dll.c:1352
+#: emultempl/pe.em:1160 emultempl/pe.em:1366 emultempl/pe.em:1573 ldcref.c:490
+#: ldcref.c:588 ldmain.c:1158 ldmisc.c:290 pe-dll.c:706 pe-dll.c:1254
+#: pe-dll.c:1349
msgid "%B%F: could not read symbols: %E\n"
msgstr ""
-#: emultempl/pe.em:1243
+#: emultempl/pe.em:1242
msgid "%F%P: cannot perform PE operations on non PE output file '%B'.\n"
msgstr ""
-#: emultempl/pe.em:1617
+#: emultempl/pe.em:1616
#, c-format
msgid "Errors encountered processing file %s\n"
msgstr ""
-#: emultempl/pe.em:1640
+#: emultempl/pe.em:1639
#, c-format
msgid "Errors encountered processing file %s for interworking\n"
msgstr ""
-#: emultempl/pe.em:1702 ldexp.c:581 ldlang.c:3416 ldlang.c:6947 ldlang.c:6978
-#: ldmain.c:1160
+#: emultempl/pe.em:1701 ldexp.c:581 ldlang.c:3458 ldlang.c:6992 ldlang.c:7023
+#: ldmain.c:1103
msgid "%P%F: bfd_link_hash_lookup failed: %E\n"
msgstr ""
msgid "%P: symbol `%T' missing from main hash table\n"
msgstr ""
-#: ldcref.c:650 ldcref.c:657 ldmain.c:1249 ldmain.c:1256
+#: ldcref.c:650 ldcref.c:657 ldmain.c:1192 ldmain.c:1199
msgid "%B%F: could not read relocs: %E\n"
msgstr ""
msgid "%P%F: cannot represent machine `%s'\n"
msgstr ""
-#: ldlang.c:1217 ldlang.c:1259 ldlang.c:3114
+#: ldlang.c:1221 ldlang.c:1263 ldlang.c:3143
msgid "%P%F: can not create hash table: %E\n"
msgstr ""
-#: ldlang.c:1310
+#: ldlang.c:1314
msgid "%P:%S: warning: redeclaration of memory region `%s'\n"
msgstr ""
-#: ldlang.c:1316
+#: ldlang.c:1320
msgid "%P:%S: warning: memory region `%s' not declared\n"
msgstr ""
-#: ldlang.c:1350
+#: ldlang.c:1354
msgid "%F%P:%S: error: alias for default memory region\n"
msgstr ""
-#: ldlang.c:1361
+#: ldlang.c:1365
msgid "%F%P:%S: error: redefinition of memory region alias `%s'\n"
msgstr ""
-#: ldlang.c:1368
+#: ldlang.c:1372
msgid "%F%P:%S: error: memory region `%s' for alias `%s' does not exist\n"
msgstr ""
-#: ldlang.c:1420 ldlang.c:1459
+#: ldlang.c:1424 ldlang.c:1463
msgid "%P%F: failed creating section `%s': %E\n"
msgstr ""
-#: ldlang.c:2021
+#: ldlang.c:2025
#, c-format
msgid ""
"\n"
"\n"
msgstr ""
-#: ldlang.c:2029
+#: ldlang.c:2033
msgid ""
"\n"
"Memory Configuration\n"
"\n"
msgstr ""
-#: ldlang.c:2031
+#: ldlang.c:2035
msgid "Name"
msgstr ""
-#: ldlang.c:2031
+#: ldlang.c:2035
msgid "Origin"
msgstr ""
-#: ldlang.c:2031
+#: ldlang.c:2035
msgid "Length"
msgstr ""
-#: ldlang.c:2031
+#: ldlang.c:2035
msgid "Attributes"
msgstr ""
-#: ldlang.c:2071
+#: ldlang.c:2075
#, c-format
msgid ""
"\n"
"\n"
msgstr ""
-#: ldlang.c:2140
+#: ldlang.c:2141
msgid "%P%F: Illegal use of `%s' section\n"
msgstr ""
-#: ldlang.c:2149
+#: ldlang.c:2150
msgid "%P%F: output format %s cannot represent section called %s\n"
msgstr ""
-#: ldlang.c:2702
+#: ldlang.c:2728
msgid "%B: file not recognized: %E\n"
msgstr ""
-#: ldlang.c:2703
+#: ldlang.c:2729
msgid "%B: matching formats:"
msgstr ""
-#: ldlang.c:2710
+#: ldlang.c:2736
msgid "%F%B: file not recognized: %E\n"
msgstr ""
-#: ldlang.c:2781
+#: ldlang.c:2810
msgid "%F%B: member %B in archive is not an object\n"
msgstr ""
-#: ldlang.c:2796 ldlang.c:2810
+#: ldlang.c:2825 ldlang.c:2839
msgid "%F%B: could not read symbols: %E\n"
msgstr ""
-#: ldlang.c:3084
+#: ldlang.c:3113
msgid ""
"%P: warning: could not find any targets that match endianness requirement\n"
msgstr ""
-#: ldlang.c:3098
+#: ldlang.c:3127
msgid "%P%F: target %s not found\n"
msgstr ""
-#: ldlang.c:3100
+#: ldlang.c:3129
msgid "%P%F: cannot open output file %s: %E\n"
msgstr ""
-#: ldlang.c:3106
+#: ldlang.c:3135
msgid "%P%F:%s: can not make object file: %E\n"
msgstr ""
-#: ldlang.c:3110
+#: ldlang.c:3139
msgid "%P%F:%s: can not set architecture: %E\n"
msgstr ""
-#: ldlang.c:3267
+#: ldlang.c:3309
msgid "%P: warning: %s contains output sections; did you forget -T?\n"
msgstr ""
-#: ldlang.c:3308
+#: ldlang.c:3350
msgid "%P%F: bfd_hash_lookup failed creating symbol %s\n"
msgstr ""
-#: ldlang.c:3326
+#: ldlang.c:3368
msgid "%P%F: bfd_hash_allocate failed creating symbol %s\n"
msgstr ""
-#: ldlang.c:3722
+#: ldlang.c:3764
msgid "%F%P: %s not found for insert\n"
msgstr ""
-#: ldlang.c:3937
+#: ldlang.c:3979
msgid " load address 0x%V"
msgstr ""
-#: ldlang.c:4212
+#: ldlang.c:4254
msgid "%W (size before relaxing)\n"
msgstr ""
-#: ldlang.c:4303
+#: ldlang.c:4345
#, c-format
msgid "Address of section %s set to "
msgstr ""
-#: ldlang.c:4456
+#: ldlang.c:4498
#, c-format
msgid "Fail with %d\n"
msgstr ""
-#: ldlang.c:4743
+#: ldlang.c:4785
msgid ""
"%X%P: section %s loaded at [%V,%V] overlaps section %s loaded at [%V,%V]\n"
msgstr ""
-#: ldlang.c:4759
+#: ldlang.c:4801
msgid "%X%P: region `%s' overflowed by %ld bytes\n"
msgstr ""
-#: ldlang.c:4782
+#: ldlang.c:4824
msgid "%X%P: address 0x%v of %B section `%s' is not within region `%s'\n"
msgstr ""
-#: ldlang.c:4793
+#: ldlang.c:4835
msgid "%X%P: %B section `%s' will not fit in region `%s'\n"
msgstr ""
-#: ldlang.c:4850
+#: ldlang.c:4892
#, c-format
msgid ""
"%F%S: non constant or forward reference address expression for section %s\n"
msgstr ""
-#: ldlang.c:4875
+#: ldlang.c:4917
msgid "%P%X: Internal error on COFF shared library section %s\n"
msgstr ""
-#: ldlang.c:4932
+#: ldlang.c:4974
msgid "%P%F: error: no memory region specified for loadable section `%s'\n"
msgstr ""
-#: ldlang.c:4937
+#: ldlang.c:4979
msgid "%P: warning: no memory region specified for loadable section `%s'\n"
msgstr ""
-#: ldlang.c:4959
+#: ldlang.c:5001
msgid "%P: warning: changing start of section %s by %lu bytes\n"
msgstr ""
-#: ldlang.c:5036
+#: ldlang.c:5078
msgid "%P: warning: dot moved backwards before `%s'\n"
msgstr ""
-#: ldlang.c:5202
+#: ldlang.c:5244
msgid "%P%F: can't relax section: %E\n"
msgstr ""
-#: ldlang.c:5531
+#: ldlang.c:5573
msgid "%F%P: invalid data statement\n"
msgstr ""
-#: ldlang.c:5564
+#: ldlang.c:5606
msgid "%F%P: invalid reloc statement\n"
msgstr ""
-#: ldlang.c:5683
+#: ldlang.c:5725
msgid "%P%F: gc-sections requires either an entry or an undefined symbol\n"
msgstr ""
-#: ldlang.c:5708
+#: ldlang.c:5750
msgid "%P%F:%s: can't set start address\n"
msgstr ""
-#: ldlang.c:5721 ldlang.c:5740
+#: ldlang.c:5763 ldlang.c:5782
msgid "%P%F: can't set start address\n"
msgstr ""
-#: ldlang.c:5733
+#: ldlang.c:5775
msgid "%P: warning: cannot find entry symbol %s; defaulting to %V\n"
msgstr ""
-#: ldlang.c:5745
+#: ldlang.c:5787
msgid "%P: warning: cannot find entry symbol %s; not setting start address\n"
msgstr ""
-#: ldlang.c:5800
+#: ldlang.c:5842
msgid ""
"%P%F: Relocatable linking with relocations from format %s (%B) to format %s "
"(%B) is not supported\n"
msgstr ""
-#: ldlang.c:5810
+#: ldlang.c:5852
msgid ""
"%P%X: %s architecture of input file `%B' is incompatible with %s output\n"
msgstr ""
-#: ldlang.c:5832
+#: ldlang.c:5874
msgid "%P%X: failed to merge target specific data of file %B\n"
msgstr ""
-#: ldlang.c:5903
+#: ldlang.c:5945
msgid "%P%F: Could not define common symbol `%T': %E\n"
msgstr ""
-#: ldlang.c:5915
+#: ldlang.c:5957
msgid ""
"\n"
"Allocating common symbols\n"
msgstr ""
-#: ldlang.c:5916
+#: ldlang.c:5958
msgid ""
"Common symbol size file\n"
"\n"
msgstr ""
-#: ldlang.c:6062
+#: ldlang.c:6104
msgid "%P%F: invalid syntax in flags\n"
msgstr ""
-#: ldlang.c:6524
+#: ldlang.c:6566
msgid "%P%F: Failed to create hash table\n"
msgstr ""
-#: ldlang.c:6547
+#: ldlang.c:6589
msgid "%P%F: %s: plugin reported error after all symbols read\n"
msgstr ""
-#: ldlang.c:6860
+#: ldlang.c:6905
msgid "%P%F: multiple STARTUP files\n"
msgstr ""
-#: ldlang.c:6906
+#: ldlang.c:6951
msgid "%X%P:%S: section has both a load address and a load region\n"
msgstr ""
-#: ldlang.c:7093
+#: ldlang.c:7138
msgid ""
"%X%P:%S: PHDRS and FILEHDR are not supported when prior PT_LOAD headers lack "
"them\n"
msgstr ""
-#: ldlang.c:7165
+#: ldlang.c:7210
msgid "%F%P: no sections assigned to phdrs\n"
msgstr ""
-#: ldlang.c:7203
+#: ldlang.c:7248
msgid "%F%P: bfd_record_phdr failed: %E\n"
msgstr ""
-#: ldlang.c:7223
+#: ldlang.c:7268
msgid "%X%P: section `%s' assigned to non-existent phdr `%s'\n"
msgstr ""
-#: ldlang.c:7636
+#: ldlang.c:7677
msgid "%X%P: unknown language `%s' in version information\n"
msgstr ""
-#: ldlang.c:7781
+#: ldlang.c:7822
msgid ""
"%X%P: anonymous version tag cannot be combined with other version tags\n"
msgstr ""
-#: ldlang.c:7790
+#: ldlang.c:7831
msgid "%X%P: duplicate version tag `%s'\n"
msgstr ""
-#: ldlang.c:7811 ldlang.c:7820 ldlang.c:7838 ldlang.c:7848
+#: ldlang.c:7852 ldlang.c:7861 ldlang.c:7879 ldlang.c:7889
msgid "%X%P: duplicate expression `%s' in version information\n"
msgstr ""
-#: ldlang.c:7888
+#: ldlang.c:7929
msgid "%X%P: unable to find version dependency `%s'\n"
msgstr ""
-#: ldlang.c:7911
+#: ldlang.c:7952
msgid "%X%P: unable to read .exports section contents\n"
msgstr ""
-#: ldlang.c:8035
+#: ldlang.c:8076
msgid "%X%P: unknown feature `%s'\n"
msgstr ""
msgid "%X%P: can't set BFD default target to `%s': %E\n"
msgstr ""
-#: ldmain.c:307
-msgid "%P%F: -r and -shared may not be used together\n"
-msgstr ""
-
-#: ldmain.c:350
-msgid "%P%F: -F may not be used without -shared\n"
-msgstr ""
-
-#: ldmain.c:352
-msgid "%P%F: -f may not be used without -shared\n"
+#: ldmain.c:303 lexsup.c:1071
+msgid "%P%F: %s: error loading plugin\n"
msgstr ""
-#: ldmain.c:400
+#: ldmain.c:340
msgid "using external linker script:"
msgstr ""
-#: ldmain.c:402
+#: ldmain.c:342
msgid "using internal linker script:"
msgstr ""
-#: ldmain.c:436
+#: ldmain.c:379
msgid "%P%F: no input files\n"
msgstr ""
-#: ldmain.c:440
+#: ldmain.c:383
msgid "%P: mode %s\n"
msgstr ""
-#: ldmain.c:456
+#: ldmain.c:399
msgid "%P%F: cannot open map file %s: %E\n"
msgstr ""
-#: ldmain.c:488
+#: ldmain.c:431
msgid "%P: link errors found, deleting executable `%s'\n"
msgstr ""
-#: ldmain.c:497
+#: ldmain.c:440
msgid "%F%B: final close failed: %E\n"
msgstr ""
-#: ldmain.c:523
+#: ldmain.c:466
msgid "%X%P: unable to open for source of copy `%s'\n"
msgstr ""
-#: ldmain.c:526
+#: ldmain.c:469
msgid "%X%P: unable to open for destination of copy `%s'\n"
msgstr ""
-#: ldmain.c:533
+#: ldmain.c:476
msgid "%P: Error writing file `%s'\n"
msgstr ""
-#: ldmain.c:538 pe-dll.c:1733
+#: ldmain.c:481 pe-dll.c:1739
#, c-format
msgid "%P: Error closing file `%s'\n"
msgstr ""
-#: ldmain.c:555
+#: ldmain.c:498
#, c-format
msgid "%s: total time in link: %ld.%06ld\n"
msgstr ""
-#: ldmain.c:558
+#: ldmain.c:501
#, c-format
msgid "%s: data size %ld\n"
msgstr ""
-#: ldmain.c:642
+#: ldmain.c:585
msgid "%P%F: missing argument to -m\n"
msgstr ""
-#: ldmain.c:690 ldmain.c:710 ldmain.c:742
+#: ldmain.c:633 ldmain.c:653 ldmain.c:685
msgid "%P%F: bfd_hash_table_init failed: %E\n"
msgstr ""
-#: ldmain.c:694 ldmain.c:714
+#: ldmain.c:637 ldmain.c:657
msgid "%P%F: bfd_hash_lookup failed: %E\n"
msgstr ""
-#: ldmain.c:728
+#: ldmain.c:671
msgid "%X%P: error: duplicate retain-symbols-file\n"
msgstr ""
-#: ldmain.c:772
+#: ldmain.c:715
msgid "%P%F: bfd_hash_lookup for insertion failed: %E\n"
msgstr ""
-#: ldmain.c:777
+#: ldmain.c:720
msgid "%P: `-retain-symbols-file' overrides `-s' and `-S'\n"
msgstr ""
-#: ldmain.c:877
+#: ldmain.c:820
#, c-format
msgid ""
"Archive member included because of file (symbol)\n"
"\n"
msgstr ""
-#: ldmain.c:983
+#: ldmain.c:926
msgid "%X%C: multiple definition of `%T'\n"
msgstr ""
-#: ldmain.c:986
+#: ldmain.c:929
msgid "%D: first defined here\n"
msgstr ""
-#: ldmain.c:990
+#: ldmain.c:933
msgid "%P: Disabling relaxation: it will not work with multiple definitions\n"
msgstr ""
-#: ldmain.c:1044
+#: ldmain.c:987
msgid "%B: warning: definition of `%T' overriding common\n"
msgstr ""
-#: ldmain.c:1047
+#: ldmain.c:990
msgid "%B: warning: common is here\n"
msgstr ""
-#: ldmain.c:1054
+#: ldmain.c:997
msgid "%B: warning: common of `%T' overridden by definition\n"
msgstr ""
-#: ldmain.c:1057
+#: ldmain.c:1000
msgid "%B: warning: defined here\n"
msgstr ""
-#: ldmain.c:1064
+#: ldmain.c:1007
msgid "%B: warning: common of `%T' overridden by larger common\n"
msgstr ""
-#: ldmain.c:1067
+#: ldmain.c:1010
msgid "%B: warning: larger common is here\n"
msgstr ""
-#: ldmain.c:1071
+#: ldmain.c:1014
msgid "%B: warning: common of `%T' overriding smaller common\n"
msgstr ""
-#: ldmain.c:1074
+#: ldmain.c:1017
msgid "%B: warning: smaller common is here\n"
msgstr ""
-#: ldmain.c:1078
+#: ldmain.c:1021
msgid "%B: warning: multiple common of `%T'\n"
msgstr ""
-#: ldmain.c:1080
+#: ldmain.c:1023
msgid "%B: warning: previous common is here\n"
msgstr ""
-#: ldmain.c:1100 ldmain.c:1138
+#: ldmain.c:1043 ldmain.c:1081
msgid "%P: warning: global constructor %s used\n"
msgstr ""
-#: ldmain.c:1148
+#: ldmain.c:1091
msgid "%P%F: BFD backend error: BFD_RELOC_CTOR unsupported\n"
msgstr ""
#. We found a reloc for the symbol we are looking for.
-#: ldmain.c:1202 ldmain.c:1204 ldmain.c:1206 ldmain.c:1224 ldmain.c:1269
+#: ldmain.c:1145 ldmain.c:1147 ldmain.c:1149 ldmain.c:1167 ldmain.c:1212
msgid "warning: "
msgstr ""
-#: ldmain.c:1305
+#: ldmain.c:1248
msgid "%F%P: bfd_hash_table_init failed: %E\n"
msgstr ""
-#: ldmain.c:1312
+#: ldmain.c:1255
msgid "%F%P: bfd_hash_lookup failed: %E\n"
msgstr ""
-#: ldmain.c:1333
+#: ldmain.c:1276
msgid "%X%C: undefined reference to `%T'\n"
msgstr ""
-#: ldmain.c:1336
+#: ldmain.c:1279
msgid "%C: warning: undefined reference to `%T'\n"
msgstr ""
-#: ldmain.c:1342
+#: ldmain.c:1285
msgid "%X%D: more undefined references to `%T' follow\n"
msgstr ""
-#: ldmain.c:1345
+#: ldmain.c:1288
msgid "%D: warning: more undefined references to `%T' follow\n"
msgstr ""
-#: ldmain.c:1356
+#: ldmain.c:1299
msgid "%X%B: undefined reference to `%T'\n"
msgstr ""
-#: ldmain.c:1359
+#: ldmain.c:1302
msgid "%B: warning: undefined reference to `%T'\n"
msgstr ""
-#: ldmain.c:1365
+#: ldmain.c:1308
msgid "%X%B: more undefined references to `%T' follow\n"
msgstr ""
-#: ldmain.c:1368
+#: ldmain.c:1311
msgid "%B: warning: more undefined references to `%T' follow\n"
msgstr ""
-#: ldmain.c:1407
+#: ldmain.c:1350
msgid " additional relocation overflows omitted from the output\n"
msgstr ""
-#: ldmain.c:1420
+#: ldmain.c:1363
msgid " relocation truncated to fit: %s against undefined symbol `%T'"
msgstr ""
-#: ldmain.c:1425
+#: ldmain.c:1368
msgid ""
" relocation truncated to fit: %s against symbol `%T' defined in %A section "
"in %B"
msgstr ""
-#: ldmain.c:1437
+#: ldmain.c:1380
msgid " relocation truncated to fit: %s against `%T'"
msgstr ""
-#: ldmain.c:1454
+#: ldmain.c:1397
msgid "%X%H: dangerous relocation: %s\n"
msgstr ""
-#: ldmain.c:1469
+#: ldmain.c:1412
msgid "%X%H: reloc refers to symbol `%T' which is not being output\n"
msgstr ""
msgid "%F%P: final link failed: %E\n"
msgstr ""
-#: lexsup.c:219 lexsup.c:373
+#: lexsup.c:220 lexsup.c:374
msgid "KEYWORD"
msgstr ""
-#: lexsup.c:219
+#: lexsup.c:220
msgid "Shared library control for HP/UX compatibility"
msgstr ""
-#: lexsup.c:222
+#: lexsup.c:223
msgid "ARCH"
msgstr ""
-#: lexsup.c:222
+#: lexsup.c:223
msgid "Set architecture"
msgstr ""
-#: lexsup.c:224 lexsup.c:492
+#: lexsup.c:225 lexsup.c:493
msgid "TARGET"
msgstr ""
-#: lexsup.c:224
+#: lexsup.c:225
msgid "Specify target for following input files"
msgstr ""
-#: lexsup.c:227 lexsup.c:278 lexsup.c:302 lexsup.c:315 lexsup.c:317
-#: lexsup.c:446 lexsup.c:506 lexsup.c:569 lexsup.c:582
+#: lexsup.c:228 lexsup.c:279 lexsup.c:303 lexsup.c:316 lexsup.c:318
+#: lexsup.c:447 lexsup.c:509 lexsup.c:572 lexsup.c:585
msgid "FILE"
msgstr ""
-#: lexsup.c:227
+#: lexsup.c:228
msgid "Read MRI format linker script"
msgstr ""
-#: lexsup.c:229
+#: lexsup.c:230
msgid "Force common symbols to be defined"
msgstr ""
-#: lexsup.c:233 lexsup.c:550 lexsup.c:552 lexsup.c:554 lexsup.c:556
+#: lexsup.c:234 lexsup.c:553 lexsup.c:555 lexsup.c:557 lexsup.c:559
msgid "ADDRESS"
msgstr ""
-#: lexsup.c:233
+#: lexsup.c:234
msgid "Set start address"
msgstr ""
-#: lexsup.c:235
+#: lexsup.c:236
msgid "Export all dynamic symbols"
msgstr ""
-#: lexsup.c:237
+#: lexsup.c:238
msgid "Undo the effect of --export-dynamic"
msgstr ""
-#: lexsup.c:239
+#: lexsup.c:240
msgid "Link big-endian objects"
msgstr ""
-#: lexsup.c:241
+#: lexsup.c:242
msgid "Link little-endian objects"
msgstr ""
-#: lexsup.c:243 lexsup.c:246
+#: lexsup.c:244 lexsup.c:247
msgid "SHLIB"
msgstr ""
-#: lexsup.c:243
+#: lexsup.c:244
msgid "Auxiliary filter for shared object symbol table"
msgstr ""
-#: lexsup.c:246
+#: lexsup.c:247
msgid "Filter for shared object symbol table"
msgstr ""
-#: lexsup.c:249
+#: lexsup.c:250
msgid "Ignored"
msgstr ""
-#: lexsup.c:251
+#: lexsup.c:252
msgid "SIZE"
msgstr ""
-#: lexsup.c:251
+#: lexsup.c:252
msgid "Small data size (if no size, same as --shared)"
msgstr ""
-#: lexsup.c:254
+#: lexsup.c:255
msgid "FILENAME"
msgstr ""
-#: lexsup.c:254
+#: lexsup.c:255
msgid "Set internal name of shared library"
msgstr ""
-#: lexsup.c:256
+#: lexsup.c:257
msgid "PROGRAM"
msgstr ""
-#: lexsup.c:256
+#: lexsup.c:257
msgid "Set PROGRAM as the dynamic linker to use"
msgstr ""
-#: lexsup.c:259
+#: lexsup.c:260
msgid "LIBNAME"
msgstr ""
-#: lexsup.c:259
+#: lexsup.c:260
msgid "Search for library LIBNAME"
msgstr ""
-#: lexsup.c:261
+#: lexsup.c:262
msgid "DIRECTORY"
msgstr ""
-#: lexsup.c:261
+#: lexsup.c:262
msgid "Add DIRECTORY to library search path"
msgstr ""
-#: lexsup.c:264
+#: lexsup.c:265
msgid "Override the default sysroot location"
msgstr ""
-#: lexsup.c:266
+#: lexsup.c:267
msgid "EMULATION"
msgstr ""
-#: lexsup.c:266
+#: lexsup.c:267
msgid "Set emulation"
msgstr ""
-#: lexsup.c:268
+#: lexsup.c:269
msgid "Print map file on standard output"
msgstr ""
-#: lexsup.c:270
+#: lexsup.c:271
msgid "Do not page align data"
msgstr ""
-#: lexsup.c:272
+#: lexsup.c:273
msgid "Do not page align data, do not make text readonly"
msgstr ""
-#: lexsup.c:275
+#: lexsup.c:276
msgid "Page align data, make text readonly"
msgstr ""
-#: lexsup.c:278
+#: lexsup.c:279
msgid "Set output file name"
msgstr ""
-#: lexsup.c:280
+#: lexsup.c:281
msgid "Optimize output file"
msgstr ""
-#: lexsup.c:283
+#: lexsup.c:284
msgid "PLUGIN"
msgstr ""
-#: lexsup.c:283
+#: lexsup.c:284
msgid "Load named plugin"
msgstr ""
-#: lexsup.c:285
+#: lexsup.c:286
msgid "ARG"
msgstr ""
-#: lexsup.c:285
+#: lexsup.c:286
msgid "Send arg to last-loaded plugin"
msgstr ""
-#: lexsup.c:287 lexsup.c:290
+#: lexsup.c:288 lexsup.c:291
msgid "Ignored for GCC LTO option compatibility"
msgstr ""
-#: lexsup.c:294
+#: lexsup.c:295
msgid "Ignored for SVR4 compatibility"
msgstr ""
-#: lexsup.c:298
+#: lexsup.c:299
msgid "Generate relocatable output"
msgstr ""
-#: lexsup.c:302
+#: lexsup.c:303
msgid "Just link symbols (if directory, same as --rpath)"
msgstr ""
-#: lexsup.c:305
+#: lexsup.c:306
msgid "Strip all symbols"
msgstr ""
-#: lexsup.c:307
+#: lexsup.c:308
msgid "Strip debugging symbols"
msgstr ""
-#: lexsup.c:309
+#: lexsup.c:310
msgid "Strip symbols in discarded sections"
msgstr ""
-#: lexsup.c:311
+#: lexsup.c:312
msgid "Do not strip symbols in discarded sections"
msgstr ""
-#: lexsup.c:313
+#: lexsup.c:314
msgid "Trace file opens"
msgstr ""
-#: lexsup.c:315
+#: lexsup.c:316
msgid "Read linker script"
msgstr ""
-#: lexsup.c:317
+#: lexsup.c:318
msgid "Read default linker script"
msgstr ""
-#: lexsup.c:321 lexsup.c:339 lexsup.c:423 lexsup.c:444 lexsup.c:543
-#: lexsup.c:572 lexsup.c:611
+#: lexsup.c:322 lexsup.c:340 lexsup.c:424 lexsup.c:445 lexsup.c:546
+#: lexsup.c:575 lexsup.c:614
msgid "SYMBOL"
msgstr ""
-#: lexsup.c:321
+#: lexsup.c:322
msgid "Start with undefined reference to SYMBOL"
msgstr ""
-#: lexsup.c:324
+#: lexsup.c:325
msgid "[=SECTION]"
msgstr ""
-#: lexsup.c:325
+#: lexsup.c:326
msgid "Don't merge input [SECTION | orphan] sections"
msgstr ""
-#: lexsup.c:327
+#: lexsup.c:328
msgid "Build global constructor/destructor tables"
msgstr ""
-#: lexsup.c:329
+#: lexsup.c:330
msgid "Print version information"
msgstr ""
-#: lexsup.c:331
+#: lexsup.c:332
msgid "Print version and emulation information"
msgstr ""
-#: lexsup.c:333
+#: lexsup.c:334
msgid "Discard all local symbols"
msgstr ""
-#: lexsup.c:335
+#: lexsup.c:336
msgid "Discard temporary local symbols (default)"
msgstr ""
-#: lexsup.c:337
+#: lexsup.c:338
msgid "Don't discard any local symbols"
msgstr ""
-#: lexsup.c:339
+#: lexsup.c:340
msgid "Trace mentions of SYMBOL"
msgstr ""
-#: lexsup.c:341 lexsup.c:508 lexsup.c:510
+#: lexsup.c:342 lexsup.c:511 lexsup.c:513
msgid "PATH"
msgstr ""
-#: lexsup.c:341
+#: lexsup.c:342
msgid "Default search path for Solaris compatibility"
msgstr ""
-#: lexsup.c:344
+#: lexsup.c:345
msgid "Start a group"
msgstr ""
-#: lexsup.c:346
+#: lexsup.c:347
msgid "End a group"
msgstr ""
-#: lexsup.c:350
+#: lexsup.c:351
msgid "Accept input files whose architecture cannot be determined"
msgstr ""
-#: lexsup.c:354
+#: lexsup.c:355
msgid "Reject input files whose architecture is unknown"
msgstr ""
-#: lexsup.c:366
+#: lexsup.c:367
msgid "Only set DT_NEEDED for following dynamic libs if used"
msgstr ""
-#: lexsup.c:369
+#: lexsup.c:370
msgid ""
"Always set DT_NEEDED for dynamic libraries mentioned on\n"
" the command line"
msgstr ""
-#: lexsup.c:373
+#: lexsup.c:374
msgid "Ignored for SunOS compatibility"
msgstr ""
-#: lexsup.c:375
+#: lexsup.c:376
msgid "Link against shared libraries"
msgstr ""
-#: lexsup.c:381
+#: lexsup.c:382
msgid "Do not link against shared libraries"
msgstr ""
-#: lexsup.c:389
+#: lexsup.c:390
msgid "Bind global references locally"
msgstr ""
-#: lexsup.c:391
+#: lexsup.c:392
msgid "Bind global function references locally"
msgstr ""
-#: lexsup.c:393
+#: lexsup.c:394
msgid "Check section addresses for overlaps (default)"
msgstr ""
-#: lexsup.c:396
+#: lexsup.c:397
msgid "Do not check section addresses for overlaps"
msgstr ""
-#: lexsup.c:400
+#: lexsup.c:401
msgid "Copy DT_NEEDED links mentioned inside DSOs that follow"
msgstr ""
-#: lexsup.c:404
+#: lexsup.c:405
msgid "Do not copy DT_NEEDED links mentioned inside DSOs that follow"
msgstr ""
-#: lexsup.c:408
+#: lexsup.c:409
msgid "Output cross reference table"
msgstr ""
-#: lexsup.c:410
+#: lexsup.c:411
msgid "SYMBOL=EXPRESSION"
msgstr ""
-#: lexsup.c:410
+#: lexsup.c:411
msgid "Define a symbol"
msgstr ""
-#: lexsup.c:412
+#: lexsup.c:413
msgid "[=STYLE]"
msgstr ""
-#: lexsup.c:412
+#: lexsup.c:413
msgid "Demangle symbol names [using STYLE]"
msgstr ""
-#: lexsup.c:415
+#: lexsup.c:416
msgid "Generate embedded relocs"
msgstr ""
-#: lexsup.c:417
+#: lexsup.c:418
msgid "Treat warnings as errors"
msgstr ""
-#: lexsup.c:420
+#: lexsup.c:421
msgid "Do not treat warnings as errors (default)"
msgstr ""
-#: lexsup.c:423
+#: lexsup.c:424
msgid "Call SYMBOL at unload-time"
msgstr ""
-#: lexsup.c:425
+#: lexsup.c:426
msgid "Force generation of file with .exe suffix"
msgstr ""
-#: lexsup.c:427
+#: lexsup.c:428
msgid "Remove unused sections (on some targets)"
msgstr ""
-#: lexsup.c:430
+#: lexsup.c:431
msgid "Don't remove unused sections (default)"
msgstr ""
-#: lexsup.c:433
+#: lexsup.c:434
msgid "List removed unused sections on stderr"
msgstr ""
-#: lexsup.c:436
+#: lexsup.c:437
msgid "Do not list removed unused sections"
msgstr ""
-#: lexsup.c:439
+#: lexsup.c:440
msgid "Set default hash table size close to <NUMBER>"
msgstr ""
-#: lexsup.c:442
+#: lexsup.c:443
msgid "Print option help"
msgstr ""
-#: lexsup.c:444
+#: lexsup.c:445
msgid "Call SYMBOL at load-time"
msgstr ""
-#: lexsup.c:446
+#: lexsup.c:447
msgid "Write a map file"
msgstr ""
-#: lexsup.c:448
+#: lexsup.c:449
msgid "Do not define Common storage"
msgstr ""
-#: lexsup.c:450
+#: lexsup.c:451
msgid "Do not demangle symbol names"
msgstr ""
-#: lexsup.c:452
+#: lexsup.c:453
msgid "Use less memory and more disk I/O"
msgstr ""
-#: lexsup.c:454
+#: lexsup.c:455
msgid "Do not allow unresolved references in object files"
msgstr ""
-#: lexsup.c:457
+#: lexsup.c:458
msgid "Allow unresolved references in shared libraries"
msgstr ""
-#: lexsup.c:461
+#: lexsup.c:462
msgid "Do not allow unresolved references in shared libs"
msgstr ""
-#: lexsup.c:465
+#: lexsup.c:466
msgid "Allow multiple definitions"
msgstr ""
-#: lexsup.c:467
+#: lexsup.c:468
msgid "Disallow undefined version"
msgstr ""
-#: lexsup.c:469
+#: lexsup.c:470
msgid "Create default symbol version"
msgstr ""
-#: lexsup.c:472
+#: lexsup.c:473
msgid "Create default symbol version for imported symbols"
msgstr ""
-#: lexsup.c:475
+#: lexsup.c:476
msgid "Don't warn about mismatched input files"
msgstr ""
-#: lexsup.c:478
+#: lexsup.c:479
msgid "Don't warn on finding an incompatible library"
msgstr ""
-#: lexsup.c:481
+#: lexsup.c:482
msgid "Turn off --whole-archive"
msgstr ""
-#: lexsup.c:483
+#: lexsup.c:484
msgid "Create an output file even if errors occur"
msgstr ""
-#: lexsup.c:488
+#: lexsup.c:489
msgid ""
"Only use library directories specified on\n"
" the command line"
msgstr ""
-#: lexsup.c:492
+#: lexsup.c:493
msgid "Specify target of output file"
msgstr ""
-#: lexsup.c:495
-msgid "Ignored for Linux compatibility"
+#: lexsup.c:496
+msgid "Print default output format"
msgstr ""
#: lexsup.c:498
-msgid "Reduce memory overheads, possibly taking much longer"
+msgid "Ignored for Linux compatibility"
msgstr ""
#: lexsup.c:501
+msgid "Reduce memory overheads, possibly taking much longer"
+msgstr ""
+
+#: lexsup.c:504
msgid "Reduce code size by using target specific optimizations"
msgstr ""
-#: lexsup.c:503
+#: lexsup.c:506
msgid "Do not use relaxation techniques to reduce code size"
msgstr ""
-#: lexsup.c:506
+#: lexsup.c:509
msgid "Keep only symbols listed in FILE"
msgstr ""
-#: lexsup.c:508
+#: lexsup.c:511
msgid "Set runtime shared library search path"
msgstr ""
-#: lexsup.c:510
+#: lexsup.c:513
msgid "Set link time shared library search path"
msgstr ""
-#: lexsup.c:513
+#: lexsup.c:516
msgid "Create a shared library"
msgstr ""
-#: lexsup.c:517
+#: lexsup.c:520
msgid "Create a position independent executable"
msgstr ""
-#: lexsup.c:521
+#: lexsup.c:524
msgid "[=ascending|descending]"
msgstr ""
-#: lexsup.c:522
+#: lexsup.c:525
msgid "Sort common symbols by alignment [in specified order]"
msgstr ""
-#: lexsup.c:527
+#: lexsup.c:530
msgid "name|alignment"
msgstr ""
-#: lexsup.c:528
+#: lexsup.c:531
msgid "Sort sections by name or maximum alignment"
msgstr ""
-#: lexsup.c:530
+#: lexsup.c:533
msgid "COUNT"
msgstr ""
-#: lexsup.c:530
+#: lexsup.c:533
msgid "How many tags to reserve in .dynamic section"
msgstr ""
-#: lexsup.c:533
+#: lexsup.c:536
msgid "[=SIZE]"
msgstr ""
-#: lexsup.c:533
+#: lexsup.c:536
msgid "Split output sections every SIZE octets"
msgstr ""
-#: lexsup.c:536
+#: lexsup.c:539
msgid "[=COUNT]"
msgstr ""
-#: lexsup.c:536
+#: lexsup.c:539
msgid "Split output sections every COUNT relocs"
msgstr ""
-#: lexsup.c:539
+#: lexsup.c:542
msgid "Print memory usage statistics"
msgstr ""
-#: lexsup.c:541
+#: lexsup.c:544
msgid "Display target specific options"
msgstr ""
-#: lexsup.c:543
+#: lexsup.c:546
msgid "Do task level linking"
msgstr ""
-#: lexsup.c:545
+#: lexsup.c:548
msgid "Use same format as native linker"
msgstr ""
-#: lexsup.c:547
+#: lexsup.c:550
msgid "SECTION=ADDRESS"
msgstr ""
-#: lexsup.c:547
+#: lexsup.c:550
msgid "Set address of named section"
msgstr ""
-#: lexsup.c:550
+#: lexsup.c:553
msgid "Set address of .bss section"
msgstr ""
-#: lexsup.c:552
+#: lexsup.c:555
msgid "Set address of .data section"
msgstr ""
-#: lexsup.c:554
+#: lexsup.c:557
msgid "Set address of .text section"
msgstr ""
-#: lexsup.c:556
+#: lexsup.c:559
msgid "Set address of text segment"
msgstr ""
-#: lexsup.c:559
+#: lexsup.c:562
msgid ""
"How to handle unresolved symbols. <method> is:\n"
" ignore-all, report-all, ignore-in-object-"
" ignore-in-shared-libs"
msgstr ""
-#: lexsup.c:564
+#: lexsup.c:567
msgid "[=NUMBER]"
msgstr ""
-#: lexsup.c:565
+#: lexsup.c:568
msgid "Output lots of information during link"
msgstr ""
-#: lexsup.c:569
+#: lexsup.c:572
msgid "Read version information script"
msgstr ""
-#: lexsup.c:572
+#: lexsup.c:575
msgid ""
"Take export symbols list from .exports, using\n"
" SYMBOL as the version."
msgstr ""
-#: lexsup.c:576
+#: lexsup.c:579
msgid "Add data symbols to dynamic list"
msgstr ""
-#: lexsup.c:578
+#: lexsup.c:581
msgid "Use C++ operator new/delete dynamic list"
msgstr ""
-#: lexsup.c:580
+#: lexsup.c:583
msgid "Use C++ typeinfo dynamic list"
msgstr ""
-#: lexsup.c:582
+#: lexsup.c:585
msgid "Read dynamic list"
msgstr ""
-#: lexsup.c:584
+#: lexsup.c:587
msgid "Warn about duplicate common symbols"
msgstr ""
-#: lexsup.c:586
+#: lexsup.c:589
msgid "Warn if global constructors/destructors are seen"
msgstr ""
-#: lexsup.c:589
+#: lexsup.c:592
msgid "Warn if the multiple GP values are used"
msgstr ""
-#: lexsup.c:591
+#: lexsup.c:594
msgid "Warn only once per undefined symbol"
msgstr ""
-#: lexsup.c:593
+#: lexsup.c:596
msgid "Warn if start of section changes due to alignment"
msgstr ""
-#: lexsup.c:596
+#: lexsup.c:599
msgid "Warn if shared object has DT_TEXTREL"
msgstr ""
-#: lexsup.c:599
+#: lexsup.c:602
msgid "Warn if an object has alternate ELF machine code"
msgstr ""
-#: lexsup.c:603
+#: lexsup.c:606
msgid "Report unresolved symbols as warnings"
msgstr ""
-#: lexsup.c:606
+#: lexsup.c:609
msgid "Report unresolved symbols as errors"
msgstr ""
-#: lexsup.c:608
+#: lexsup.c:611
msgid "Include all objects from following archives"
msgstr ""
-#: lexsup.c:611
+#: lexsup.c:614
msgid "Use wrapper functions for SYMBOL"
msgstr ""
-#: lexsup.c:760
+#: lexsup.c:763
msgid "%P: unrecognized option '%s'\n"
msgstr ""
-#: lexsup.c:764
+#: lexsup.c:767
msgid "%P%F: use the --help option for usage information\n"
msgstr ""
-#: lexsup.c:782
+#: lexsup.c:785
msgid "%P%F: unrecognized -a option `%s'\n"
msgstr ""
-#: lexsup.c:795
+#: lexsup.c:798
msgid "%P%F: unrecognized -assert option `%s'\n"
msgstr ""
-#: lexsup.c:838
+#: lexsup.c:841
msgid "%F%P: unknown demangling style `%s'"
msgstr ""
-#: lexsup.c:904 lexsup.c:1335
+#: lexsup.c:907 lexsup.c:1341
msgid "%P%F: invalid number `%s'\n"
msgstr ""
-#: lexsup.c:1002
+#: lexsup.c:1005
msgid "%P%F: bad --unresolved-symbols option: %s\n"
msgstr ""
-#: lexsup.c:1065 lexsup.c:1564
-msgid "%P%F: %s: error loading plugin\n"
-msgstr ""
-
-#: lexsup.c:1070
+#: lexsup.c:1076
msgid "%P%F: bad -plugin-opt option\n"
msgstr ""
#. an error message here. We cannot just make this a warning,
#. increment optind, and continue because getopt is too confused
#. and will seg-fault the next time around.
-#: lexsup.c:1087
+#: lexsup.c:1093
msgid "%P%F: bad -rpath option\n"
msgstr ""
-#: lexsup.c:1201
+#: lexsup.c:1207
msgid "%P%F: -shared not supported\n"
msgstr ""
-#: lexsup.c:1210
+#: lexsup.c:1216
msgid "%P%F: -pie not supported\n"
msgstr ""
-#: lexsup.c:1218
+#: lexsup.c:1224
msgid "descending"
msgstr ""
-#: lexsup.c:1220
+#: lexsup.c:1226
msgid "ascending"
msgstr ""
-#: lexsup.c:1223
+#: lexsup.c:1229
msgid "%P%F: invalid common section sorting option: %s\n"
msgstr ""
-#: lexsup.c:1227
+#: lexsup.c:1233
msgid "name"
msgstr ""
-#: lexsup.c:1229
+#: lexsup.c:1235
msgid "alignment"
msgstr ""
-#: lexsup.c:1232
+#: lexsup.c:1238
msgid "%P%F: invalid section sorting option: %s\n"
msgstr ""
-#: lexsup.c:1266
+#: lexsup.c:1272
msgid "%P%F: invalid argument to option \"--section-start\"\n"
msgstr ""
-#: lexsup.c:1273
+#: lexsup.c:1279
msgid "%P%F: missing argument(s) to option \"--section-start\"\n"
msgstr ""
-#: lexsup.c:1507
+#: lexsup.c:1513
msgid "%P%F: group ended before it began (--help for usage)\n"
msgstr ""
-#: lexsup.c:1535
+#: lexsup.c:1541
msgid "%P%X: --hash-size needs a numeric argument\n"
msgstr ""
-#: lexsup.c:1595 lexsup.c:1608
+#: lexsup.c:1572
+msgid "%P%F: -r and -shared may not be used together\n"
+msgstr ""
+
+#: lexsup.c:1615
+msgid "%P%F: -F may not be used without -shared\n"
+msgstr ""
+
+#: lexsup.c:1617
+msgid "%P%F: -f may not be used without -shared\n"
+msgstr ""
+
+#: lexsup.c:1661 lexsup.c:1674
msgid "%P%F: invalid hex number `%s'\n"
msgstr ""
-#: lexsup.c:1644
+#: lexsup.c:1710
#, c-format
msgid "Usage: %s [options] file...\n"
msgstr ""
-#: lexsup.c:1646
+#: lexsup.c:1712
#, c-format
msgid "Options:\n"
msgstr ""
-#: lexsup.c:1724
+#: lexsup.c:1790
#, c-format
msgid " @FILE"
msgstr ""
-#: lexsup.c:1727
+#: lexsup.c:1793
#, c-format
msgid "Read options from FILE\n"
msgstr ""
#. Note: Various tools (such as libtool) depend upon the
#. format of the listings below - do not change them.
-#: lexsup.c:1732
+#: lexsup.c:1798
#, c-format
msgid "%s: supported targets:"
msgstr ""
-#: lexsup.c:1740
+#: lexsup.c:1806
#, c-format
msgid "%s: supported emulations: "
msgstr ""
-#: lexsup.c:1745
+#: lexsup.c:1811
#, c-format
msgid "%s: emulation specific options:\n"
msgstr ""
-#: lexsup.c:1750
+#: lexsup.c:1816
#, c-format
msgid "Report bugs to %s\n"
msgstr ""
-#: mri.c:292
+#: mri.c:294
msgid "%P%F: unknown format type %s\n"
msgstr ""
msgid "%XUnsupported PEI architecture: %s\n"
msgstr ""
-#: pe-dll.c:791
+#: pe-dll.c:788
#, c-format
msgid "%XCannot export %s: invalid export name\n"
msgstr ""
-#: pe-dll.c:848
+#: pe-dll.c:845
#, c-format
msgid "%XError, duplicate EXPORT with ordinals: %s (%d vs %d)\n"
msgstr ""
-#: pe-dll.c:855
+#: pe-dll.c:852
#, c-format
msgid "Warning, duplicate EXPORT: %s\n"
msgstr ""
-#: pe-dll.c:942
+#: pe-dll.c:939
#, c-format
msgid "%XCannot export %s: symbol not defined\n"
msgstr ""
-#: pe-dll.c:948
+#: pe-dll.c:945
#, c-format
msgid "%XCannot export %s: symbol wrong type (%d vs %d)\n"
msgstr ""
-#: pe-dll.c:955
+#: pe-dll.c:952
#, c-format
msgid "%XCannot export %s: symbol not found\n"
msgstr ""
-#: pe-dll.c:1069
+#: pe-dll.c:1066
#, c-format
msgid "%XError, ordinal used twice: %d (%s vs %s)\n"
msgstr ""
-#: pe-dll.c:1450
+#: pe-dll.c:1456
#, c-format
msgid "%XError: %d-bit reloc in dll\n"
msgstr ""
-#: pe-dll.c:1578
+#: pe-dll.c:1584
#, c-format
msgid "%s: Can't open output def file %s\n"
msgstr ""
-#: pe-dll.c:1729
+#: pe-dll.c:1735
#, c-format
msgid "; no contents available\n"
msgstr ""
-#: pe-dll.c:2656
+#: pe-dll.c:2662
msgid ""
"%C: variable '%T' can't be auto-imported. Please read the documentation for "
"ld's --enable-auto-import for details.\n"
msgstr ""
-#: pe-dll.c:2686
+#: pe-dll.c:2692
#, c-format
msgid "%XCan't open .lib file: %s\n"
msgstr ""
-#: pe-dll.c:2691
+#: pe-dll.c:2697
#, c-format
msgid "Creating library file: %s\n"
msgstr ""
-#: pe-dll.c:2720
+#: pe-dll.c:2726
#, c-format
msgid "%Xbfd_openr %s: %E\n"
msgstr ""
-#: pe-dll.c:2732
+#: pe-dll.c:2738
#, c-format
msgid "%X%s(%s): can't find member in non-archive file"
msgstr ""
-#: pe-dll.c:2744
+#: pe-dll.c:2750
#, c-format
msgid "%X%s(%s): can't find member in archive"
msgstr ""
-#: pe-dll.c:3183
+#: pe-dll.c:3189
#, c-format
msgid "%XError: can't use long section names on this arch\n"
msgstr ""
-#: plugin.c:176 plugin.c:210
+#: plugin.c:177 plugin.c:211
msgid "<no plugin>"
msgstr ""
-#: plugin.c:249
+#: plugin.c:250
#, c-format
msgid "could not create dummy IR bfd: %F%E\n"
msgstr ""
-#: plugin.c:322
+#: plugin.c:343
msgid "%P%F: %s: non-ELF symbol in ELF BFD!\n"
msgstr ""
-#: plugin.c:326
+#: plugin.c:347
msgid "%P%F: unknown ELF symbol visibility: %d!\n"
msgstr ""
-#: plugin.c:559
+#: plugin.c:586
msgid "%P: %B: symbol `%s' definition: %d, visibility: %d, resolution: %d\n"
msgstr ""
-#: plugin.c:825
+#: plugin.c:863
msgid "%P%F: %s: plugin reported error claiming file\n"
msgstr ""
-#: plugin.c:896
+#: plugin.c:934
msgid "%P: %s: error in plugin cleanup (ignored)\n"
msgstr ""
+2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
+
+ * ld-srec/srec.exp: xfail epiphany.
+ * lib/ld-lib.exp (check_shared_lib_support): Add Epiphany to list
+ of targets not supporting shared libraries.
+
2011-10-21 H.J. Lu <hongjiu.lu@intel.com>
PR ld/13302
set flags "$flags --no-toc-optimize"
}
+ # Epiphany needs some help too
+ if [istarget epiphany*-*-*] {
+ set flags "$flags --defsym _start=00000060"
+ setup_xfail "epiphany*-*-*"
+ }
+
if { ![ld_simple_link $ld tmpdir/sr1 "$flags $objs"] \
|| ![ld_simple_link $ld tmpdir/sr2.sr "$flags --oformat srec $objs"] } {
fail $test
&& ![istarget d10v-*-*]
&& ![istarget d30v-*-*]
&& ![istarget dlx-*-*]
+ && ![istarget epiphany-*-*]
&& ![istarget fr30-*-*]
&& ![istarget frv-*-*]
&& ![istarget h8300-*-*]
+2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
+
+ * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
+ (TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c,
+ epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
+ (CLEANFILES): Add stamp-epiphany.
+ (EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it.
+ (stamp-epiphany): New rule.
+ * configure.in: Handle bfd_epiphany_arch.
+ * disassemble.c (ARCH_epiphany): Define.
+ (disassembler): Handle bfd_arch_epiphany.
+ * epiphany-asm.c: New file.
+ * epiphany-desc.c: New file.
+ * epiphany-desc.h: New file.
+ * epiphany-dis.c: New file.
+ * epiphany-ibld.c: New file.
+ * epiphany-opc.c: New file.
+ * epiphany-opc.h: New file.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+ * po/POTFILES.in: Regenerate.
+ * po/opcodes.pot: Regenerate.
+
2011-10-24 Julian Brown <julian@codesourcery.com>
* m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
# Header files.
HFILES = \
+ epiphany-desc.h epiphany-opc.h \
fr30-desc.h fr30-opc.h \
frv-desc.h frv-opc.h \
h8500-opc.h \
d30v-dis.c \
d30v-opc.c \
dlx-dis.c \
+ epiphany-asm.c \
+ epiphany-desc.c \
+ epiphany-dis.c \
+ epiphany-ibld.c \
+ epiphany-opc.c \
fr30-asm.c \
fr30-desc.c \
fr30-dis.c \
&& mv tmp $(srcdir)/po/POTFILES.in
CLEANFILES = \
- stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \
+ stamp-epiphany stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \
stamp-m32c stamp-m32r stamp-mep stamp-mt \
stamp-openrisc stamp-xc16x stamp-xstormy16 \
libopcodes.a stamp-lib
$(CGENDIR)/opc-opinst.scm \
cgen-asm.in cgen-dis.in cgen-ibld.in
-CGEN_CPUS = fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16
+CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16
if CGEN_MAINT
+EPIPHANY_DEPS = stamp-epiphany
FR30_DEPS = stamp-fr30
FRV_DEPS = stamp-frv
IP2K_DEPS = stamp-ip2k
XC16X_DEPS = stamp-xc16x
XSTORMY16_DEPS = stamp-xstormy16
else
+EPIPHANY_DEPS =
FR30_DEPS =
FRV_DEPS =
IP2K_DEPS =
# For now, require developers to configure with --enable-cgen-maint.
+$(srcdir)/epiphany-desc.h $(srcdir)/epiphany-desc.c $(srcdir)/epiphany-opc.h \
+ $(srcdir)/epiphany-opc.c $(srcdir)/epiphany-ibld.c \
+ $(srcdir)/epiphany-opinst.c $(srcdir)/epiphany-asm.c \
+ $(srcdir)/epiphany-dis.c: $(EPIPHANY_DEPS)
+ @true
+
+stamp-epiphany: $(CGENDEPS) $(CPUDIR)/epiphany.cpu $(CPUDIR)/epiphany.opc
+ $(MAKE) run-cgen arch=epiphany prefix=epiphany options= \
+ archfile=$(CPUDIR)/epiphany.cpu opcfile=$(CPUDIR)/epiphany.opc extrafiles=
+
$(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS)
@true
stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc
# Header files.
HFILES = \
+ epiphany-desc.h epiphany-opc.h \
fr30-desc.h fr30-opc.h \
frv-desc.h frv-opc.h \
h8500-opc.h \
d30v-dis.c \
d30v-opc.c \
dlx-dis.c \
+ epiphany-asm.c \
+ epiphany-desc.c \
+ epiphany-dis.c \
+ epiphany-ibld.c \
+ epiphany-opc.c \
fr30-asm.c \
fr30-desc.c \
fr30-dis.c \
libopcodes_a_SOURCES =
POTFILES = $(HFILES) $(CFILES)
CLEANFILES = \
- stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \
+ stamp-epiphany stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \
stamp-m32c stamp-m32r stamp-mep stamp-mt \
stamp-openrisc stamp-xc16x stamp-xstormy16 \
libopcodes.a stamp-lib
$(CGENDIR)/opc-opinst.scm \
cgen-asm.in cgen-dis.in cgen-ibld.in
-CGEN_CPUS = fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16
+CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16
+@CGEN_MAINT_FALSE@EPIPHANY_DEPS =
+@CGEN_MAINT_TRUE@EPIPHANY_DEPS = stamp-epiphany
@CGEN_MAINT_FALSE@FR30_DEPS =
@CGEN_MAINT_TRUE@FR30_DEPS = stamp-fr30
@CGEN_MAINT_FALSE@FRV_DEPS =
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dis-init.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/disassemble.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dlx-dis.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-asm.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-desc.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-dis.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-ibld.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fr30-asm.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fr30-desc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fr30-dis.Plo@am__quote@
# For now, require developers to configure with --enable-cgen-maint.
+$(srcdir)/epiphany-desc.h $(srcdir)/epiphany-desc.c $(srcdir)/epiphany-opc.h \
+ $(srcdir)/epiphany-opc.c $(srcdir)/epiphany-ibld.c \
+ $(srcdir)/epiphany-opinst.c $(srcdir)/epiphany-asm.c \
+ $(srcdir)/epiphany-dis.c: $(EPIPHANY_DEPS)
+ @true
+
+stamp-epiphany: $(CGENDEPS) $(CPUDIR)/epiphany.cpu $(CPUDIR)/epiphany.opc
+ $(MAKE) run-cgen arch=epiphany prefix=epiphany options= \
+ archfile=$(CPUDIR)/epiphany.cpu opcfile=$(CPUDIR)/epiphany.opc extrafiles=
+
$(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS)
@true
stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;;
+ bfd_epiphany_arch) ta="$ta epiphany-asm.lo epiphany-desc.lo epiphany-dis.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=yes ;;
bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;;
bfd_lm32_arch) ta="$ta lm32-asm.lo lm32-desc.lo lm32-dis.lo lm32-ibld.lo lm32-opc.lo lm32-opinst.lo" using_cgen=yes ;;
bfd_m32c_arch) ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;;
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;;
+ bfd_epiphany_arch) ta="$ta epiphany-asm.lo epiphany-desc.lo epiphany-dis.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=yes ;;
bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;;
bfd_lm32_arch) ta="$ta lm32-asm.lo lm32-desc.lo lm32-dis.lo lm32-ibld.lo lm32-opc.lo lm32-opinst.lo" using_cgen=yes ;;
bfd_m32c_arch) ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;;
#define ARCH_alpha
#define ARCH_arc
#define ARCH_arm
+#define ARCH_epiphany
#define ARCH_avr
#define ARCH_bfin
#define ARCH_cr16
disassemble = print_insn_ip2k;
break;
#endif
+#ifdef ARCH_epiphany
+ case bfd_arch_epiphany:
+ disassemble = print_insn_epiphany;
+ break;
+#endif
#ifdef ARCH_fr30
case bfd_arch_fr30:
disassemble = print_insn_fr30;
--- /dev/null
+/* Assembler interface for targets using CGEN. -*- C -*-
+ CGEN: Cpu tools GENerator
+
+ THIS FILE IS MACHINE GENERATED WITH CGEN.
+ - the resultant file is machine generated, cgen-asm.in isn't
+
+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2010
+ Free Software Foundation, Inc.
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+ Keep that in mind. */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "epiphany-desc.h"
+#include "epiphany-opc.h"
+#include "opintl.h"
+#include "xregex.h"
+#include "libiberty.h"
+#include "safe-ctype.h"
+
+#undef min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+static const char * parse_insn_normal
+ (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
+\f
+/* -- assembler routines inserted here. */
+
+/* -- asm.c */
+const char *
+parse_shortregs (CGEN_CPU_DESC cd,
+ const char ** strp,
+ CGEN_KEYWORD * keywords,
+ long * regno)
+{
+ const char * errmsg;
+
+ /* Parse register. */
+ errmsg = cgen_parse_keyword (cd, strp, keywords, regno);
+
+ if (errmsg)
+ return errmsg;
+
+ if (*regno > 7)
+ errmsg = _("register unavailable for short instructions");
+
+ return errmsg;
+}
+
+static const char * parse_simm_not_reg (CGEN_CPU_DESC, const char **, int,
+ long *);
+
+static const char *
+parse_uimm_not_reg (CGEN_CPU_DESC cd,
+ const char ** strp,
+ int opindex,
+ unsigned long * valuep)
+{
+ long * svalp = (void *) valuep;
+ return parse_simm_not_reg (cd, strp, opindex, svalp);
+}
+
+/* Handle simm3/simm11/imm3/imm12. */
+
+static const char *
+parse_simm_not_reg (CGEN_CPU_DESC cd,
+ const char ** strp,
+ int opindex,
+ long * valuep)
+{
+ const char * errmsg;
+
+ int sign = 0;
+ int bits = 0;
+
+ switch (opindex)
+ {
+ case EPIPHANY_OPERAND_SIMM3:
+ sign = 1; bits = 3; break;
+ case EPIPHANY_OPERAND_SIMM11:
+ sign = 1; bits = 11; break;
+ case EPIPHANY_OPERAND_DISP3:
+ sign = 0; bits = 3; break;
+ case EPIPHANY_OPERAND_DISP11:
+ /* Load/store displacement is a sign-magnitude 12 bit value. */
+ sign = 0; bits = 11; break;
+ }
+
+ /* First try to parse as a register name and reject the operand. */
+ errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names,valuep);
+ if (!errmsg)
+ return _("register name used as immediate value");
+
+ errmsg = (sign ? cgen_parse_signed_integer (cd, strp, opindex, valuep)
+ : cgen_parse_unsigned_integer (cd, strp, opindex,
+ (unsigned long *) valuep));
+ if (errmsg)
+ return errmsg;
+
+ if (sign)
+ errmsg = cgen_validate_signed_integer (*valuep,
+ -((1L << bits) - 1), (1 << (bits - 1)) - 1);
+ else
+ errmsg = cgen_validate_unsigned_integer (*valuep, 0, (1L << bits) - 1);
+
+ return errmsg;
+}
+
+static const char *
+parse_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ const char ** strp,
+ int opindex ATTRIBUTE_UNUSED,
+ bfd_vma * valuep)
+{
+ if (**strp == '#')
+ ++*strp; /* Skip leading hashes. */
+
+ if (**strp == '-')
+ {
+ *valuep = 1;
+ ++*strp;
+ }
+ else if (**strp == '+')
+ {
+ *valuep = 0;
+ ++*strp;
+ }
+ else
+ *valuep = 0;
+
+ return NULL;
+}
+
+static const char *
+parse_imm8 (CGEN_CPU_DESC cd,
+ const char ** strp,
+ int opindex,
+ bfd_reloc_code_real_type code,
+ enum cgen_parse_operand_result * result_type,
+ bfd_vma * valuep)
+{
+ const char * errmsg;
+ enum cgen_parse_operand_result rt;
+ long dummyval;
+
+ if (!result_type)
+ result_type = &rt;
+
+ code = BFD_RELOC_NONE;
+
+ if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names, &dummyval)
+ || !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names,
+ &dummyval))
+ /* Don't treat "mov ip,ip" as a move-immediate. */
+ return _("register source in immediate move");
+
+ errmsg = cgen_parse_address (cd, strp, opindex, code, result_type, valuep);
+ if (errmsg)
+ return errmsg;
+
+ if (*result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xff);
+ else
+ errmsg = _("byte relocation unsupported");
+
+ *valuep &= 0xff;
+ return errmsg;
+}
+
+static const char * MISSING_CLOSE_PARENTHESIS = N_("missing `)'");
+
+static const char *
+parse_imm16 (CGEN_CPU_DESC cd,
+ const char ** strp,
+ int opindex,
+ bfd_reloc_code_real_type code ATTRIBUTE_UNUSED,
+ enum cgen_parse_operand_result * result_type,
+ bfd_vma * valuep)
+{
+ const char * errmsg;
+ enum cgen_parse_operand_result rt;
+ long dummyval;
+
+ if (!result_type)
+ result_type = &rt;
+
+ if (strncasecmp (*strp, "%high(", 6) == 0)
+ {
+ *strp += 6;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_HIGH,
+ result_type, valuep);
+ if (**strp != ')')
+ return MISSING_CLOSE_PARENTHESIS;
+ ++*strp;
+ *valuep >>= 16;
+ }
+ else if (strncasecmp (*strp, "%low(", 5) == 0)
+ {
+ *strp += 5;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_LOW,
+ result_type, valuep);
+ if (**strp != ')')
+ return MISSING_CLOSE_PARENTHESIS;
+ ++*strp;
+ }
+ else if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names,
+ &dummyval)
+ || !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names,
+ &dummyval))
+ /* Don't treat "mov ip,ip" as a move-immediate. */
+ return _("register source in immediate move");
+ else
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16,
+ result_type, valuep);
+
+ if (!errmsg && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xffff);
+
+ *valuep &= 0xffff;
+ return errmsg;
+}
+
+const char *
+parse_branch_addr (CGEN_CPU_DESC cd,
+ const char ** strp,
+ int opindex,
+ int opinfo ATTRIBUTE_UNUSED,
+ enum cgen_parse_operand_result * resultp ATTRIBUTE_UNUSED,
+ unsigned long * valuep ATTRIBUTE_UNUSED)
+{
+ const char * errmsg;
+ enum cgen_parse_operand_result result_type;
+ bfd_reloc_code_real_type code = BFD_RELOC_NONE;
+ bfd_vma value;
+
+ switch (opindex)
+ {
+ case EPIPHANY_OPERAND_SIMM24:
+ code = BFD_RELOC_EPIPHANY_SIMM24;
+ break;
+
+ case EPIPHANY_OPERAND_SIMM8:
+ code = BFD_RELOC_EPIPHANY_SIMM8;
+ break;
+
+ default:
+ errmsg = _("ABORT: unknown operand");
+ return errmsg;
+ }
+
+ errmsg = cgen_parse_address (cd, strp, opindex, code,
+ &result_type, &value);
+ if (errmsg == NULL)
+ {
+ if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ {
+ /* Act as if we had done a PC-relative branch, ala .+num. */
+ char buf[20];
+ const char * bufp = (const char *) buf;
+
+ sprintf (buf, ".+%ld", value);
+ errmsg = cgen_parse_address (cd, &bufp, opindex, code, &result_type,
+ &value);
+ }
+
+ if (result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED)
+ {
+ /* This will happen for things like (s2-s1) where s2 and s1
+ are labels. */
+ /* Nothing further to be done. */
+ }
+ else
+ errmsg = _("Not a pc-relative address.");
+ }
+ return errmsg;
+}
+\f
+/* -- dis.c */
+
+const char * epiphany_cgen_parse_operand
+ (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
+
+/* Main entry point for operand parsing.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `parse_insn_normal', but keeping it
+ separate makes clear the interface between `parse_insn_normal' and each of
+ the handlers. */
+
+const char *
+epiphany_cgen_parse_operand (CGEN_CPU_DESC cd,
+ int opindex,
+ const char ** strp,
+ CGEN_FIELDS * fields)
+{
+ const char * errmsg = NULL;
+ /* Used by scalar operands that still need to be parsed. */
+ long junk ATTRIBUTE_UNUSED;
+
+ switch (opindex)
+ {
+ case EPIPHANY_OPERAND_DIRECTION :
+ errmsg = parse_postindex (cd, strp, EPIPHANY_OPERAND_DIRECTION, (unsigned long *) (& fields->f_addsubx));
+ break;
+ case EPIPHANY_OPERAND_DISP11 :
+ errmsg = parse_uimm_not_reg (cd, strp, EPIPHANY_OPERAND_DISP11, (unsigned long *) (& fields->f_disp11));
+ break;
+ case EPIPHANY_OPERAND_DISP3 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, EPIPHANY_OPERAND_DISP3, (unsigned long *) (& fields->f_disp3));
+ break;
+ case EPIPHANY_OPERAND_DPMI :
+ errmsg = parse_postindex (cd, strp, EPIPHANY_OPERAND_DPMI, (unsigned long *) (& fields->f_subd));
+ break;
+ case EPIPHANY_OPERAND_FRD :
+ errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd);
+ break;
+ case EPIPHANY_OPERAND_FRD6 :
+ errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd6);
+ break;
+ case EPIPHANY_OPERAND_FRM :
+ errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm);
+ break;
+ case EPIPHANY_OPERAND_FRM6 :
+ errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm6);
+ break;
+ case EPIPHANY_OPERAND_FRN :
+ errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn);
+ break;
+ case EPIPHANY_OPERAND_FRN6 :
+ errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn6);
+ break;
+ case EPIPHANY_OPERAND_IMM16 :
+ {
+ bfd_vma value = 0;
+ errmsg = parse_imm16 (cd, strp, EPIPHANY_OPERAND_IMM16, 0, NULL, & value);
+ fields->f_imm16 = value;
+ }
+ break;
+ case EPIPHANY_OPERAND_IMM8 :
+ {
+ bfd_vma value = 0;
+ errmsg = parse_imm8 (cd, strp, EPIPHANY_OPERAND_IMM8, 0, NULL, & value);
+ fields->f_imm8 = value;
+ }
+ break;
+ case EPIPHANY_OPERAND_RD :
+ errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd);
+ break;
+ case EPIPHANY_OPERAND_RD6 :
+ errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd6);
+ break;
+ case EPIPHANY_OPERAND_RM :
+ errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm);
+ break;
+ case EPIPHANY_OPERAND_RM6 :
+ errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm6);
+ break;
+ case EPIPHANY_OPERAND_RN :
+ errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn);
+ break;
+ case EPIPHANY_OPERAND_RN6 :
+ errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn6);
+ break;
+ case EPIPHANY_OPERAND_SD :
+ errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sd);
+ break;
+ case EPIPHANY_OPERAND_SD6 :
+ errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sd6);
+ break;
+ case EPIPHANY_OPERAND_SDDMA :
+ errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crdma_names, & fields->f_sd6);
+ break;
+ case EPIPHANY_OPERAND_SDMEM :
+ errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmem_names, & fields->f_sd6);
+ break;
+ case EPIPHANY_OPERAND_SDMESH :
+ errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmesh_names, & fields->f_sd6);
+ break;
+ case EPIPHANY_OPERAND_SHIFT :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, EPIPHANY_OPERAND_SHIFT, (unsigned long *) (& fields->f_shift));
+ break;
+ case EPIPHANY_OPERAND_SIMM11 :
+ errmsg = parse_simm_not_reg (cd, strp, EPIPHANY_OPERAND_SIMM11, (long *) (& fields->f_sdisp11));
+ break;
+ case EPIPHANY_OPERAND_SIMM24 :
+ {
+ bfd_vma value = 0;
+ errmsg = parse_branch_addr (cd, strp, EPIPHANY_OPERAND_SIMM24, 0, NULL, & value);
+ fields->f_simm24 = value;
+ }
+ break;
+ case EPIPHANY_OPERAND_SIMM3 :
+ errmsg = parse_simm_not_reg (cd, strp, EPIPHANY_OPERAND_SIMM3, (long *) (& fields->f_sdisp3));
+ break;
+ case EPIPHANY_OPERAND_SIMM8 :
+ {
+ bfd_vma value = 0;
+ errmsg = parse_branch_addr (cd, strp, EPIPHANY_OPERAND_SIMM8, 0, NULL, & value);
+ fields->f_simm8 = value;
+ }
+ break;
+ case EPIPHANY_OPERAND_SN :
+ errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sn);
+ break;
+ case EPIPHANY_OPERAND_SN6 :
+ errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sn6);
+ break;
+ case EPIPHANY_OPERAND_SNDMA :
+ errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crdma_names, & fields->f_sn6);
+ break;
+ case EPIPHANY_OPERAND_SNMEM :
+ errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmem_names, & fields->f_sn6);
+ break;
+ case EPIPHANY_OPERAND_SNMESH :
+ errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmesh_names, & fields->f_sn6);
+ break;
+ case EPIPHANY_OPERAND_SWI_NUM :
+ errmsg = parse_uimm_not_reg (cd, strp, EPIPHANY_OPERAND_SWI_NUM, (unsigned long *) (& fields->f_trap_num));
+ break;
+ case EPIPHANY_OPERAND_TRAPNUM6 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, EPIPHANY_OPERAND_TRAPNUM6, (unsigned long *) (& fields->f_trap_num));
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex);
+ abort ();
+ }
+
+ return errmsg;
+}
+
+cgen_parse_fn * const epiphany_cgen_parse_handlers[] =
+{
+ parse_insn_normal,
+};
+
+void
+epiphany_cgen_init_asm (CGEN_CPU_DESC cd)
+{
+ epiphany_cgen_init_opcode_table (cd);
+ epiphany_cgen_init_ibld_table (cd);
+ cd->parse_handlers = & epiphany_cgen_parse_handlers[0];
+ cd->parse_operand = epiphany_cgen_parse_operand;
+#ifdef CGEN_ASM_INIT_HOOK
+CGEN_ASM_INIT_HOOK
+#endif
+}
+
+\f
+
+/* Regex construction routine.
+
+ This translates an opcode syntax string into a regex string,
+ by replacing any non-character syntax element (such as an
+ opcode) with the pattern '.*'
+
+ It then compiles the regex and stores it in the opcode, for
+ later use by epiphany_cgen_assemble_insn
+
+ Returns NULL for success, an error message for failure. */
+
+char *
+epiphany_cgen_build_insn_regex (CGEN_INSN *insn)
+{
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+ const char *mnem = CGEN_INSN_MNEMONIC (insn);
+ char rxbuf[CGEN_MAX_RX_ELEMENTS];
+ char *rx = rxbuf;
+ const CGEN_SYNTAX_CHAR_TYPE *syn;
+ int reg_err;
+
+ syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc));
+
+ /* Mnemonics come first in the syntax string. */
+ if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+ return _("missing mnemonic in syntax string");
+ ++syn;
+
+ /* Generate a case sensitive regular expression that emulates case
+ insensitive matching in the "C" locale. We cannot generate a case
+ insensitive regular expression because in Turkish locales, 'i' and 'I'
+ are not equal modulo case conversion. */
+
+ /* Copy the literal mnemonic out of the insn. */
+ for (; *mnem; mnem++)
+ {
+ char c = *mnem;
+
+ if (ISALPHA (c))
+ {
+ *rx++ = '[';
+ *rx++ = TOLOWER (c);
+ *rx++ = TOUPPER (c);
+ *rx++ = ']';
+ }
+ else
+ *rx++ = c;
+ }
+
+ /* Copy any remaining literals from the syntax string into the rx. */
+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+ {
+ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ char c = CGEN_SYNTAX_CHAR (* syn);
+
+ switch (c)
+ {
+ /* Escape any regex metacharacters in the syntax. */
+ case '.': case '[': case '\\':
+ case '*': case '^': case '$':
+
+#ifdef CGEN_ESCAPE_EXTENDED_REGEX
+ case '?': case '{': case '}':
+ case '(': case ')': case '*':
+ case '|': case '+': case ']':
+#endif
+ *rx++ = '\\';
+ *rx++ = c;
+ break;
+
+ default:
+ if (ISALPHA (c))
+ {
+ *rx++ = '[';
+ *rx++ = TOLOWER (c);
+ *rx++ = TOUPPER (c);
+ *rx++ = ']';
+ }
+ else
+ *rx++ = c;
+ break;
+ }
+ }
+ else
+ {
+ /* Replace non-syntax fields with globs. */
+ *rx++ = '.';
+ *rx++ = '*';
+ }
+ }
+
+ /* Trailing whitespace ok. */
+ * rx++ = '[';
+ * rx++ = ' ';
+ * rx++ = '\t';
+ * rx++ = ']';
+ * rx++ = '*';
+
+ /* But anchor it after that. */
+ * rx++ = '$';
+ * rx = '\0';
+
+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+ if (reg_err == 0)
+ return NULL;
+ else
+ {
+ static char msg[80];
+
+ regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80);
+ regfree ((regex_t *) CGEN_INSN_RX (insn));
+ free (CGEN_INSN_RX (insn));
+ (CGEN_INSN_RX (insn)) = NULL;
+ return msg;
+ }
+}
+
+\f
+/* Default insn parser.
+
+ The syntax string is scanned and operands are parsed and stored in FIELDS.
+ Relocs are queued as we go via other callbacks.
+
+ ??? Note that this is currently an all-or-nothing parser. If we fail to
+ parse the instruction, we return 0 and the caller will start over from
+ the beginning. Backtracking will be necessary in parsing subexpressions,
+ but that can be handled there. Not handling backtracking here may get
+ expensive in the case of the m68k. Deal with later.
+
+ Returns NULL for success, an error message for failure. */
+
+static const char *
+parse_insn_normal (CGEN_CPU_DESC cd,
+ const CGEN_INSN *insn,
+ const char **strp,
+ CGEN_FIELDS *fields)
+{
+ /* ??? Runtime added insns not handled yet. */
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ const char *str = *strp;
+ const char *errmsg;
+ const char *p;
+ const CGEN_SYNTAX_CHAR_TYPE * syn;
+#ifdef CGEN_MNEMONIC_OPERANDS
+ /* FIXME: wip */
+ int past_opcode_p;
+#endif
+
+ /* For now we assume the mnemonic is first (there are no leading operands).
+ We can parse it without needing to set up operand parsing.
+ GAS's input scrubber will ensure mnemonics are lowercase, but we may
+ not be called from GAS. */
+ p = CGEN_INSN_MNEMONIC (insn);
+ while (*p && TOLOWER (*p) == TOLOWER (*str))
+ ++p, ++str;
+
+ if (* p)
+ return _("unrecognized instruction");
+
+#ifndef CGEN_MNEMONIC_OPERANDS
+ if (* str && ! ISSPACE (* str))
+ return _("unrecognized instruction");
+#endif
+
+ CGEN_INIT_PARSE (cd);
+ cgen_init_parse_operand (cd);
+#ifdef CGEN_MNEMONIC_OPERANDS
+ past_opcode_p = 0;
+#endif
+
+ /* We don't check for (*str != '\0') here because we want to parse
+ any trailing fake arguments in the syntax string. */
+ syn = CGEN_SYNTAX_STRING (syntax);
+
+ /* Mnemonics come first for now, ensure valid string. */
+ if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+ abort ();
+
+ ++syn;
+
+ while (* syn != 0)
+ {
+ /* Non operand chars must match exactly. */
+ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ /* FIXME: While we allow for non-GAS callers above, we assume the
+ first char after the mnemonic part is a space. */
+ /* FIXME: We also take inappropriate advantage of the fact that
+ GAS's input scrubber will remove extraneous blanks. */
+ if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn)))
+ {
+#ifdef CGEN_MNEMONIC_OPERANDS
+ if (CGEN_SYNTAX_CHAR(* syn) == ' ')
+ past_opcode_p = 1;
+#endif
+ ++ syn;
+ ++ str;
+ }
+ else if (*str)
+ {
+ /* Syntax char didn't match. Can't be this insn. */
+ static char msg [80];
+
+ /* xgettext:c-format */
+ sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
+ CGEN_SYNTAX_CHAR(*syn), *str);
+ return msg;
+ }
+ else
+ {
+ /* Ran out of input. */
+ static char msg [80];
+
+ /* xgettext:c-format */
+ sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"),
+ CGEN_SYNTAX_CHAR(*syn));
+ return msg;
+ }
+ continue;
+ }
+
+#ifdef CGEN_MNEMONIC_OPERANDS
+ (void) past_opcode_p;
+#endif
+ /* We have an operand of some sort. */
+ errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields);
+ if (errmsg)
+ return errmsg;
+
+ /* Done with this operand, continue with next one. */
+ ++ syn;
+ }
+
+ /* If we're at the end of the syntax string, we're done. */
+ if (* syn == 0)
+ {
+ /* FIXME: For the moment we assume a valid `str' can only contain
+ blanks now. IE: We needn't try again with a longer version of
+ the insn and it is assumed that longer versions of insns appear
+ before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */
+ while (ISSPACE (* str))
+ ++ str;
+
+ if (* str != '\0')
+ return _("junk at end of line"); /* FIXME: would like to include `str' */
+
+ return NULL;
+ }
+
+ /* We couldn't parse it. */
+ return _("unrecognized instruction");
+}
+\f
+/* Main entry point.
+ This routine is called for each instruction to be assembled.
+ STR points to the insn to be assembled.
+ We assume all necessary tables have been initialized.
+ The assembled instruction, less any fixups, is stored in BUF.
+ Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
+ still needs to be converted to target byte order, otherwise BUF is an array
+ of bytes in target byte order.
+ The result is a pointer to the insn's entry in the opcode table,
+ or NULL if an error occured (an error message will have already been
+ printed).
+
+ Note that when processing (non-alias) macro-insns,
+ this function recurses.
+
+ ??? It's possible to make this cpu-independent.
+ One would have to deal with a few minor things.
+ At this point in time doing so would be more of a curiosity than useful
+ [for example this file isn't _that_ big], but keeping the possibility in
+ mind helps keep the design clean. */
+
+const CGEN_INSN *
+epiphany_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ const char *str,
+ CGEN_FIELDS *fields,
+ CGEN_INSN_BYTES_PTR buf,
+ char **errmsg)
+{
+ const char *start;
+ CGEN_INSN_LIST *ilist;
+ const char *parse_errmsg = NULL;
+ const char *insert_errmsg = NULL;
+ int recognized_mnemonic = 0;
+
+ /* Skip leading white space. */
+ while (ISSPACE (* str))
+ ++ str;
+
+ /* The instructions are stored in hashed lists.
+ Get the first in the list. */
+ ilist = CGEN_ASM_LOOKUP_INSN (cd, str);
+
+ /* Keep looking until we find a match. */
+ start = str;
+ for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
+ {
+ const CGEN_INSN *insn = ilist->insn;
+ recognized_mnemonic = 1;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not usually needed as unsupported opcodes
+ shouldn't be in the hash lists. */
+ /* Is this insn supported by the selected cpu? */
+ if (! epiphany_cgen_insn_supported (cd, insn))
+ continue;
+#endif
+ /* If the RELAXED attribute is set, this is an insn that shouldn't be
+ chosen immediately. Instead, it is used during assembler/linker
+ relaxation if possible. */
+ if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
+ continue;
+
+ str = start;
+
+ /* Skip this insn if str doesn't look right lexically. */
+ if (CGEN_INSN_RX (insn) != NULL &&
+ regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
+ continue;
+
+ /* Allow parse/insert handlers to obtain length of insn. */
+ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+ parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
+ if (parse_errmsg != NULL)
+ continue;
+
+ /* ??? 0 is passed for `pc'. */
+ insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
+ (bfd_vma) 0);
+ if (insert_errmsg != NULL)
+ continue;
+
+ /* It is up to the caller to actually output the insn and any
+ queued relocs. */
+ return insn;
+ }
+
+ {
+ static char errbuf[150];
+ const char *tmp_errmsg;
+#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
+#define be_verbose 1
+#else
+#define be_verbose 0
+#endif
+
+ if (be_verbose)
+ {
+ /* If requesting verbose error messages, use insert_errmsg.
+ Failing that, use parse_errmsg. */
+ tmp_errmsg = (insert_errmsg ? insert_errmsg :
+ parse_errmsg ? parse_errmsg :
+ recognized_mnemonic ?
+ _("unrecognized form of instruction") :
+ _("unrecognized instruction"));
+
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+ }
+ else
+ {
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+ else
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s'"), start);
+ }
+
+ *errmsg = errbuf;
+ return NULL;
+ }
+}
--- /dev/null
+/* CPU data for epiphany.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#include "sysdep.h"
+#include <stdio.h>
+#include <stdarg.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "epiphany-desc.h"
+#include "epiphany-opc.h"
+#include "opintl.h"
+#include "libiberty.h"
+#include "xregex.h"
+
+/* Attributes. */
+
+static const CGEN_ATTR_ENTRY bool_attr[] =
+{
+ { "#f", 0 },
+ { "#t", 1 },
+ { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
+{
+ { "base", MACH_BASE },
+ { "epiphany32", MACH_EPIPHANY32 },
+ { "max", MACH_MAX },
+ { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
+{
+ { "epiphany", ISA_EPIPHANY },
+ { "max", ISA_MAX },
+ { 0, 0 }
+};
+
+const CGEN_ATTR_TABLE epiphany_cgen_ifield_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "RESERVED", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "SIGNED", &bool_attr[0], &bool_attr[0] },
+ { "RELOC", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE epiphany_cgen_hardware_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "PC", &bool_attr[0], &bool_attr[0] },
+ { "PROFILE", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE epiphany_cgen_operand_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "SIGNED", &bool_attr[0], &bool_attr[0] },
+ { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
+ { "RELAX", &bool_attr[0], &bool_attr[0] },
+ { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
+ { "RELOC", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE epiphany_cgen_insn_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "ALIAS", &bool_attr[0], &bool_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "COND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
+ { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
+ { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
+ { "RELAXED", &bool_attr[0], &bool_attr[0] },
+ { "NO-DIS", &bool_attr[0], &bool_attr[0] },
+ { "PBB", &bool_attr[0], &bool_attr[0] },
+ { "SHORT-INSN", &bool_attr[0], &bool_attr[0] },
+ { "IMM3", &bool_attr[0], &bool_attr[0] },
+ { "IMM8", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+/* Instruction set variants. */
+
+static const CGEN_ISA epiphany_cgen_isa_table[] = {
+ { "epiphany", 32, 32, 16, 32 },
+ { 0, 0, 0, 0, 0 }
+};
+
+/* Machine variants. */
+
+static const CGEN_MACH epiphany_cgen_mach_table[] = {
+ { "epiphany32", "epiphany32", MACH_EPIPHANY32, 0 },
+ { 0, 0, 0, 0 }
+};
+
+static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_gr_names_entries[] =
+{
+ { "sb", 9, {0, {{{0, 0}}}}, 0, 0 },
+ { "sl", 10, {0, {{{0, 0}}}}, 0, 0 },
+ { "fp", 11, {0, {{{0, 0}}}}, 0, 0 },
+ { "ip", 12, {0, {{{0, 0}}}}, 0, 0 },
+ { "sp", 13, {0, {{{0, 0}}}}, 0, 0 },
+ { "lr", 14, {0, {{{0, 0}}}}, 0, 0 },
+ { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+ { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
+ { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
+ { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
+ { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
+ { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
+ { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
+ { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
+ { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
+ { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
+ { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
+ { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
+ { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
+ { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
+ { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
+ { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
+ { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
+ { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
+ { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
+ { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
+ { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
+ { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
+ { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
+ { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
+ { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
+ { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
+ { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
+ { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
+ { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
+ { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
+ { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
+ { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
+ { "r32", 32, {0, {{{0, 0}}}}, 0, 0 },
+ { "r33", 33, {0, {{{0, 0}}}}, 0, 0 },
+ { "r34", 34, {0, {{{0, 0}}}}, 0, 0 },
+ { "r35", 35, {0, {{{0, 0}}}}, 0, 0 },
+ { "r36", 36, {0, {{{0, 0}}}}, 0, 0 },
+ { "r37", 37, {0, {{{0, 0}}}}, 0, 0 },
+ { "r38", 38, {0, {{{0, 0}}}}, 0, 0 },
+ { "r39", 39, {0, {{{0, 0}}}}, 0, 0 },
+ { "r40", 40, {0, {{{0, 0}}}}, 0, 0 },
+ { "r41", 41, {0, {{{0, 0}}}}, 0, 0 },
+ { "r42", 42, {0, {{{0, 0}}}}, 0, 0 },
+ { "r43", 43, {0, {{{0, 0}}}}, 0, 0 },
+ { "r44", 44, {0, {{{0, 0}}}}, 0, 0 },
+ { "r45", 45, {0, {{{0, 0}}}}, 0, 0 },
+ { "r46", 46, {0, {{{0, 0}}}}, 0, 0 },
+ { "r47", 47, {0, {{{0, 0}}}}, 0, 0 },
+ { "r48", 48, {0, {{{0, 0}}}}, 0, 0 },
+ { "r49", 49, {0, {{{0, 0}}}}, 0, 0 },
+ { "r50", 50, {0, {{{0, 0}}}}, 0, 0 },
+ { "r51", 51, {0, {{{0, 0}}}}, 0, 0 },
+ { "r52", 52, {0, {{{0, 0}}}}, 0, 0 },
+ { "r53", 53, {0, {{{0, 0}}}}, 0, 0 },
+ { "r54", 54, {0, {{{0, 0}}}}, 0, 0 },
+ { "r55", 55, {0, {{{0, 0}}}}, 0, 0 },
+ { "r56", 56, {0, {{{0, 0}}}}, 0, 0 },
+ { "r57", 57, {0, {{{0, 0}}}}, 0, 0 },
+ { "r58", 58, {0, {{{0, 0}}}}, 0, 0 },
+ { "r59", 59, {0, {{{0, 0}}}}, 0, 0 },
+ { "r60", 60, {0, {{{0, 0}}}}, 0, 0 },
+ { "r61", 61, {0, {{{0, 0}}}}, 0, 0 },
+ { "r62", 62, {0, {{{0, 0}}}}, 0, 0 },
+ { "r63", 63, {0, {{{0, 0}}}}, 0, 0 },
+ { "a1", 0, {0, {{{0, 0}}}}, 0, 0 },
+ { "a2", 1, {0, {{{0, 0}}}}, 0, 0 },
+ { "a3", 2, {0, {{{0, 0}}}}, 0, 0 },
+ { "a4", 3, {0, {{{0, 0}}}}, 0, 0 },
+ { "v1", 4, {0, {{{0, 0}}}}, 0, 0 },
+ { "v2", 5, {0, {{{0, 0}}}}, 0, 0 },
+ { "v3", 6, {0, {{{0, 0}}}}, 0, 0 },
+ { "v4", 7, {0, {{{0, 0}}}}, 0, 0 },
+ { "v5", 8, {0, {{{0, 0}}}}, 0, 0 },
+ { "v6", 9, {0, {{{0, 0}}}}, 0, 0 },
+ { "v7", 10, {0, {{{0, 0}}}}, 0, 0 },
+ { "v8", 11, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD epiphany_cgen_opval_gr_names =
+{
+ & epiphany_cgen_opval_gr_names_entries[0],
+ 82,
+ 0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_cr_names_entries[] =
+{
+ { "config", 0, {0, {{{0, 0}}}}, 0, 0 },
+ { "status", 1, {0, {{{0, 0}}}}, 0, 0 },
+ { "pc", 2, {0, {{{0, 0}}}}, 0, 0 },
+ { "debug", 3, {0, {{{0, 0}}}}, 0, 0 },
+ { "iab", 4, {0, {{{0, 0}}}}, 0, 0 },
+ { "lc", 5, {0, {{{0, 0}}}}, 0, 0 },
+ { "ls", 6, {0, {{{0, 0}}}}, 0, 0 },
+ { "le", 7, {0, {{{0, 0}}}}, 0, 0 },
+ { "iret", 8, {0, {{{0, 0}}}}, 0, 0 },
+ { "imask", 9, {0, {{{0, 0}}}}, 0, 0 },
+ { "ilat", 10, {0, {{{0, 0}}}}, 0, 0 },
+ { "ilatst", 11, {0, {{{0, 0}}}}, 0, 0 },
+ { "ilatcl", 12, {0, {{{0, 0}}}}, 0, 0 },
+ { "ipend", 13, {0, {{{0, 0}}}}, 0, 0 },
+ { "ctimer0", 14, {0, {{{0, 0}}}}, 0, 0 },
+ { "ctimer1", 15, {0, {{{0, 0}}}}, 0, 0 },
+ { "hstatus", 16, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD epiphany_cgen_opval_cr_names =
+{
+ & epiphany_cgen_opval_cr_names_entries[0],
+ 17,
+ 0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_crdma_names_entries[] =
+{
+ { "dma0config", 0, {0, {{{0, 0}}}}, 0, 0 },
+ { "dma0stride", 1, {0, {{{0, 0}}}}, 0, 0 },
+ { "dma0count", 2, {0, {{{0, 0}}}}, 0, 0 },
+ { "dma0srcaddr", 3, {0, {{{0, 0}}}}, 0, 0 },
+ { "dma0dstaddr", 4, {0, {{{0, 0}}}}, 0, 0 },
+ { "dma0auto0", 5, {0, {{{0, 0}}}}, 0, 0 },
+ { "dma0auto1", 6, {0, {{{0, 0}}}}, 0, 0 },
+ { "dma0status", 7, {0, {{{0, 0}}}}, 0, 0 },
+ { "dma1config", 8, {0, {{{0, 0}}}}, 0, 0 },
+ { "dma1stride", 9, {0, {{{0, 0}}}}, 0, 0 },
+ { "dma1count", 10, {0, {{{0, 0}}}}, 0, 0 },
+ { "dma1srcaddr", 11, {0, {{{0, 0}}}}, 0, 0 },
+ { "dma1dstaddr", 12, {0, {{{0, 0}}}}, 0, 0 },
+ { "dma1auto0", 13, {0, {{{0, 0}}}}, 0, 0 },
+ { "dma1auto1", 14, {0, {{{0, 0}}}}, 0, 0 },
+ { "dma1status", 15, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD epiphany_cgen_opval_crdma_names =
+{
+ & epiphany_cgen_opval_crdma_names_entries[0],
+ 16,
+ 0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_crmem_names_entries[] =
+{
+ { "memconfig", 0, {0, {{{0, 0}}}}, 0, 0 },
+ { "memstatus", 1, {0, {{{0, 0}}}}, 0, 0 },
+ { "memprotect", 2, {0, {{{0, 0}}}}, 0, 0 },
+ { "memreserve", 3, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD epiphany_cgen_opval_crmem_names =
+{
+ & epiphany_cgen_opval_crmem_names_entries[0],
+ 4,
+ 0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_crmesh_names_entries[] =
+{
+ { "meshconfig", 0, {0, {{{0, 0}}}}, 0, 0 },
+ { "coreid", 1, {0, {{{0, 0}}}}, 0, 0 },
+ { "meshmulticast", 2, {0, {{{0, 0}}}}, 0, 0 },
+ { "swreset", 3, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD epiphany_cgen_opval_crmesh_names =
+{
+ & epiphany_cgen_opval_crmesh_names_entries[0],
+ 4,
+ 0, 0, 0, 0, ""
+};
+
+
+/* The hardware table. */
+
+#define A(a) (1 << CGEN_HW_##a)
+
+const CGEN_HW_ENTRY epiphany_cgen_hw_table[] =
+{
+ { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-registers", HW_H_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-fpregisters", HW_H_FPREGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-vsbit", HW_H_VSBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-bzbit", HW_H_BZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-bnbit", HW_H_BNBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-bvbit", HW_H_BVBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-bubit", HW_H_BUBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-bibit", HW_H_BIBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-bcbit", HW_H_BCBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-bvsbit", HW_H_BVSBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-bisbit", HW_H_BISBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-busbit", HW_H_BUSBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-expcause0bit", HW_H_EXPCAUSE0BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-expcause1bit", HW_H_EXPCAUSE1BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-expcause2bit", HW_H_EXPCAUSE2BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-extFstallbit", HW_H_EXTFSTALLBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-trmbit", HW_H_TRMBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-invExcEnbit", HW_H_INVEXCENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-ovfExcEnbit", HW_H_OVFEXCENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-unExcEnbit", HW_H_UNEXCENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-timer0bit0", HW_H_TIMER0BIT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-timer0bit1", HW_H_TIMER0BIT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-timer0bit2", HW_H_TIMER0BIT2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-timer0bit3", HW_H_TIMER0BIT3, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-timer1bit0", HW_H_TIMER1BIT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-timer1bit1", HW_H_TIMER1BIT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-timer1bit2", HW_H_TIMER1BIT2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-timer1bit3", HW_H_TIMER1BIT3, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-mbkptEnbit", HW_H_MBKPTENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-clockGateEnbit", HW_H_CLOCKGATEENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-coreCfgResBit12", HW_H_CORECFGRESBIT12, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-coreCfgResBit13", HW_H_CORECFGRESBIT13, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-coreCfgResBit14", HW_H_CORECFGRESBIT14, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-coreCfgResBit15", HW_H_CORECFGRESBIT15, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-coreCfgResBit16", HW_H_CORECFGRESBIT16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-coreCfgResBit20", HW_H_CORECFGRESBIT20, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-coreCfgResBit21", HW_H_CORECFGRESBIT21, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-coreCfgResBit24", HW_H_CORECFGRESBIT24, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-coreCfgResBit25", HW_H_CORECFGRESBIT25, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-coreCfgResBit26", HW_H_CORECFGRESBIT26, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-coreCfgResBit27", HW_H_CORECFGRESBIT27, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-coreCfgResBit28", HW_H_CORECFGRESBIT28, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-coreCfgResBit29", HW_H_CORECFGRESBIT29, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-coreCfgResBit30", HW_H_CORECFGRESBIT30, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-coreCfgResBit31", HW_H_CORECFGRESBIT31, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-arithmetic-modebit0", HW_H_ARITHMETIC_MODEBIT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-arithmetic-modebit1", HW_H_ARITHMETIC_MODEBIT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-arithmetic-modebit2", HW_H_ARITHMETIC_MODEBIT2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-gidisablebit", HW_H_GIDISABLEBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-kmbit", HW_H_KMBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-caibit", HW_H_CAIBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-sflagbit", HW_H_SFLAGBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-memaddr", HW_H_MEMADDR, CGEN_ASM_NONE, 0, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-core-registers", HW_H_CORE_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-coredma-registers", HW_H_COREDMA_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_crdma_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-coremem-registers", HW_H_COREMEM_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_crmem_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-coremesh-registers", HW_H_COREMESH_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_crmesh_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
+};
+
+#undef A
+
+
+/* The instruction field table. */
+
+#define A(a) (1 << CGEN_IFLD_##a)
+
+const CGEN_IFLD epiphany_cgen_ifld_table[] =
+{
+ { EPIPHANY_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_OPC, "f-opc", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_OPC_4_1, "f-opc-4-1", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_OPC_6_3, "f-opc-6-3", 0, 32, 6, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_OPC_8_5, "f-opc-8-5", 0, 32, 8, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_OPC_19_4, "f-opc-19-4", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_CONDCODE, "f-condcode", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_SECONDARY_CCS, "f-secondary-ccs", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_SHIFT, "f-shift", 0, 32, 9, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_WORDSIZE, "f-wordsize", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_STORE, "f-store", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_OPC_8_1, "f-opc-8-1", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_OPC_31_32, "f-opc-31-32", 0, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_SIMM8, "f-simm8", 0, 32, 15, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_SIMM24, "f-simm24", 0, 32, 31, 24, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_SDISP3, "f-sdisp3", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DISP3, "f-disp3", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DISP8, "f-disp8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_IMM8, "f-imm8", 0, 32, 12, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_IMM_27_8, "f-imm-27-8", 0, 32, 27, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_ADDSUBX, "f-addsubx", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_SUBD, "f-subd", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_PM, "f-pm", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_RM, "f-rm", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_RN, "f-rn", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_RD, "f-rd", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_RM_X, "f-rm-x", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_RN_X, "f-rn-x", 0, 32, 28, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_RD_X, "f-rd-x", 0, 32, 31, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DC_9_1, "f-dc-9-1", 0, 32, 9, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_SN, "f-sn", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_SD, "f-sd", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_SN_X, "f-sn-x", 0, 32, 28, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_SD_X, "f-sd-x", 0, 32, 31, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DC_7_4, "f-dc-7-4", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_TRAP_SWI_9_1, "f-trap-swi-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_GIEN_GIDIS_9_1, "f-gien-gidis-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DC_15_3, "f-dc-15-3", 0, 32, 15, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DC_15_7, "f-dc-15-7", 0, 32, 15, 7, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DC_15_6, "f-dc-15-6", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_TRAP_NUM, "f-trap-num", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DC_20_1, "f-dc-20-1", 0, 32, 20, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DC_21_1, "f-dc-21-1", 0, 32, 21, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DC_21_2, "f-dc-21-2", 0, 32, 21, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DC_22_3, "f-dc-22-3", 0, 32, 22, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DC_22_2, "f-dc-22-2", 0, 32, 22, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DC_22_1, "f-dc-22-1", 0, 32, 22, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DC_25_6, "f-dc-25-6", 0, 32, 25, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DC_25_4, "f-dc-25-4", 0, 32, 25, 4, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DC_25_2, "f-dc-25-2", 0, 32, 25, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DC_25_1, "f-dc-25-1", 0, 32, 25, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DC_28_1, "f-dc-28-1", 0, 32, 28, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DC_31_3, "f-dc-31-3", 0, 32, 31, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_DISP11, "f-disp11", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_SDISP11, "f-sdisp11", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_IMM16, "f-imm16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_RD6, "f-rd6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_RN6, "f-rn6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_RM6, "f-rm6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_SD6, "f-sd6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ { EPIPHANY_F_SN6, "f-sn6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
+};
+
+#undef A
+
+
+
+/* multi ifield declarations */
+
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_DISP11_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SDISP11_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_IMM16_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RD6_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RN6_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RM6_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SD6_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SN6_MULTI_IFIELD [];
+
+
+/* multi ifield definitions */
+
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_DISP11_MULTI_IFIELD [] =
+{
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP8] } },
+ { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SDISP11_MULTI_IFIELD [] =
+{
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP8] } },
+ { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_IMM16_MULTI_IFIELD [] =
+{
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM_27_8] } },
+ { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RD6_MULTI_IFIELD [] =
+{
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD_X] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
+ { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RN6_MULTI_IFIELD [] =
+{
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN_X] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
+ { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RM6_MULTI_IFIELD [] =
+{
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM_X] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
+ { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SD6_MULTI_IFIELD [] =
+{
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD_X] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } },
+ { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SN6_MULTI_IFIELD [] =
+{
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN_X] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } },
+ { 0, { (const PTR) 0 } }
+};
+
+/* The operand table. */
+
+#define A(a) (1 << CGEN_OPERAND_##a)
+#define OPERAND(op) EPIPHANY_OPERAND_##op
+
+const CGEN_OPERAND epiphany_cgen_operand_table[] =
+{
+/* pc: program counter */
+ { "pc", EPIPHANY_OPERAND_PC, HW_H_PC, 0, 0,
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_NIL] } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* zbit: integer zero bit */
+ { "zbit", EPIPHANY_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* nbit: integer neg bit */
+ { "nbit", EPIPHANY_OPERAND_NBIT, HW_H_NBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* cbit: integer carry bit */
+ { "cbit", EPIPHANY_OPERAND_CBIT, HW_H_CBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* vbit: integer overflow bit */
+ { "vbit", EPIPHANY_OPERAND_VBIT, HW_H_VBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* bzbit: floating point zero bit */
+ { "bzbit", EPIPHANY_OPERAND_BZBIT, HW_H_BZBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* bnbit: floating point neg bit */
+ { "bnbit", EPIPHANY_OPERAND_BNBIT, HW_H_BNBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* bvbit: floating point ovfl bit */
+ { "bvbit", EPIPHANY_OPERAND_BVBIT, HW_H_BVBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* bcbit: floating point carry bit */
+ { "bcbit", EPIPHANY_OPERAND_BCBIT, HW_H_BCBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* bubit: floating point underfl bit */
+ { "bubit", EPIPHANY_OPERAND_BUBIT, HW_H_BUBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* bibit: floating point invalid bit */
+ { "bibit", EPIPHANY_OPERAND_BIBIT, HW_H_BIBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* vsbit: integer overflow sticky */
+ { "vsbit", EPIPHANY_OPERAND_VSBIT, HW_H_VSBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* bvsbit: floating point overflow sticky */
+ { "bvsbit", EPIPHANY_OPERAND_BVSBIT, HW_H_BVSBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* bisbit: floating point invalid sticky */
+ { "bisbit", EPIPHANY_OPERAND_BISBIT, HW_H_BISBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* busbit: floating point underflow sticky */
+ { "busbit", EPIPHANY_OPERAND_BUSBIT, HW_H_BUSBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* expcause0bit: exceprion cause bit0 */
+ { "expcause0bit", EPIPHANY_OPERAND_EXPCAUSE0BIT, HW_H_EXPCAUSE0BIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* expcause1bit: exceprion cause bit1 */
+ { "expcause1bit", EPIPHANY_OPERAND_EXPCAUSE1BIT, HW_H_EXPCAUSE1BIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* expcause2bit: external load stalled bit */
+ { "expcause2bit", EPIPHANY_OPERAND_EXPCAUSE2BIT, HW_H_EXPCAUSE2BIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* extFstallbit: external fetch stalled bit */
+ { "extFstallbit", EPIPHANY_OPERAND_EXTFSTALLBIT, HW_H_EXTFSTALLBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* trmbit: 0=round to nearest, 1=trunacte selct bit */
+ { "trmbit", EPIPHANY_OPERAND_TRMBIT, HW_H_TRMBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* invExcEnbit: invalid exception enable bit */
+ { "invExcEnbit", EPIPHANY_OPERAND_INVEXCENBIT, HW_H_INVEXCENBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* ovfExcEnbit: overflow exception enable bit */
+ { "ovfExcEnbit", EPIPHANY_OPERAND_OVFEXCENBIT, HW_H_OVFEXCENBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* unExcEnbit: underflow exception enable bit */
+ { "unExcEnbit", EPIPHANY_OPERAND_UNEXCENBIT, HW_H_UNEXCENBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* timer0bit0: timer 0 mode selection 0 */
+ { "timer0bit0", EPIPHANY_OPERAND_TIMER0BIT0, HW_H_TIMER0BIT0, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* timer0bit1: timer 0 mode selection 1 */
+ { "timer0bit1", EPIPHANY_OPERAND_TIMER0BIT1, HW_H_TIMER0BIT1, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* timer0bit2: timer 0 mode selection 2 */
+ { "timer0bit2", EPIPHANY_OPERAND_TIMER0BIT2, HW_H_TIMER0BIT2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* timer0bit3: timer 0 mode selection 3 */
+ { "timer0bit3", EPIPHANY_OPERAND_TIMER0BIT3, HW_H_TIMER0BIT3, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* timer1bit0: timer 1 mode selection 0 */
+ { "timer1bit0", EPIPHANY_OPERAND_TIMER1BIT0, HW_H_TIMER1BIT0, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* timer1bit1: timer 1 mode selection 1 */
+ { "timer1bit1", EPIPHANY_OPERAND_TIMER1BIT1, HW_H_TIMER1BIT1, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* timer1bit2: timer 1 mode selection 2 */
+ { "timer1bit2", EPIPHANY_OPERAND_TIMER1BIT2, HW_H_TIMER1BIT2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* timer1bit3: timer 1 mode selection 3 */
+ { "timer1bit3", EPIPHANY_OPERAND_TIMER1BIT3, HW_H_TIMER1BIT3, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* mbkptEnbit: multicore bkpt enable */
+ { "mbkptEnbit", EPIPHANY_OPERAND_MBKPTENBIT, HW_H_MBKPTENBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* clockGateEnbit: clock gate enable enable */
+ { "clockGateEnbit", EPIPHANY_OPERAND_CLOCKGATEENBIT, HW_H_CLOCKGATEENBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* arithmetic-modebit0: arithmetic mode bit0 */
+ { "arithmetic-modebit0", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT0, HW_H_ARITHMETIC_MODEBIT0, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* arithmetic-modebit1: arithmetic mode bit1 */
+ { "arithmetic-modebit1", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT1, HW_H_ARITHMETIC_MODEBIT1, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* arithmetic-modebit2: arithmetic mode bit2 */
+ { "arithmetic-modebit2", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT2, HW_H_ARITHMETIC_MODEBIT2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* coreCfgResBit12: core config bit 12 */
+ { "coreCfgResBit12", EPIPHANY_OPERAND_CORECFGRESBIT12, HW_H_CORECFGRESBIT12, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* coreCfgResBit13: core config bit 13 */
+ { "coreCfgResBit13", EPIPHANY_OPERAND_CORECFGRESBIT13, HW_H_CORECFGRESBIT13, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* coreCfgResBit14: core config bit 14 */
+ { "coreCfgResBit14", EPIPHANY_OPERAND_CORECFGRESBIT14, HW_H_CORECFGRESBIT14, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* coreCfgResBit15: core config bit 15 */
+ { "coreCfgResBit15", EPIPHANY_OPERAND_CORECFGRESBIT15, HW_H_CORECFGRESBIT15, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* coreCfgResBit16: core config bit 16 */
+ { "coreCfgResBit16", EPIPHANY_OPERAND_CORECFGRESBIT16, HW_H_CORECFGRESBIT16, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* coreCfgResBit20: core config bit 20 */
+ { "coreCfgResBit20", EPIPHANY_OPERAND_CORECFGRESBIT20, HW_H_CORECFGRESBIT20, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* coreCfgResBit21: core config bit 21 */
+ { "coreCfgResBit21", EPIPHANY_OPERAND_CORECFGRESBIT21, HW_H_CORECFGRESBIT21, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* coreCfgResBit24: core config bit 24 */
+ { "coreCfgResBit24", EPIPHANY_OPERAND_CORECFGRESBIT24, HW_H_CORECFGRESBIT24, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* coreCfgResBit25: core config bit 25 */
+ { "coreCfgResBit25", EPIPHANY_OPERAND_CORECFGRESBIT25, HW_H_CORECFGRESBIT25, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* coreCfgResBit26: core config bit 26 */
+ { "coreCfgResBit26", EPIPHANY_OPERAND_CORECFGRESBIT26, HW_H_CORECFGRESBIT26, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* coreCfgResBit27: core config bit 27 */
+ { "coreCfgResBit27", EPIPHANY_OPERAND_CORECFGRESBIT27, HW_H_CORECFGRESBIT27, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* coreCfgResBit28: core config bit 28 */
+ { "coreCfgResBit28", EPIPHANY_OPERAND_CORECFGRESBIT28, HW_H_CORECFGRESBIT28, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* coreCfgResBit29: core config bit 29 */
+ { "coreCfgResBit29", EPIPHANY_OPERAND_CORECFGRESBIT29, HW_H_CORECFGRESBIT29, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* coreCfgResBit30: core config bit 30 */
+ { "coreCfgResBit30", EPIPHANY_OPERAND_CORECFGRESBIT30, HW_H_CORECFGRESBIT30, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* coreCfgResBit31: core config bit 31 */
+ { "coreCfgResBit31", EPIPHANY_OPERAND_CORECFGRESBIT31, HW_H_CORECFGRESBIT31, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* gidisablebit: global interrupt disable bit */
+ { "gidisablebit", EPIPHANY_OPERAND_GIDISABLEBIT, HW_H_GIDISABLEBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* kmbit: kernel mode bit */
+ { "kmbit", EPIPHANY_OPERAND_KMBIT, HW_H_KMBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* caibit: core actibe indicator bit */
+ { "caibit", EPIPHANY_OPERAND_CAIBIT, HW_H_CAIBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* sflagbit: sflag bit */
+ { "sflagbit", EPIPHANY_OPERAND_SFLAGBIT, HW_H_SFLAGBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* memaddr: memory effective address */
+ { "memaddr", EPIPHANY_OPERAND_MEMADDR, HW_H_MEMADDR, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+/* simm24: branch address pc-relative */
+ { "simm24", EPIPHANY_OPERAND_SIMM24, HW_H_IADDR, 31, 24,
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM24] } },
+ { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+/* simm8: branch address pc-relative */
+ { "simm8", EPIPHANY_OPERAND_SIMM8, HW_H_IADDR, 15, 8,
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM8] } },
+ { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+/* rd: destination register */
+ { "rd", EPIPHANY_OPERAND_RD, HW_H_REGISTERS, 15, 3,
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+/* rn: source register */
+ { "rn", EPIPHANY_OPERAND_RN, HW_H_REGISTERS, 12, 3,
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+/* rm: source register */
+ { "rm", EPIPHANY_OPERAND_RM, HW_H_REGISTERS, 9, 3,
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+/* frd: fp destination register */
+ { "frd", EPIPHANY_OPERAND_FRD, HW_H_FPREGISTERS, 15, 3,
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+/* frn: fp source register */
+ { "frn", EPIPHANY_OPERAND_FRN, HW_H_FPREGISTERS, 12, 3,
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+/* frm: fp source register */
+ { "frm", EPIPHANY_OPERAND_FRM, HW_H_FPREGISTERS, 9, 3,
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+/* rd6: destination register */
+ { "rd6", EPIPHANY_OPERAND_RD6, HW_H_REGISTERS, 15, 6,
+ { 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+/* rn6: source register */
+ { "rn6", EPIPHANY_OPERAND_RN6, HW_H_REGISTERS, 12, 6,
+ { 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+/* rm6: source register */
+ { "rm6", EPIPHANY_OPERAND_RM6, HW_H_REGISTERS, 9, 6,
+ { 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+/* frd6: fp destination register */
+ { "frd6", EPIPHANY_OPERAND_FRD6, HW_H_FPREGISTERS, 15, 6,
+ { 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+/* frn6: fp source register */
+ { "frn6", EPIPHANY_OPERAND_FRN6, HW_H_FPREGISTERS, 12, 6,
+ { 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+/* frm6: fp source register */
+ { "frm6", EPIPHANY_OPERAND_FRM6, HW_H_FPREGISTERS, 9, 6,
+ { 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+/* sd: special destination */
+ { "sd", EPIPHANY_OPERAND_SD, HW_H_CORE_REGISTERS, 15, 3,
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+/* sn: special source */
+ { "sn", EPIPHANY_OPERAND_SN, HW_H_CORE_REGISTERS, 12, 3,
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+/* sd6: special destination register */
+ { "sd6", EPIPHANY_OPERAND_SD6, HW_H_CORE_REGISTERS, 15, 6,
+ { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+/* sn6: special source register */
+ { "sn6", EPIPHANY_OPERAND_SN6, HW_H_CORE_REGISTERS, 12, 6,
+ { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+/* sddma: dma register */
+ { "sddma", EPIPHANY_OPERAND_SDDMA, HW_H_COREDMA_REGISTERS, 15, 6,
+ { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+/* sndma: dma register */
+ { "sndma", EPIPHANY_OPERAND_SNDMA, HW_H_COREDMA_REGISTERS, 12, 6,
+ { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+/* sdmem: mem register */
+ { "sdmem", EPIPHANY_OPERAND_SDMEM, HW_H_COREMEM_REGISTERS, 15, 6,
+ { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+/* snmem: mem register */
+ { "snmem", EPIPHANY_OPERAND_SNMEM, HW_H_COREMEM_REGISTERS, 12, 6,
+ { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+/* sdmesh: mesh register */
+ { "sdmesh", EPIPHANY_OPERAND_SDMESH, HW_H_COREMESH_REGISTERS, 15, 6,
+ { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+/* snmesh: mesh register */
+ { "snmesh", EPIPHANY_OPERAND_SNMESH, HW_H_COREMESH_REGISTERS, 12, 6,
+ { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+/* simm3: signed 3-bit literal */
+ { "simm3", EPIPHANY_OPERAND_SIMM3, HW_H_SINT, 9, 3,
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SDISP3] } },
+ { 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } } },
+/* simm11: signed 11-bit literal */
+ { "simm11", EPIPHANY_OPERAND_SIMM11, HW_H_SINT, 9, 11,
+ { 2, { (const PTR) &EPIPHANY_F_SDISP11_MULTI_IFIELD[0] } },
+ { 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+/* disp3: short data displacement */
+ { "disp3", EPIPHANY_OPERAND_DISP3, HW_H_UINT, 9, 3,
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+/* trapnum6: parameter for swi or trap */
+ { "trapnum6", EPIPHANY_OPERAND_TRAPNUM6, HW_H_UINT, 15, 6,
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+/* swi_num: unsigned 6-bit swi# */
+ { "swi_num", EPIPHANY_OPERAND_SWI_NUM, HW_H_UINT, 15, 6,
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+/* disp11: sign-magnitude data displacement */
+ { "disp11", EPIPHANY_OPERAND_DISP11, HW_H_UINT, 9, 11,
+ { 2, { (const PTR) &EPIPHANY_F_DISP11_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+/* shift: immediate shift amount */
+ { "shift", EPIPHANY_OPERAND_SHIFT, HW_H_UINT, 9, 5,
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SHIFT] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+/* imm16: 16-bit unsigned literal */
+ { "imm16", EPIPHANY_OPERAND_IMM16, HW_H_ADDR, 12, 16,
+ { 2, { (const PTR) &EPIPHANY_F_IMM16_MULTI_IFIELD[0] } },
+ { 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+/* imm8: 8-bit unsigned literal */
+ { "imm8", EPIPHANY_OPERAND_IMM8, HW_H_ADDR, 12, 8,
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } },
+ { 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } } },
+/* direction: +/- indexing */
+ { "direction", EPIPHANY_OPERAND_DIRECTION, HW_H_UINT, 20, 1,
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_ADDSUBX] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+/* dpmi: +/- magnitude immediate displacement */
+ { "dpmi", EPIPHANY_OPERAND_DPMI, HW_H_UINT, 24, 1,
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SUBD] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+/* sentinel */
+ { 0, 0, 0, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } }
+};
+
+#undef A
+
+
+/* The instruction table. */
+
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+#define A(a) (1 << CGEN_INSN_##a)
+
+static const CGEN_IBASE epiphany_cgen_insn_table[MAX_INSNS] =
+{
+ /* Special null first entry.
+ A `num' value of zero is thus invalid.
+ Also, the special `invalid' insn resides here. */
+ { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+/* beq.s $simm8 */
+ {
+ EPIPHANY_INSN_BEQ16, "beq16", "beq.s", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* beq.l $simm24 */
+ {
+ EPIPHANY_INSN_BEQ, "beq", "beq.l", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bne.s $simm8 */
+ {
+ EPIPHANY_INSN_BNE16, "bne16", "bne.s", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bne.l $simm24 */
+ {
+ EPIPHANY_INSN_BNE, "bne", "bne.l", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bgtu.s $simm8 */
+ {
+ EPIPHANY_INSN_BGTU16, "bgtu16", "bgtu.s", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bgtu.l $simm24 */
+ {
+ EPIPHANY_INSN_BGTU, "bgtu", "bgtu.l", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bgteu.s $simm8 */
+ {
+ EPIPHANY_INSN_BGTEU16, "bgteu16", "bgteu.s", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bgteu.l $simm24 */
+ {
+ EPIPHANY_INSN_BGTEU, "bgteu", "bgteu.l", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* blteu.s $simm8 */
+ {
+ EPIPHANY_INSN_BLTEU16, "blteu16", "blteu.s", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* blteu.l $simm24 */
+ {
+ EPIPHANY_INSN_BLTEU, "blteu", "blteu.l", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bltu.s $simm8 */
+ {
+ EPIPHANY_INSN_BLTU16, "bltu16", "bltu.s", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bltu.l $simm24 */
+ {
+ EPIPHANY_INSN_BLTU, "bltu", "bltu.l", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bgt.s $simm8 */
+ {
+ EPIPHANY_INSN_BGT16, "bgt16", "bgt.s", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bgt.l $simm24 */
+ {
+ EPIPHANY_INSN_BGT, "bgt", "bgt.l", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bgte.s $simm8 */
+ {
+ EPIPHANY_INSN_BGTE16, "bgte16", "bgte.s", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bgte.l $simm24 */
+ {
+ EPIPHANY_INSN_BGTE, "bgte", "bgte.l", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* blt.s $simm8 */
+ {
+ EPIPHANY_INSN_BLT16, "blt16", "blt.s", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* blt.l $simm24 */
+ {
+ EPIPHANY_INSN_BLT, "blt", "blt.l", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* blte.s $simm8 */
+ {
+ EPIPHANY_INSN_BLTE16, "blte16", "blte.s", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* blte.l $simm24 */
+ {
+ EPIPHANY_INSN_BLTE, "blte", "blte.l", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bbeq.s $simm8 */
+ {
+ EPIPHANY_INSN_BBEQ16, "bbeq16", "bbeq.s", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bbeq.l $simm24 */
+ {
+ EPIPHANY_INSN_BBEQ, "bbeq", "bbeq.l", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bbne.s $simm8 */
+ {
+ EPIPHANY_INSN_BBNE16, "bbne16", "bbne.s", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bbne.l $simm24 */
+ {
+ EPIPHANY_INSN_BBNE, "bbne", "bbne.l", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bblt.s $simm8 */
+ {
+ EPIPHANY_INSN_BBLT16, "bblt16", "bblt.s", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bblt.l $simm24 */
+ {
+ EPIPHANY_INSN_BBLT, "bblt", "bblt.l", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bblte.s $simm8 */
+ {
+ EPIPHANY_INSN_BBLTE16, "bblte16", "bblte.s", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bblte.l $simm24 */
+ {
+ EPIPHANY_INSN_BBLTE, "bblte", "bblte.l", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* b.s $simm8 */
+ {
+ EPIPHANY_INSN_B16, "b16", "b.s", 16,
+ { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* b.l $simm24 */
+ {
+ EPIPHANY_INSN_B, "b", "b.l", 32,
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bl.s $simm8 */
+ {
+ EPIPHANY_INSN_BL16, "bl16", "bl.s", 16,
+ { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bl.l $simm24 */
+ {
+ EPIPHANY_INSN_BL, "bl", "bl.l", 32,
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* jr $rn */
+ {
+ EPIPHANY_INSN_JR16, "jr16", "jr", 16,
+ { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* rts */
+ {
+ -1, "rts", "rts", 32,
+ { 0|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* jr $rn6 */
+ {
+ EPIPHANY_INSN_JR, "jr", "jr", 32,
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* jalr $rn */
+ {
+ EPIPHANY_INSN_JALR16, "jalr16", "jalr", 16,
+ { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* jalr $rn6 */
+ {
+ EPIPHANY_INSN_JALR, "jalr", "jalr", 32,
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrb $rd,[$rn,$rm] */
+ {
+ EPIPHANY_INSN_LDRBX16_S, "ldrbx16.s", "ldrb", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrb $rd,[$rn],$rm */
+ {
+ EPIPHANY_INSN_LDRBP16_S, "ldrbp16.s", "ldrb", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrb $rd6,[$rn6,$direction$rm6] */
+ {
+ EPIPHANY_INSN_LDRBX_L, "ldrbx.l", "ldrb", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrb $rd6,[$rn6],$direction$rm6 */
+ {
+ EPIPHANY_INSN_LDRBP_L, "ldrbp.l", "ldrb", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrb $rd,[$rn,$disp3] */
+ {
+ EPIPHANY_INSN_LDRBD16_S, "ldrbd16.s", "ldrb", 16,
+ { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrb $rd6,[$rn6,$dpmi$disp11] */
+ {
+ EPIPHANY_INSN_LDRBD_L, "ldrbd.l", "ldrb", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrb $rd6,[$rn6],$dpmi$disp11 */
+ {
+ EPIPHANY_INSN_LDRBDPM_L, "ldrbdpm.l", "ldrb", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrh $rd,[$rn,$rm] */
+ {
+ EPIPHANY_INSN_LDRHX16_S, "ldrhx16.s", "ldrh", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrh $rd,[$rn],$rm */
+ {
+ EPIPHANY_INSN_LDRHP16_S, "ldrhp16.s", "ldrh", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrh $rd6,[$rn6,$direction$rm6] */
+ {
+ EPIPHANY_INSN_LDRHX_L, "ldrhx.l", "ldrh", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrh $rd6,[$rn6],$direction$rm6 */
+ {
+ EPIPHANY_INSN_LDRHP_L, "ldrhp.l", "ldrh", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrh $rd,[$rn,$disp3] */
+ {
+ EPIPHANY_INSN_LDRHD16_S, "ldrhd16.s", "ldrh", 16,
+ { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrh $rd6,[$rn6,$dpmi$disp11] */
+ {
+ EPIPHANY_INSN_LDRHD_L, "ldrhd.l", "ldrh", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrh $rd6,[$rn6],$dpmi$disp11 */
+ {
+ EPIPHANY_INSN_LDRHDPM_L, "ldrhdpm.l", "ldrh", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldr $rd,[$rn,$rm] */
+ {
+ EPIPHANY_INSN_LDRX16_S, "ldrx16.s", "ldr", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldr $rd,[$rn],$rm */
+ {
+ EPIPHANY_INSN_LDRP16_S, "ldrp16.s", "ldr", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldr $rd6,[$rn6,$direction$rm6] */
+ {
+ EPIPHANY_INSN_LDRX_L, "ldrx.l", "ldr", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldr $rd6,[$rn6],$direction$rm6 */
+ {
+ EPIPHANY_INSN_LDRP_L, "ldrp.l", "ldr", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldr $rd,[$rn,$disp3] */
+ {
+ EPIPHANY_INSN_LDRD16_S, "ldrd16.s", "ldr", 16,
+ { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldr $rd6,[$rn6,$dpmi$disp11] */
+ {
+ EPIPHANY_INSN_LDRD_L, "ldrd.l", "ldr", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldr $rd6,[$rn6],$dpmi$disp11 */
+ {
+ EPIPHANY_INSN_LDRDPM_L, "ldrdpm.l", "ldr", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrd $rd,[$rn,$rm] */
+ {
+ EPIPHANY_INSN_LDRDX16_S, "ldrdx16.s", "ldrd", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrd $rd,[$rn],$rm */
+ {
+ EPIPHANY_INSN_LDRDP16_S, "ldrdp16.s", "ldrd", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrd $rd6,[$rn6,$direction$rm6] */
+ {
+ EPIPHANY_INSN_LDRDX_L, "ldrdx.l", "ldrd", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrd $rd6,[$rn6],$direction$rm6 */
+ {
+ EPIPHANY_INSN_LDRDP_L, "ldrdp.l", "ldrd", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrd $rd,[$rn,$disp3] */
+ {
+ EPIPHANY_INSN_LDRDD16_S, "ldrdd16.s", "ldrd", 16,
+ { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrd $rd6,[$rn6,$dpmi$disp11] */
+ {
+ EPIPHANY_INSN_LDRDD_L, "ldrdd.l", "ldrd", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrd $rd6,[$rn6],$dpmi$disp11 */
+ {
+ EPIPHANY_INSN_LDRDDPM_L, "ldrddpm.l", "ldrd", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* testsetb $rd6,[$rn6,$direction$rm6] */
+ {
+ EPIPHANY_INSN_TESTSETBT, "testsetbt", "testsetb", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* testseth $rd6,[$rn6,$direction$rm6] */
+ {
+ EPIPHANY_INSN_TESTSETHT, "testsetht", "testseth", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* testset $rd6,[$rn6,$direction$rm6] */
+ {
+ EPIPHANY_INSN_TESTSETT, "testsett", "testset", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strb $rd,[$rn,$rm] */
+ {
+ EPIPHANY_INSN_STRBX16, "strbx16", "strb", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strb $rd6,[$rn6,$direction$rm6] */
+ {
+ EPIPHANY_INSN_STRBX, "strbx", "strb", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strb $rd,[$rn],$rm */
+ {
+ EPIPHANY_INSN_STRBP16, "strbp16", "strb", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strb $rd6,[$rn6],$direction$rm6 */
+ {
+ EPIPHANY_INSN_STRBP, "strbp", "strb", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strb $rd,[$rn,$disp3] */
+ {
+ EPIPHANY_INSN_STRBD16, "strbd16", "strb", 16,
+ { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strb $rd6,[$rn6,$dpmi$disp11] */
+ {
+ EPIPHANY_INSN_STRBD, "strbd", "strb", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strb $rd6,[$rn6],$dpmi$disp11 */
+ {
+ EPIPHANY_INSN_STRBDPM, "strbdpm", "strb", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strh $rd,[$rn,$rm] */
+ {
+ EPIPHANY_INSN_STRHX16, "strhx16", "strh", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strh $rd6,[$rn6,$direction$rm6] */
+ {
+ EPIPHANY_INSN_STRHX, "strhx", "strh", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strh $rd,[$rn],$rm */
+ {
+ EPIPHANY_INSN_STRHP16, "strhp16", "strh", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strh $rd6,[$rn6],$direction$rm6 */
+ {
+ EPIPHANY_INSN_STRHP, "strhp", "strh", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strh $rd,[$rn,$disp3] */
+ {
+ EPIPHANY_INSN_STRHD16, "strhd16", "strh", 16,
+ { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strh $rd6,[$rn6,$dpmi$disp11] */
+ {
+ EPIPHANY_INSN_STRHD, "strhd", "strh", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strh $rd6,[$rn6],$dpmi$disp11 */
+ {
+ EPIPHANY_INSN_STRHDPM, "strhdpm", "strh", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* str $rd,[$rn,$rm] */
+ {
+ EPIPHANY_INSN_STRX16, "strx16", "str", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* str $rd6,[$rn6,$direction$rm6] */
+ {
+ EPIPHANY_INSN_STRX, "strx", "str", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* str $rd,[$rn],$rm */
+ {
+ EPIPHANY_INSN_STRP16, "strp16", "str", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* str $rd6,[$rn6],$direction$rm6 */
+ {
+ EPIPHANY_INSN_STRP, "strp", "str", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* str $rd,[$rn,$disp3] */
+ {
+ EPIPHANY_INSN_STRD16, "strd16", "str", 16,
+ { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* str $rd6,[$rn6,$dpmi$disp11] */
+ {
+ EPIPHANY_INSN_STRD, "strd", "str", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* str $rd6,[$rn6],$dpmi$disp11 */
+ {
+ EPIPHANY_INSN_STRDPM, "strdpm", "str", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strd $rd,[$rn,$rm] */
+ {
+ EPIPHANY_INSN_STRDX16, "strdx16", "strd", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strd $rd6,[$rn6,$direction$rm6] */
+ {
+ EPIPHANY_INSN_STRDX, "strdx", "strd", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strd $rd,[$rn],$rm */
+ {
+ EPIPHANY_INSN_STRDP16, "strdp16", "strd", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strd $rd6,[$rn6],$direction$rm6 */
+ {
+ EPIPHANY_INSN_STRDP, "strdp", "strd", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strd $rd,[$rn,$disp3] */
+ {
+ EPIPHANY_INSN_STRDD16, "strdd16", "strd", 16,
+ { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strd $rd6,[$rn6,$dpmi$disp11] */
+ {
+ EPIPHANY_INSN_STRDD, "strdd", "strd", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strd $rd6,[$rn6],$dpmi$disp11 */
+ {
+ EPIPHANY_INSN_STRDDPM, "strddpm", "strd", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* moveq $rd,$rn */
+ {
+ EPIPHANY_INSN_CMOV16EQ, "cmov16EQ", "moveq", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* moveq $rd6,$rn6 */
+ {
+ EPIPHANY_INSN_CMOVEQ, "cmovEQ", "moveq", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movne $rd,$rn */
+ {
+ EPIPHANY_INSN_CMOV16NE, "cmov16NE", "movne", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movne $rd6,$rn6 */
+ {
+ EPIPHANY_INSN_CMOVNE, "cmovNE", "movne", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movgtu $rd,$rn */
+ {
+ EPIPHANY_INSN_CMOV16GTU, "cmov16GTU", "movgtu", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movgtu $rd6,$rn6 */
+ {
+ EPIPHANY_INSN_CMOVGTU, "cmovGTU", "movgtu", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movgteu $rd,$rn */
+ {
+ EPIPHANY_INSN_CMOV16GTEU, "cmov16GTEU", "movgteu", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movgteu $rd6,$rn6 */
+ {
+ EPIPHANY_INSN_CMOVGTEU, "cmovGTEU", "movgteu", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movlteu $rd,$rn */
+ {
+ EPIPHANY_INSN_CMOV16LTEU, "cmov16LTEU", "movlteu", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movlteu $rd6,$rn6 */
+ {
+ EPIPHANY_INSN_CMOVLTEU, "cmovLTEU", "movlteu", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movltu $rd,$rn */
+ {
+ EPIPHANY_INSN_CMOV16LTU, "cmov16LTU", "movltu", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movltu $rd6,$rn6 */
+ {
+ EPIPHANY_INSN_CMOVLTU, "cmovLTU", "movltu", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movgt $rd,$rn */
+ {
+ EPIPHANY_INSN_CMOV16GT, "cmov16GT", "movgt", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movgt $rd6,$rn6 */
+ {
+ EPIPHANY_INSN_CMOVGT, "cmovGT", "movgt", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movgte $rd,$rn */
+ {
+ EPIPHANY_INSN_CMOV16GTE, "cmov16GTE", "movgte", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movgte $rd6,$rn6 */
+ {
+ EPIPHANY_INSN_CMOVGTE, "cmovGTE", "movgte", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movlt $rd,$rn */
+ {
+ EPIPHANY_INSN_CMOV16LT, "cmov16LT", "movlt", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movlt $rd6,$rn6 */
+ {
+ EPIPHANY_INSN_CMOVLT, "cmovLT", "movlt", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movlte $rd,$rn */
+ {
+ EPIPHANY_INSN_CMOV16LTE, "cmov16LTE", "movlte", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movlte $rd6,$rn6 */
+ {
+ EPIPHANY_INSN_CMOVLTE, "cmovLTE", "movlte", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* mov $rd,$rn */
+ {
+ EPIPHANY_INSN_CMOV16B, "cmov16B", "mov", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* mov $rd6,$rn6 */
+ {
+ EPIPHANY_INSN_CMOVB, "cmovB", "mov", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movbeq $rd,$rn */
+ {
+ EPIPHANY_INSN_CMOV16BEQ, "cmov16BEQ", "movbeq", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movbeq $rd6,$rn6 */
+ {
+ EPIPHANY_INSN_CMOVBEQ, "cmovBEQ", "movbeq", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movbne $rd,$rn */
+ {
+ EPIPHANY_INSN_CMOV16BNE, "cmov16BNE", "movbne", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movbne $rd6,$rn6 */
+ {
+ EPIPHANY_INSN_CMOVBNE, "cmovBNE", "movbne", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movblt $rd,$rn */
+ {
+ EPIPHANY_INSN_CMOV16BLT, "cmov16BLT", "movblt", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movblt $rd6,$rn6 */
+ {
+ EPIPHANY_INSN_CMOVBLT, "cmovBLT", "movblt", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movblte $rd,$rn */
+ {
+ EPIPHANY_INSN_CMOV16BLTE, "cmov16BLTE", "movblte", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movblte $rd6,$rn6 */
+ {
+ EPIPHANY_INSN_CMOVBLTE, "cmovBLTE", "movblte", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movts $sn,$rd */
+ {
+ EPIPHANY_INSN_MOVTS16, "movts16", "movts", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movts $sn6,$rd6 */
+ {
+ EPIPHANY_INSN_MOVTS6, "movts6", "movts", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movts $sndma,$rd6 */
+ {
+ EPIPHANY_INSN_MOVTSDMA, "movtsdma", "movts", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movts $snmem,$rd6 */
+ {
+ EPIPHANY_INSN_MOVTSMEM, "movtsmem", "movts", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movts $snmesh,$rd6 */
+ {
+ EPIPHANY_INSN_MOVTSMESH, "movtsmesh", "movts", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movfs $rd,$sn */
+ {
+ EPIPHANY_INSN_MOVFS16, "movfs16", "movfs", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movfs $rd6,$sn6 */
+ {
+ EPIPHANY_INSN_MOVFS6, "movfs6", "movfs", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movfs $rd6,$sndma */
+ {
+ EPIPHANY_INSN_MOVFSDMA, "movfsdma", "movfs", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movfs $rd6,$snmem */
+ {
+ EPIPHANY_INSN_MOVFSMEM, "movfsmem", "movfs", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movfs $rd6,$snmesh */
+ {
+ EPIPHANY_INSN_MOVFSMESH, "movfsmesh", "movfs", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* nop */
+ {
+ EPIPHANY_INSN_NOP, "nop", "nop", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* snop */
+ {
+ EPIPHANY_INSN_SNOP, "snop", "snop", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* unimpl */
+ {
+ EPIPHANY_INSN_UNIMPL, "unimpl", "unimpl", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* idle */
+ {
+ EPIPHANY_INSN_IDLE, "idle", "idle", 16,
+ { 0, { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bkpt */
+ {
+ EPIPHANY_INSN_BKPT, "bkpt", "bkpt", 16,
+ { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* mbkpt */
+ {
+ EPIPHANY_INSN_MBKPT, "mbkpt", "mbkpt", 16,
+ { 0|A(SHORT_INSN), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* rti */
+ {
+ EPIPHANY_INSN_RTI, "rti", "rti", 16,
+ { 0|A(UNCOND_CTI)|A(SHORT_INSN), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* wand */
+ {
+ EPIPHANY_INSN_WAND, "wand", "wand", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* sync */
+ {
+ EPIPHANY_INSN_SYNC, "sync", "sync", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* gie */
+ {
+ EPIPHANY_INSN_GIEN, "gien", "gie", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* gid */
+ {
+ EPIPHANY_INSN_GIDIS, "gidis", "gid", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* swi $swi_num */
+ {
+ EPIPHANY_INSN_SWI_NUM, "swi_num", "swi", 16,
+ { 0|A(UNCOND_CTI)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* swi */
+ {
+ -1, "swi", "swi", 16,
+ { 0|A(UNCOND_CTI)|A(SHORT_INSN)|A(ALIAS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* trap $trapnum6 */
+ {
+ EPIPHANY_INSN_TRAP16, "trap16", "trap", 16,
+ { 0|A(UNCOND_CTI)|A(SHORT_INSN), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* add $rd,$rn,$rm */
+ {
+ EPIPHANY_INSN_ADD16, "add16", "add", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* add $rd6,$rn6,$rm6 */
+ {
+ EPIPHANY_INSN_ADD, "add", "add", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* sub $rd,$rn,$rm */
+ {
+ EPIPHANY_INSN_SUB16, "sub16", "sub", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* sub $rd6,$rn6,$rm6 */
+ {
+ EPIPHANY_INSN_SUB, "sub", "sub", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* and $rd,$rn,$rm */
+ {
+ EPIPHANY_INSN_AND16, "and16", "and", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* and $rd6,$rn6,$rm6 */
+ {
+ EPIPHANY_INSN_AND, "and", "and", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* orr $rd,$rn,$rm */
+ {
+ EPIPHANY_INSN_ORR16, "orr16", "orr", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* orr $rd6,$rn6,$rm6 */
+ {
+ EPIPHANY_INSN_ORR, "orr", "orr", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* eor $rd,$rn,$rm */
+ {
+ EPIPHANY_INSN_EOR16, "eor16", "eor", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* eor $rd6,$rn6,$rm6 */
+ {
+ EPIPHANY_INSN_EOR, "eor", "eor", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* add.s $rd,$rn,$simm3 */
+ {
+ EPIPHANY_INSN_ADDI16, "addi16", "add.s", 16,
+ { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* add.l $rd6,$rn6,$simm11 */
+ {
+ EPIPHANY_INSN_ADDI, "addi", "add.l", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* sub.s $rd,$rn,$simm3 */
+ {
+ EPIPHANY_INSN_SUBI16, "subi16", "sub.s", 16,
+ { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* sub.l $rd6,$rn6,$simm11 */
+ {
+ EPIPHANY_INSN_SUBI, "subi", "sub.l", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* asr $rd,$rn,$rm */
+ {
+ EPIPHANY_INSN_ASR16, "asr16", "asr", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* asr $rd6,$rn6,$rm6 */
+ {
+ EPIPHANY_INSN_ASR, "asr", "asr", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* lsr $rd,$rn,$rm */
+ {
+ EPIPHANY_INSN_LSR16, "lsr16", "lsr", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* lsr $rd6,$rn6,$rm6 */
+ {
+ EPIPHANY_INSN_LSR, "lsr", "lsr", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* lsl $rd,$rn,$rm */
+ {
+ EPIPHANY_INSN_LSL16, "lsl16", "lsl", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* lsl $rd6,$rn6,$rm6 */
+ {
+ EPIPHANY_INSN_LSL, "lsl", "lsl", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* lsr $rd,$rn,$shift */
+ {
+ EPIPHANY_INSN_LSRI16, "lsri16", "lsr", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* lsr $rd6,$rn6,$shift */
+ {
+ EPIPHANY_INSN_LSRI32, "lsri32", "lsr", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* lsl $rd,$rn,$shift */
+ {
+ EPIPHANY_INSN_LSLI16, "lsli16", "lsl", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* lsl $rd6,$rn6,$shift */
+ {
+ EPIPHANY_INSN_LSLI32, "lsli32", "lsl", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* asr $rd,$rn,$shift */
+ {
+ EPIPHANY_INSN_ASRI16, "asri16", "asr", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* asr $rd6,$rn6,$shift */
+ {
+ EPIPHANY_INSN_ASRI32, "asri32", "asr", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bitr $rd,$rn */
+ {
+ EPIPHANY_INSN_BITR16, "bitr16", "bitr", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bitr $rd6,$rn6 */
+ {
+ EPIPHANY_INSN_BITR, "bitr", "bitr", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fext $rd6,$rn6,$rm6 */
+ {
+ EPIPHANY_INSN_FEXT, "fext", "fext", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fdep $rd6,$rn6,$rm6 */
+ {
+ EPIPHANY_INSN_FDEP, "fdep", "fdep", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* lfsr $rd6,$rn6,$rm6 */
+ {
+ EPIPHANY_INSN_LFSR, "lfsr", "lfsr", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* mov.b $rd,$imm8 */
+ {
+ EPIPHANY_INSN_MOV8, "mov8", "mov.b", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* mov.l $rd6,$imm16 */
+ {
+ EPIPHANY_INSN_MOV16, "mov16", "mov.l", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movt $rd6,$imm16 */
+ {
+ EPIPHANY_INSN_MOVT, "movt", "movt", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fadd $rd,$rn,$rm */
+ {
+ EPIPHANY_INSN_F_ADDF16, "f_addf16", "fadd", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fadd $rd6,$rn6,$rm6 */
+ {
+ EPIPHANY_INSN_F_ADDF32, "f_addf32", "fadd", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fsub $rd,$rn,$rm */
+ {
+ EPIPHANY_INSN_F_SUBF16, "f_subf16", "fsub", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fsub $rd6,$rn6,$rm6 */
+ {
+ EPIPHANY_INSN_F_SUBF32, "f_subf32", "fsub", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fmul $rd,$rn,$rm */
+ {
+ EPIPHANY_INSN_F_MULF16, "f_mulf16", "fmul", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fmul $rd6,$rn6,$rm6 */
+ {
+ EPIPHANY_INSN_F_MULF32, "f_mulf32", "fmul", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fmadd $rd,$rn,$rm */
+ {
+ EPIPHANY_INSN_F_MADDF16, "f_maddf16", "fmadd", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fmadd $rd6,$rn6,$rm6 */
+ {
+ EPIPHANY_INSN_F_MADDF32, "f_maddf32", "fmadd", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fmsub $rd,$rn,$rm */
+ {
+ EPIPHANY_INSN_F_MSUBF16, "f_msubf16", "fmsub", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fmsub $rd6,$rn6,$rm6 */
+ {
+ EPIPHANY_INSN_F_MSUBF32, "f_msubf32", "fmsub", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fabs rd,rn */
+ {
+ EPIPHANY_INSN_F_ABSF16, "f_absf16", "fabs", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fabs $rd6,$rn6 */
+ {
+ EPIPHANY_INSN_F_ABSF32, "f_absf32", "fabs", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* float $rd,$rn */
+ {
+ EPIPHANY_INSN_F_LOATF16, "f_loatf16", "float", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* float $rd6,$rn6 */
+ {
+ EPIPHANY_INSN_F_LOATF32, "f_loatf32", "float", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fix $rd,$rn */
+ {
+ EPIPHANY_INSN_F_IXF16, "f_ixf16", "fix", 16,
+ { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fix $rd6,$rn6 */
+ {
+ EPIPHANY_INSN_F_IXF32, "f_ixf32", "fix", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* frecip $frd6,$frn6 */
+ {
+ EPIPHANY_INSN_F_RECIPF32, "f_recipf32", "frecip", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fsqrt $frd6,$frn6 */
+ {
+ EPIPHANY_INSN_F_SQRTF32, "f_sqrtf32", "fsqrt", 32,
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+ },
+};
+
+#undef OP
+#undef A
+
+/* Initialize anything needed to be done once, before any cpu_open call. */
+
+static void
+init_tables (void)
+{
+}
+
+static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
+static void build_hw_table (CGEN_CPU_TABLE *);
+static void build_ifield_table (CGEN_CPU_TABLE *);
+static void build_operand_table (CGEN_CPU_TABLE *);
+static void build_insn_table (CGEN_CPU_TABLE *);
+static void epiphany_cgen_rebuild_tables (CGEN_CPU_TABLE *);
+
+/* Subroutine of epiphany_cgen_cpu_open to look up a mach via its bfd name. */
+
+static const CGEN_MACH *
+lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
+{
+ while (table->name)
+ {
+ if (strcmp (name, table->bfd_name) == 0)
+ return table;
+ ++table;
+ }
+ abort ();
+}
+
+/* Subroutine of epiphany_cgen_cpu_open to build the hardware table. */
+
+static void
+build_hw_table (CGEN_CPU_TABLE *cd)
+{
+ int i;
+ int machs = cd->machs;
+ const CGEN_HW_ENTRY *init = & epiphany_cgen_hw_table[0];
+ /* MAX_HW is only an upper bound on the number of selected entries.
+ However each entry is indexed by it's enum so there can be holes in
+ the table. */
+ const CGEN_HW_ENTRY **selected =
+ (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
+
+ cd->hw_table.init_entries = init;
+ cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
+ memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
+ /* ??? For now we just use machs to determine which ones we want. */
+ for (i = 0; init[i].name != NULL; ++i)
+ if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
+ & machs)
+ selected[init[i].type] = &init[i];
+ cd->hw_table.entries = selected;
+ cd->hw_table.num_entries = MAX_HW;
+}
+
+/* Subroutine of epiphany_cgen_cpu_open to build the hardware table. */
+
+static void
+build_ifield_table (CGEN_CPU_TABLE *cd)
+{
+ cd->ifld_table = & epiphany_cgen_ifld_table[0];
+}
+
+/* Subroutine of epiphany_cgen_cpu_open to build the hardware table. */
+
+static void
+build_operand_table (CGEN_CPU_TABLE *cd)
+{
+ int i;
+ int machs = cd->machs;
+ const CGEN_OPERAND *init = & epiphany_cgen_operand_table[0];
+ /* MAX_OPERANDS is only an upper bound on the number of selected entries.
+ However each entry is indexed by it's enum so there can be holes in
+ the table. */
+ const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
+
+ cd->operand_table.init_entries = init;
+ cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
+ memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+ /* ??? For now we just use mach to determine which ones we want. */
+ for (i = 0; init[i].name != NULL; ++i)
+ if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
+ & machs)
+ selected[init[i].type] = &init[i];
+ cd->operand_table.entries = selected;
+ cd->operand_table.num_entries = MAX_OPERANDS;
+}
+
+/* Subroutine of epiphany_cgen_cpu_open to build the hardware table.
+ ??? This could leave out insns not supported by the specified mach/isa,
+ but that would cause errors like "foo only supported by bar" to become
+ "unknown insn", so for now we include all insns and require the app to
+ do the checking later.
+ ??? On the other hand, parsing of such insns may require their hardware or
+ operand elements to be in the table [which they mightn't be]. */
+
+static void
+build_insn_table (CGEN_CPU_TABLE *cd)
+{
+ int i;
+ const CGEN_IBASE *ib = & epiphany_cgen_insn_table[0];
+ CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+
+ memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
+ for (i = 0; i < MAX_INSNS; ++i)
+ insns[i].base = &ib[i];
+ cd->insn_table.init_entries = insns;
+ cd->insn_table.entry_size = sizeof (CGEN_IBASE);
+ cd->insn_table.num_init_entries = MAX_INSNS;
+}
+
+/* Subroutine of epiphany_cgen_cpu_open to rebuild the tables. */
+
+static void
+epiphany_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
+{
+ int i;
+ CGEN_BITSET *isas = cd->isas;
+ unsigned int machs = cd->machs;
+
+ cd->int_insn_p = CGEN_INT_INSN_P;
+
+ /* Data derived from the isa spec. */
+#define UNSET (CGEN_SIZE_UNKNOWN + 1)
+ cd->default_insn_bitsize = UNSET;
+ cd->base_insn_bitsize = UNSET;
+ cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
+ cd->max_insn_bitsize = 0;
+ for (i = 0; i < MAX_ISAS; ++i)
+ if (cgen_bitset_contains (isas, i))
+ {
+ const CGEN_ISA *isa = & epiphany_cgen_isa_table[i];
+
+ /* Default insn sizes of all selected isas must be
+ equal or we set the result to 0, meaning "unknown". */
+ if (cd->default_insn_bitsize == UNSET)
+ cd->default_insn_bitsize = isa->default_insn_bitsize;
+ else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
+ ; /* This is ok. */
+ else
+ cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+ /* Base insn sizes of all selected isas must be equal
+ or we set the result to 0, meaning "unknown". */
+ if (cd->base_insn_bitsize == UNSET)
+ cd->base_insn_bitsize = isa->base_insn_bitsize;
+ else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
+ ; /* This is ok. */
+ else
+ cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+ /* Set min,max insn sizes. */
+ if (isa->min_insn_bitsize < cd->min_insn_bitsize)
+ cd->min_insn_bitsize = isa->min_insn_bitsize;
+ if (isa->max_insn_bitsize > cd->max_insn_bitsize)
+ cd->max_insn_bitsize = isa->max_insn_bitsize;
+ }
+
+ /* Data derived from the mach spec. */
+ for (i = 0; i < MAX_MACHS; ++i)
+ if (((1 << i) & machs) != 0)
+ {
+ const CGEN_MACH *mach = & epiphany_cgen_mach_table[i];
+
+ if (mach->insn_chunk_bitsize != 0)
+ {
+ if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
+ {
+ fprintf (stderr, "epiphany_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
+ cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
+ abort ();
+ }
+
+ cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
+ }
+ }
+
+ /* Determine which hw elements are used by MACH. */
+ build_hw_table (cd);
+
+ /* Build the ifield table. */
+ build_ifield_table (cd);
+
+ /* Determine which operands are used by MACH/ISA. */
+ build_operand_table (cd);
+
+ /* Build the instruction table. */
+ build_insn_table (cd);
+}
+
+/* Initialize a cpu table and return a descriptor.
+ It's much like opening a file, and must be the first function called.
+ The arguments are a set of (type/value) pairs, terminated with
+ CGEN_CPU_OPEN_END.
+
+ Currently supported values:
+ CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
+ CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
+ CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
+ CGEN_CPU_OPEN_ENDIAN: specify endian choice
+ CGEN_CPU_OPEN_END: terminates arguments
+
+ ??? Simultaneous multiple isas might not make sense, but it's not (yet)
+ precluded. */
+
+CGEN_CPU_DESC
+epiphany_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+{
+ CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
+ static int init_p;
+ CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
+ unsigned int machs = 0; /* 0 = "unspecified" */
+ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
+ va_list ap;
+
+ if (! init_p)
+ {
+ init_tables ();
+ init_p = 1;
+ }
+
+ memset (cd, 0, sizeof (*cd));
+
+ va_start (ap, arg_type);
+ while (arg_type != CGEN_CPU_OPEN_END)
+ {
+ switch (arg_type)
+ {
+ case CGEN_CPU_OPEN_ISAS :
+ isas = va_arg (ap, CGEN_BITSET *);
+ break;
+ case CGEN_CPU_OPEN_MACHS :
+ machs = va_arg (ap, unsigned int);
+ break;
+ case CGEN_CPU_OPEN_BFDMACH :
+ {
+ const char *name = va_arg (ap, const char *);
+ const CGEN_MACH *mach =
+ lookup_mach_via_bfd_name (epiphany_cgen_mach_table, name);
+
+ machs |= 1 << mach->num;
+ break;
+ }
+ case CGEN_CPU_OPEN_ENDIAN :
+ endian = va_arg (ap, enum cgen_endian);
+ break;
+ default :
+ fprintf (stderr, "epiphany_cgen_cpu_open: unsupported argument `%d'\n",
+ arg_type);
+ abort (); /* ??? return NULL? */
+ }
+ arg_type = va_arg (ap, enum cgen_cpu_open_arg);
+ }
+ va_end (ap);
+
+ /* Mach unspecified means "all". */
+ if (machs == 0)
+ machs = (1 << MAX_MACHS) - 1;
+ /* Base mach is always selected. */
+ machs |= 1;
+ if (endian == CGEN_ENDIAN_UNKNOWN)
+ {
+ /* ??? If target has only one, could have a default. */
+ fprintf (stderr, "epiphany_cgen_cpu_open: no endianness specified\n");
+ abort ();
+ }
+
+ cd->isas = cgen_bitset_copy (isas);
+ cd->machs = machs;
+ cd->endian = endian;
+ /* FIXME: for the sparc case we can determine insn-endianness statically.
+ The worry here is where both data and insn endian can be independently
+ chosen, in which case this function will need another argument.
+ Actually, will want to allow for more arguments in the future anyway. */
+ cd->insn_endian = endian;
+
+ /* Table (re)builder. */
+ cd->rebuild_tables = epiphany_cgen_rebuild_tables;
+ epiphany_cgen_rebuild_tables (cd);
+
+ /* Default to not allowing signed overflow. */
+ cd->signed_overflow_ok_p = 0;
+
+ return (CGEN_CPU_DESC) cd;
+}
+
+/* Cover fn to epiphany_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
+ MACH_NAME is the bfd name of the mach. */
+
+CGEN_CPU_DESC
+epiphany_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
+{
+ return epiphany_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
+ CGEN_CPU_OPEN_ENDIAN, endian,
+ CGEN_CPU_OPEN_END);
+}
+
+/* Close a cpu table.
+ ??? This can live in a machine independent file, but there's currently
+ no place to put this file (there's no libcgen). libopcodes is the wrong
+ place as some simulator ports use this but they don't use libopcodes. */
+
+void
+epiphany_cgen_cpu_close (CGEN_CPU_DESC cd)
+{
+ unsigned int i;
+ const CGEN_INSN *insns;
+
+ if (cd->macro_insn_table.init_entries)
+ {
+ insns = cd->macro_insn_table.init_entries;
+ for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
+ if (CGEN_INSN_RX ((insns)))
+ regfree (CGEN_INSN_RX (insns));
+ }
+
+ if (cd->insn_table.init_entries)
+ {
+ insns = cd->insn_table.init_entries;
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ if (CGEN_INSN_RX (insns))
+ regfree (CGEN_INSN_RX (insns));
+ }
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+
+ if (cd->insn_table.init_entries)
+ free ((CGEN_INSN *) cd->insn_table.init_entries);
+
+ if (cd->hw_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+
+ if (cd->operand_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+
+ free (cd);
+}
+
--- /dev/null
+/* CPU data header for epiphany.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef EPIPHANY_CPU_H
+#define EPIPHANY_CPU_H
+
+#define CGEN_ARCH epiphany
+
+/* Given symbol S, return epiphany_cgen_<S>. */
+#define CGEN_SYM(s) epiphany##_cgen_##s
+
+
+/* Selected cpu families. */
+#define HAVE_CPU_EPIPHANYBF
+#define HAVE_CPU_EPIPHANYMF
+
+#define CGEN_INSN_LSB0_P 1
+
+/* Minimum size of any insn (in bytes). */
+#define CGEN_MIN_INSN_SIZE 2
+
+/* Maximum size of any insn (in bytes). */
+#define CGEN_MAX_INSN_SIZE 4
+
+#define CGEN_INT_INSN_P 1
+
+/* Maximum number of syntax elements in an instruction. */
+#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19
+
+/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
+ e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
+ we can't hash on everything up to the space. */
+#define CGEN_MNEMONIC_OPERANDS
+
+/* Maximum number of fields in an instruction. */
+#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 10
+
+/* Enums. */
+
+/* Enum declaration for opc enums. */
+typedef enum insn_opc {
+ OP4_BRANCH16, OP4_LDSTR16X, OP4_FLOW16, OP4_IMM16
+ , OP4_LDSTR16D, OP4_LDSTR16P, OP4_LSHIFT16, OP4_DSP16
+ , OP4_BRANCH, OP4_LDSTRX, OP4_ALU16, OP4_IMM32
+ , OP4_LDSTRD, OP4_LDSTRP, OP4_ASHIFT16, OP4_MISC
+} INSN_OPC;
+
+/* Enum declaration for memory access width. */
+typedef enum insn_wordsize {
+ OPW_BYTE, OPW_SHORT, OPW_WORD, OPW_DOUBLE
+} INSN_WORDSIZE;
+
+/* Enum declaration for memory access direction. */
+typedef enum insn_memory_access {
+ OP_LOAD, OP_STORE
+} INSN_MEMORY_ACCESS;
+
+/* Enum declaration for trap instruction dispatch code. */
+typedef enum trap_codes {
+ TRAP_WRITE, TRAP_READ, TRAP_OPEN, TRAP_EXIT
+ , TRAP_PASS, TRAP_FAIL, TRAP_CLOSE, TRAP_OTHER
+} TRAP_CODES;
+
+/* Enum declaration for branch conditions. */
+typedef enum insn_cond {
+ OPC_EQ, OPC_NE, OPC_GTU, OPC_GTEU
+ , OPC_LTEU, OPC_LTU, OPC_GT, OPC_GTE
+ , OPC_LT, OPC_LTE, OPC_BEQ, OPC_BNE
+ , OPC_BLT, OPC_BLTE, OPC_B, OPC_BL
+} INSN_COND;
+
+/* Enum declaration for binary operator subcodes. */
+typedef enum insn_bop {
+ OPB_EOR, OPB_ADD, OPB_LSL, OPB_SUB
+ , OPB_LSR, OPB_AND, OPB_ASR, OPB_ORR
+} INSN_BOP;
+
+/* Enum declaration for binary operator subcodes. */
+typedef enum insn_bopext {
+ OPBE_FEXT, OPBE_FDEP, OPBE_LFSR
+} INSN_BOPEXT;
+
+/* Enum declaration for floating operators. */
+typedef enum insn_fop {
+ OPF_ADD, OPF_SUB, OPF_MUL, OPF_MADD
+ , OPF_MSUB, OPF_FLOAT, OPF_FIX, OPF_FABS
+} INSN_FOP;
+
+/* Enum declaration for extended floating operators. */
+typedef enum insn_fopexn {
+ OPF_FRECIP, OPF_FSQRT
+} INSN_FOPEXN;
+
+/* Enum declaration for immediate operators. */
+typedef enum insn_immop {
+ OPI_ADD = 1, OPI_SUB = 3, OPI_TRAP = 7
+} INSN_IMMOP;
+
+/* Enum declaration for don't cares. */
+typedef enum insn_dc_25_2 {
+ OPI_25_2_MBZ
+} INSN_DC_25_2;
+
+/* Enum declaration for . */
+typedef enum gr_names {
+ H_REGISTERS_SB = 9, H_REGISTERS_SL = 10, H_REGISTERS_FP = 11, H_REGISTERS_IP = 12
+ , H_REGISTERS_SP = 13, H_REGISTERS_LR = 14, H_REGISTERS_R0 = 0, H_REGISTERS_R1 = 1
+ , H_REGISTERS_R2 = 2, H_REGISTERS_R3 = 3, H_REGISTERS_R4 = 4, H_REGISTERS_R5 = 5
+ , H_REGISTERS_R6 = 6, H_REGISTERS_R7 = 7, H_REGISTERS_R8 = 8, H_REGISTERS_R9 = 9
+ , H_REGISTERS_R10 = 10, H_REGISTERS_R11 = 11, H_REGISTERS_R12 = 12, H_REGISTERS_R13 = 13
+ , H_REGISTERS_R14 = 14, H_REGISTERS_R15 = 15, H_REGISTERS_R16 = 16, H_REGISTERS_R17 = 17
+ , H_REGISTERS_R18 = 18, H_REGISTERS_R19 = 19, H_REGISTERS_R20 = 20, H_REGISTERS_R21 = 21
+ , H_REGISTERS_R22 = 22, H_REGISTERS_R23 = 23, H_REGISTERS_R24 = 24, H_REGISTERS_R25 = 25
+ , H_REGISTERS_R26 = 26, H_REGISTERS_R27 = 27, H_REGISTERS_R28 = 28, H_REGISTERS_R29 = 29
+ , H_REGISTERS_R30 = 30, H_REGISTERS_R31 = 31, H_REGISTERS_R32 = 32, H_REGISTERS_R33 = 33
+ , H_REGISTERS_R34 = 34, H_REGISTERS_R35 = 35, H_REGISTERS_R36 = 36, H_REGISTERS_R37 = 37
+ , H_REGISTERS_R38 = 38, H_REGISTERS_R39 = 39, H_REGISTERS_R40 = 40, H_REGISTERS_R41 = 41
+ , H_REGISTERS_R42 = 42, H_REGISTERS_R43 = 43, H_REGISTERS_R44 = 44, H_REGISTERS_R45 = 45
+ , H_REGISTERS_R46 = 46, H_REGISTERS_R47 = 47, H_REGISTERS_R48 = 48, H_REGISTERS_R49 = 49
+ , H_REGISTERS_R50 = 50, H_REGISTERS_R51 = 51, H_REGISTERS_R52 = 52, H_REGISTERS_R53 = 53
+ , H_REGISTERS_R54 = 54, H_REGISTERS_R55 = 55, H_REGISTERS_R56 = 56, H_REGISTERS_R57 = 57
+ , H_REGISTERS_R58 = 58, H_REGISTERS_R59 = 59, H_REGISTERS_R60 = 60, H_REGISTERS_R61 = 61
+ , H_REGISTERS_R62 = 62, H_REGISTERS_R63 = 63, H_REGISTERS_A1 = 0, H_REGISTERS_A2 = 1
+ , H_REGISTERS_A3 = 2, H_REGISTERS_A4 = 3, H_REGISTERS_V1 = 4, H_REGISTERS_V2 = 5
+ , H_REGISTERS_V3 = 6, H_REGISTERS_V4 = 7, H_REGISTERS_V5 = 8, H_REGISTERS_V6 = 9
+ , H_REGISTERS_V7 = 10, H_REGISTERS_V8 = 11
+} GR_NAMES;
+
+/* Enum declaration for +/- index register. */
+typedef enum post_index {
+ DIR_POSTINC, DIR_POSTDEC
+} POST_INDEX;
+
+/* Enum declaration for postmodify displacement. */
+typedef enum disp_post_modify {
+ PMOD_DISP, PMOD_POST
+} DISP_POST_MODIFY;
+
+/* Enum declaration for . */
+typedef enum cr_names {
+ H_CORE_REGISTERS_CONFIG, H_CORE_REGISTERS_STATUS, H_CORE_REGISTERS_PC, H_CORE_REGISTERS_DEBUG
+ , H_CORE_REGISTERS_IAB, H_CORE_REGISTERS_LC, H_CORE_REGISTERS_LS, H_CORE_REGISTERS_LE
+ , H_CORE_REGISTERS_IRET, H_CORE_REGISTERS_IMASK, H_CORE_REGISTERS_ILAT, H_CORE_REGISTERS_ILATST
+ , H_CORE_REGISTERS_ILATCL, H_CORE_REGISTERS_IPEND, H_CORE_REGISTERS_CTIMER0, H_CORE_REGISTERS_CTIMER1
+ , H_CORE_REGISTERS_HSTATUS
+} CR_NAMES;
+
+/* Enum declaration for . */
+typedef enum crdma_names {
+ H_COREDMA_REGISTERS_DMA0CONFIG, H_COREDMA_REGISTERS_DMA0STRIDE, H_COREDMA_REGISTERS_DMA0COUNT, H_COREDMA_REGISTERS_DMA0SRCADDR
+ , H_COREDMA_REGISTERS_DMA0DSTADDR, H_COREDMA_REGISTERS_DMA0AUTO0, H_COREDMA_REGISTERS_DMA0AUTO1, H_COREDMA_REGISTERS_DMA0STATUS
+ , H_COREDMA_REGISTERS_DMA1CONFIG, H_COREDMA_REGISTERS_DMA1STRIDE, H_COREDMA_REGISTERS_DMA1COUNT, H_COREDMA_REGISTERS_DMA1SRCADDR
+ , H_COREDMA_REGISTERS_DMA1DSTADDR, H_COREDMA_REGISTERS_DMA1AUTO0, H_COREDMA_REGISTERS_DMA1AUTO1, H_COREDMA_REGISTERS_DMA1STATUS
+} CRDMA_NAMES;
+
+/* Enum declaration for . */
+typedef enum crmem_names {
+ H_COREMEM_REGISTERS_MEMCONFIG, H_COREMEM_REGISTERS_MEMSTATUS, H_COREMEM_REGISTERS_MEMPROTECT, H_COREMEM_REGISTERS_MEMRESERVE
+} CRMEM_NAMES;
+
+/* Enum declaration for . */
+typedef enum crmesh_names {
+ H_COREMESH_REGISTERS_MESHCONFIG, H_COREMESH_REGISTERS_COREID, H_COREMESH_REGISTERS_MESHMULTICAST, H_COREMESH_REGISTERS_SWRESET
+} CRMESH_NAMES;
+
+/* Attributes. */
+
+/* Enum declaration for machine type selection. */
+typedef enum mach_attr {
+ MACH_BASE, MACH_EPIPHANY32, MACH_MAX
+} MACH_ATTR;
+
+/* Enum declaration for instruction set selection. */
+typedef enum isa_attr {
+ ISA_EPIPHANY, ISA_MAX
+} ISA_ATTR;
+
+/* Number of architecture variants. */
+#define MAX_ISAS 1
+#define MAX_MACHS ((int) MACH_MAX)
+
+/* Ifield support. */
+
+/* Ifield attribute indices. */
+
+/* Enum declaration for cgen_ifld attrs. */
+typedef enum cgen_ifld_attr {
+ CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
+ , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS
+ , CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
+} CGEN_IFLD_ATTR;
+
+/* Number of non-boolean elements in cgen_ifld_attr. */
+#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
+
+/* cgen_ifld attribute accessor macros. */
+#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RELOC)) != 0)
+
+/* Enum declaration for epiphany ifield types. */
+typedef enum ifield_type {
+ EPIPHANY_F_NIL, EPIPHANY_F_ANYOF, EPIPHANY_F_OPC, EPIPHANY_F_OPC_4_1
+ , EPIPHANY_F_OPC_6_3, EPIPHANY_F_OPC_8_5, EPIPHANY_F_OPC_19_4, EPIPHANY_F_CONDCODE
+ , EPIPHANY_F_SECONDARY_CCS, EPIPHANY_F_SHIFT, EPIPHANY_F_WORDSIZE, EPIPHANY_F_STORE
+ , EPIPHANY_F_OPC_8_1, EPIPHANY_F_OPC_31_32, EPIPHANY_F_SIMM8, EPIPHANY_F_SIMM24
+ , EPIPHANY_F_SDISP3, EPIPHANY_F_DISP3, EPIPHANY_F_DISP8, EPIPHANY_F_IMM8
+ , EPIPHANY_F_IMM_27_8, EPIPHANY_F_ADDSUBX, EPIPHANY_F_SUBD, EPIPHANY_F_PM
+ , EPIPHANY_F_RM, EPIPHANY_F_RN, EPIPHANY_F_RD, EPIPHANY_F_RM_X
+ , EPIPHANY_F_RN_X, EPIPHANY_F_RD_X, EPIPHANY_F_DC_9_1, EPIPHANY_F_SN
+ , EPIPHANY_F_SD, EPIPHANY_F_SN_X, EPIPHANY_F_SD_X, EPIPHANY_F_DC_7_4
+ , EPIPHANY_F_TRAP_SWI_9_1, EPIPHANY_F_GIEN_GIDIS_9_1, EPIPHANY_F_DC_15_3, EPIPHANY_F_DC_15_7
+ , EPIPHANY_F_DC_15_6, EPIPHANY_F_TRAP_NUM, EPIPHANY_F_DC_20_1, EPIPHANY_F_DC_21_1
+ , EPIPHANY_F_DC_21_2, EPIPHANY_F_DC_22_3, EPIPHANY_F_DC_22_2, EPIPHANY_F_DC_22_1
+ , EPIPHANY_F_DC_25_6, EPIPHANY_F_DC_25_4, EPIPHANY_F_DC_25_2, EPIPHANY_F_DC_25_1
+ , EPIPHANY_F_DC_28_1, EPIPHANY_F_DC_31_3, EPIPHANY_F_DISP11, EPIPHANY_F_SDISP11
+ , EPIPHANY_F_IMM16, EPIPHANY_F_RD6, EPIPHANY_F_RN6, EPIPHANY_F_RM6
+ , EPIPHANY_F_SD6, EPIPHANY_F_SN6, EPIPHANY_F_MAX
+} IFIELD_TYPE;
+
+#define MAX_IFLD ((int) EPIPHANY_F_MAX)
+
+/* Hardware attribute indices. */
+
+/* Enum declaration for cgen_hw attrs. */
+typedef enum cgen_hw_attr {
+ CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
+ , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
+} CGEN_HW_ATTR;
+
+/* Number of non-boolean elements in cgen_hw_attr. */
+#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
+
+/* cgen_hw attribute accessor macros. */
+#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0)
+#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0)
+
+/* Enum declaration for epiphany hardware types. */
+typedef enum cgen_hw_type {
+ HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
+ , HW_H_IADDR, HW_H_REGISTERS, HW_H_FPREGISTERS, HW_H_ZBIT
+ , HW_H_NBIT, HW_H_CBIT, HW_H_VBIT, HW_H_VSBIT
+ , HW_H_BZBIT, HW_H_BNBIT, HW_H_BVBIT, HW_H_BUBIT
+ , HW_H_BIBIT, HW_H_BCBIT, HW_H_BVSBIT, HW_H_BISBIT
+ , HW_H_BUSBIT, HW_H_EXPCAUSE0BIT, HW_H_EXPCAUSE1BIT, HW_H_EXPCAUSE2BIT
+ , HW_H_EXTFSTALLBIT, HW_H_TRMBIT, HW_H_INVEXCENBIT, HW_H_OVFEXCENBIT
+ , HW_H_UNEXCENBIT, HW_H_TIMER0BIT0, HW_H_TIMER0BIT1, HW_H_TIMER0BIT2
+ , HW_H_TIMER0BIT3, HW_H_TIMER1BIT0, HW_H_TIMER1BIT1, HW_H_TIMER1BIT2
+ , HW_H_TIMER1BIT3, HW_H_MBKPTENBIT, HW_H_CLOCKGATEENBIT, HW_H_CORECFGRESBIT12
+ , HW_H_CORECFGRESBIT13, HW_H_CORECFGRESBIT14, HW_H_CORECFGRESBIT15, HW_H_CORECFGRESBIT16
+ , HW_H_CORECFGRESBIT20, HW_H_CORECFGRESBIT21, HW_H_CORECFGRESBIT24, HW_H_CORECFGRESBIT25
+ , HW_H_CORECFGRESBIT26, HW_H_CORECFGRESBIT27, HW_H_CORECFGRESBIT28, HW_H_CORECFGRESBIT29
+ , HW_H_CORECFGRESBIT30, HW_H_CORECFGRESBIT31, HW_H_ARITHMETIC_MODEBIT0, HW_H_ARITHMETIC_MODEBIT1
+ , HW_H_ARITHMETIC_MODEBIT2, HW_H_GIDISABLEBIT, HW_H_KMBIT, HW_H_CAIBIT
+ , HW_H_SFLAGBIT, HW_H_PC, HW_H_MEMADDR, HW_H_CORE_REGISTERS
+ , HW_H_COREDMA_REGISTERS, HW_H_COREMEM_REGISTERS, HW_H_COREMESH_REGISTERS, HW_MAX
+} CGEN_HW_TYPE;
+
+#define MAX_HW ((int) HW_MAX)
+
+/* Operand attribute indices. */
+
+/* Enum declaration for cgen_operand attrs. */
+typedef enum cgen_operand_attr {
+ CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
+ , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
+ , CGEN_OPERAND_RELOC, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH
+ , CGEN_OPERAND_END_NBOOLS
+} CGEN_OPERAND_ATTR;
+
+/* Number of non-boolean elements in cgen_operand_attr. */
+#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
+
+/* cgen_operand attribute accessor macros. */
+#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELOC)) != 0)
+
+/* Enum declaration for epiphany operand types. */
+typedef enum cgen_operand_type {
+ EPIPHANY_OPERAND_PC, EPIPHANY_OPERAND_ZBIT, EPIPHANY_OPERAND_NBIT, EPIPHANY_OPERAND_CBIT
+ , EPIPHANY_OPERAND_VBIT, EPIPHANY_OPERAND_BZBIT, EPIPHANY_OPERAND_BNBIT, EPIPHANY_OPERAND_BVBIT
+ , EPIPHANY_OPERAND_BCBIT, EPIPHANY_OPERAND_BUBIT, EPIPHANY_OPERAND_BIBIT, EPIPHANY_OPERAND_VSBIT
+ , EPIPHANY_OPERAND_BVSBIT, EPIPHANY_OPERAND_BISBIT, EPIPHANY_OPERAND_BUSBIT, EPIPHANY_OPERAND_EXPCAUSE0BIT
+ , EPIPHANY_OPERAND_EXPCAUSE1BIT, EPIPHANY_OPERAND_EXPCAUSE2BIT, EPIPHANY_OPERAND_EXTFSTALLBIT, EPIPHANY_OPERAND_TRMBIT
+ , EPIPHANY_OPERAND_INVEXCENBIT, EPIPHANY_OPERAND_OVFEXCENBIT, EPIPHANY_OPERAND_UNEXCENBIT, EPIPHANY_OPERAND_TIMER0BIT0
+ , EPIPHANY_OPERAND_TIMER0BIT1, EPIPHANY_OPERAND_TIMER0BIT2, EPIPHANY_OPERAND_TIMER0BIT3, EPIPHANY_OPERAND_TIMER1BIT0
+ , EPIPHANY_OPERAND_TIMER1BIT1, EPIPHANY_OPERAND_TIMER1BIT2, EPIPHANY_OPERAND_TIMER1BIT3, EPIPHANY_OPERAND_MBKPTENBIT
+ , EPIPHANY_OPERAND_CLOCKGATEENBIT, EPIPHANY_OPERAND_ARITHMETIC_MODEBIT0, EPIPHANY_OPERAND_ARITHMETIC_MODEBIT1, EPIPHANY_OPERAND_ARITHMETIC_MODEBIT2
+ , EPIPHANY_OPERAND_CORECFGRESBIT12, EPIPHANY_OPERAND_CORECFGRESBIT13, EPIPHANY_OPERAND_CORECFGRESBIT14, EPIPHANY_OPERAND_CORECFGRESBIT15
+ , EPIPHANY_OPERAND_CORECFGRESBIT16, EPIPHANY_OPERAND_CORECFGRESBIT20, EPIPHANY_OPERAND_CORECFGRESBIT21, EPIPHANY_OPERAND_CORECFGRESBIT24
+ , EPIPHANY_OPERAND_CORECFGRESBIT25, EPIPHANY_OPERAND_CORECFGRESBIT26, EPIPHANY_OPERAND_CORECFGRESBIT27, EPIPHANY_OPERAND_CORECFGRESBIT28
+ , EPIPHANY_OPERAND_CORECFGRESBIT29, EPIPHANY_OPERAND_CORECFGRESBIT30, EPIPHANY_OPERAND_CORECFGRESBIT31, EPIPHANY_OPERAND_GIDISABLEBIT
+ , EPIPHANY_OPERAND_KMBIT, EPIPHANY_OPERAND_CAIBIT, EPIPHANY_OPERAND_SFLAGBIT, EPIPHANY_OPERAND_MEMADDR
+ , EPIPHANY_OPERAND_SIMM24, EPIPHANY_OPERAND_SIMM8, EPIPHANY_OPERAND_RD, EPIPHANY_OPERAND_RN
+ , EPIPHANY_OPERAND_RM, EPIPHANY_OPERAND_FRD, EPIPHANY_OPERAND_FRN, EPIPHANY_OPERAND_FRM
+ , EPIPHANY_OPERAND_RD6, EPIPHANY_OPERAND_RN6, EPIPHANY_OPERAND_RM6, EPIPHANY_OPERAND_FRD6
+ , EPIPHANY_OPERAND_FRN6, EPIPHANY_OPERAND_FRM6, EPIPHANY_OPERAND_SD, EPIPHANY_OPERAND_SN
+ , EPIPHANY_OPERAND_SD6, EPIPHANY_OPERAND_SN6, EPIPHANY_OPERAND_SDDMA, EPIPHANY_OPERAND_SNDMA
+ , EPIPHANY_OPERAND_SDMEM, EPIPHANY_OPERAND_SNMEM, EPIPHANY_OPERAND_SDMESH, EPIPHANY_OPERAND_SNMESH
+ , EPIPHANY_OPERAND_SIMM3, EPIPHANY_OPERAND_SIMM11, EPIPHANY_OPERAND_DISP3, EPIPHANY_OPERAND_TRAPNUM6
+ , EPIPHANY_OPERAND_SWI_NUM, EPIPHANY_OPERAND_DISP11, EPIPHANY_OPERAND_SHIFT, EPIPHANY_OPERAND_IMM16
+ , EPIPHANY_OPERAND_IMM8, EPIPHANY_OPERAND_DIRECTION, EPIPHANY_OPERAND_DPMI, EPIPHANY_OPERAND_MAX
+} CGEN_OPERAND_TYPE;
+
+/* Number of operands types. */
+#define MAX_OPERANDS 91
+
+/* Maximum number of operands referenced by any insn. */
+#define MAX_OPERAND_INSTANCES 8
+
+/* Insn attribute indices. */
+
+/* Enum declaration for cgen_insn attrs. */
+typedef enum cgen_insn_attr {
+ CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
+ , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_SHORT_INSN, CGEN_INSN_IMM3
+ , CGEN_INSN_IMM8, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH
+ , CGEN_INSN_END_NBOOLS
+} CGEN_INSN_ATTR;
+
+/* Number of non-boolean elements in cgen_insn_attr. */
+#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
+
+/* cgen_insn attribute accessor macros. */
+#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0)
+#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SHORT_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SHORT_INSN)) != 0)
+#define CGEN_ATTR_CGEN_INSN_IMM3_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_IMM3)) != 0)
+#define CGEN_ATTR_CGEN_INSN_IMM8_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_IMM8)) != 0)
+
+/* cgen.h uses things we just defined. */
+#include "opcode/cgen.h"
+
+extern const struct cgen_ifld epiphany_cgen_ifld_table[];
+
+/* Attributes. */
+extern const CGEN_ATTR_TABLE epiphany_cgen_hardware_attr_table[];
+extern const CGEN_ATTR_TABLE epiphany_cgen_ifield_attr_table[];
+extern const CGEN_ATTR_TABLE epiphany_cgen_operand_attr_table[];
+extern const CGEN_ATTR_TABLE epiphany_cgen_insn_attr_table[];
+
+/* Hardware decls. */
+
+extern CGEN_KEYWORD epiphany_cgen_opval_gr_names;
+extern CGEN_KEYWORD epiphany_cgen_opval_gr_names;
+extern CGEN_KEYWORD epiphany_cgen_opval_cr_names;
+extern CGEN_KEYWORD epiphany_cgen_opval_crdma_names;
+extern CGEN_KEYWORD epiphany_cgen_opval_crmem_names;
+extern CGEN_KEYWORD epiphany_cgen_opval_crmesh_names;
+
+extern const CGEN_HW_ENTRY epiphany_cgen_hw_table[];
+
+
+
+#endif /* EPIPHANY_CPU_H */
--- /dev/null
+/* Disassembler interface for targets using CGEN. -*- C -*-
+ CGEN: Cpu tools GENerator
+
+ THIS FILE IS MACHINE GENERATED WITH CGEN.
+ - the resultant file is machine generated, cgen-dis.in isn't
+
+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007,
+ 2008, 2010 Free Software Foundation, Inc.
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+ Keep that in mind. */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "dis-asm.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "libiberty.h"
+#include "epiphany-desc.h"
+#include "epiphany-opc.h"
+#include "opintl.h"
+
+/* Default text to print if an instruction isn't recognized. */
+#define UNKNOWN_INSN_MSG _("*unknown*")
+
+static void print_normal
+ (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
+static void print_address
+ (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
+static void print_keyword
+ (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
+static void print_insn_normal
+ (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
+static int print_insn
+ (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned);
+static int default_print_insn
+ (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
+static int read_insn
+ (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
+ unsigned long *);
+\f
+/* -- disassembler routines inserted here. */
+
+/* -- dis.c */
+
+#define CGEN_PRINT_INSN epiphany_print_insn
+
+static int
+epiphany_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
+{
+ bfd_byte buf[CGEN_MAX_INSN_SIZE];
+ int buflen;
+ int status;
+
+ info->bytes_per_chunk = 2;
+
+ /* Attempt to read the base part of the insn. */
+ info->bytes_per_line = buflen = cd->base_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+
+ /* Try again with the minimum part, if min < base. */
+ if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
+ {
+ info->bytes_per_line = buflen = cd->min_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+ }
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ return print_insn (cd, pc, info, buf, buflen);
+}
+
+
+static void
+print_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void * dis_info,
+ long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+ (*info->fprintf_func) (info->stream, value ? "-" : "+");
+}
+
+static void
+print_simm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void * dis_info,
+ long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ print_address (cd, dis_info, value, attrs, pc, length);
+}
+
+static void
+print_uimm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void * dis_info,
+ unsigned long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *)dis_info;
+
+ if (value & 0x800)
+ (*info->fprintf_func) (info->stream, "-");
+
+ value &= 0x7ff;
+ print_address (cd, dis_info, value, attrs, pc, length);
+}
+
+\f
+/* -- */
+
+void epiphany_cgen_print_operand
+ (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
+
+/* Main entry point for printing operands.
+ XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
+ of dis-asm.h on cgen.h.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `print_insn_normal', but keeping it
+ separate makes clear the interface between `print_insn_normal' and each of
+ the handlers. */
+
+void
+epiphany_cgen_print_operand (CGEN_CPU_DESC cd,
+ int opindex,
+ void * xinfo,
+ CGEN_FIELDS *fields,
+ void const *attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc,
+ int length)
+{
+ disassemble_info *info = (disassemble_info *) xinfo;
+
+ switch (opindex)
+ {
+ case EPIPHANY_OPERAND_DIRECTION :
+ print_postindex (cd, info, fields->f_addsubx, 0, pc, length);
+ break;
+ case EPIPHANY_OPERAND_DISP11 :
+ print_uimm_not_reg (cd, info, fields->f_disp11, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
+ case EPIPHANY_OPERAND_DISP3 :
+ print_normal (cd, info, fields->f_disp3, 0, pc, length);
+ break;
+ case EPIPHANY_OPERAND_DPMI :
+ print_postindex (cd, info, fields->f_subd, 0, pc, length);
+ break;
+ case EPIPHANY_OPERAND_FRD :
+ print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd, 0);
+ break;
+ case EPIPHANY_OPERAND_FRD6 :
+ print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case EPIPHANY_OPERAND_FRM :
+ print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm, 0);
+ break;
+ case EPIPHANY_OPERAND_FRM6 :
+ print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case EPIPHANY_OPERAND_FRN :
+ print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn, 0);
+ break;
+ case EPIPHANY_OPERAND_FRN6 :
+ print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case EPIPHANY_OPERAND_IMM16 :
+ print_address (cd, info, fields->f_imm16, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
+ case EPIPHANY_OPERAND_IMM8 :
+ print_address (cd, info, fields->f_imm8, 0|(1<<CGEN_OPERAND_RELAX), pc, length);
+ break;
+ case EPIPHANY_OPERAND_RD :
+ print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd, 0);
+ break;
+ case EPIPHANY_OPERAND_RD6 :
+ print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case EPIPHANY_OPERAND_RM :
+ print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm, 0);
+ break;
+ case EPIPHANY_OPERAND_RM6 :
+ print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case EPIPHANY_OPERAND_RN :
+ print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn, 0);
+ break;
+ case EPIPHANY_OPERAND_RN6 :
+ print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case EPIPHANY_OPERAND_SD :
+ print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sd, 0);
+ break;
+ case EPIPHANY_OPERAND_SD6 :
+ print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case EPIPHANY_OPERAND_SDDMA :
+ print_keyword (cd, info, & epiphany_cgen_opval_crdma_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case EPIPHANY_OPERAND_SDMEM :
+ print_keyword (cd, info, & epiphany_cgen_opval_crmem_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case EPIPHANY_OPERAND_SDMESH :
+ print_keyword (cd, info, & epiphany_cgen_opval_crmesh_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case EPIPHANY_OPERAND_SHIFT :
+ print_normal (cd, info, fields->f_shift, 0, pc, length);
+ break;
+ case EPIPHANY_OPERAND_SIMM11 :
+ print_simm_not_reg (cd, info, fields->f_sdisp11, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
+ case EPIPHANY_OPERAND_SIMM24 :
+ print_address (cd, info, fields->f_simm24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case EPIPHANY_OPERAND_SIMM3 :
+ print_simm_not_reg (cd, info, fields->f_sdisp3, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX), pc, length);
+ break;
+ case EPIPHANY_OPERAND_SIMM8 :
+ print_address (cd, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case EPIPHANY_OPERAND_SN :
+ print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sn, 0);
+ break;
+ case EPIPHANY_OPERAND_SN6 :
+ print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case EPIPHANY_OPERAND_SNDMA :
+ print_keyword (cd, info, & epiphany_cgen_opval_crdma_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case EPIPHANY_OPERAND_SNMEM :
+ print_keyword (cd, info, & epiphany_cgen_opval_crmem_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case EPIPHANY_OPERAND_SNMESH :
+ print_keyword (cd, info, & epiphany_cgen_opval_crmesh_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case EPIPHANY_OPERAND_SWI_NUM :
+ print_uimm_not_reg (cd, info, fields->f_trap_num, 0, pc, length);
+ break;
+ case EPIPHANY_OPERAND_TRAPNUM6 :
+ print_normal (cd, info, fields->f_trap_num, 0, pc, length);
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
+ opindex);
+ abort ();
+ }
+}
+
+cgen_print_fn * const epiphany_cgen_print_handlers[] =
+{
+ print_insn_normal,
+};
+
+
+void
+epiphany_cgen_init_dis (CGEN_CPU_DESC cd)
+{
+ epiphany_cgen_init_opcode_table (cd);
+ epiphany_cgen_init_ibld_table (cd);
+ cd->print_handlers = & epiphany_cgen_print_handlers[0];
+ cd->print_operand = epiphany_cgen_print_operand;
+}
+
+\f
+/* Default print handler. */
+
+static void
+print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void *dis_info,
+ long value,
+ unsigned int attrs,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+ /* Print the operand as directed by the attributes. */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+ ; /* nothing to do */
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+ (*info->fprintf_func) (info->stream, "%ld", value);
+ else
+ (*info->fprintf_func) (info->stream, "0x%lx", value);
+}
+
+/* Default address handler. */
+
+static void
+print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void *dis_info,
+ bfd_vma value,
+ unsigned int attrs,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+ /* Print the operand as directed by the attributes. */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+ ; /* Nothing to do. */
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
+ (*info->print_address_func) (value, info);
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
+ (*info->print_address_func) (value, info);
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+ (*info->fprintf_func) (info->stream, "%ld", (long) value);
+ else
+ (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
+}
+
+/* Keyword print handler. */
+
+static void
+print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void *dis_info,
+ CGEN_KEYWORD *keyword_table,
+ long value,
+ unsigned int attrs ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+ const CGEN_KEYWORD_ENTRY *ke;
+
+ ke = cgen_keyword_lookup_value (keyword_table, value);
+ if (ke != NULL)
+ (*info->fprintf_func) (info->stream, "%s", ke->name);
+ else
+ (*info->fprintf_func) (info->stream, "???");
+}
+\f
+/* Default insn printer.
+
+ DIS_INFO is defined as `void *' so the disassembler needn't know anything
+ about disassemble_info. */
+
+static void
+print_insn_normal (CGEN_CPU_DESC cd,
+ void *dis_info,
+ const CGEN_INSN *insn,
+ CGEN_FIELDS *fields,
+ bfd_vma pc,
+ int length)
+{
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ disassemble_info *info = (disassemble_info *) dis_info;
+ const CGEN_SYNTAX_CHAR_TYPE *syn;
+
+ CGEN_INIT_PRINT (cd);
+
+ for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+ {
+ if (CGEN_SYNTAX_MNEMONIC_P (*syn))
+ {
+ (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
+ continue;
+ }
+ if (CGEN_SYNTAX_CHAR_P (*syn))
+ {
+ (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
+ continue;
+ }
+
+ /* We have an operand. */
+ epiphany_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
+ fields, CGEN_INSN_ATTRS (insn), pc, length);
+ }
+}
+\f
+/* Subroutine of print_insn. Reads an insn into the given buffers and updates
+ the extract info.
+ Returns 0 if all is well, non-zero otherwise. */
+
+static int
+read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ bfd_vma pc,
+ disassemble_info *info,
+ bfd_byte *buf,
+ int buflen,
+ CGEN_EXTRACT_INFO *ex_info,
+ unsigned long *insn_value)
+{
+ int status = (*info->read_memory_func) (pc, buf, buflen, info);
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ ex_info->dis_info = info;
+ ex_info->valid = (1 << buflen) - 1;
+ ex_info->insn_bytes = buf;
+
+ *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
+ return 0;
+}
+
+/* Utility to print an insn.
+ BUF is the base part of the insn, target byte order, BUFLEN bytes long.
+ The result is the size of the insn in bytes or zero for an unknown insn
+ or -1 if an error occurs fetching data (memory_error_func will have
+ been called). */
+
+static int
+print_insn (CGEN_CPU_DESC cd,
+ bfd_vma pc,
+ disassemble_info *info,
+ bfd_byte *buf,
+ unsigned int buflen)
+{
+ CGEN_INSN_INT insn_value;
+ const CGEN_INSN_LIST *insn_list;
+ CGEN_EXTRACT_INFO ex_info;
+ int basesize;
+
+ /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
+ basesize = cd->base_insn_bitsize < buflen * 8 ?
+ cd->base_insn_bitsize : buflen * 8;
+ insn_value = cgen_get_insn_value (cd, buf, basesize);
+
+
+ /* Fill in ex_info fields like read_insn would. Don't actually call
+ read_insn, since the incoming buffer is already read (and possibly
+ modified a la m32r). */
+ ex_info.valid = (1 << buflen) - 1;
+ ex_info.dis_info = info;
+ ex_info.insn_bytes = buf;
+
+ /* The instructions are stored in hash lists.
+ Pick the first one and keep trying until we find the right one. */
+
+ insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
+ while (insn_list != NULL)
+ {
+ const CGEN_INSN *insn = insn_list->insn;
+ CGEN_FIELDS fields;
+ int length;
+ unsigned long insn_value_cropped;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
+ /* Supported by this cpu? */
+ if (! epiphany_cgen_insn_supported (cd, insn))
+ {
+ insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+ continue;
+ }
+#endif
+
+ /* Basic bit mask must be correct. */
+ /* ??? May wish to allow target to defer this check until the extract
+ handler. */
+
+ /* Base size may exceed this instruction's size. Extract the
+ relevant part from the buffer. */
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ info->endian == BFD_ENDIAN_BIG);
+ else
+ insn_value_cropped = insn_value;
+
+ if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
+ == CGEN_INSN_BASE_VALUE (insn))
+ {
+ /* Printing is handled in two passes. The first pass parses the
+ machine insn and extracts the fields. The second pass prints
+ them. */
+
+ /* Make sure the entire insn is loaded into insn_value, if it
+ can fit. */
+ if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ {
+ unsigned long full_insn_value;
+ int rc = read_insn (cd, pc, info, buf,
+ CGEN_INSN_BITSIZE (insn) / 8,
+ & ex_info, & full_insn_value);
+ if (rc != 0)
+ return rc;
+ length = CGEN_EXTRACT_FN (cd, insn)
+ (cd, insn, &ex_info, full_insn_value, &fields, pc);
+ }
+ else
+ length = CGEN_EXTRACT_FN (cd, insn)
+ (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
+
+ /* Length < 0 -> error. */
+ if (length < 0)
+ return length;
+ if (length > 0)
+ {
+ CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
+ /* Length is in bits, result is in bytes. */
+ return length / 8;
+ }
+ }
+
+ insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+ }
+
+ return 0;
+}
+
+/* Default value for CGEN_PRINT_INSN.
+ The result is the size of the insn in bytes or zero for an unknown insn
+ or -1 if an error occured fetching bytes. */
+
+#ifndef CGEN_PRINT_INSN
+#define CGEN_PRINT_INSN default_print_insn
+#endif
+
+static int
+default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
+{
+ bfd_byte buf[CGEN_MAX_INSN_SIZE];
+ int buflen;
+ int status;
+
+ /* Attempt to read the base part of the insn. */
+ buflen = cd->base_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+
+ /* Try again with the minimum part, if min < base. */
+ if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
+ {
+ buflen = cd->min_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+ }
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ return print_insn (cd, pc, info, buf, buflen);
+}
+
+/* Main entry point.
+ Print one instruction from PC on INFO->STREAM.
+ Return the size of the instruction (in bytes). */
+
+typedef struct cpu_desc_list
+{
+ struct cpu_desc_list *next;
+ CGEN_BITSET *isa;
+ int mach;
+ int endian;
+ CGEN_CPU_DESC cd;
+} cpu_desc_list;
+
+int
+print_insn_epiphany (bfd_vma pc, disassemble_info *info)
+{
+ static cpu_desc_list *cd_list = 0;
+ cpu_desc_list *cl = 0;
+ static CGEN_CPU_DESC cd = 0;
+ static CGEN_BITSET *prev_isa;
+ static int prev_mach;
+ static int prev_endian;
+ int length;
+ CGEN_BITSET *isa;
+ int mach;
+ int endian = (info->endian == BFD_ENDIAN_BIG
+ ? CGEN_ENDIAN_BIG
+ : CGEN_ENDIAN_LITTLE);
+ enum bfd_architecture arch;
+
+ /* ??? gdb will set mach but leave the architecture as "unknown" */
+#ifndef CGEN_BFD_ARCH
+#define CGEN_BFD_ARCH bfd_arch_epiphany
+#endif
+ arch = info->arch;
+ if (arch == bfd_arch_unknown)
+ arch = CGEN_BFD_ARCH;
+
+ /* There's no standard way to compute the machine or isa number
+ so we leave it to the target. */
+#ifdef CGEN_COMPUTE_MACH
+ mach = CGEN_COMPUTE_MACH (info);
+#else
+ mach = info->mach;
+#endif
+
+#ifdef CGEN_COMPUTE_ISA
+ {
+ static CGEN_BITSET *permanent_isa;
+
+ if (!permanent_isa)
+ permanent_isa = cgen_bitset_create (MAX_ISAS);
+ isa = permanent_isa;
+ cgen_bitset_clear (isa);
+ cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
+ }
+#else
+ isa = info->insn_sets;
+#endif
+
+ /* If we've switched cpu's, try to find a handle we've used before */
+ if (cd
+ && (cgen_bitset_compare (isa, prev_isa) != 0
+ || mach != prev_mach
+ || endian != prev_endian))
+ {
+ cd = 0;
+ for (cl = cd_list; cl; cl = cl->next)
+ {
+ if (cgen_bitset_compare (cl->isa, isa) == 0 &&
+ cl->mach == mach &&
+ cl->endian == endian)
+ {
+ cd = cl->cd;
+ prev_isa = cd->isas;
+ break;
+ }
+ }
+ }
+
+ /* If we haven't initialized yet, initialize the opcode table. */
+ if (! cd)
+ {
+ const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
+ const char *mach_name;
+
+ if (!arch_type)
+ abort ();
+ mach_name = arch_type->printable_name;
+
+ prev_isa = cgen_bitset_copy (isa);
+ prev_mach = mach;
+ prev_endian = endian;
+ cd = epiphany_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
+ CGEN_CPU_OPEN_BFDMACH, mach_name,
+ CGEN_CPU_OPEN_ENDIAN, prev_endian,
+ CGEN_CPU_OPEN_END);
+ if (!cd)
+ abort ();
+
+ /* Save this away for future reference. */
+ cl = xmalloc (sizeof (struct cpu_desc_list));
+ cl->cd = cd;
+ cl->isa = prev_isa;
+ cl->mach = mach;
+ cl->endian = endian;
+ cl->next = cd_list;
+ cd_list = cl;
+
+ epiphany_cgen_init_dis (cd);
+ }
+
+ /* We try to have as much common code as possible.
+ But at this point some targets need to take over. */
+ /* ??? Some targets may need a hook elsewhere. Try to avoid this,
+ but if not possible try to move this hook elsewhere rather than
+ have two hooks. */
+ length = CGEN_PRINT_INSN (cd, pc, info);
+ if (length > 0)
+ return length;
+ if (length < 0)
+ return -1;
+
+ (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
+ return cd->default_insn_bitsize / 8;
+}
--- /dev/null
+/* Instruction building/extraction support for epiphany. -*- C -*-
+
+ THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
+ - the resultant file is machine generated, cgen-ibld.in isn't
+
+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007,
+ 2008, 2010 Free Software Foundation, Inc.
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+ Keep that in mind. */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "dis-asm.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "epiphany-desc.h"
+#include "epiphany-opc.h"
+#include "cgen/basic-modes.h"
+#include "opintl.h"
+#include "safe-ctype.h"
+
+#undef min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+/* Used by the ifield rtx function. */
+#define FLD(f) (fields->f)
+
+static const char * insert_normal
+ (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
+ unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
+static const char * insert_insn_normal
+ (CGEN_CPU_DESC, const CGEN_INSN *,
+ CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
+static int extract_normal
+ (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+ unsigned int, unsigned int, unsigned int, unsigned int,
+ unsigned int, unsigned int, bfd_vma, long *);
+static int extract_insn_normal
+ (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
+ CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
+#if CGEN_INT_INSN_P
+static void put_insn_int_value
+ (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
+#endif
+#if ! CGEN_INT_INSN_P
+static CGEN_INLINE void insert_1
+ (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
+static CGEN_INLINE int fill_cache
+ (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma);
+static CGEN_INLINE long extract_1
+ (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
+#endif
+\f
+/* Operand insertion. */
+
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of insert_normal. */
+
+static CGEN_INLINE void
+insert_1 (CGEN_CPU_DESC cd,
+ unsigned long value,
+ int start,
+ int length,
+ int word_length,
+ unsigned char *bufp)
+{
+ unsigned long x,mask;
+ int shift;
+
+ x = cgen_get_insn_value (cd, bufp, word_length);
+
+ /* Written this way to avoid undefined behaviour. */
+ mask = (((1L << (length - 1)) - 1) << 1) | 1;
+ if (CGEN_INSN_LSB0_P)
+ shift = (start + 1) - length;
+ else
+ shift = (word_length - (start + length));
+ x = (x & ~(mask << shift)) | ((value & mask) << shift);
+
+ cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default insertion routine.
+
+ ATTRS is a mask of the boolean attributes.
+ WORD_OFFSET is the offset in bits from the start of the insn of the value.
+ WORD_LENGTH is the length of the word in bits in which the value resides.
+ START is the starting bit number in the word, architecture origin.
+ LENGTH is the length of VALUE in bits.
+ TOTAL_LENGTH is the total length of the insn in bits.
+
+ The result is an error message or NULL if success. */
+
+/* ??? This duplicates functionality with bfd's howto table and
+ bfd_install_relocation. */
+/* ??? This doesn't handle bfd_vma's. Create another function when
+ necessary. */
+
+static const char *
+insert_normal (CGEN_CPU_DESC cd,
+ long value,
+ unsigned int attrs,
+ unsigned int word_offset,
+ unsigned int start,
+ unsigned int length,
+ unsigned int word_length,
+ unsigned int total_length,
+ CGEN_INSN_BYTES_PTR buffer)
+{
+ static char errbuf[100];
+ /* Written this way to avoid undefined behaviour. */
+ unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+ /* If LENGTH is zero, this operand doesn't contribute to the value. */
+ if (length == 0)
+ return NULL;
+
+ if (word_length > 8 * sizeof (CGEN_INSN_INT))
+ abort ();
+
+ /* For architectures with insns smaller than the base-insn-bitsize,
+ word_length may be too big. */
+ if (cd->min_insn_bitsize < cd->base_insn_bitsize)
+ {
+ if (word_offset == 0
+ && word_length > total_length)
+ word_length = total_length;
+ }
+
+ /* Ensure VALUE will fit. */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
+ {
+ long minval = - (1L << (length - 1));
+ unsigned long maxval = mask;
+
+ if ((value > 0 && (unsigned long) value > maxval)
+ || value < minval)
+ {
+ /* xgettext:c-format */
+ sprintf (errbuf,
+ _("operand out of range (%ld not between %ld and %lu)"),
+ value, minval, maxval);
+ return errbuf;
+ }
+ }
+ else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
+ {
+ unsigned long maxval = mask;
+ unsigned long val = (unsigned long) value;
+
+ /* For hosts with a word size > 32 check to see if value has been sign
+ extended beyond 32 bits. If so then ignore these higher sign bits
+ as the user is attempting to store a 32-bit signed value into an
+ unsigned 32-bit field which is allowed. */
+ if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
+ val &= 0xFFFFFFFF;
+
+ if (val > maxval)
+ {
+ /* xgettext:c-format */
+ sprintf (errbuf,
+ _("operand out of range (0x%lx not between 0 and 0x%lx)"),
+ val, maxval);
+ return errbuf;
+ }
+ }
+ else
+ {
+ if (! cgen_signed_overflow_ok_p (cd))
+ {
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+
+ if (value < minval || value > maxval)
+ {
+ sprintf
+ /* xgettext:c-format */
+ (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
+ value, minval, maxval);
+ return errbuf;
+ }
+ }
+ }
+
+#if CGEN_INT_INSN_P
+
+ {
+ int shift;
+
+ if (CGEN_INSN_LSB0_P)
+ shift = (word_offset + start + 1) - length;
+ else
+ shift = total_length - (word_offset + start + length);
+ *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
+ }
+
+#else /* ! CGEN_INT_INSN_P */
+
+ {
+ unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
+
+ insert_1 (cd, value, start, length, word_length, bufp);
+ }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+ return NULL;
+}
+
+/* Default insn builder (insert handler).
+ The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
+ that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
+ recorded in host byte order, otherwise BUFFER is an array of bytes
+ and the value is recorded in target byte order).
+ The result is an error message or NULL if success. */
+
+static const char *
+insert_insn_normal (CGEN_CPU_DESC cd,
+ const CGEN_INSN * insn,
+ CGEN_FIELDS * fields,
+ CGEN_INSN_BYTES_PTR buffer,
+ bfd_vma pc)
+{
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ unsigned long value;
+ const CGEN_SYNTAX_CHAR_TYPE * syn;
+
+ CGEN_INIT_INSERT (cd);
+ value = CGEN_INSN_BASE_VALUE (insn);
+
+ /* If we're recording insns as numbers (rather than a string of bytes),
+ target byte order handling is deferred until later. */
+
+#if CGEN_INT_INSN_P
+
+ put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
+ CGEN_FIELDS_BITSIZE (fields), value);
+
+#else
+
+ cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
+ (unsigned) CGEN_FIELDS_BITSIZE (fields)),
+ value);
+
+#endif /* ! CGEN_INT_INSN_P */
+
+ /* ??? It would be better to scan the format's fields.
+ Still need to be able to insert a value based on the operand though;
+ e.g. storing a branch displacement that got resolved later.
+ Needs more thought first. */
+
+ for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
+ {
+ const char *errmsg;
+
+ if (CGEN_SYNTAX_CHAR_P (* syn))
+ continue;
+
+ errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
+ fields, buffer, pc);
+ if (errmsg)
+ return errmsg;
+ }
+
+ return NULL;
+}
+
+#if CGEN_INT_INSN_P
+/* Cover function to store an insn value into an integral insn. Must go here
+ because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
+
+static void
+put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ CGEN_INSN_BYTES_PTR buf,
+ int length,
+ int insn_length,
+ CGEN_INSN_INT value)
+{
+ /* For architectures with insns smaller than the base-insn-bitsize,
+ length may be too big. */
+ if (length > insn_length)
+ *buf = value;
+ else
+ {
+ int shift = insn_length - length;
+ /* Written this way to avoid undefined behaviour. */
+ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+ *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
+ }
+}
+#endif
+\f
+/* Operand extraction. */
+
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of extract_normal.
+ Ensure sufficient bytes are cached in EX_INFO.
+ OFFSET is the offset in bytes from the start of the insn of the value.
+ BYTES is the length of the needed value.
+ Returns 1 for success, 0 for failure. */
+
+static CGEN_INLINE int
+fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ CGEN_EXTRACT_INFO *ex_info,
+ int offset,
+ int bytes,
+ bfd_vma pc)
+{
+ /* It's doubtful that the middle part has already been fetched so
+ we don't optimize that case. kiss. */
+ unsigned int mask;
+ disassemble_info *info = (disassemble_info *) ex_info->dis_info;
+
+ /* First do a quick check. */
+ mask = (1 << bytes) - 1;
+ if (((ex_info->valid >> offset) & mask) == mask)
+ return 1;
+
+ /* Search for the first byte we need to read. */
+ for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
+ if (! (mask & ex_info->valid))
+ break;
+
+ if (bytes)
+ {
+ int status;
+
+ pc += offset;
+ status = (*info->read_memory_func)
+ (pc, ex_info->insn_bytes + offset, bytes, info);
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return 0;
+ }
+
+ ex_info->valid |= ((1 << bytes) - 1) << offset;
+ }
+
+ return 1;
+}
+
+/* Subroutine of extract_normal. */
+
+static CGEN_INLINE long
+extract_1 (CGEN_CPU_DESC cd,
+ CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
+ int start,
+ int length,
+ int word_length,
+ unsigned char *bufp,
+ bfd_vma pc ATTRIBUTE_UNUSED)
+{
+ unsigned long x;
+ int shift;
+
+ x = cgen_get_insn_value (cd, bufp, word_length);
+
+ if (CGEN_INSN_LSB0_P)
+ shift = (start + 1) - length;
+ else
+ shift = (word_length - (start + length));
+ return x >> shift;
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default extraction routine.
+
+ INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
+ or sometimes less for cases like the m32r where the base insn size is 32
+ but some insns are 16 bits.
+ ATTRS is a mask of the boolean attributes. We only need `SIGNED',
+ but for generality we take a bitmask of all of them.
+ WORD_OFFSET is the offset in bits from the start of the insn of the value.
+ WORD_LENGTH is the length of the word in bits in which the value resides.
+ START is the starting bit number in the word, architecture origin.
+ LENGTH is the length of VALUE in bits.
+ TOTAL_LENGTH is the total length of the insn in bits.
+
+ Returns 1 for success, 0 for failure. */
+
+/* ??? The return code isn't properly used. wip. */
+
+/* ??? This doesn't handle bfd_vma's. Create another function when
+ necessary. */
+
+static int
+extract_normal (CGEN_CPU_DESC cd,
+#if ! CGEN_INT_INSN_P
+ CGEN_EXTRACT_INFO *ex_info,
+#else
+ CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
+#endif
+ CGEN_INSN_INT insn_value,
+ unsigned int attrs,
+ unsigned int word_offset,
+ unsigned int start,
+ unsigned int length,
+ unsigned int word_length,
+ unsigned int total_length,
+#if ! CGEN_INT_INSN_P
+ bfd_vma pc,
+#else
+ bfd_vma pc ATTRIBUTE_UNUSED,
+#endif
+ long *valuep)
+{
+ long value, mask;
+
+ /* If LENGTH is zero, this operand doesn't contribute to the value
+ so give it a standard value of zero. */
+ if (length == 0)
+ {
+ *valuep = 0;
+ return 1;
+ }
+
+ if (word_length > 8 * sizeof (CGEN_INSN_INT))
+ abort ();
+
+ /* For architectures with insns smaller than the insn-base-bitsize,
+ word_length may be too big. */
+ if (cd->min_insn_bitsize < cd->base_insn_bitsize)
+ {
+ if (word_offset + word_length > total_length)
+ word_length = total_length - word_offset;
+ }
+
+ /* Does the value reside in INSN_VALUE, and at the right alignment? */
+
+ if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
+ {
+ if (CGEN_INSN_LSB0_P)
+ value = insn_value >> ((word_offset + start + 1) - length);
+ else
+ value = insn_value >> (total_length - ( word_offset + start + length));
+ }
+
+#if ! CGEN_INT_INSN_P
+
+ else
+ {
+ unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
+
+ if (word_length > 8 * sizeof (CGEN_INSN_INT))
+ abort ();
+
+ if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
+ return 0;
+
+ value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
+ }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+ /* Written this way to avoid undefined behaviour. */
+ mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+ value &= mask;
+ /* sign extend? */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
+ && (value & (1L << (length - 1))))
+ value |= ~mask;
+
+ *valuep = value;
+
+ return 1;
+}
+
+/* Default insn extractor.
+
+ INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
+ The extracted fields are stored in FIELDS.
+ EX_INFO is used to handle reading variable length insns.
+ Return the length of the insn in bits, or 0 if no match,
+ or -1 if an error occurs fetching data (memory_error_func will have
+ been called). */
+
+static int
+extract_insn_normal (CGEN_CPU_DESC cd,
+ const CGEN_INSN *insn,
+ CGEN_EXTRACT_INFO *ex_info,
+ CGEN_INSN_INT insn_value,
+ CGEN_FIELDS *fields,
+ bfd_vma pc)
+{
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ const CGEN_SYNTAX_CHAR_TYPE *syn;
+
+ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+ CGEN_INIT_EXTRACT (cd);
+
+ for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+ {
+ int length;
+
+ if (CGEN_SYNTAX_CHAR_P (*syn))
+ continue;
+
+ length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
+ ex_info, insn_value, fields, pc);
+ if (length <= 0)
+ return length;
+ }
+
+ /* We recognized and successfully extracted this insn. */
+ return CGEN_INSN_BITSIZE (insn);
+}
+\f
+/* Machine generated code added here. */
+
+const char * epiphany_cgen_insert_operand
+ (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
+
+/* Main entry point for operand insertion.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `parse_insn_normal', but keeping it
+ separate makes clear the interface between `parse_insn_normal' and each of
+ the handlers. It's also needed by GAS to insert operands that couldn't be
+ resolved during parsing. */
+
+const char *
+epiphany_cgen_insert_operand (CGEN_CPU_DESC cd,
+ int opindex,
+ CGEN_FIELDS * fields,
+ CGEN_INSN_BYTES_PTR buffer,
+ bfd_vma pc ATTRIBUTE_UNUSED)
+{
+ const char * errmsg = NULL;
+ unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
+
+ switch (opindex)
+ {
+ case EPIPHANY_OPERAND_DIRECTION :
+ errmsg = insert_normal (cd, fields->f_addsubx, 0, 0, 20, 1, 32, total_length, buffer);
+ break;
+ case EPIPHANY_OPERAND_DISP11 :
+ {
+{
+ FLD (f_disp8) = ((((UINT) (FLD (f_disp11)) >> (3))) & (255));
+ FLD (f_disp3) = ((FLD (f_disp11)) & (7));
+}
+ errmsg = insert_normal (cd, fields->f_disp3, 0, 0, 9, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_disp8, 0, 0, 23, 8, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case EPIPHANY_OPERAND_DISP3 :
+ errmsg = insert_normal (cd, fields->f_disp3, 0, 0, 9, 3, 32, total_length, buffer);
+ break;
+ case EPIPHANY_OPERAND_DPMI :
+ errmsg = insert_normal (cd, fields->f_subd, 0, 0, 24, 1, 32, total_length, buffer);
+ break;
+ case EPIPHANY_OPERAND_FRD :
+ errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer);
+ break;
+ case EPIPHANY_OPERAND_FRD6 :
+ {
+{
+ FLD (f_rd) = ((FLD (f_rd6)) & (7));
+ FLD (f_rd_x) = ((UINT) (FLD (f_rd6)) >> (3));
+}
+ errmsg = insert_normal (cd, fields->f_rd_x, 0, 0, 31, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case EPIPHANY_OPERAND_FRM :
+ errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer);
+ break;
+ case EPIPHANY_OPERAND_FRM6 :
+ {
+{
+ FLD (f_rm) = ((FLD (f_rm6)) & (7));
+ FLD (f_rm_x) = ((UINT) (FLD (f_rm6)) >> (3));
+}
+ errmsg = insert_normal (cd, fields->f_rm_x, 0, 0, 25, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case EPIPHANY_OPERAND_FRN :
+ errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer);
+ break;
+ case EPIPHANY_OPERAND_FRN6 :
+ {
+{
+ FLD (f_rn) = ((FLD (f_rn6)) & (7));
+ FLD (f_rn_x) = ((UINT) (FLD (f_rn6)) >> (3));
+}
+ errmsg = insert_normal (cd, fields->f_rn_x, 0, 0, 28, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case EPIPHANY_OPERAND_IMM16 :
+ {
+{
+ FLD (f_imm8) = ((FLD (f_imm16)) & (255));
+ FLD (f_imm_27_8) = ((UINT) (FLD (f_imm16)) >> (8));
+}
+ errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 12, 8, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_imm_27_8, 0, 0, 27, 8, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case EPIPHANY_OPERAND_IMM8 :
+ errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 12, 8, 32, total_length, buffer);
+ break;
+ case EPIPHANY_OPERAND_RD :
+ errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer);
+ break;
+ case EPIPHANY_OPERAND_RD6 :
+ {
+{
+ FLD (f_rd) = ((FLD (f_rd6)) & (7));
+ FLD (f_rd_x) = ((UINT) (FLD (f_rd6)) >> (3));
+}
+ errmsg = insert_normal (cd, fields->f_rd_x, 0, 0, 31, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case EPIPHANY_OPERAND_RM :
+ errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer);
+ break;
+ case EPIPHANY_OPERAND_RM6 :
+ {
+{
+ FLD (f_rm) = ((FLD (f_rm6)) & (7));
+ FLD (f_rm_x) = ((UINT) (FLD (f_rm6)) >> (3));
+}
+ errmsg = insert_normal (cd, fields->f_rm_x, 0, 0, 25, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case EPIPHANY_OPERAND_RN :
+ errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer);
+ break;
+ case EPIPHANY_OPERAND_RN6 :
+ {
+{
+ FLD (f_rn) = ((FLD (f_rn6)) & (7));
+ FLD (f_rn_x) = ((UINT) (FLD (f_rn6)) >> (3));
+}
+ errmsg = insert_normal (cd, fields->f_rn_x, 0, 0, 28, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case EPIPHANY_OPERAND_SD :
+ errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer);
+ break;
+ case EPIPHANY_OPERAND_SD6 :
+ {
+{
+ FLD (f_sd) = ((FLD (f_sd6)) & (7));
+ FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3));
+}
+ errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case EPIPHANY_OPERAND_SDDMA :
+ {
+{
+ FLD (f_sd) = ((FLD (f_sd6)) & (7));
+ FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3));
+}
+ errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case EPIPHANY_OPERAND_SDMEM :
+ {
+{
+ FLD (f_sd) = ((FLD (f_sd6)) & (7));
+ FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3));
+}
+ errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case EPIPHANY_OPERAND_SDMESH :
+ {
+{
+ FLD (f_sd) = ((FLD (f_sd6)) & (7));
+ FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3));
+}
+ errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case EPIPHANY_OPERAND_SHIFT :
+ errmsg = insert_normal (cd, fields->f_shift, 0, 0, 9, 5, 32, total_length, buffer);
+ break;
+ case EPIPHANY_OPERAND_SIMM11 :
+ {
+{
+ FLD (f_disp8) = ((255) & (((USI) (FLD (f_sdisp11)) >> (3))));
+ FLD (f_disp3) = ((FLD (f_sdisp11)) & (7));
+}
+ errmsg = insert_normal (cd, fields->f_disp3, 0, 0, 9, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_disp8, 0, 0, 23, 8, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case EPIPHANY_OPERAND_SIMM24 :
+ {
+ long value = fields->f_simm24;
+ value = ((SI) (((value) - (pc))) >> (1));
+ errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 31, 24, 32, total_length, buffer);
+ }
+ break;
+ case EPIPHANY_OPERAND_SIMM3 :
+ errmsg = insert_normal (cd, fields->f_sdisp3, 0|(1<<CGEN_IFLD_SIGNED), 0, 9, 3, 32, total_length, buffer);
+ break;
+ case EPIPHANY_OPERAND_SIMM8 :
+ {
+ long value = fields->f_simm8;
+ value = ((SI) (((value) - (pc))) >> (1));
+ errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 8, 32, total_length, buffer);
+ }
+ break;
+ case EPIPHANY_OPERAND_SN :
+ errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer);
+ break;
+ case EPIPHANY_OPERAND_SN6 :
+ {
+{
+ FLD (f_sn) = ((FLD (f_sn6)) & (7));
+ FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3));
+}
+ errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case EPIPHANY_OPERAND_SNDMA :
+ {
+{
+ FLD (f_sn) = ((FLD (f_sn6)) & (7));
+ FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3));
+}
+ errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case EPIPHANY_OPERAND_SNMEM :
+ {
+{
+ FLD (f_sn) = ((FLD (f_sn6)) & (7));
+ FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3));
+}
+ errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case EPIPHANY_OPERAND_SNMESH :
+ {
+{
+ FLD (f_sn) = ((FLD (f_sn6)) & (7));
+ FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3));
+}
+ errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case EPIPHANY_OPERAND_SWI_NUM :
+ errmsg = insert_normal (cd, fields->f_trap_num, 0, 0, 15, 6, 32, total_length, buffer);
+ break;
+ case EPIPHANY_OPERAND_TRAPNUM6 :
+ errmsg = insert_normal (cd, fields->f_trap_num, 0, 0, 15, 6, 32, total_length, buffer);
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
+ opindex);
+ abort ();
+ }
+
+ return errmsg;
+}
+
+int epiphany_cgen_extract_operand
+ (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
+
+/* Main entry point for operand extraction.
+ The result is <= 0 for error, >0 for success.
+ ??? Actual values aren't well defined right now.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `print_insn_normal', but keeping it
+ separate makes clear the interface between `print_insn_normal' and each of
+ the handlers. */
+
+int
+epiphany_cgen_extract_operand (CGEN_CPU_DESC cd,
+ int opindex,
+ CGEN_EXTRACT_INFO *ex_info,
+ CGEN_INSN_INT insn_value,
+ CGEN_FIELDS * fields,
+ bfd_vma pc)
+{
+ /* Assume success (for those operands that are nops). */
+ int length = 1;
+ unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
+
+ switch (opindex)
+ {
+ case EPIPHANY_OPERAND_DIRECTION :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 1, 32, total_length, pc, & fields->f_addsubx);
+ break;
+ case EPIPHANY_OPERAND_DISP11 :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_disp3);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_disp8);
+ if (length <= 0) break;
+{
+ FLD (f_disp11) = ((((FLD (f_disp8)) << (3))) | (FLD (f_disp3)));
+}
+ }
+ break;
+ case EPIPHANY_OPERAND_DISP3 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_disp3);
+ break;
+ case EPIPHANY_OPERAND_DPMI :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 1, 32, total_length, pc, & fields->f_subd);
+ break;
+ case EPIPHANY_OPERAND_FRD :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd);
+ break;
+ case EPIPHANY_OPERAND_FRD6 :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_rd_x);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd);
+ if (length <= 0) break;
+{
+ FLD (f_rd6) = ((((FLD (f_rd_x)) << (3))) | (FLD (f_rd)));
+}
+ }
+ break;
+ case EPIPHANY_OPERAND_FRM :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm);
+ break;
+ case EPIPHANY_OPERAND_FRM6 :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_rm_x);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm);
+ if (length <= 0) break;
+{
+ FLD (f_rm6) = ((((FLD (f_rm_x)) << (3))) | (FLD (f_rm)));
+}
+ }
+ break;
+ case EPIPHANY_OPERAND_FRN :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn);
+ break;
+ case EPIPHANY_OPERAND_FRN6 :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_rn_x);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn);
+ if (length <= 0) break;
+{
+ FLD (f_rn6) = ((((FLD (f_rn_x)) << (3))) | (FLD (f_rn)));
+}
+ }
+ break;
+ case EPIPHANY_OPERAND_IMM16 :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 8, 32, total_length, pc, & fields->f_imm8);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 8, 32, total_length, pc, & fields->f_imm_27_8);
+ if (length <= 0) break;
+{
+ FLD (f_imm16) = ((((FLD (f_imm_27_8)) << (8))) | (FLD (f_imm8)));
+}
+ }
+ break;
+ case EPIPHANY_OPERAND_IMM8 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 8, 32, total_length, pc, & fields->f_imm8);
+ break;
+ case EPIPHANY_OPERAND_RD :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd);
+ break;
+ case EPIPHANY_OPERAND_RD6 :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_rd_x);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd);
+ if (length <= 0) break;
+{
+ FLD (f_rd6) = ((((FLD (f_rd_x)) << (3))) | (FLD (f_rd)));
+}
+ }
+ break;
+ case EPIPHANY_OPERAND_RM :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm);
+ break;
+ case EPIPHANY_OPERAND_RM6 :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_rm_x);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm);
+ if (length <= 0) break;
+{
+ FLD (f_rm6) = ((((FLD (f_rm_x)) << (3))) | (FLD (f_rm)));
+}
+ }
+ break;
+ case EPIPHANY_OPERAND_RN :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn);
+ break;
+ case EPIPHANY_OPERAND_RN6 :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_rn_x);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn);
+ if (length <= 0) break;
+{
+ FLD (f_rn6) = ((((FLD (f_rn_x)) << (3))) | (FLD (f_rn)));
+}
+ }
+ break;
+ case EPIPHANY_OPERAND_SD :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd);
+ break;
+ case EPIPHANY_OPERAND_SD6 :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd);
+ if (length <= 0) break;
+{
+ FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd)));
+}
+ }
+ break;
+ case EPIPHANY_OPERAND_SDDMA :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd);
+ if (length <= 0) break;
+{
+ FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd)));
+}
+ }
+ break;
+ case EPIPHANY_OPERAND_SDMEM :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd);
+ if (length <= 0) break;
+{
+ FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd)));
+}
+ }
+ break;
+ case EPIPHANY_OPERAND_SDMESH :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd);
+ if (length <= 0) break;
+{
+ FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd)));
+}
+ }
+ break;
+ case EPIPHANY_OPERAND_SHIFT :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 5, 32, total_length, pc, & fields->f_shift);
+ break;
+ case EPIPHANY_OPERAND_SIMM11 :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_disp3);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_disp8);
+ if (length <= 0) break;
+{
+ FLD (f_sdisp11) = ((SI) (((((((FLD (f_disp8)) << (3))) | (FLD (f_disp3)))) << (21))) >> (21));
+}
+ }
+ break;
+ case EPIPHANY_OPERAND_SIMM24 :
+ {
+ long value;
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 31, 24, 32, total_length, pc, & value);
+ value = ((((value) << (1))) + (pc));
+ fields->f_simm24 = value;
+ }
+ break;
+ case EPIPHANY_OPERAND_SIMM3 :
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 9, 3, 32, total_length, pc, & fields->f_sdisp3);
+ break;
+ case EPIPHANY_OPERAND_SIMM8 :
+ {
+ long value;
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 8, 32, total_length, pc, & value);
+ value = ((((value) << (1))) + (pc));
+ fields->f_simm8 = value;
+ }
+ break;
+ case EPIPHANY_OPERAND_SN :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn);
+ break;
+ case EPIPHANY_OPERAND_SN6 :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn);
+ if (length <= 0) break;
+{
+ FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn)));
+}
+ }
+ break;
+ case EPIPHANY_OPERAND_SNDMA :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn);
+ if (length <= 0) break;
+{
+ FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn)));
+}
+ }
+ break;
+ case EPIPHANY_OPERAND_SNMEM :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn);
+ if (length <= 0) break;
+{
+ FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn)));
+}
+ }
+ break;
+ case EPIPHANY_OPERAND_SNMESH :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn);
+ if (length <= 0) break;
+{
+ FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn)));
+}
+ }
+ break;
+ case EPIPHANY_OPERAND_SWI_NUM :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 6, 32, total_length, pc, & fields->f_trap_num);
+ break;
+ case EPIPHANY_OPERAND_TRAPNUM6 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 6, 32, total_length, pc, & fields->f_trap_num);
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
+ opindex);
+ abort ();
+ }
+
+ return length;
+}
+
+cgen_insert_fn * const epiphany_cgen_insert_handlers[] =
+{
+ insert_insn_normal,
+};
+
+cgen_extract_fn * const epiphany_cgen_extract_handlers[] =
+{
+ extract_insn_normal,
+};
+
+int epiphany_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+bfd_vma epiphany_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+
+/* Getting values from cgen_fields is handled by a collection of functions.
+ They are distinguished by the type of the VALUE argument they return.
+ TODO: floating point, inlining support, remove cases where result type
+ not appropriate. */
+
+int
+epiphany_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ int opindex,
+ const CGEN_FIELDS * fields)
+{
+ int value;
+
+ switch (opindex)
+ {
+ case EPIPHANY_OPERAND_DIRECTION :
+ value = fields->f_addsubx;
+ break;
+ case EPIPHANY_OPERAND_DISP11 :
+ value = fields->f_disp11;
+ break;
+ case EPIPHANY_OPERAND_DISP3 :
+ value = fields->f_disp3;
+ break;
+ case EPIPHANY_OPERAND_DPMI :
+ value = fields->f_subd;
+ break;
+ case EPIPHANY_OPERAND_FRD :
+ value = fields->f_rd;
+ break;
+ case EPIPHANY_OPERAND_FRD6 :
+ value = fields->f_rd6;
+ break;
+ case EPIPHANY_OPERAND_FRM :
+ value = fields->f_rm;
+ break;
+ case EPIPHANY_OPERAND_FRM6 :
+ value = fields->f_rm6;
+ break;
+ case EPIPHANY_OPERAND_FRN :
+ value = fields->f_rn;
+ break;
+ case EPIPHANY_OPERAND_FRN6 :
+ value = fields->f_rn6;
+ break;
+ case EPIPHANY_OPERAND_IMM16 :
+ value = fields->f_imm16;
+ break;
+ case EPIPHANY_OPERAND_IMM8 :
+ value = fields->f_imm8;
+ break;
+ case EPIPHANY_OPERAND_RD :
+ value = fields->f_rd;
+ break;
+ case EPIPHANY_OPERAND_RD6 :
+ value = fields->f_rd6;
+ break;
+ case EPIPHANY_OPERAND_RM :
+ value = fields->f_rm;
+ break;
+ case EPIPHANY_OPERAND_RM6 :
+ value = fields->f_rm6;
+ break;
+ case EPIPHANY_OPERAND_RN :
+ value = fields->f_rn;
+ break;
+ case EPIPHANY_OPERAND_RN6 :
+ value = fields->f_rn6;
+ break;
+ case EPIPHANY_OPERAND_SD :
+ value = fields->f_sd;
+ break;
+ case EPIPHANY_OPERAND_SD6 :
+ value = fields->f_sd6;
+ break;
+ case EPIPHANY_OPERAND_SDDMA :
+ value = fields->f_sd6;
+ break;
+ case EPIPHANY_OPERAND_SDMEM :
+ value = fields->f_sd6;
+ break;
+ case EPIPHANY_OPERAND_SDMESH :
+ value = fields->f_sd6;
+ break;
+ case EPIPHANY_OPERAND_SHIFT :
+ value = fields->f_shift;
+ break;
+ case EPIPHANY_OPERAND_SIMM11 :
+ value = fields->f_sdisp11;
+ break;
+ case EPIPHANY_OPERAND_SIMM24 :
+ value = fields->f_simm24;
+ break;
+ case EPIPHANY_OPERAND_SIMM3 :
+ value = fields->f_sdisp3;
+ break;
+ case EPIPHANY_OPERAND_SIMM8 :
+ value = fields->f_simm8;
+ break;
+ case EPIPHANY_OPERAND_SN :
+ value = fields->f_sn;
+ break;
+ case EPIPHANY_OPERAND_SN6 :
+ value = fields->f_sn6;
+ break;
+ case EPIPHANY_OPERAND_SNDMA :
+ value = fields->f_sn6;
+ break;
+ case EPIPHANY_OPERAND_SNMEM :
+ value = fields->f_sn6;
+ break;
+ case EPIPHANY_OPERAND_SNMESH :
+ value = fields->f_sn6;
+ break;
+ case EPIPHANY_OPERAND_SWI_NUM :
+ value = fields->f_trap_num;
+ break;
+ case EPIPHANY_OPERAND_TRAPNUM6 :
+ value = fields->f_trap_num;
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
+ opindex);
+ abort ();
+ }
+
+ return value;
+}
+
+bfd_vma
+epiphany_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ int opindex,
+ const CGEN_FIELDS * fields)
+{
+ bfd_vma value;
+
+ switch (opindex)
+ {
+ case EPIPHANY_OPERAND_DIRECTION :
+ value = fields->f_addsubx;
+ break;
+ case EPIPHANY_OPERAND_DISP11 :
+ value = fields->f_disp11;
+ break;
+ case EPIPHANY_OPERAND_DISP3 :
+ value = fields->f_disp3;
+ break;
+ case EPIPHANY_OPERAND_DPMI :
+ value = fields->f_subd;
+ break;
+ case EPIPHANY_OPERAND_FRD :
+ value = fields->f_rd;
+ break;
+ case EPIPHANY_OPERAND_FRD6 :
+ value = fields->f_rd6;
+ break;
+ case EPIPHANY_OPERAND_FRM :
+ value = fields->f_rm;
+ break;
+ case EPIPHANY_OPERAND_FRM6 :
+ value = fields->f_rm6;
+ break;
+ case EPIPHANY_OPERAND_FRN :
+ value = fields->f_rn;
+ break;
+ case EPIPHANY_OPERAND_FRN6 :
+ value = fields->f_rn6;
+ break;
+ case EPIPHANY_OPERAND_IMM16 :
+ value = fields->f_imm16;
+ break;
+ case EPIPHANY_OPERAND_IMM8 :
+ value = fields->f_imm8;
+ break;
+ case EPIPHANY_OPERAND_RD :
+ value = fields->f_rd;
+ break;
+ case EPIPHANY_OPERAND_RD6 :
+ value = fields->f_rd6;
+ break;
+ case EPIPHANY_OPERAND_RM :
+ value = fields->f_rm;
+ break;
+ case EPIPHANY_OPERAND_RM6 :
+ value = fields->f_rm6;
+ break;
+ case EPIPHANY_OPERAND_RN :
+ value = fields->f_rn;
+ break;
+ case EPIPHANY_OPERAND_RN6 :
+ value = fields->f_rn6;
+ break;
+ case EPIPHANY_OPERAND_SD :
+ value = fields->f_sd;
+ break;
+ case EPIPHANY_OPERAND_SD6 :
+ value = fields->f_sd6;
+ break;
+ case EPIPHANY_OPERAND_SDDMA :
+ value = fields->f_sd6;
+ break;
+ case EPIPHANY_OPERAND_SDMEM :
+ value = fields->f_sd6;
+ break;
+ case EPIPHANY_OPERAND_SDMESH :
+ value = fields->f_sd6;
+ break;
+ case EPIPHANY_OPERAND_SHIFT :
+ value = fields->f_shift;
+ break;
+ case EPIPHANY_OPERAND_SIMM11 :
+ value = fields->f_sdisp11;
+ break;
+ case EPIPHANY_OPERAND_SIMM24 :
+ value = fields->f_simm24;
+ break;
+ case EPIPHANY_OPERAND_SIMM3 :
+ value = fields->f_sdisp3;
+ break;
+ case EPIPHANY_OPERAND_SIMM8 :
+ value = fields->f_simm8;
+ break;
+ case EPIPHANY_OPERAND_SN :
+ value = fields->f_sn;
+ break;
+ case EPIPHANY_OPERAND_SN6 :
+ value = fields->f_sn6;
+ break;
+ case EPIPHANY_OPERAND_SNDMA :
+ value = fields->f_sn6;
+ break;
+ case EPIPHANY_OPERAND_SNMEM :
+ value = fields->f_sn6;
+ break;
+ case EPIPHANY_OPERAND_SNMESH :
+ value = fields->f_sn6;
+ break;
+ case EPIPHANY_OPERAND_SWI_NUM :
+ value = fields->f_trap_num;
+ break;
+ case EPIPHANY_OPERAND_TRAPNUM6 :
+ value = fields->f_trap_num;
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
+ opindex);
+ abort ();
+ }
+
+ return value;
+}
+
+void epiphany_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
+void epiphany_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
+
+/* Stuffing values in cgen_fields is handled by a collection of functions.
+ They are distinguished by the type of the VALUE argument they accept.
+ TODO: floating point, inlining support, remove cases where argument type
+ not appropriate. */
+
+void
+epiphany_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ int opindex,
+ CGEN_FIELDS * fields,
+ int value)
+{
+ switch (opindex)
+ {
+ case EPIPHANY_OPERAND_DIRECTION :
+ fields->f_addsubx = value;
+ break;
+ case EPIPHANY_OPERAND_DISP11 :
+ fields->f_disp11 = value;
+ break;
+ case EPIPHANY_OPERAND_DISP3 :
+ fields->f_disp3 = value;
+ break;
+ case EPIPHANY_OPERAND_DPMI :
+ fields->f_subd = value;
+ break;
+ case EPIPHANY_OPERAND_FRD :
+ fields->f_rd = value;
+ break;
+ case EPIPHANY_OPERAND_FRD6 :
+ fields->f_rd6 = value;
+ break;
+ case EPIPHANY_OPERAND_FRM :
+ fields->f_rm = value;
+ break;
+ case EPIPHANY_OPERAND_FRM6 :
+ fields->f_rm6 = value;
+ break;
+ case EPIPHANY_OPERAND_FRN :
+ fields->f_rn = value;
+ break;
+ case EPIPHANY_OPERAND_FRN6 :
+ fields->f_rn6 = value;
+ break;
+ case EPIPHANY_OPERAND_IMM16 :
+ fields->f_imm16 = value;
+ break;
+ case EPIPHANY_OPERAND_IMM8 :
+ fields->f_imm8 = value;
+ break;
+ case EPIPHANY_OPERAND_RD :
+ fields->f_rd = value;
+ break;
+ case EPIPHANY_OPERAND_RD6 :
+ fields->f_rd6 = value;
+ break;
+ case EPIPHANY_OPERAND_RM :
+ fields->f_rm = value;
+ break;
+ case EPIPHANY_OPERAND_RM6 :
+ fields->f_rm6 = value;
+ break;
+ case EPIPHANY_OPERAND_RN :
+ fields->f_rn = value;
+ break;
+ case EPIPHANY_OPERAND_RN6 :
+ fields->f_rn6 = value;
+ break;
+ case EPIPHANY_OPERAND_SD :
+ fields->f_sd = value;
+ break;
+ case EPIPHANY_OPERAND_SD6 :
+ fields->f_sd6 = value;
+ break;
+ case EPIPHANY_OPERAND_SDDMA :
+ fields->f_sd6 = value;
+ break;
+ case EPIPHANY_OPERAND_SDMEM :
+ fields->f_sd6 = value;
+ break;
+ case EPIPHANY_OPERAND_SDMESH :
+ fields->f_sd6 = value;
+ break;
+ case EPIPHANY_OPERAND_SHIFT :
+ fields->f_shift = value;
+ break;
+ case EPIPHANY_OPERAND_SIMM11 :
+ fields->f_sdisp11 = value;
+ break;
+ case EPIPHANY_OPERAND_SIMM24 :
+ fields->f_simm24 = value;
+ break;
+ case EPIPHANY_OPERAND_SIMM3 :
+ fields->f_sdisp3 = value;
+ break;
+ case EPIPHANY_OPERAND_SIMM8 :
+ fields->f_simm8 = value;
+ break;
+ case EPIPHANY_OPERAND_SN :
+ fields->f_sn = value;
+ break;
+ case EPIPHANY_OPERAND_SN6 :
+ fields->f_sn6 = value;
+ break;
+ case EPIPHANY_OPERAND_SNDMA :
+ fields->f_sn6 = value;
+ break;
+ case EPIPHANY_OPERAND_SNMEM :
+ fields->f_sn6 = value;
+ break;
+ case EPIPHANY_OPERAND_SNMESH :
+ fields->f_sn6 = value;
+ break;
+ case EPIPHANY_OPERAND_SWI_NUM :
+ fields->f_trap_num = value;
+ break;
+ case EPIPHANY_OPERAND_TRAPNUM6 :
+ fields->f_trap_num = value;
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
+ opindex);
+ abort ();
+ }
+}
+
+void
+epiphany_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ int opindex,
+ CGEN_FIELDS * fields,
+ bfd_vma value)
+{
+ switch (opindex)
+ {
+ case EPIPHANY_OPERAND_DIRECTION :
+ fields->f_addsubx = value;
+ break;
+ case EPIPHANY_OPERAND_DISP11 :
+ fields->f_disp11 = value;
+ break;
+ case EPIPHANY_OPERAND_DISP3 :
+ fields->f_disp3 = value;
+ break;
+ case EPIPHANY_OPERAND_DPMI :
+ fields->f_subd = value;
+ break;
+ case EPIPHANY_OPERAND_FRD :
+ fields->f_rd = value;
+ break;
+ case EPIPHANY_OPERAND_FRD6 :
+ fields->f_rd6 = value;
+ break;
+ case EPIPHANY_OPERAND_FRM :
+ fields->f_rm = value;
+ break;
+ case EPIPHANY_OPERAND_FRM6 :
+ fields->f_rm6 = value;
+ break;
+ case EPIPHANY_OPERAND_FRN :
+ fields->f_rn = value;
+ break;
+ case EPIPHANY_OPERAND_FRN6 :
+ fields->f_rn6 = value;
+ break;
+ case EPIPHANY_OPERAND_IMM16 :
+ fields->f_imm16 = value;
+ break;
+ case EPIPHANY_OPERAND_IMM8 :
+ fields->f_imm8 = value;
+ break;
+ case EPIPHANY_OPERAND_RD :
+ fields->f_rd = value;
+ break;
+ case EPIPHANY_OPERAND_RD6 :
+ fields->f_rd6 = value;
+ break;
+ case EPIPHANY_OPERAND_RM :
+ fields->f_rm = value;
+ break;
+ case EPIPHANY_OPERAND_RM6 :
+ fields->f_rm6 = value;
+ break;
+ case EPIPHANY_OPERAND_RN :
+ fields->f_rn = value;
+ break;
+ case EPIPHANY_OPERAND_RN6 :
+ fields->f_rn6 = value;
+ break;
+ case EPIPHANY_OPERAND_SD :
+ fields->f_sd = value;
+ break;
+ case EPIPHANY_OPERAND_SD6 :
+ fields->f_sd6 = value;
+ break;
+ case EPIPHANY_OPERAND_SDDMA :
+ fields->f_sd6 = value;
+ break;
+ case EPIPHANY_OPERAND_SDMEM :
+ fields->f_sd6 = value;
+ break;
+ case EPIPHANY_OPERAND_SDMESH :
+ fields->f_sd6 = value;
+ break;
+ case EPIPHANY_OPERAND_SHIFT :
+ fields->f_shift = value;
+ break;
+ case EPIPHANY_OPERAND_SIMM11 :
+ fields->f_sdisp11 = value;
+ break;
+ case EPIPHANY_OPERAND_SIMM24 :
+ fields->f_simm24 = value;
+ break;
+ case EPIPHANY_OPERAND_SIMM3 :
+ fields->f_sdisp3 = value;
+ break;
+ case EPIPHANY_OPERAND_SIMM8 :
+ fields->f_simm8 = value;
+ break;
+ case EPIPHANY_OPERAND_SN :
+ fields->f_sn = value;
+ break;
+ case EPIPHANY_OPERAND_SN6 :
+ fields->f_sn6 = value;
+ break;
+ case EPIPHANY_OPERAND_SNDMA :
+ fields->f_sn6 = value;
+ break;
+ case EPIPHANY_OPERAND_SNMEM :
+ fields->f_sn6 = value;
+ break;
+ case EPIPHANY_OPERAND_SNMESH :
+ fields->f_sn6 = value;
+ break;
+ case EPIPHANY_OPERAND_SWI_NUM :
+ fields->f_trap_num = value;
+ break;
+ case EPIPHANY_OPERAND_TRAPNUM6 :
+ fields->f_trap_num = value;
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
+ opindex);
+ abort ();
+ }
+}
+
+/* Function to call before using the instruction builder tables. */
+
+void
+epiphany_cgen_init_ibld_table (CGEN_CPU_DESC cd)
+{
+ cd->insert_handlers = & epiphany_cgen_insert_handlers[0];
+ cd->extract_handlers = & epiphany_cgen_extract_handlers[0];
+
+ cd->insert_operand = epiphany_cgen_insert_operand;
+ cd->extract_operand = epiphany_cgen_extract_operand;
+
+ cd->get_int_operand = epiphany_cgen_get_int_operand;
+ cd->set_int_operand = epiphany_cgen_set_int_operand;
+ cd->get_vma_operand = epiphany_cgen_get_vma_operand;
+ cd->set_vma_operand = epiphany_cgen_set_vma_operand;
+}
--- /dev/null
+/* Instruction opcode table for epiphany.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#include "sysdep.h"
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "epiphany-desc.h"
+#include "epiphany-opc.h"
+#include "libiberty.h"
+
+/* -- opc.c */
+
+
+\f
+/* -- asm.c */
+/* The hash functions are recorded here to help keep assembler code out of
+ the disassembler and vice versa. */
+
+static int asm_hash_insn_p (const CGEN_INSN *);
+static unsigned int asm_hash_insn (const char *);
+static int dis_hash_insn_p (const CGEN_INSN *);
+static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
+
+/* Instruction formats. */
+
+#define F(f) & epiphany_cgen_ifld_table[EPIPHANY_##f]
+static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
+ 0, 0, 0x0, { { 0 } }
+};
+
+static const CGEN_IFMT ifmt_beq16 ATTRIBUTE_UNUSED = {
+ 16, 16, 0xff, { { F (F_SIMM8) }, { F (F_CONDCODE) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_beq ATTRIBUTE_UNUSED = {
+ 32, 32, 0xff, { { F (F_SIMM24) }, { F (F_CONDCODE) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jr16 ATTRIBUTE_UNUSED = {
+ 16, 16, 0xe3ff, { { F (F_DC_15_3) }, { F (F_RN) }, { F (F_DC_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_rts ATTRIBUTE_UNUSED = {
+ 32, 32, 0xffffffff, { { F (F_DC_31_3) }, { F (F_RN_X) }, { F (F_DC_25_6) }, { F (F_OPC_19_4) }, { F (F_DC_15_3) }, { F (F_RN) }, { F (F_DC_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jr ATTRIBUTE_UNUSED = {
+ 32, 32, 0xe3ffe3ff, { { F (F_DC_31_3) }, { F (F_DC_25_6) }, { F (F_OPC_19_4) }, { F (F_DC_15_3) }, { F (F_RN6) }, { F (F_DC_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbx16_s ATTRIBUTE_UNUSED = {
+ 16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbx_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_ADDSUBX) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbp_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_DC_22_2) }, { F (F_ADDSUBX) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbd16_s ATTRIBUTE_UNUSED = {
+ 16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbd_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x200007f, { { F (F_PM) }, { F (F_SUBD) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_DISP11) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov16EQ ATTRIBUTE_UNUSED = {
+ 16, 16, 0x3ff, { { F (F_RD) }, { F (F_RN) }, { F (F_DC_9_1) }, { F (F_OPC_8_1) }, { F (F_CONDCODE) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmovEQ ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_DC_25_6) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_DC_9_1) }, { F (F_OPC_8_1) }, { F (F_CONDCODE) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movts16 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x3ff, { { F (F_RD) }, { F (F_SN) }, { F (F_DC_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movts6 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_SN6) }, { F (F_DC_9_1) }, { F (F_OPC_8_1) }, { F (F_DC_7_4) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movtsdma ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_SN6) }, { F (F_DC_9_1) }, { F (F_OPC_8_1) }, { F (F_DC_7_4) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movtsmem ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_SN6) }, { F (F_DC_9_1) }, { F (F_OPC_8_1) }, { F (F_DC_7_4) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movtsmesh ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_SN6) }, { F (F_DC_9_1) }, { F (F_OPC_8_1) }, { F (F_DC_7_4) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = {
+ 16, 16, 0xffff, { { F (F_DC_15_7) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_unimpl ATTRIBUTE_UNUSED = {
+ 32, 32, 0xffffffff, { { F (F_OPC_31_32) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_gien ATTRIBUTE_UNUSED = {
+ 16, 16, 0xffff, { { F (F_DC_15_6) }, { F (F_GIEN_GIDIS_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_swi_num ATTRIBUTE_UNUSED = {
+ 16, 16, 0x3ff, { { F (F_TRAP_NUM) }, { F (F_TRAP_SWI_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_swi ATTRIBUTE_UNUSED = {
+ 16, 16, 0xffff, { { F (F_DC_15_6) }, { F (F_TRAP_SWI_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_trap16 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x3ff, { { F (F_TRAP_NUM) }, { F (F_TRAP_SWI_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_add16 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_add ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_DC_22_3) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addi16 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_SDISP3) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addi ATTRIBUTE_UNUSED = {
+ 32, 32, 0x300007f, { { F (F_DC_25_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SDISP11) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lsri16 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x1f, { { F (F_RD) }, { F (F_RN) }, { F (F_SHIFT) }, { F (F_OPC_4_1) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lsri32 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff001f, { { F (F_DC_25_6) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SHIFT) }, { F (F_OPC_4_1) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bitr16 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x3ff, { { F (F_RD) }, { F (F_RN) }, { F (F_SHIFT) }, { F (F_OPC_4_1) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bitr ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_DC_25_6) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SHIFT) }, { F (F_OPC_4_1) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fext ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mov8 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x1f, { { F (F_RD) }, { F (F_IMM8) }, { F (F_OPC_4_1) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mov16 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x100f001f, { { F (F_DC_28_1) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_IMM16) }, { F (F_OPC_4_1) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_absf16 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_RN) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_absf32 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_DC_22_3) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_loatf16 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_RN) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_recipf32 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } }
+};
+
+#undef F
+
+#define A(a) (1 << CGEN_INSN_##a)
+#define OPERAND(op) EPIPHANY_OPERAND_##op
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The instruction table. */
+
+static const CGEN_OPCODE epiphany_cgen_insn_opcode_table[MAX_INSNS] =
+{
+ /* Special null first entry.
+ A `num' value of zero is thus invalid.
+ Also, the special `invalid' insn resides here. */
+ { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
+/* beq.s $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_beq16, { 0x0 }
+ },
+/* beq.l $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_beq, { 0x8 }
+ },
+/* bne.s $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_beq16, { 0x10 }
+ },
+/* bne.l $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_beq, { 0x18 }
+ },
+/* bgtu.s $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_beq16, { 0x20 }
+ },
+/* bgtu.l $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_beq, { 0x28 }
+ },
+/* bgteu.s $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_beq16, { 0x30 }
+ },
+/* bgteu.l $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_beq, { 0x38 }
+ },
+/* blteu.s $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_beq16, { 0x40 }
+ },
+/* blteu.l $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_beq, { 0x48 }
+ },
+/* bltu.s $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_beq16, { 0x50 }
+ },
+/* bltu.l $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_beq, { 0x58 }
+ },
+/* bgt.s $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_beq16, { 0x60 }
+ },
+/* bgt.l $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_beq, { 0x68 }
+ },
+/* bgte.s $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_beq16, { 0x70 }
+ },
+/* bgte.l $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_beq, { 0x78 }
+ },
+/* blt.s $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_beq16, { 0x80 }
+ },
+/* blt.l $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_beq, { 0x88 }
+ },
+/* blte.s $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_beq16, { 0x90 }
+ },
+/* blte.l $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_beq, { 0x98 }
+ },
+/* bbeq.s $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_beq16, { 0xa0 }
+ },
+/* bbeq.l $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_beq, { 0xa8 }
+ },
+/* bbne.s $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_beq16, { 0xb0 }
+ },
+/* bbne.l $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_beq, { 0xb8 }
+ },
+/* bblt.s $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_beq16, { 0xc0 }
+ },
+/* bblt.l $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_beq, { 0xc8 }
+ },
+/* bblte.s $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_beq16, { 0xd0 }
+ },
+/* bblte.l $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_beq, { 0xd8 }
+ },
+/* b.s $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_beq16, { 0xe0 }
+ },
+/* b.l $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_beq, { 0xe8 }
+ },
+/* bl.s $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_beq16, { 0xf0 }
+ },
+/* bl.l $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_beq, { 0xf8 }
+ },
+/* jr $rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RN), 0 } },
+ & ifmt_jr16, { 0x142 }
+ },
+/* rts */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_rts, { 0x402194f }
+ },
+/* jr $rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RN6), 0 } },
+ & ifmt_jr, { 0x2014f }
+ },
+/* jalr $rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RN), 0 } },
+ & ifmt_jr16, { 0x152 }
+ },
+/* jalr $rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RN6), 0 } },
+ & ifmt_jr, { 0x2015f }
+ },
+/* ldrb $rd,[$rn,$rm] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } },
+ & ifmt_ldrbx16_s, { 0x1 }
+ },
+/* ldrb $rd,[$rn],$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } },
+ & ifmt_ldrbx16_s, { 0x5 }
+ },
+/* ldrb $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_ldrbx_l, { 0x9 }
+ },
+/* ldrb $rd6,[$rn6],$direction$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+ & ifmt_ldrbp_l, { 0xd }
+ },
+/* ldrb $rd,[$rn,$disp3] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } },
+ & ifmt_ldrbd16_s, { 0x4 }
+ },
+/* ldrb $rd6,[$rn6,$dpmi$disp11] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+ & ifmt_ldrbd_l, { 0xc }
+ },
+/* ldrb $rd6,[$rn6],$dpmi$disp11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+ & ifmt_ldrbd_l, { 0x200000c }
+ },
+/* ldrh $rd,[$rn,$rm] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } },
+ & ifmt_ldrbx16_s, { 0x21 }
+ },
+/* ldrh $rd,[$rn],$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } },
+ & ifmt_ldrbx16_s, { 0x25 }
+ },
+/* ldrh $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_ldrbx_l, { 0x29 }
+ },
+/* ldrh $rd6,[$rn6],$direction$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+ & ifmt_ldrbp_l, { 0x2d }
+ },
+/* ldrh $rd,[$rn,$disp3] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } },
+ & ifmt_ldrbd16_s, { 0x24 }
+ },
+/* ldrh $rd6,[$rn6,$dpmi$disp11] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+ & ifmt_ldrbd_l, { 0x2c }
+ },
+/* ldrh $rd6,[$rn6],$dpmi$disp11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+ & ifmt_ldrbd_l, { 0x200002c }
+ },
+/* ldr $rd,[$rn,$rm] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } },
+ & ifmt_ldrbx16_s, { 0x41 }
+ },
+/* ldr $rd,[$rn],$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } },
+ & ifmt_ldrbx16_s, { 0x45 }
+ },
+/* ldr $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_ldrbx_l, { 0x49 }
+ },
+/* ldr $rd6,[$rn6],$direction$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+ & ifmt_ldrbp_l, { 0x4d }
+ },
+/* ldr $rd,[$rn,$disp3] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } },
+ & ifmt_ldrbd16_s, { 0x44 }
+ },
+/* ldr $rd6,[$rn6,$dpmi$disp11] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+ & ifmt_ldrbd_l, { 0x4c }
+ },
+/* ldr $rd6,[$rn6],$dpmi$disp11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+ & ifmt_ldrbd_l, { 0x200004c }
+ },
+/* ldrd $rd,[$rn,$rm] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } },
+ & ifmt_ldrbx16_s, { 0x61 }
+ },
+/* ldrd $rd,[$rn],$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } },
+ & ifmt_ldrbx16_s, { 0x65 }
+ },
+/* ldrd $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_ldrbx_l, { 0x69 }
+ },
+/* ldrd $rd6,[$rn6],$direction$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+ & ifmt_ldrbp_l, { 0x6d }
+ },
+/* ldrd $rd,[$rn,$disp3] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } },
+ & ifmt_ldrbd16_s, { 0x64 }
+ },
+/* ldrd $rd6,[$rn6,$dpmi$disp11] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+ & ifmt_ldrbd_l, { 0x6c }
+ },
+/* ldrd $rd6,[$rn6],$dpmi$disp11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+ & ifmt_ldrbd_l, { 0x200006c }
+ },
+/* testsetb $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_ldrbx_l, { 0x200009 }
+ },
+/* testseth $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_ldrbx_l, { 0x200029 }
+ },
+/* testset $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_ldrbx_l, { 0x200049 }
+ },
+/* strb $rd,[$rn,$rm] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } },
+ & ifmt_ldrbx16_s, { 0x11 }
+ },
+/* strb $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_ldrbx_l, { 0x19 }
+ },
+/* strb $rd,[$rn],$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } },
+ & ifmt_ldrbx16_s, { 0x15 }
+ },
+/* strb $rd6,[$rn6],$direction$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+ & ifmt_ldrbp_l, { 0x1d }
+ },
+/* strb $rd,[$rn,$disp3] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } },
+ & ifmt_ldrbd16_s, { 0x14 }
+ },
+/* strb $rd6,[$rn6,$dpmi$disp11] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+ & ifmt_ldrbd_l, { 0x1c }
+ },
+/* strb $rd6,[$rn6],$dpmi$disp11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+ & ifmt_ldrbd_l, { 0x200001c }
+ },
+/* strh $rd,[$rn,$rm] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } },
+ & ifmt_ldrbx16_s, { 0x31 }
+ },
+/* strh $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_ldrbx_l, { 0x39 }
+ },
+/* strh $rd,[$rn],$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } },
+ & ifmt_ldrbx16_s, { 0x35 }
+ },
+/* strh $rd6,[$rn6],$direction$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+ & ifmt_ldrbp_l, { 0x3d }
+ },
+/* strh $rd,[$rn,$disp3] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } },
+ & ifmt_ldrbd16_s, { 0x34 }
+ },
+/* strh $rd6,[$rn6,$dpmi$disp11] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+ & ifmt_ldrbd_l, { 0x3c }
+ },
+/* strh $rd6,[$rn6],$dpmi$disp11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+ & ifmt_ldrbd_l, { 0x200003c }
+ },
+/* str $rd,[$rn,$rm] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } },
+ & ifmt_ldrbx16_s, { 0x51 }
+ },
+/* str $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_ldrbx_l, { 0x59 }
+ },
+/* str $rd,[$rn],$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } },
+ & ifmt_ldrbx16_s, { 0x55 }
+ },
+/* str $rd6,[$rn6],$direction$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+ & ifmt_ldrbp_l, { 0x5d }
+ },
+/* str $rd,[$rn,$disp3] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } },
+ & ifmt_ldrbd16_s, { 0x54 }
+ },
+/* str $rd6,[$rn6,$dpmi$disp11] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+ & ifmt_ldrbd_l, { 0x5c }
+ },
+/* str $rd6,[$rn6],$dpmi$disp11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+ & ifmt_ldrbd_l, { 0x200005c }
+ },
+/* strd $rd,[$rn,$rm] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } },
+ & ifmt_ldrbx16_s, { 0x71 }
+ },
+/* strd $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_ldrbx_l, { 0x79 }
+ },
+/* strd $rd,[$rn],$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } },
+ & ifmt_ldrbx16_s, { 0x75 }
+ },
+/* strd $rd6,[$rn6],$direction$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+ & ifmt_ldrbp_l, { 0x7d }
+ },
+/* strd $rd,[$rn,$disp3] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } },
+ & ifmt_ldrbd16_s, { 0x74 }
+ },
+/* strd $rd6,[$rn6,$dpmi$disp11] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+ & ifmt_ldrbd_l, { 0x7c }
+ },
+/* strd $rd6,[$rn6],$dpmi$disp11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+ & ifmt_ldrbd_l, { 0x200007c }
+ },
+/* moveq $rd,$rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+ & ifmt_cmov16EQ, { 0x2 }
+ },
+/* moveq $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmovEQ, { 0x2000f }
+ },
+/* movne $rd,$rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+ & ifmt_cmov16EQ, { 0x12 }
+ },
+/* movne $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmovEQ, { 0x2001f }
+ },
+/* movgtu $rd,$rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+ & ifmt_cmov16EQ, { 0x22 }
+ },
+/* movgtu $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmovEQ, { 0x2002f }
+ },
+/* movgteu $rd,$rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+ & ifmt_cmov16EQ, { 0x32 }
+ },
+/* movgteu $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmovEQ, { 0x2003f }
+ },
+/* movlteu $rd,$rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+ & ifmt_cmov16EQ, { 0x42 }
+ },
+/* movlteu $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmovEQ, { 0x2004f }
+ },
+/* movltu $rd,$rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+ & ifmt_cmov16EQ, { 0x52 }
+ },
+/* movltu $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmovEQ, { 0x2005f }
+ },
+/* movgt $rd,$rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+ & ifmt_cmov16EQ, { 0x62 }
+ },
+/* movgt $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmovEQ, { 0x2006f }
+ },
+/* movgte $rd,$rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+ & ifmt_cmov16EQ, { 0x72 }
+ },
+/* movgte $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmovEQ, { 0x2007f }
+ },
+/* movlt $rd,$rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+ & ifmt_cmov16EQ, { 0x82 }
+ },
+/* movlt $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmovEQ, { 0x2008f }
+ },
+/* movlte $rd,$rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+ & ifmt_cmov16EQ, { 0x92 }
+ },
+/* movlte $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmovEQ, { 0x2009f }
+ },
+/* mov $rd,$rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+ & ifmt_cmov16EQ, { 0xe2 }
+ },
+/* mov $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmovEQ, { 0x200ef }
+ },
+/* movbeq $rd,$rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+ & ifmt_cmov16EQ, { 0xa2 }
+ },
+/* movbeq $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmovEQ, { 0x200af }
+ },
+/* movbne $rd,$rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+ & ifmt_cmov16EQ, { 0xb2 }
+ },
+/* movbne $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmovEQ, { 0x200bf }
+ },
+/* movblt $rd,$rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+ & ifmt_cmov16EQ, { 0xc2 }
+ },
+/* movblt $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmovEQ, { 0x200cf }
+ },
+/* movblte $rd,$rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+ & ifmt_cmov16EQ, { 0xd2 }
+ },
+/* movblte $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmovEQ, { 0x200df }
+ },
+/* movts $sn,$rd */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SN), ',', OP (RD), 0 } },
+ & ifmt_movts16, { 0x102 }
+ },
+/* movts $sn6,$rd6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SN6), ',', OP (RD6), 0 } },
+ & ifmt_movts6, { 0x2010f }
+ },
+/* movts $sndma,$rd6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SNDMA), ',', OP (RD6), 0 } },
+ & ifmt_movtsdma, { 0x12010f }
+ },
+/* movts $snmem,$rd6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SNMEM), ',', OP (RD6), 0 } },
+ & ifmt_movtsmem, { 0x22010f }
+ },
+/* movts $snmesh,$rd6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SNMESH), ',', OP (RD6), 0 } },
+ & ifmt_movtsmesh, { 0x32010f }
+ },
+/* movfs $rd,$sn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (SN), 0 } },
+ & ifmt_movts16, { 0x112 }
+ },
+/* movfs $rd6,$sn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (SN6), 0 } },
+ & ifmt_movts6, { 0x2011f }
+ },
+/* movfs $rd6,$sndma */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (SNDMA), 0 } },
+ & ifmt_movtsdma, { 0x12011f }
+ },
+/* movfs $rd6,$snmem */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (SNMEM), 0 } },
+ & ifmt_movtsmem, { 0x22011f }
+ },
+/* movfs $rd6,$snmesh */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (SNMESH), 0 } },
+ & ifmt_movtsmesh, { 0x32011f }
+ },
+/* nop */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_nop, { 0x1a2 }
+ },
+/* snop */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_nop, { 0x3a2 }
+ },
+/* unimpl */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_unimpl, { 0xf000f }
+ },
+/* idle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_nop, { 0x1b2 }
+ },
+/* bkpt */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_nop, { 0x1c2 }
+ },
+/* mbkpt */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_nop, { 0x3c2 }
+ },
+/* rti */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_nop, { 0x1d2 }
+ },
+/* wand */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_nop, { 0x182 }
+ },
+/* sync */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_nop, { 0x1f2 }
+ },
+/* gie */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_gien, { 0x192 }
+ },
+/* gid */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_gien, { 0x392 }
+ },
+/* swi $swi_num */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SWI_NUM), 0 } },
+ & ifmt_swi_num, { 0x1e2 }
+ },
+/* swi */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_swi, { 0x1e2 }
+ },
+/* trap $trapnum6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (TRAPNUM6), 0 } },
+ & ifmt_trap16, { 0x3e2 }
+ },
+/* add $rd,$rn,$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+ & ifmt_add16, { 0x1a }
+ },
+/* add $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_add, { 0xa001f }
+ },
+/* sub $rd,$rn,$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+ & ifmt_add16, { 0x3a }
+ },
+/* sub $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_add, { 0xa003f }
+ },
+/* and $rd,$rn,$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+ & ifmt_add16, { 0x5a }
+ },
+/* and $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_add, { 0xa005f }
+ },
+/* orr $rd,$rn,$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+ & ifmt_add16, { 0x7a }
+ },
+/* orr $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_add, { 0xa007f }
+ },
+/* eor $rd,$rn,$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+ & ifmt_add16, { 0xa }
+ },
+/* eor $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_add, { 0xa000f }
+ },
+/* add.s $rd,$rn,$simm3 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SIMM3), 0 } },
+ & ifmt_addi16, { 0x13 }
+ },
+/* add.l $rd6,$rn6,$simm11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SIMM11), 0 } },
+ & ifmt_addi, { 0x1b }
+ },
+/* sub.s $rd,$rn,$simm3 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SIMM3), 0 } },
+ & ifmt_addi16, { 0x33 }
+ },
+/* sub.l $rd6,$rn6,$simm11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SIMM11), 0 } },
+ & ifmt_addi, { 0x3b }
+ },
+/* asr $rd,$rn,$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+ & ifmt_add16, { 0x6a }
+ },
+/* asr $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_add, { 0xa006f }
+ },
+/* lsr $rd,$rn,$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+ & ifmt_add16, { 0x4a }
+ },
+/* lsr $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_add, { 0xa004f }
+ },
+/* lsl $rd,$rn,$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+ & ifmt_add16, { 0x2a }
+ },
+/* lsl $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_add, { 0xa002f }
+ },
+/* lsr $rd,$rn,$shift */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SHIFT), 0 } },
+ & ifmt_lsri16, { 0x6 }
+ },
+/* lsr $rd6,$rn6,$shift */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SHIFT), 0 } },
+ & ifmt_lsri32, { 0x6000f }
+ },
+/* lsl $rd,$rn,$shift */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SHIFT), 0 } },
+ & ifmt_lsri16, { 0x16 }
+ },
+/* lsl $rd6,$rn6,$shift */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SHIFT), 0 } },
+ & ifmt_lsri32, { 0x6001f }
+ },
+/* asr $rd,$rn,$shift */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SHIFT), 0 } },
+ & ifmt_lsri16, { 0xe }
+ },
+/* asr $rd6,$rn6,$shift */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SHIFT), 0 } },
+ & ifmt_lsri32, { 0xe000f }
+ },
+/* bitr $rd,$rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+ & ifmt_bitr16, { 0x1e }
+ },
+/* bitr $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_bitr, { 0xe001f }
+ },
+/* fext $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_fext, { 0x1a000f }
+ },
+/* fdep $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_fext, { 0x1a001f }
+ },
+/* lfsr $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_fext, { 0x1a002f }
+ },
+/* mov.b $rd,$imm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (IMM8), 0 } },
+ & ifmt_mov8, { 0x3 }
+ },
+/* mov.l $rd6,$imm16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (IMM16), 0 } },
+ & ifmt_mov16, { 0x2000b }
+ },
+/* movt $rd6,$imm16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (IMM16), 0 } },
+ & ifmt_mov16, { 0x1002000b }
+ },
+/* fadd $rd,$rn,$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+ & ifmt_add16, { 0x7 }
+ },
+/* fadd $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_add, { 0x7000f }
+ },
+/* fsub $rd,$rn,$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+ & ifmt_add16, { 0x17 }
+ },
+/* fsub $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_add, { 0x7001f }
+ },
+/* fmul $rd,$rn,$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+ & ifmt_add16, { 0x27 }
+ },
+/* fmul $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_add, { 0x7002f }
+ },
+/* fmadd $rd,$rn,$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+ & ifmt_add16, { 0x37 }
+ },
+/* fmadd $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_add, { 0x7003f }
+ },
+/* fmsub $rd,$rn,$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+ & ifmt_add16, { 0x47 }
+ },
+/* fmsub $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_add, { 0x7004f }
+ },
+/* fabs rd,rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'r', 'd', ',', 'r', 'n', 0 } },
+ & ifmt_f_absf16, { 0x77 }
+ },
+/* fabs $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_f_absf32, { 0x7007f }
+ },
+/* float $rd,$rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+ & ifmt_f_loatf16, { 0x57 }
+ },
+/* float $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_f_absf32, { 0x7005f }
+ },
+/* fix $rd,$rn */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+ & ifmt_f_absf16, { 0x67 }
+ },
+/* fix $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_f_absf32, { 0x7006f }
+ },
+/* frecip $frd6,$frn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FRD6), ',', OP (FRN6), 0 } },
+ & ifmt_f_recipf32, { 0x17000f }
+ },
+/* fsqrt $frd6,$frn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FRD6), ',', OP (FRN6), 0 } },
+ & ifmt_f_recipf32, { 0x17001f }
+ },
+};
+
+#undef A
+#undef OPERAND
+#undef MNEM
+#undef OP
+
+/* Formats for ALIAS macro-insns. */
+
+#define F(f) & epiphany_cgen_ifld_table[EPIPHANY_##f]
+static const CGEN_IFMT ifmt_beq16r ATTRIBUTE_UNUSED = {
+ 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_beq32r ATTRIBUTE_UNUSED = {
+ 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bne16r ATTRIBUTE_UNUSED = {
+ 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bne32r ATTRIBUTE_UNUSED = {
+ 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bgtu16r ATTRIBUTE_UNUSED = {
+ 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bgtu32r ATTRIBUTE_UNUSED = {
+ 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bgteu16r ATTRIBUTE_UNUSED = {
+ 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bgteu32r ATTRIBUTE_UNUSED = {
+ 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_blteu16r ATTRIBUTE_UNUSED = {
+ 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_blteu32r ATTRIBUTE_UNUSED = {
+ 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bltu16r ATTRIBUTE_UNUSED = {
+ 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bltu32r ATTRIBUTE_UNUSED = {
+ 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bgt16r ATTRIBUTE_UNUSED = {
+ 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bgt32r ATTRIBUTE_UNUSED = {
+ 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bgte16r ATTRIBUTE_UNUSED = {
+ 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bgte32r ATTRIBUTE_UNUSED = {
+ 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_blt16r ATTRIBUTE_UNUSED = {
+ 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_blt32r ATTRIBUTE_UNUSED = {
+ 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_blte16r ATTRIBUTE_UNUSED = {
+ 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_blte32r ATTRIBUTE_UNUSED = {
+ 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bbeq16r ATTRIBUTE_UNUSED = {
+ 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bbeq32r ATTRIBUTE_UNUSED = {
+ 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bbne16r ATTRIBUTE_UNUSED = {
+ 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bbne32r ATTRIBUTE_UNUSED = {
+ 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bblt16r ATTRIBUTE_UNUSED = {
+ 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bblt32r ATTRIBUTE_UNUSED = {
+ 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bblte16r ATTRIBUTE_UNUSED = {
+ 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bblte32r ATTRIBUTE_UNUSED = {
+ 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_b16r ATTRIBUTE_UNUSED = {
+ 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_b32r ATTRIBUTE_UNUSED = {
+ 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bl16r ATTRIBUTE_UNUSED = {
+ 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_blr ATTRIBUTE_UNUSED = {
+ 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbx ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbp ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbd ATTRIBUTE_UNUSED = {
+ 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbdpm ATTRIBUTE_UNUSED = {
+ 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbds0 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbdl0 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbdl0_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrhx ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrhp ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrhd ATTRIBUTE_UNUSED = {
+ 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrhdpm ATTRIBUTE_UNUSED = {
+ 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrhds0 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrhdl0 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrhdl0_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrx ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrp ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrd ATTRIBUTE_UNUSED = {
+ 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrdpm ATTRIBUTE_UNUSED = {
+ 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrds0 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrdl0 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrdl0_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrdx ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrdp ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrdd ATTRIBUTE_UNUSED = {
+ 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrddpm ATTRIBUTE_UNUSED = {
+ 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrdds0 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrddl0 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrddl0_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_testsetbt_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_testsetht_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_testsett_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strbx_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strbp_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strbd_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strbdpm_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strbds0 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strbdl0 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strbdl0_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strhx_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strhp_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strhd_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strhdpm_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strhds0 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strhdl0 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strhdl0_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strx_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strp_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strd_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strdpm_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strds0 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strdl0 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strdl0_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strdx_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strdp_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strdd_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strddpm_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strdds0 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strddl0 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strddl0_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lEQ ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lNE ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lGTU ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lGTEU ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lLTEU ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lLTU ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lGT ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lGTE ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lLT ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lLTE ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lB ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lBEQ ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lBNE ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lBLT ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lBLTE ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movts_l6 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_SN6) }, { F (F_RD6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movts_ldma ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_SN6) }, { F (F_RD6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movts_lmem ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_SN6) }, { F (F_RD6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movts_lmesh ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_SN6) }, { F (F_RD6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movfs_l6 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_RD6) }, { F (F_SN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movfs_ldma ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_RD6) }, { F (F_SN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movfs_lmem ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_RD6) }, { F (F_SN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movfs_lmesh ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_RD6) }, { F (F_SN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_add_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_sub_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_and_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_orr_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_eor_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addir ATTRIBUTE_UNUSED = {
+ 16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_SDISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addi32r ATTRIBUTE_UNUSED = {
+ 32, 32, 0x300007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_DC_25_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SDISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addi32m ATTRIBUTE_UNUSED = {
+ 32, 32, 0x300007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_DC_25_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SDISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_subir ATTRIBUTE_UNUSED = {
+ 16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_SDISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_subi32r ATTRIBUTE_UNUSED = {
+ 32, 32, 0x300007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_DC_25_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SDISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_subi32m ATTRIBUTE_UNUSED = {
+ 32, 32, 0x300007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_DC_25_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SDISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_asr_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lsr_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lsl_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lsri32_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff001f, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SHIFT) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lsli32_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff001f, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SHIFT) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_asri32_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff001f, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SHIFT) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bitrl ATTRIBUTE_UNUSED = {
+ 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SHIFT) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fext_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fdep_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lfsr_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mov8r ATTRIBUTE_UNUSED = {
+ 16, 16, 0x1f, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_RD) }, { F (F_IMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mov16r ATTRIBUTE_UNUSED = {
+ 32, 32, 0x100f001f, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_OPC_19_4) }, { F (F_DC_28_1) }, { F (F_RD6) }, { F (F_IMM16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movtl ATTRIBUTE_UNUSED = {
+ 32, 32, 0x100f001f, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_OPC_19_4) }, { F (F_DC_28_1) }, { F (F_RD6) }, { F (F_IMM16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_addf16 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_addf32_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_addf32 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_addf32_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_subf16 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_subf32_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_subf32 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_subf32_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_mulf16 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_mulf32_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_mulf32 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_mulf32_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_maddf16 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_maddf32_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_maddf32 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_maddf32_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_msubf16 ATTRIBUTE_UNUSED = {
+ 16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_msubf32_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_msubf32 ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_msubf32_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_absf32_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_loatf32_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_ixf32_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_recipf32_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_sqrtf32_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { 0 } }
+};
+
+#undef F
+
+/* Each non-simple macro entry points to an array of expansion possibilities. */
+
+#define A(a) (1 << CGEN_INSN_##a)
+#define OPERAND(op) EPIPHANY_OPERAND_##op
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The macro instruction table. */
+
+static const CGEN_IBASE epiphany_cgen_macro_insn_table[] =
+{
+/* beq $simm8 */
+ {
+ -1, "beq16r", "beq", 16,
+ { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* beq $simm24 */
+ {
+ -1, "beq32r", "beq", 32,
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bne $simm8 */
+ {
+ -1, "bne16r", "bne", 16,
+ { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bne $simm24 */
+ {
+ -1, "bne32r", "bne", 32,
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bgtu $simm8 */
+ {
+ -1, "bgtu16r", "bgtu", 16,
+ { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bgtu $simm24 */
+ {
+ -1, "bgtu32r", "bgtu", 32,
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bgteu $simm8 */
+ {
+ -1, "bgteu16r", "bgteu", 16,
+ { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bgteu $simm24 */
+ {
+ -1, "bgteu32r", "bgteu", 32,
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* blteu $simm8 */
+ {
+ -1, "blteu16r", "blteu", 16,
+ { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* blteu $simm24 */
+ {
+ -1, "blteu32r", "blteu", 32,
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bltu $simm8 */
+ {
+ -1, "bltu16r", "bltu", 16,
+ { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bltu $simm24 */
+ {
+ -1, "bltu32r", "bltu", 32,
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bgt $simm8 */
+ {
+ -1, "bgt16r", "bgt", 16,
+ { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bgt $simm24 */
+ {
+ -1, "bgt32r", "bgt", 32,
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bgte $simm8 */
+ {
+ -1, "bgte16r", "bgte", 16,
+ { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bgte $simm24 */
+ {
+ -1, "bgte32r", "bgte", 32,
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* blt $simm8 */
+ {
+ -1, "blt16r", "blt", 16,
+ { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* blt $simm24 */
+ {
+ -1, "blt32r", "blt", 32,
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* blte $simm8 */
+ {
+ -1, "blte16r", "blte", 16,
+ { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* blte $simm24 */
+ {
+ -1, "blte32r", "blte", 32,
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bbeq $simm8 */
+ {
+ -1, "bbeq16r", "bbeq", 16,
+ { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bbeq $simm24 */
+ {
+ -1, "bbeq32r", "bbeq", 32,
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bbne $simm8 */
+ {
+ -1, "bbne16r", "bbne", 16,
+ { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bbne $simm24 */
+ {
+ -1, "bbne32r", "bbne", 32,
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bblt $simm8 */
+ {
+ -1, "bblt16r", "bblt", 16,
+ { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bblt $simm24 */
+ {
+ -1, "bblt32r", "bblt", 32,
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bblte $simm8 */
+ {
+ -1, "bblte16r", "bblte", 16,
+ { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bblte $simm24 */
+ {
+ -1, "bblte32r", "bblte", 32,
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* b $simm8 */
+ {
+ -1, "b16r", "b", 16,
+ { 0|A(RELAXABLE)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* b $simm24 */
+ {
+ -1, "b32r", "b", 32,
+ { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bl $simm8 */
+ {
+ -1, "bl16r", "bl", 16,
+ { 0|A(RELAXABLE)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bl $simm24 */
+ {
+ -1, "blr", "bl", 32,
+ { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrb.l $rd6,[$rn6,$direction$rm6] */
+ {
+ -1, "ldrbx", "ldrb.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrb.l $rd6,[$rn6],$direction$rm6 */
+ {
+ -1, "ldrbp", "ldrb.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrb.l $rd6,[$rn6,$dpmi$disp11] */
+ {
+ -1, "ldrbd", "ldrb.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrb.l $rd6,[$rn6],$dpmi$disp11 */
+ {
+ -1, "ldrbdpm", "ldrb.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrb $rd,[$rn] */
+ {
+ -1, "ldrbds0", "ldrb", 16,
+ { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrb $rd6,[$rn6] */
+ {
+ -1, "ldrbdl0", "ldrb", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrb.l $rd6,[$rn6] */
+ {
+ -1, "ldrbdl0.l", "ldrb.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrh.l $rd6,[$rn6,$direction$rm6] */
+ {
+ -1, "ldrhx", "ldrh.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrh.l $rd6,[$rn6],$direction$rm6 */
+ {
+ -1, "ldrhp", "ldrh.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrh.l $rd6,[$rn6,$dpmi$disp11] */
+ {
+ -1, "ldrhd", "ldrh.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrh.l $rd6,[$rn6],$dpmi$disp11 */
+ {
+ -1, "ldrhdpm", "ldrh.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrh $rd,[$rn] */
+ {
+ -1, "ldrhds0", "ldrh", 16,
+ { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrh $rd6,[$rn6] */
+ {
+ -1, "ldrhdl0", "ldrh", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrh.l $rd6,[$rn6] */
+ {
+ -1, "ldrhdl0.l", "ldrh.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldr.l $rd6,[$rn6,$direction$rm6] */
+ {
+ -1, "ldrx", "ldr.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldr.l $rd6,[$rn6],$direction$rm6 */
+ {
+ -1, "ldrp", "ldr.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldr.l $rd6,[$rn6,$dpmi$disp11] */
+ {
+ -1, "ldrd", "ldr.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldr.l $rd6,[$rn6],$dpmi$disp11 */
+ {
+ -1, "ldrdpm", "ldr.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldr $rd,[$rn] */
+ {
+ -1, "ldrds0", "ldr", 16,
+ { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldr $rd6,[$rn6] */
+ {
+ -1, "ldrdl0", "ldr", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldr.l $rd6,[$rn6] */
+ {
+ -1, "ldrdl0.l", "ldr.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrd.l $rd6,[$rn6,$direction$rm6] */
+ {
+ -1, "ldrdx", "ldrd.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrd.l $rd6,[$rn6],$direction$rm6 */
+ {
+ -1, "ldrdp", "ldrd.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrd.l $rd6,[$rn6,$dpmi$disp11] */
+ {
+ -1, "ldrdd", "ldrd.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrd.l $rd6,[$rn6],$dpmi$disp11 */
+ {
+ -1, "ldrddpm", "ldrd.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrd $rd,[$rn] */
+ {
+ -1, "ldrdds0", "ldrd", 16,
+ { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrd $rd6,[$rn6] */
+ {
+ -1, "ldrddl0", "ldrd", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* ldrd.l $rd6,[$rn6] */
+ {
+ -1, "ldrddl0.l", "ldrd.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* testsetb.l $rd6,[$rn6,$direction$rm6] */
+ {
+ -1, "testsetbt.l", "testsetb.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* testseth.l $rd6,[$rn6,$direction$rm6] */
+ {
+ -1, "testsetht.l", "testseth.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* testset.l $rd6,[$rn6,$direction$rm6] */
+ {
+ -1, "testsett.l", "testset.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strb.l $rd6,[$rn6,$direction$rm6] */
+ {
+ -1, "strbx.l", "strb.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strb.l $rd6,[$rn6],$direction$rm6 */
+ {
+ -1, "strbp.l", "strb.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strb.l $rd6,[$rn6,$dpmi$disp11] */
+ {
+ -1, "strbd.l", "strb.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strb.l $rd6,[$rn6],$dpmi$disp11 */
+ {
+ -1, "strbdpm.l", "strb.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strb $rd,[$rn] */
+ {
+ -1, "strbds0", "strb", 16,
+ { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strb $rd6,[$rn6] */
+ {
+ -1, "strbdl0", "strb", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strb.l $rd6,[$rn6] */
+ {
+ -1, "strbdl0.l", "strb.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strh.l $rd6,[$rn6,$direction$rm6] */
+ {
+ -1, "strhx.l", "strh.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strh.l $rd6,[$rn6],$direction$rm6 */
+ {
+ -1, "strhp.l", "strh.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strh.l $rd6,[$rn6,$dpmi$disp11] */
+ {
+ -1, "strhd.l", "strh.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strh.l $rd6,[$rn6],$dpmi$disp11 */
+ {
+ -1, "strhdpm.l", "strh.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strh $rd,[$rn] */
+ {
+ -1, "strhds0", "strh", 16,
+ { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strh $rd6,[$rn6] */
+ {
+ -1, "strhdl0", "strh", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strh.l $rd6,[$rn6] */
+ {
+ -1, "strhdl0.l", "strh.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* str.l $rd6,[$rn6,$direction$rm6] */
+ {
+ -1, "strx.l", "str.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* str.l $rd6,[$rn6],$direction$rm6 */
+ {
+ -1, "strp.l", "str.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* str.l $rd6,[$rn6,$dpmi$disp11] */
+ {
+ -1, "strd.l", "str.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* str.l $rd6,[$rn6],$dpmi$disp11 */
+ {
+ -1, "strdpm.l", "str.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* str $rd,[$rn] */
+ {
+ -1, "strds0", "str", 16,
+ { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* str $rd6,[$rn6] */
+ {
+ -1, "strdl0", "str", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* str.l $rd6,[$rn6] */
+ {
+ -1, "strdl0.l", "str.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strd.l $rd6,[$rn6,$direction$rm6] */
+ {
+ -1, "strdx.l", "strd.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strd.l $rd6,[$rn6],$direction$rm6 */
+ {
+ -1, "strdp.l", "strd.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strd.l $rd6,[$rn6,$dpmi$disp11] */
+ {
+ -1, "strdd.l", "strd.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strd.l $rd6,[$rn6],$dpmi$disp11 */
+ {
+ -1, "strddpm.l", "strd.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strd $rd,[$rn] */
+ {
+ -1, "strdds0", "strd", 16,
+ { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strd $rd6,[$rn6] */
+ {
+ -1, "strddl0", "strd", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* strd.l $rd6,[$rn6] */
+ {
+ -1, "strddl0.l", "strd.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* moveq.l $rd6,$rn6 */
+ {
+ -1, "cmov.lEQ", "moveq.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movne.l $rd6,$rn6 */
+ {
+ -1, "cmov.lNE", "movne.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movgtu.l $rd6,$rn6 */
+ {
+ -1, "cmov.lGTU", "movgtu.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movgteu.l $rd6,$rn6 */
+ {
+ -1, "cmov.lGTEU", "movgteu.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movlteu.l $rd6,$rn6 */
+ {
+ -1, "cmov.lLTEU", "movlteu.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movltu.l $rd6,$rn6 */
+ {
+ -1, "cmov.lLTU", "movltu.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movgt.l $rd6,$rn6 */
+ {
+ -1, "cmov.lGT", "movgt.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movgte.l $rd6,$rn6 */
+ {
+ -1, "cmov.lGTE", "movgte.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movlt.l $rd6,$rn6 */
+ {
+ -1, "cmov.lLT", "movlt.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movlte.l $rd6,$rn6 */
+ {
+ -1, "cmov.lLTE", "movlte.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* mov.l $rd6,$rn6 */
+ {
+ -1, "cmov.lB", "mov.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movbeq.l $rd6,$rn6 */
+ {
+ -1, "cmov.lBEQ", "movbeq.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movbne.l $rd6,$rn6 */
+ {
+ -1, "cmov.lBNE", "movbne.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movblt.l $rd6,$rn6 */
+ {
+ -1, "cmov.lBLT", "movblt.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movblte.l $rd6,$rn6 */
+ {
+ -1, "cmov.lBLTE", "movblte.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movts.l $sn6,$rd6 */
+ {
+ -1, "movts.l6", "movts.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movts.l $sndma,$rd6 */
+ {
+ -1, "movts.ldma", "movts.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movts.l $snmem,$rd6 */
+ {
+ -1, "movts.lmem", "movts.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movts.l $snmesh,$rd6 */
+ {
+ -1, "movts.lmesh", "movts.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movfs.l $rd6,$sn6 */
+ {
+ -1, "movfs.l6", "movfs.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movfs.l $rd6,$sndma */
+ {
+ -1, "movfs.ldma", "movfs.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movfs.l $rd6,$snmem */
+ {
+ -1, "movfs.lmem", "movfs.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movfs.l $rd6,$snmesh */
+ {
+ -1, "movfs.lmesh", "movfs.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* add.l $rd6,$rn6,$rm6 */
+ {
+ -1, "add.l", "add.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* sub.l $rd6,$rn6,$rm6 */
+ {
+ -1, "sub.l", "sub.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* and.l $rd6,$rn6,$rm6 */
+ {
+ -1, "and.l", "and.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* orr.l $rd6,$rn6,$rm6 */
+ {
+ -1, "orr.l", "orr.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* eor.l $rd6,$rn6,$rm6 */
+ {
+ -1, "eor.l", "eor.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* add $rd,$rn,$simm3 */
+ {
+ -1, "addir", "add", 16,
+ { 0|A(IMM3)|A(RELAXABLE)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* add $rd6,$rn6,$simm11 */
+ {
+ -1, "addi32r", "add", 32,
+ { 0|A(RELAXED)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* add $rd6,$rn6,$simm11 */
+ {
+ -1, "addi32m", "add", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* sub $rd,$rn,$simm3 */
+ {
+ -1, "subir", "sub", 16,
+ { 0|A(IMM3)|A(RELAXABLE)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* sub $rd6,$rn6,$simm11 */
+ {
+ -1, "subi32r", "sub", 32,
+ { 0|A(RELAXED)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* sub $rd6,$rn6,$simm11 */
+ {
+ -1, "subi32m", "sub", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* asr.l $rd6,$rn6,$rm6 */
+ {
+ -1, "asr.l", "asr.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* lsr.l $rd6,$rn6,$rm6 */
+ {
+ -1, "lsr.l", "lsr.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* lsl.l $rd6,$rn6,$rm6 */
+ {
+ -1, "lsl.l", "lsl.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* lsr.l $rd6,$rn6,$shift */
+ {
+ -1, "lsri32.l", "lsr.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* lsl.l $rd6,$rn6,$shift */
+ {
+ -1, "lsli32.l", "lsl.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* asr.l $rd6,$rn6,$shift */
+ {
+ -1, "asri32.l", "asr.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* bitr.l $rd6,$rn6 */
+ {
+ -1, "bitrl", "bitr.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fext.l $rd6,$rn6,$rm6 */
+ {
+ -1, "fext.l", "fext.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fdep.l $rd6,$rn6,$rm6 */
+ {
+ -1, "fdep.l", "fdep.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* lfsr.l $rd6,$rn6,$rm6 */
+ {
+ -1, "lfsr.l", "lfsr.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* mov $rd,$imm8 */
+ {
+ -1, "mov8r", "mov", 16,
+ { 0|A(RELAXABLE)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* mov $rd6,$imm16 */
+ {
+ -1, "mov16r", "mov", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* movt.l $rd6,$imm16 */
+ {
+ -1, "movtl", "movt.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* iadd $rd,$rn,$rm */
+ {
+ -1, "i_addf16", "iadd", 16,
+ { 0|A(NO_DIS)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fadd.l $rd6,$rn6,$rm6 */
+ {
+ -1, "f_addf32.l", "fadd.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* iadd $rd6,$rn6,$rm6 */
+ {
+ -1, "i_addf32", "iadd", 32,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* iadd.l $rd6,$rn6,$rm6 */
+ {
+ -1, "i_addf32.l", "iadd.l", 32,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* isub $rd,$rn,$rm */
+ {
+ -1, "i_subf16", "isub", 16,
+ { 0|A(NO_DIS)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fsub.l $rd6,$rn6,$rm6 */
+ {
+ -1, "f_subf32.l", "fsub.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* isub $rd6,$rn6,$rm6 */
+ {
+ -1, "i_subf32", "isub", 32,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* isub.l $rd6,$rn6,$rm6 */
+ {
+ -1, "i_subf32.l", "isub.l", 32,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* imul $rd,$rn,$rm */
+ {
+ -1, "i_mulf16", "imul", 16,
+ { 0|A(NO_DIS)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fmul.l $rd6,$rn6,$rm6 */
+ {
+ -1, "f_mulf32.l", "fmul.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* imul $rd6,$rn6,$rm6 */
+ {
+ -1, "i_mulf32", "imul", 32,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* imul.l $rd6,$rn6,$rm6 */
+ {
+ -1, "i_mulf32.l", "imul.l", 32,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* imadd $rd,$rn,$rm */
+ {
+ -1, "i_maddf16", "imadd", 16,
+ { 0|A(NO_DIS)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fmadd.l $rd6,$rn6,$rm6 */
+ {
+ -1, "f_maddf32.l", "fmadd.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* imadd $rd6,$rn6,$rm6 */
+ {
+ -1, "i_maddf32", "imadd", 32,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* imadd.l $rd6,$rn6,$rm6 */
+ {
+ -1, "i_maddf32.l", "imadd.l", 32,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* imsub $rd,$rn,$rm */
+ {
+ -1, "i_msubf16", "imsub", 16,
+ { 0|A(NO_DIS)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fmsub.l $rd6,$rn6,$rm6 */
+ {
+ -1, "f_msubf32.l", "fmsub.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* imsub $rd6,$rn6,$rm6 */
+ {
+ -1, "i_msubf32", "imsub", 32,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* imsub.l $rd6,$rn6,$rm6 */
+ {
+ -1, "i_msubf32.l", "imsub.l", 32,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fabs.l $rd6,$rn6 */
+ {
+ -1, "f_absf32.l", "fabs.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* float.l $rd6,$rn6 */
+ {
+ -1, "f_loatf32.l", "float.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fix.l $rd6,$rn6 */
+ {
+ -1, "f_ixf32.l", "fix.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* frecip.l $frd6,$frn6 */
+ {
+ -1, "f_recipf32.l", "frecip.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+/* fsqrt.l $frd6,$frn6 */
+ {
+ -1, "f_sqrtf32.l", "fsqrt.l", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+ },
+};
+
+/* The macro instruction opcode table. */
+
+static const CGEN_OPCODE epiphany_cgen_macro_insn_opcode_table[] =
+{
+/* beq $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_beq16r, { 0x0 }
+ },
+/* beq $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_beq32r, { 0x8 }
+ },
+/* bne $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_bne16r, { 0x10 }
+ },
+/* bne $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_bne32r, { 0x18 }
+ },
+/* bgtu $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_bgtu16r, { 0x20 }
+ },
+/* bgtu $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_bgtu32r, { 0x28 }
+ },
+/* bgteu $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_bgteu16r, { 0x30 }
+ },
+/* bgteu $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_bgteu32r, { 0x38 }
+ },
+/* blteu $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_blteu16r, { 0x40 }
+ },
+/* blteu $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_blteu32r, { 0x48 }
+ },
+/* bltu $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_bltu16r, { 0x50 }
+ },
+/* bltu $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_bltu32r, { 0x58 }
+ },
+/* bgt $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_bgt16r, { 0x60 }
+ },
+/* bgt $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_bgt32r, { 0x68 }
+ },
+/* bgte $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_bgte16r, { 0x70 }
+ },
+/* bgte $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_bgte32r, { 0x78 }
+ },
+/* blt $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_blt16r, { 0x80 }
+ },
+/* blt $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_blt32r, { 0x88 }
+ },
+/* blte $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_blte16r, { 0x90 }
+ },
+/* blte $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_blte32r, { 0x98 }
+ },
+/* bbeq $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_bbeq16r, { 0xa0 }
+ },
+/* bbeq $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_bbeq32r, { 0xa8 }
+ },
+/* bbne $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_bbne16r, { 0xb0 }
+ },
+/* bbne $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_bbne32r, { 0xb8 }
+ },
+/* bblt $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_bblt16r, { 0xc0 }
+ },
+/* bblt $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_bblt32r, { 0xc8 }
+ },
+/* bblte $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_bblte16r, { 0xd0 }
+ },
+/* bblte $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_bblte32r, { 0xd8 }
+ },
+/* b $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_b16r, { 0xe0 }
+ },
+/* b $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_b32r, { 0xe8 }
+ },
+/* bl $simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM8), 0 } },
+ & ifmt_bl16r, { 0xf0 }
+ },
+/* bl $simm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM24), 0 } },
+ & ifmt_blr, { 0xf8 }
+ },
+/* ldrb.l $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_ldrbx, { 0x9 }
+ },
+/* ldrb.l $rd6,[$rn6],$direction$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+ & ifmt_ldrbp, { 0xd }
+ },
+/* ldrb.l $rd6,[$rn6,$dpmi$disp11] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+ & ifmt_ldrbd, { 0xc }
+ },
+/* ldrb.l $rd6,[$rn6],$dpmi$disp11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+ & ifmt_ldrbdpm, { 0x200000c }
+ },
+/* ldrb $rd,[$rn] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } },
+ & ifmt_ldrbds0, { 0x4 }
+ },
+/* ldrb $rd6,[$rn6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+ & ifmt_ldrbdl0, { 0xc }
+ },
+/* ldrb.l $rd6,[$rn6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+ & ifmt_ldrbdl0_l, { 0xc }
+ },
+/* ldrh.l $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_ldrhx, { 0x29 }
+ },
+/* ldrh.l $rd6,[$rn6],$direction$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+ & ifmt_ldrhp, { 0x2d }
+ },
+/* ldrh.l $rd6,[$rn6,$dpmi$disp11] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+ & ifmt_ldrhd, { 0x2c }
+ },
+/* ldrh.l $rd6,[$rn6],$dpmi$disp11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+ & ifmt_ldrhdpm, { 0x200002c }
+ },
+/* ldrh $rd,[$rn] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } },
+ & ifmt_ldrhds0, { 0x24 }
+ },
+/* ldrh $rd6,[$rn6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+ & ifmt_ldrhdl0, { 0x2c }
+ },
+/* ldrh.l $rd6,[$rn6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+ & ifmt_ldrhdl0_l, { 0x2c }
+ },
+/* ldr.l $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_ldrx, { 0x49 }
+ },
+/* ldr.l $rd6,[$rn6],$direction$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+ & ifmt_ldrp, { 0x4d }
+ },
+/* ldr.l $rd6,[$rn6,$dpmi$disp11] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+ & ifmt_ldrd, { 0x4c }
+ },
+/* ldr.l $rd6,[$rn6],$dpmi$disp11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+ & ifmt_ldrdpm, { 0x200004c }
+ },
+/* ldr $rd,[$rn] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } },
+ & ifmt_ldrds0, { 0x44 }
+ },
+/* ldr $rd6,[$rn6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+ & ifmt_ldrdl0, { 0x4c }
+ },
+/* ldr.l $rd6,[$rn6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+ & ifmt_ldrdl0_l, { 0x4c }
+ },
+/* ldrd.l $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_ldrdx, { 0x69 }
+ },
+/* ldrd.l $rd6,[$rn6],$direction$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+ & ifmt_ldrdp, { 0x6d }
+ },
+/* ldrd.l $rd6,[$rn6,$dpmi$disp11] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+ & ifmt_ldrdd, { 0x6c }
+ },
+/* ldrd.l $rd6,[$rn6],$dpmi$disp11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+ & ifmt_ldrddpm, { 0x200006c }
+ },
+/* ldrd $rd,[$rn] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } },
+ & ifmt_ldrdds0, { 0x64 }
+ },
+/* ldrd $rd6,[$rn6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+ & ifmt_ldrddl0, { 0x6c }
+ },
+/* ldrd.l $rd6,[$rn6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+ & ifmt_ldrddl0_l, { 0x6c }
+ },
+/* testsetb.l $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_testsetbt_l, { 0x200009 }
+ },
+/* testseth.l $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_testsetht_l, { 0x200029 }
+ },
+/* testset.l $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_testsett_l, { 0x200049 }
+ },
+/* strb.l $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_strbx_l, { 0x19 }
+ },
+/* strb.l $rd6,[$rn6],$direction$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+ & ifmt_strbp_l, { 0x1d }
+ },
+/* strb.l $rd6,[$rn6,$dpmi$disp11] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+ & ifmt_strbd_l, { 0x1c }
+ },
+/* strb.l $rd6,[$rn6],$dpmi$disp11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+ & ifmt_strbdpm_l, { 0x200001c }
+ },
+/* strb $rd,[$rn] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } },
+ & ifmt_strbds0, { 0x14 }
+ },
+/* strb $rd6,[$rn6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+ & ifmt_strbdl0, { 0x1c }
+ },
+/* strb.l $rd6,[$rn6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+ & ifmt_strbdl0_l, { 0x1c }
+ },
+/* strh.l $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_strhx_l, { 0x39 }
+ },
+/* strh.l $rd6,[$rn6],$direction$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+ & ifmt_strhp_l, { 0x3d }
+ },
+/* strh.l $rd6,[$rn6,$dpmi$disp11] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+ & ifmt_strhd_l, { 0x3c }
+ },
+/* strh.l $rd6,[$rn6],$dpmi$disp11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+ & ifmt_strhdpm_l, { 0x200003c }
+ },
+/* strh $rd,[$rn] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } },
+ & ifmt_strhds0, { 0x34 }
+ },
+/* strh $rd6,[$rn6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+ & ifmt_strhdl0, { 0x3c }
+ },
+/* strh.l $rd6,[$rn6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+ & ifmt_strhdl0_l, { 0x3c }
+ },
+/* str.l $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_strx_l, { 0x59 }
+ },
+/* str.l $rd6,[$rn6],$direction$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+ & ifmt_strp_l, { 0x5d }
+ },
+/* str.l $rd6,[$rn6,$dpmi$disp11] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+ & ifmt_strd_l, { 0x5c }
+ },
+/* str.l $rd6,[$rn6],$dpmi$disp11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+ & ifmt_strdpm_l, { 0x200005c }
+ },
+/* str $rd,[$rn] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } },
+ & ifmt_strds0, { 0x54 }
+ },
+/* str $rd6,[$rn6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+ & ifmt_strdl0, { 0x5c }
+ },
+/* str.l $rd6,[$rn6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+ & ifmt_strdl0_l, { 0x5c }
+ },
+/* strd.l $rd6,[$rn6,$direction$rm6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+ & ifmt_strdx_l, { 0x79 }
+ },
+/* strd.l $rd6,[$rn6],$direction$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+ & ifmt_strdp_l, { 0x7d }
+ },
+/* strd.l $rd6,[$rn6,$dpmi$disp11] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+ & ifmt_strdd_l, { 0x7c }
+ },
+/* strd.l $rd6,[$rn6],$dpmi$disp11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+ & ifmt_strddpm_l, { 0x200007c }
+ },
+/* strd $rd,[$rn] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } },
+ & ifmt_strdds0, { 0x74 }
+ },
+/* strd $rd6,[$rn6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+ & ifmt_strddl0, { 0x7c }
+ },
+/* strd.l $rd6,[$rn6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+ & ifmt_strddl0_l, { 0x7c }
+ },
+/* moveq.l $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmov_lEQ, { 0x2000f }
+ },
+/* movne.l $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmov_lNE, { 0x2001f }
+ },
+/* movgtu.l $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmov_lGTU, { 0x2002f }
+ },
+/* movgteu.l $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmov_lGTEU, { 0x2003f }
+ },
+/* movlteu.l $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmov_lLTEU, { 0x2004f }
+ },
+/* movltu.l $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmov_lLTU, { 0x2005f }
+ },
+/* movgt.l $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmov_lGT, { 0x2006f }
+ },
+/* movgte.l $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmov_lGTE, { 0x2007f }
+ },
+/* movlt.l $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmov_lLT, { 0x2008f }
+ },
+/* movlte.l $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmov_lLTE, { 0x2009f }
+ },
+/* mov.l $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmov_lB, { 0x200ef }
+ },
+/* movbeq.l $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmov_lBEQ, { 0x200af }
+ },
+/* movbne.l $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmov_lBNE, { 0x200bf }
+ },
+/* movblt.l $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmov_lBLT, { 0x200cf }
+ },
+/* movblte.l $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_cmov_lBLTE, { 0x200df }
+ },
+/* movts.l $sn6,$rd6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SN6), ',', OP (RD6), 0 } },
+ & ifmt_movts_l6, { 0x2010f }
+ },
+/* movts.l $sndma,$rd6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SNDMA), ',', OP (RD6), 0 } },
+ & ifmt_movts_ldma, { 0x12010f }
+ },
+/* movts.l $snmem,$rd6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SNMEM), ',', OP (RD6), 0 } },
+ & ifmt_movts_lmem, { 0x22010f }
+ },
+/* movts.l $snmesh,$rd6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SNMESH), ',', OP (RD6), 0 } },
+ & ifmt_movts_lmesh, { 0x32010f }
+ },
+/* movfs.l $rd6,$sn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (SN6), 0 } },
+ & ifmt_movfs_l6, { 0x2011f }
+ },
+/* movfs.l $rd6,$sndma */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (SNDMA), 0 } },
+ & ifmt_movfs_ldma, { 0x12011f }
+ },
+/* movfs.l $rd6,$snmem */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (SNMEM), 0 } },
+ & ifmt_movfs_lmem, { 0x22011f }
+ },
+/* movfs.l $rd6,$snmesh */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (SNMESH), 0 } },
+ & ifmt_movfs_lmesh, { 0x32011f }
+ },
+/* add.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_add_l, { 0xa001f }
+ },
+/* sub.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_sub_l, { 0xa003f }
+ },
+/* and.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_and_l, { 0xa005f }
+ },
+/* orr.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_orr_l, { 0xa007f }
+ },
+/* eor.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_eor_l, { 0xa000f }
+ },
+/* add $rd,$rn,$simm3 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SIMM3), 0 } },
+ & ifmt_addir, { 0x13 }
+ },
+/* add $rd6,$rn6,$simm11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SIMM11), 0 } },
+ & ifmt_addi32r, { 0x1b }
+ },
+/* add $rd6,$rn6,$simm11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SIMM11), 0 } },
+ & ifmt_addi32m, { 0x1b }
+ },
+/* sub $rd,$rn,$simm3 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SIMM3), 0 } },
+ & ifmt_subir, { 0x33 }
+ },
+/* sub $rd6,$rn6,$simm11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SIMM11), 0 } },
+ & ifmt_subi32r, { 0x3b }
+ },
+/* sub $rd6,$rn6,$simm11 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SIMM11), 0 } },
+ & ifmt_subi32m, { 0x3b }
+ },
+/* asr.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_asr_l, { 0xa006f }
+ },
+/* lsr.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_lsr_l, { 0xa004f }
+ },
+/* lsl.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_lsl_l, { 0xa002f }
+ },
+/* lsr.l $rd6,$rn6,$shift */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SHIFT), 0 } },
+ & ifmt_lsri32_l, { 0x6000f }
+ },
+/* lsl.l $rd6,$rn6,$shift */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SHIFT), 0 } },
+ & ifmt_lsli32_l, { 0x6001f }
+ },
+/* asr.l $rd6,$rn6,$shift */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SHIFT), 0 } },
+ & ifmt_asri32_l, { 0xe000f }
+ },
+/* bitr.l $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_bitrl, { 0xe001f }
+ },
+/* fext.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_fext_l, { 0x1a000f }
+ },
+/* fdep.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_fdep_l, { 0x1a001f }
+ },
+/* lfsr.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_lfsr_l, { 0x1a002f }
+ },
+/* mov $rd,$imm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (IMM8), 0 } },
+ & ifmt_mov8r, { 0x3 }
+ },
+/* mov $rd6,$imm16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (IMM16), 0 } },
+ & ifmt_mov16r, { 0x2000b }
+ },
+/* movt.l $rd6,$imm16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (IMM16), 0 } },
+ & ifmt_movtl, { 0x1002000b }
+ },
+/* iadd $rd,$rn,$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+ & ifmt_i_addf16, { 0x7 }
+ },
+/* fadd.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_f_addf32_l, { 0x7000f }
+ },
+/* iadd $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_i_addf32, { 0x7000f }
+ },
+/* iadd.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_i_addf32_l, { 0x7000f }
+ },
+/* isub $rd,$rn,$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+ & ifmt_i_subf16, { 0x17 }
+ },
+/* fsub.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_f_subf32_l, { 0x7001f }
+ },
+/* isub $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_i_subf32, { 0x7001f }
+ },
+/* isub.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_i_subf32_l, { 0x7001f }
+ },
+/* imul $rd,$rn,$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+ & ifmt_i_mulf16, { 0x27 }
+ },
+/* fmul.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_f_mulf32_l, { 0x7002f }
+ },
+/* imul $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_i_mulf32, { 0x7002f }
+ },
+/* imul.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_i_mulf32_l, { 0x7002f }
+ },
+/* imadd $rd,$rn,$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+ & ifmt_i_maddf16, { 0x37 }
+ },
+/* fmadd.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_f_maddf32_l, { 0x7003f }
+ },
+/* imadd $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_i_maddf32, { 0x7003f }
+ },
+/* imadd.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_i_maddf32_l, { 0x7003f }
+ },
+/* imsub $rd,$rn,$rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+ & ifmt_i_msubf16, { 0x47 }
+ },
+/* fmsub.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_f_msubf32_l, { 0x7004f }
+ },
+/* imsub $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_i_msubf32, { 0x7004f }
+ },
+/* imsub.l $rd6,$rn6,$rm6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+ & ifmt_i_msubf32_l, { 0x7004f }
+ },
+/* fabs.l $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_f_absf32_l, { 0x7007f }
+ },
+/* float.l $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_f_loatf32_l, { 0x7005f }
+ },
+/* fix.l $rd6,$rn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+ & ifmt_f_ixf32_l, { 0x7006f }
+ },
+/* frecip.l $frd6,$frn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FRD6), ',', OP (FRN6), 0 } },
+ & ifmt_f_recipf32_l, { 0x17000f }
+ },
+/* fsqrt.l $frd6,$frn6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (FRD6), ',', OP (FRN6), 0 } },
+ & ifmt_f_sqrtf32_l, { 0x17001f }
+ },
+};
+
+#undef A
+#undef OPERAND
+#undef MNEM
+#undef OP
+
+#ifndef CGEN_ASM_HASH_P
+#define CGEN_ASM_HASH_P(insn) 1
+#endif
+
+#ifndef CGEN_DIS_HASH_P
+#define CGEN_DIS_HASH_P(insn) 1
+#endif
+
+/* Return non-zero if INSN is to be added to the hash table.
+ Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
+
+static int
+asm_hash_insn_p (insn)
+ const CGEN_INSN *insn ATTRIBUTE_UNUSED;
+{
+ return CGEN_ASM_HASH_P (insn);
+}
+
+static int
+dis_hash_insn_p (insn)
+ const CGEN_INSN *insn;
+{
+ /* If building the hash table and the NO-DIS attribute is present,
+ ignore. */
+ if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
+ return 0;
+ return CGEN_DIS_HASH_P (insn);
+}
+
+#ifndef CGEN_ASM_HASH
+#define CGEN_ASM_HASH_SIZE 127
+#ifdef CGEN_MNEMONIC_OPERANDS
+#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
+#else
+#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
+#endif
+#endif
+
+/* It doesn't make much sense to provide a default here,
+ but while this is under development we do.
+ BUFFER is a pointer to the bytes of the insn, target order.
+ VALUE is the first base_insn_bitsize bits as an int in host order. */
+
+#ifndef CGEN_DIS_HASH
+#define CGEN_DIS_HASH_SIZE 256
+#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
+#endif
+
+/* The result is the hash value of the insn.
+ Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
+
+static unsigned int
+asm_hash_insn (mnem)
+ const char * mnem;
+{
+ return CGEN_ASM_HASH (mnem);
+}
+
+/* BUF is a pointer to the bytes of the insn, target order.
+ VALUE is the first base_insn_bitsize bits as an int in host order. */
+
+static unsigned int
+dis_hash_insn (buf, value)
+ const char * buf ATTRIBUTE_UNUSED;
+ CGEN_INSN_INT value ATTRIBUTE_UNUSED;
+{
+ return CGEN_DIS_HASH (buf, value);
+}
+
+/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
+
+static void
+set_fields_bitsize (CGEN_FIELDS *fields, int size)
+{
+ CGEN_FIELDS_BITSIZE (fields) = size;
+}
+
+/* Function to call before using the operand instance table.
+ This plugs the opcode entries and macro instructions into the cpu table. */
+
+void
+epiphany_cgen_init_opcode_table (CGEN_CPU_DESC cd)
+{
+ int i;
+ int num_macros = (sizeof (epiphany_cgen_macro_insn_table) /
+ sizeof (epiphany_cgen_macro_insn_table[0]));
+ const CGEN_IBASE *ib = & epiphany_cgen_macro_insn_table[0];
+ const CGEN_OPCODE *oc = & epiphany_cgen_macro_insn_opcode_table[0];
+ CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
+
+ /* This test has been added to avoid a warning generated
+ if memset is called with a third argument of value zero. */
+ if (num_macros >= 1)
+ memset (insns, 0, num_macros * sizeof (CGEN_INSN));
+ for (i = 0; i < num_macros; ++i)
+ {
+ insns[i].base = &ib[i];
+ insns[i].opcode = &oc[i];
+ epiphany_cgen_build_insn_regex (& insns[i]);
+ }
+ cd->macro_insn_table.init_entries = insns;
+ cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
+ cd->macro_insn_table.num_init_entries = num_macros;
+
+ oc = & epiphany_cgen_insn_opcode_table[0];
+ insns = (CGEN_INSN *) cd->insn_table.init_entries;
+ for (i = 0; i < MAX_INSNS; ++i)
+ {
+ insns[i].opcode = &oc[i];
+ epiphany_cgen_build_insn_regex (& insns[i]);
+ }
+
+ cd->sizeof_fields = sizeof (CGEN_FIELDS);
+ cd->set_fields_bitsize = set_fields_bitsize;
+
+ cd->asm_hash_p = asm_hash_insn_p;
+ cd->asm_hash = asm_hash_insn;
+ cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
+
+ cd->dis_hash_p = dis_hash_insn_p;
+ cd->dis_hash = dis_hash_insn;
+ cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
+}
--- /dev/null
+/* Instruction opcode header for epiphany.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef EPIPHANY_OPC_H
+#define EPIPHANY_OPC_H
+
+/* -- opc.h */
+
+/* enumerate relaxation types for gas. */
+typedef enum epiphany_relax_types
+{
+ EPIPHANY_RELAX_NONE=0,
+ EPIPHANY_RELAX_NEED_RELAXING,
+
+ EPIPHANY_RELAX_BRANCH_SHORT, /* Fits into +127..-128 */
+ EPIPHANY_RELAX_BRANCH_LONG, /* b/bl/b<cond> +-2*16 */
+
+ EPIPHANY_RELAX_ARITH_SIMM3, /* add/sub -7..3 */
+ EPIPHANY_RELAX_ARITH_SIMM11, /* add/sub -2**11-1 .. 2**10-1 */
+
+ EPIPHANY_RELAX_MOV_IMM8, /* mov r,imm8 */
+ EPIPHANY_RELAX_MOV_IMM16, /* mov r,imm16 */
+
+ EPIPHANY_RELAX_LDST_IMM3, /* (ldr|str)* r,[r,disp3] */
+ EPIPHANY_RELAX_LDST_IMM11 /* (ldr|str)* r,[r,disp11] */
+
+} EPIPHANY_RELAX_TYPES;
+
+/* Override disassembly hashing... */
+
+/* Can only depend on instruction having 4 decode bits which gets us to the
+ major groups of 16/32 instructions. */
+#undef CGEN_DIS_HASH_SIZE
+#if 1
+
+/* hash code on the 4 LSBs */
+#define CGEN_DIS_HASH_SIZE 16
+
+#define CGEN_DIS_HASH(buf, value) ((*buf) & 0xf)
+#else
+#define CGEN_DIS_HASH_SIZE 1
+#define CGEN_DIS_HASH(buf, value) 0
+#endif
+
+extern const char * parse_shortregs (CGEN_CPU_DESC cd,
+ const char ** strp,
+ CGEN_KEYWORD * keywords,
+ long * valuep);
+
+extern const char * parse_branch_addr (CGEN_CPU_DESC cd,
+ const char ** strp,
+ int opindex,
+ int opinfo,
+ enum cgen_parse_operand_result * resultp,
+ unsigned long * valuep);
+
+/* Allows reason codes to be output when assembler errors occur. */
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+
+\f
+/* -- opc.c */
+/* Enum declaration for epiphany instruction types. */
+typedef enum cgen_insn_type {
+ EPIPHANY_INSN_INVALID, EPIPHANY_INSN_BEQ16, EPIPHANY_INSN_BEQ, EPIPHANY_INSN_BNE16
+ , EPIPHANY_INSN_BNE, EPIPHANY_INSN_BGTU16, EPIPHANY_INSN_BGTU, EPIPHANY_INSN_BGTEU16
+ , EPIPHANY_INSN_BGTEU, EPIPHANY_INSN_BLTEU16, EPIPHANY_INSN_BLTEU, EPIPHANY_INSN_BLTU16
+ , EPIPHANY_INSN_BLTU, EPIPHANY_INSN_BGT16, EPIPHANY_INSN_BGT, EPIPHANY_INSN_BGTE16
+ , EPIPHANY_INSN_BGTE, EPIPHANY_INSN_BLT16, EPIPHANY_INSN_BLT, EPIPHANY_INSN_BLTE16
+ , EPIPHANY_INSN_BLTE, EPIPHANY_INSN_BBEQ16, EPIPHANY_INSN_BBEQ, EPIPHANY_INSN_BBNE16
+ , EPIPHANY_INSN_BBNE, EPIPHANY_INSN_BBLT16, EPIPHANY_INSN_BBLT, EPIPHANY_INSN_BBLTE16
+ , EPIPHANY_INSN_BBLTE, EPIPHANY_INSN_B16, EPIPHANY_INSN_B, EPIPHANY_INSN_BL16
+ , EPIPHANY_INSN_BL, EPIPHANY_INSN_JR16, EPIPHANY_INSN_RTS, EPIPHANY_INSN_JR
+ , EPIPHANY_INSN_JALR16, EPIPHANY_INSN_JALR, EPIPHANY_INSN_LDRBX16_S, EPIPHANY_INSN_LDRBP16_S
+ , EPIPHANY_INSN_LDRBX_L, EPIPHANY_INSN_LDRBP_L, EPIPHANY_INSN_LDRBD16_S, EPIPHANY_INSN_LDRBD_L
+ , EPIPHANY_INSN_LDRBDPM_L, EPIPHANY_INSN_LDRHX16_S, EPIPHANY_INSN_LDRHP16_S, EPIPHANY_INSN_LDRHX_L
+ , EPIPHANY_INSN_LDRHP_L, EPIPHANY_INSN_LDRHD16_S, EPIPHANY_INSN_LDRHD_L, EPIPHANY_INSN_LDRHDPM_L
+ , EPIPHANY_INSN_LDRX16_S, EPIPHANY_INSN_LDRP16_S, EPIPHANY_INSN_LDRX_L, EPIPHANY_INSN_LDRP_L
+ , EPIPHANY_INSN_LDRD16_S, EPIPHANY_INSN_LDRD_L, EPIPHANY_INSN_LDRDPM_L, EPIPHANY_INSN_LDRDX16_S
+ , EPIPHANY_INSN_LDRDP16_S, EPIPHANY_INSN_LDRDX_L, EPIPHANY_INSN_LDRDP_L, EPIPHANY_INSN_LDRDD16_S
+ , EPIPHANY_INSN_LDRDD_L, EPIPHANY_INSN_LDRDDPM_L, EPIPHANY_INSN_TESTSETBT, EPIPHANY_INSN_TESTSETHT
+ , EPIPHANY_INSN_TESTSETT, EPIPHANY_INSN_STRBX16, EPIPHANY_INSN_STRBX, EPIPHANY_INSN_STRBP16
+ , EPIPHANY_INSN_STRBP, EPIPHANY_INSN_STRBD16, EPIPHANY_INSN_STRBD, EPIPHANY_INSN_STRBDPM
+ , EPIPHANY_INSN_STRHX16, EPIPHANY_INSN_STRHX, EPIPHANY_INSN_STRHP16, EPIPHANY_INSN_STRHP
+ , EPIPHANY_INSN_STRHD16, EPIPHANY_INSN_STRHD, EPIPHANY_INSN_STRHDPM, EPIPHANY_INSN_STRX16
+ , EPIPHANY_INSN_STRX, EPIPHANY_INSN_STRP16, EPIPHANY_INSN_STRP, EPIPHANY_INSN_STRD16
+ , EPIPHANY_INSN_STRD, EPIPHANY_INSN_STRDPM, EPIPHANY_INSN_STRDX16, EPIPHANY_INSN_STRDX
+ , EPIPHANY_INSN_STRDP16, EPIPHANY_INSN_STRDP, EPIPHANY_INSN_STRDD16, EPIPHANY_INSN_STRDD
+ , EPIPHANY_INSN_STRDDPM, EPIPHANY_INSN_CMOV16EQ, EPIPHANY_INSN_CMOVEQ, EPIPHANY_INSN_CMOV16NE
+ , EPIPHANY_INSN_CMOVNE, EPIPHANY_INSN_CMOV16GTU, EPIPHANY_INSN_CMOVGTU, EPIPHANY_INSN_CMOV16GTEU
+ , EPIPHANY_INSN_CMOVGTEU, EPIPHANY_INSN_CMOV16LTEU, EPIPHANY_INSN_CMOVLTEU, EPIPHANY_INSN_CMOV16LTU
+ , EPIPHANY_INSN_CMOVLTU, EPIPHANY_INSN_CMOV16GT, EPIPHANY_INSN_CMOVGT, EPIPHANY_INSN_CMOV16GTE
+ , EPIPHANY_INSN_CMOVGTE, EPIPHANY_INSN_CMOV16LT, EPIPHANY_INSN_CMOVLT, EPIPHANY_INSN_CMOV16LTE
+ , EPIPHANY_INSN_CMOVLTE, EPIPHANY_INSN_CMOV16B, EPIPHANY_INSN_CMOVB, EPIPHANY_INSN_CMOV16BEQ
+ , EPIPHANY_INSN_CMOVBEQ, EPIPHANY_INSN_CMOV16BNE, EPIPHANY_INSN_CMOVBNE, EPIPHANY_INSN_CMOV16BLT
+ , EPIPHANY_INSN_CMOVBLT, EPIPHANY_INSN_CMOV16BLTE, EPIPHANY_INSN_CMOVBLTE, EPIPHANY_INSN_MOVTS16
+ , EPIPHANY_INSN_MOVTS6, EPIPHANY_INSN_MOVTSDMA, EPIPHANY_INSN_MOVTSMEM, EPIPHANY_INSN_MOVTSMESH
+ , EPIPHANY_INSN_MOVFS16, EPIPHANY_INSN_MOVFS6, EPIPHANY_INSN_MOVFSDMA, EPIPHANY_INSN_MOVFSMEM
+ , EPIPHANY_INSN_MOVFSMESH, EPIPHANY_INSN_NOP, EPIPHANY_INSN_SNOP, EPIPHANY_INSN_UNIMPL
+ , EPIPHANY_INSN_IDLE, EPIPHANY_INSN_BKPT, EPIPHANY_INSN_MBKPT, EPIPHANY_INSN_RTI
+ , EPIPHANY_INSN_WAND, EPIPHANY_INSN_SYNC, EPIPHANY_INSN_GIEN, EPIPHANY_INSN_GIDIS
+ , EPIPHANY_INSN_SWI_NUM, EPIPHANY_INSN_SWI, EPIPHANY_INSN_TRAP16, EPIPHANY_INSN_ADD16
+ , EPIPHANY_INSN_ADD, EPIPHANY_INSN_SUB16, EPIPHANY_INSN_SUB, EPIPHANY_INSN_AND16
+ , EPIPHANY_INSN_AND, EPIPHANY_INSN_ORR16, EPIPHANY_INSN_ORR, EPIPHANY_INSN_EOR16
+ , EPIPHANY_INSN_EOR, EPIPHANY_INSN_ADDI16, EPIPHANY_INSN_ADDI, EPIPHANY_INSN_SUBI16
+ , EPIPHANY_INSN_SUBI, EPIPHANY_INSN_ASR16, EPIPHANY_INSN_ASR, EPIPHANY_INSN_LSR16
+ , EPIPHANY_INSN_LSR, EPIPHANY_INSN_LSL16, EPIPHANY_INSN_LSL, EPIPHANY_INSN_LSRI16
+ , EPIPHANY_INSN_LSRI32, EPIPHANY_INSN_LSLI16, EPIPHANY_INSN_LSLI32, EPIPHANY_INSN_ASRI16
+ , EPIPHANY_INSN_ASRI32, EPIPHANY_INSN_BITR16, EPIPHANY_INSN_BITR, EPIPHANY_INSN_FEXT
+ , EPIPHANY_INSN_FDEP, EPIPHANY_INSN_LFSR, EPIPHANY_INSN_MOV8, EPIPHANY_INSN_MOV16
+ , EPIPHANY_INSN_MOVT, EPIPHANY_INSN_F_ADDF16, EPIPHANY_INSN_F_ADDF32, EPIPHANY_INSN_F_SUBF16
+ , EPIPHANY_INSN_F_SUBF32, EPIPHANY_INSN_F_MULF16, EPIPHANY_INSN_F_MULF32, EPIPHANY_INSN_F_MADDF16
+ , EPIPHANY_INSN_F_MADDF32, EPIPHANY_INSN_F_MSUBF16, EPIPHANY_INSN_F_MSUBF32, EPIPHANY_INSN_F_ABSF16
+ , EPIPHANY_INSN_F_ABSF32, EPIPHANY_INSN_F_LOATF16, EPIPHANY_INSN_F_LOATF32, EPIPHANY_INSN_F_IXF16
+ , EPIPHANY_INSN_F_IXF32, EPIPHANY_INSN_F_RECIPF32, EPIPHANY_INSN_F_SQRTF32
+} CGEN_INSN_TYPE;
+
+/* Index of `invalid' insn place holder. */
+#define CGEN_INSN_INVALID EPIPHANY_INSN_INVALID
+
+/* Total number of insns in table. */
+#define MAX_INSNS ((int) EPIPHANY_INSN_F_SQRTF32 + 1)
+
+/* This struct records data prior to insertion or after extraction. */
+struct cgen_fields
+{
+ int length;
+ long f_nil;
+ long f_anyof;
+ long f_opc;
+ long f_opc_4_1;
+ long f_opc_6_3;
+ long f_opc_8_5;
+ long f_opc_19_4;
+ long f_condcode;
+ long f_secondary_ccs;
+ long f_shift;
+ long f_wordsize;
+ long f_store;
+ long f_opc_8_1;
+ long f_opc_31_32;
+ long f_simm8;
+ long f_simm24;
+ long f_sdisp3;
+ long f_disp3;
+ long f_disp8;
+ long f_imm8;
+ long f_imm_27_8;
+ long f_addsubx;
+ long f_subd;
+ long f_pm;
+ long f_rm;
+ long f_rn;
+ long f_rd;
+ long f_rm_x;
+ long f_rn_x;
+ long f_rd_x;
+ long f_dc_9_1;
+ long f_sn;
+ long f_sd;
+ long f_sn_x;
+ long f_sd_x;
+ long f_dc_7_4;
+ long f_trap_swi_9_1;
+ long f_gien_gidis_9_1;
+ long f_dc_15_3;
+ long f_dc_15_7;
+ long f_dc_15_6;
+ long f_trap_num;
+ long f_dc_20_1;
+ long f_dc_21_1;
+ long f_dc_21_2;
+ long f_dc_22_3;
+ long f_dc_22_2;
+ long f_dc_22_1;
+ long f_dc_25_6;
+ long f_dc_25_4;
+ long f_dc_25_2;
+ long f_dc_25_1;
+ long f_dc_28_1;
+ long f_dc_31_3;
+ long f_disp11;
+ long f_sdisp11;
+ long f_imm16;
+ long f_rd6;
+ long f_rn6;
+ long f_rm6;
+ long f_sd6;
+ long f_sn6;
+};
+
+#define CGEN_INIT_PARSE(od) \
+{\
+}
+#define CGEN_INIT_INSERT(od) \
+{\
+}
+#define CGEN_INIT_EXTRACT(od) \
+{\
+}
+#define CGEN_INIT_PRINT(od) \
+{\
+}
+
+
+#endif /* EPIPHANY_OPC_H */
dis-init.c
disassemble.c
dlx-dis.c
+epiphany-asm.c
+epiphany-desc.c
+epiphany-desc.h
+epiphany-dis.c
+epiphany-ibld.c
+epiphany-opc.c
+epiphany-opc.h
fr30-asm.c
fr30-desc.c
fr30-desc.h
mep-opc.h
microblaze-dis.c
microblaze-opc.h
+micromips-opc.c
mips-dis.c
mips-opc.c
mips16-opc.c
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n"
-"POT-Creation-Date: 2011-06-02 14:30+0100\n"
+"POT-Creation-Date: 2011-10-25 11:34+0100\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n"
msgid "must specify .jd or no nullify suffix"
msgstr ""
-#: arm-dis.c:1994
+#: arm-dis.c:2000
msgid "<illegal precision>"
msgstr ""
#. XXX - should break 'option' at following delimiter.
-#: arm-dis.c:4376
+#: arm-dis.c:4395
#, c-format
msgid "Unrecognised register name set: %s\n"
msgstr ""
#. XXX - should break 'option' at following delimiter.
-#: arm-dis.c:4384
+#: arm-dis.c:4403
#, c-format
msgid "Unrecognised disassembler option: %s\n"
msgstr ""
-#: arm-dis.c:4976
+#: arm-dis.c:4995
#, c-format
msgid ""
"\n"
"the -M switch:\n"
msgstr ""
-#: avr-dis.c:115 avr-dis.c:135
+#: avr-dis.c:115 avr-dis.c:136
#, c-format
msgid "undefined"
msgstr ""
-#: avr-dis.c:197
+#: avr-dis.c:198
#, c-format
msgid "Internal disassembler error"
msgstr ""
-#: avr-dis.c:250
+#: avr-dis.c:251
#, c-format
msgid "unknown constraint `%c'"
msgstr ""
-#: cgen-asm.c:336 fr30-ibld.c:201 frv-ibld.c:201 ip2k-ibld.c:201
-#: iq2000-ibld.c:201 lm32-ibld.c:201 m32c-ibld.c:201 m32r-ibld.c:201
-#: mep-ibld.c:201 mt-ibld.c:201 openrisc-ibld.c:201 xc16x-ibld.c:201
-#: xstormy16-ibld.c:201
+#: cgen-asm.c:336 epiphany-ibld.c:201 fr30-ibld.c:201 frv-ibld.c:201
+#: ip2k-ibld.c:201 iq2000-ibld.c:201 lm32-ibld.c:201 m32c-ibld.c:201
+#: m32r-ibld.c:201 mep-ibld.c:201 mt-ibld.c:201 openrisc-ibld.c:201
+#: xc16x-ibld.c:201 xstormy16-ibld.c:201
#, c-format
msgid "operand out of range (%ld not between %ld and %ld)"
msgstr ""
msgid "Address 0x%s is out of bounds.\n"
msgstr ""
-#: fr30-asm.c:93 m32c-asm.c:872 m32c-asm.c:879
-msgid "Register number is not valid"
+#: epiphany-asm.c:68
+msgid "register unavailable for short instructions"
msgstr ""
-#: fr30-asm.c:95
-msgid "Register must be between r0 and r7"
+#: epiphany-asm.c:115
+msgid "register name used as immediate value"
msgstr ""
-#: fr30-asm.c:97
-msgid "Register must be between r8 and r15"
+#. Don't treat "mov ip,ip" as a move-immediate.
+#: epiphany-asm.c:178 epiphany-asm.c:234
+msgid "register source in immediate move"
msgstr ""
-#: fr30-asm.c:116 m32c-asm.c:910
-msgid "Register list is not valid"
+#: epiphany-asm.c:187
+msgid "byte relocation unsupported"
+msgstr ""
+
+#. -- assembler routines inserted here.
+#. -- asm.c
+#: epiphany-asm.c:193 frv-asm.c:972 iq2000-asm.c:56 lm32-asm.c:95
+#: lm32-asm.c:127 lm32-asm.c:157 lm32-asm.c:187 lm32-asm.c:217 lm32-asm.c:247
+#: m32c-asm.c:140 m32c-asm.c:235 m32c-asm.c:276 m32c-asm.c:334 m32c-asm.c:355
+#: m32r-asm.c:53 mep-asm.c:241 mep-asm.c:259 mep-asm.c:274 mep-asm.c:289
+#: mep-asm.c:301 openrisc-asm.c:54
+msgid "missing `)'"
msgstr ""
-#: fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511 iq2000-asm.c:459
-#: lm32-asm.c:349 m32c-asm.c:1584 m32r-asm.c:328 mep-asm.c:1286 mt-asm.c:595
-#: openrisc-asm.c:241 xc16x-asm.c:376 xstormy16-asm.c:276
+#: epiphany-asm.c:270
+msgid "ABORT: unknown operand"
+msgstr ""
+
+#: epiphany-asm.c:296
+msgid "Not a pc-relative address."
+msgstr ""
+
+#: epiphany-asm.c:455 fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511
+#: iq2000-asm.c:459 lm32-asm.c:349 m32c-asm.c:1584 m32r-asm.c:328
+#: mep-asm.c:1286 mt-asm.c:595 openrisc-asm.c:241 xc16x-asm.c:376
+#: xstormy16-asm.c:276
#, c-format
msgid "Unrecognized field %d while parsing.\n"
msgstr ""
-#: fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562 iq2000-asm.c:510
-#: lm32-asm.c:400 m32c-asm.c:1635 m32r-asm.c:379 mep-asm.c:1337 mt-asm.c:646
-#: openrisc-asm.c:292 xc16x-asm.c:427 xstormy16-asm.c:327
+#: epiphany-asm.c:506 fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562
+#: iq2000-asm.c:510 lm32-asm.c:400 m32c-asm.c:1635 m32r-asm.c:379
+#: mep-asm.c:1337 mt-asm.c:646 openrisc-asm.c:292 xc16x-asm.c:427
+#: xstormy16-asm.c:327
msgid "missing mnemonic in syntax string"
msgstr ""
#. We couldn't parse it.
+#: epiphany-asm.c:641 epiphany-asm.c:645 epiphany-asm.c:734 epiphany-asm.c:841
#: fr30-asm.c:496 fr30-asm.c:500 fr30-asm.c:589 fr30-asm.c:696 frv-asm.c:1449
#: frv-asm.c:1453 frv-asm.c:1542 frv-asm.c:1649 ip2k-asm.c:697 ip2k-asm.c:701
#: ip2k-asm.c:790 ip2k-asm.c:897 iq2000-asm.c:645 iq2000-asm.c:649
msgid "unrecognized instruction"
msgstr ""
-#: fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744 iq2000-asm.c:692
-#: lm32-asm.c:582 m32c-asm.c:1817 m32r-asm.c:561 mep-asm.c:1519 mt-asm.c:828
-#: openrisc-asm.c:474 xc16x-asm.c:609 xstormy16-asm.c:509
+#: epiphany-asm.c:688 fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744
+#: iq2000-asm.c:692 lm32-asm.c:582 m32c-asm.c:1817 m32r-asm.c:561
+#: mep-asm.c:1519 mt-asm.c:828 openrisc-asm.c:474 xc16x-asm.c:609
+#: xstormy16-asm.c:509
#, c-format
msgid "syntax error (expected char `%c', found `%c')"
msgstr ""
-#: fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754 iq2000-asm.c:702
-#: lm32-asm.c:592 m32c-asm.c:1827 m32r-asm.c:571 mep-asm.c:1529 mt-asm.c:838
-#: openrisc-asm.c:484 xc16x-asm.c:619 xstormy16-asm.c:519
+#: epiphany-asm.c:698 fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754
+#: iq2000-asm.c:702 lm32-asm.c:592 m32c-asm.c:1827 m32r-asm.c:571
+#: mep-asm.c:1529 mt-asm.c:838 openrisc-asm.c:484 xc16x-asm.c:619
+#: xstormy16-asm.c:519
#, c-format
msgid "syntax error (expected char `%c', found end of instruction)"
msgstr ""
-#: fr30-asm.c:583 frv-asm.c:1536 ip2k-asm.c:784 iq2000-asm.c:732
-#: lm32-asm.c:622 m32c-asm.c:1857 m32r-asm.c:601 mep-asm.c:1559 mt-asm.c:868
-#: openrisc-asm.c:514 xc16x-asm.c:649 xstormy16-asm.c:549
+#: epiphany-asm.c:728 fr30-asm.c:583 frv-asm.c:1536 ip2k-asm.c:784
+#: iq2000-asm.c:732 lm32-asm.c:622 m32c-asm.c:1857 m32r-asm.c:601
+#: mep-asm.c:1559 mt-asm.c:868 openrisc-asm.c:514 xc16x-asm.c:649
+#: xstormy16-asm.c:549
msgid "junk at end of line"
msgstr ""
-#: fr30-asm.c:695 frv-asm.c:1648 ip2k-asm.c:896 iq2000-asm.c:844
-#: lm32-asm.c:734 m32c-asm.c:1969 m32r-asm.c:713 mep-asm.c:1671 mt-asm.c:980
-#: openrisc-asm.c:626 xc16x-asm.c:761 xstormy16-asm.c:661
+#: epiphany-asm.c:840 fr30-asm.c:695 frv-asm.c:1648 ip2k-asm.c:896
+#: iq2000-asm.c:844 lm32-asm.c:734 m32c-asm.c:1969 m32r-asm.c:713
+#: mep-asm.c:1671 mt-asm.c:980 openrisc-asm.c:626 xc16x-asm.c:761
+#: xstormy16-asm.c:661
msgid "unrecognized form of instruction"
msgstr ""
-#: fr30-asm.c:709 frv-asm.c:1662 ip2k-asm.c:910 iq2000-asm.c:858
-#: lm32-asm.c:748 m32c-asm.c:1983 m32r-asm.c:727 mep-asm.c:1685 mt-asm.c:994
-#: openrisc-asm.c:640 xc16x-asm.c:775 xstormy16-asm.c:675
+#: epiphany-asm.c:854 fr30-asm.c:709 frv-asm.c:1662 ip2k-asm.c:910
+#: iq2000-asm.c:858 lm32-asm.c:748 m32c-asm.c:1983 m32r-asm.c:727
+#: mep-asm.c:1685 mt-asm.c:994 openrisc-asm.c:640 xc16x-asm.c:775
+#: xstormy16-asm.c:675
#, c-format
msgid "bad instruction `%.50s...'"
msgstr ""
-#: fr30-asm.c:712 frv-asm.c:1665 ip2k-asm.c:913 iq2000-asm.c:861
-#: lm32-asm.c:751 m32c-asm.c:1986 m32r-asm.c:730 mep-asm.c:1688 mt-asm.c:997
-#: openrisc-asm.c:643 xc16x-asm.c:778 xstormy16-asm.c:678
+#: epiphany-asm.c:857 fr30-asm.c:712 frv-asm.c:1665 ip2k-asm.c:913
+#: iq2000-asm.c:861 lm32-asm.c:751 m32c-asm.c:1986 m32r-asm.c:730
+#: mep-asm.c:1688 mt-asm.c:997 openrisc-asm.c:643 xc16x-asm.c:778
+#: xstormy16-asm.c:678
#, c-format
msgid "bad instruction `%.50s'"
msgstr ""
#. Default text to print if an instruction isn't recognized.
-#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 lm32-dis.c:41
-#: m32c-dis.c:41 m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:277 mt-dis.c:41
-#: openrisc-dis.c:41 xc16x-dis.c:41 xstormy16-dis.c:41
+#: epiphany-dis.c:41 fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41
+#: lm32-dis.c:41 m32c-dis.c:41 m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:277
+#: mt-dis.c:41 openrisc-dis.c:41 xc16x-dis.c:41 xstormy16-dis.c:41
msgid "*unknown*"
msgstr ""
-#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 lm32-dis.c:147
-#: m32c-dis.c:891 m32r-dis.c:279 mep-dis.c:1187 mt-dis.c:290
-#: openrisc-dis.c:135 xc16x-dis.c:420 xstormy16-dis.c:168
+#: epiphany-dis.c:277 fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288
+#: iq2000-dis.c:189 lm32-dis.c:147 m32c-dis.c:891 m32r-dis.c:279
+#: mep-dis.c:1187 mt-dis.c:290 openrisc-dis.c:135 xc16x-dis.c:420
+#: xstormy16-dis.c:168
#, c-format
msgid "Unrecognized field %d while printing insn.\n"
msgstr ""
-#: fr30-ibld.c:164 frv-ibld.c:164 ip2k-ibld.c:164 iq2000-ibld.c:164
-#: lm32-ibld.c:164 m32c-ibld.c:164 m32r-ibld.c:164 mep-ibld.c:164
-#: mt-ibld.c:164 openrisc-ibld.c:164 xc16x-ibld.c:164 xstormy16-ibld.c:164
+#: epiphany-ibld.c:164 fr30-ibld.c:164 frv-ibld.c:164 ip2k-ibld.c:164
+#: iq2000-ibld.c:164 lm32-ibld.c:164 m32c-ibld.c:164 m32r-ibld.c:164
+#: mep-ibld.c:164 mt-ibld.c:164 openrisc-ibld.c:164 xc16x-ibld.c:164
+#: xstormy16-ibld.c:164
#, c-format
msgid "operand out of range (%ld not between %ld and %lu)"
msgstr ""
-#: fr30-ibld.c:185 frv-ibld.c:185 ip2k-ibld.c:185 iq2000-ibld.c:185
-#: lm32-ibld.c:185 m32c-ibld.c:185 m32r-ibld.c:185 mep-ibld.c:185
-#: mt-ibld.c:185 openrisc-ibld.c:185 xc16x-ibld.c:185 xstormy16-ibld.c:185
+#: epiphany-ibld.c:185 fr30-ibld.c:185 frv-ibld.c:185 ip2k-ibld.c:185
+#: iq2000-ibld.c:185 lm32-ibld.c:185 m32c-ibld.c:185 m32r-ibld.c:185
+#: mep-ibld.c:185 mt-ibld.c:185 openrisc-ibld.c:185 xc16x-ibld.c:185
+#: xstormy16-ibld.c:185
#, c-format
msgid "operand out of range (0x%lx not between 0 and 0x%lx)"
msgstr ""
-#: fr30-ibld.c:727 frv-ibld.c:853 ip2k-ibld.c:604 iq2000-ibld.c:710
-#: lm32-ibld.c:631 m32c-ibld.c:1728 m32r-ibld.c:662 mep-ibld.c:1205
-#: mt-ibld.c:746 openrisc-ibld.c:630 xc16x-ibld.c:749 xstormy16-ibld.c:675
+#: epiphany-ibld.c:872 fr30-ibld.c:727 frv-ibld.c:853 ip2k-ibld.c:604
+#: iq2000-ibld.c:710 lm32-ibld.c:631 m32c-ibld.c:1728 m32r-ibld.c:662
+#: mep-ibld.c:1205 mt-ibld.c:746 openrisc-ibld.c:630 xc16x-ibld.c:749
+#: xstormy16-ibld.c:675
#, c-format
msgid "Unrecognized field %d while building insn.\n"
msgstr ""
-#: fr30-ibld.c:932 frv-ibld.c:1170 ip2k-ibld.c:679 iq2000-ibld.c:885
-#: lm32-ibld.c:735 m32c-ibld.c:2889 m32r-ibld.c:799 mep-ibld.c:1804
-#: mt-ibld.c:966 openrisc-ibld.c:730 xc16x-ibld.c:969 xstormy16-ibld.c:821
+#: epiphany-ibld.c:1166 fr30-ibld.c:932 frv-ibld.c:1170 ip2k-ibld.c:679
+#: iq2000-ibld.c:885 lm32-ibld.c:735 m32c-ibld.c:2889 m32r-ibld.c:799
+#: mep-ibld.c:1804 mt-ibld.c:966 openrisc-ibld.c:730 xc16x-ibld.c:969
+#: xstormy16-ibld.c:821
#, c-format
msgid "Unrecognized field %d while decoding insn.\n"
msgstr ""
-#: fr30-ibld.c:1078 frv-ibld.c:1448 ip2k-ibld.c:753 iq2000-ibld.c:1016
-#: lm32-ibld.c:824 m32c-ibld.c:3506 m32r-ibld.c:912 mep-ibld.c:2274
-#: mt-ibld.c:1166 openrisc-ibld.c:807 xc16x-ibld.c:1190 xstormy16-ibld.c:931
+#: epiphany-ibld.c:1309 fr30-ibld.c:1078 frv-ibld.c:1448 ip2k-ibld.c:753
+#: iq2000-ibld.c:1016 lm32-ibld.c:824 m32c-ibld.c:3506 m32r-ibld.c:912
+#: mep-ibld.c:2274 mt-ibld.c:1166 openrisc-ibld.c:807 xc16x-ibld.c:1190
+#: xstormy16-ibld.c:931
#, c-format
msgid "Unrecognized field %d while getting int operand.\n"
msgstr ""
-#: fr30-ibld.c:1206 frv-ibld.c:1708 ip2k-ibld.c:809 iq2000-ibld.c:1129
-#: lm32-ibld.c:895 m32c-ibld.c:4105 m32r-ibld.c:1007 mep-ibld.c:2726
-#: mt-ibld.c:1348 openrisc-ibld.c:866 xc16x-ibld.c:1393 xstormy16-ibld.c:1023
+#: epiphany-ibld.c:1434 fr30-ibld.c:1206 frv-ibld.c:1708 ip2k-ibld.c:809
+#: iq2000-ibld.c:1129 lm32-ibld.c:895 m32c-ibld.c:4105 m32r-ibld.c:1007
+#: mep-ibld.c:2726 mt-ibld.c:1348 openrisc-ibld.c:866 xc16x-ibld.c:1393
+#: xstormy16-ibld.c:1023
#, c-format
msgid "Unrecognized field %d while getting vma operand.\n"
msgstr ""
-#: fr30-ibld.c:1337 frv-ibld.c:1975 ip2k-ibld.c:868 iq2000-ibld.c:1249
-#: lm32-ibld.c:973 m32c-ibld.c:4692 m32r-ibld.c:1108 mep-ibld.c:3139
-#: mt-ibld.c:1537 openrisc-ibld.c:932 xc16x-ibld.c:1597 xstormy16-ibld.c:1122
+#: epiphany-ibld.c:1566 fr30-ibld.c:1337 frv-ibld.c:1975 ip2k-ibld.c:868
+#: iq2000-ibld.c:1249 lm32-ibld.c:973 m32c-ibld.c:4692 m32r-ibld.c:1108
+#: mep-ibld.c:3139 mt-ibld.c:1537 openrisc-ibld.c:932 xc16x-ibld.c:1597
+#: xstormy16-ibld.c:1122
#, c-format
msgid "Unrecognized field %d while setting int operand.\n"
msgstr ""
-#: fr30-ibld.c:1458 frv-ibld.c:2232 ip2k-ibld.c:917 iq2000-ibld.c:1359
-#: lm32-ibld.c:1041 m32c-ibld.c:5269 m32r-ibld.c:1199 mep-ibld.c:3542
-#: mt-ibld.c:1716 openrisc-ibld.c:988 xc16x-ibld.c:1791 xstormy16-ibld.c:1211
+#: epiphany-ibld.c:1688 fr30-ibld.c:1458 frv-ibld.c:2232 ip2k-ibld.c:917
+#: iq2000-ibld.c:1359 lm32-ibld.c:1041 m32c-ibld.c:5269 m32r-ibld.c:1199
+#: mep-ibld.c:3542 mt-ibld.c:1716 openrisc-ibld.c:988 xc16x-ibld.c:1791
+#: xstormy16-ibld.c:1211
#, c-format
msgid "Unrecognized field %d while setting vma operand.\n"
msgstr ""
+#: fr30-asm.c:93 m32c-asm.c:872 m32c-asm.c:879
+msgid "Register number is not valid"
+msgstr ""
+
+#: fr30-asm.c:95
+msgid "Register must be between r0 and r7"
+msgstr ""
+
+#: fr30-asm.c:97
+msgid "Register must be between r8 and r15"
+msgstr ""
+
+#: fr30-asm.c:116 m32c-asm.c:910
+msgid "Register list is not valid"
+msgstr ""
+
#: frv-asm.c:608
msgid "missing `]'"
msgstr ""
msgid "register number must be even"
msgstr ""
-#. -- assembler routines inserted here.
-#. -- asm.c
-#: frv-asm.c:972 iq2000-asm.c:56 lm32-asm.c:95 lm32-asm.c:127 lm32-asm.c:157
-#: lm32-asm.c:187 lm32-asm.c:217 lm32-asm.c:247 m32c-asm.c:140 m32c-asm.c:235
-#: m32c-asm.c:276 m32c-asm.c:334 m32c-asm.c:355 m32r-asm.c:53 mep-asm.c:241
-#: mep-asm.c:259 mep-asm.c:274 mep-asm.c:289 mep-asm.c:301 openrisc-asm.c:54
-msgid "missing `)'"
-msgstr ""
-
#: h8300-dis.c:314
#, c-format
msgid "Hmmmm 0x%x"
msgid "%02x\t\t*unknown*"
msgstr ""
-#: i386-dis.c:10774
+#: i386-dis.c:10504
msgid "<internal disassembler error>"
msgstr ""
-#: i386-dis.c:11071
+#: i386-dis.c:10801
#, c-format
msgid ""
"\n"
"with the -M switch (multiple options should be separated by commas):\n"
msgstr ""
-#: i386-dis.c:11075
+#: i386-dis.c:10805
#, c-format
msgid " x86-64 Disassemble in 64bit mode\n"
msgstr ""
-#: i386-dis.c:11076
+#: i386-dis.c:10806
#, c-format
msgid " i386 Disassemble in 32bit mode\n"
msgstr ""
-#: i386-dis.c:11077
+#: i386-dis.c:10807
#, c-format
msgid " i8086 Disassemble in 16bit mode\n"
msgstr ""
-#: i386-dis.c:11078
+#: i386-dis.c:10808
#, c-format
msgid " att Display instruction in AT&T syntax\n"
msgstr ""
-#: i386-dis.c:11079
+#: i386-dis.c:10809
#, c-format
msgid " intel Display instruction in Intel syntax\n"
msgstr ""
-#: i386-dis.c:11080
+#: i386-dis.c:10810
#, c-format
msgid ""
" att-mnemonic\n"
" Display instruction in AT&T mnemonic\n"
msgstr ""
-#: i386-dis.c:11082
+#: i386-dis.c:10812
#, c-format
msgid ""
" intel-mnemonic\n"
" Display instruction in Intel mnemonic\n"
msgstr ""
-#: i386-dis.c:11084
+#: i386-dis.c:10814
#, c-format
msgid " addr64 Assume 64bit address size\n"
msgstr ""
-#: i386-dis.c:11085
+#: i386-dis.c:10815
#, c-format
msgid " addr32 Assume 32bit address size\n"
msgstr ""
-#: i386-dis.c:11086
+#: i386-dis.c:10816
#, c-format
msgid " addr16 Assume 16bit address size\n"
msgstr ""
-#: i386-dis.c:11087
+#: i386-dis.c:10817
#, c-format
msgid " data32 Assume 32bit data size\n"
msgstr ""
-#: i386-dis.c:11088
+#: i386-dis.c:10818
#, c-format
msgid " data16 Assume 16bit data size\n"
msgstr ""
-#: i386-dis.c:11089
+#: i386-dis.c:10819
#, c-format
msgid " suffix Always display instruction suffix in AT&T syntax\n"
msgstr ""
-#: i386-gen.c:467 ia64-gen.c:307
+#: i386-gen.c:483 ia64-gen.c:307
#, c-format
msgid "%s: Error: "
msgstr ""
-#: i386-gen.c:599
+#: i386-gen.c:615
#, c-format
msgid "%s: %d: Unknown bitfield: %s\n"
msgstr ""
-#: i386-gen.c:601
+#: i386-gen.c:617
#, c-format
msgid "Unknown bitfield: %s\n"
msgstr ""
-#: i386-gen.c:657
+#: i386-gen.c:673
#, c-format
msgid "%s: %d: Missing `)' in bitfield: %s\n"
msgstr ""
-#: i386-gen.c:922
+#: i386-gen.c:938
#, c-format
msgid "can't find i386-opc.tbl for reading, errno = %s\n"
msgstr ""
-#: i386-gen.c:1053
+#: i386-gen.c:1069
#, c-format
msgid "can't find i386-reg.tbl for reading, errno = %s\n"
msgstr ""
-#: i386-gen.c:1130
+#: i386-gen.c:1146
#, c-format
msgid "can't create i386-init.h, errno = %s\n"
msgstr ""
-#: i386-gen.c:1219 ia64-gen.c:2820
+#: i386-gen.c:1235 ia64-gen.c:2820
#, c-format
msgid "unable to change directory to \"%s\", errno = %s\n"
msgstr ""
-#: i386-gen.c:1226
+#: i386-gen.c:1242
#, c-format
msgid "%d unused bits in i386_cpu_flags.\n"
msgstr ""
-#: i386-gen.c:1233
+#: i386-gen.c:1249
#, c-format
msgid "%d unused bits in i386_operand_type.\n"
msgstr ""
-#: i386-gen.c:1247
+#: i386-gen.c:1263
#, c-format
msgid "can't create i386-tbl.h, errno = %s\n"
msgstr ""
msgid "Value is not aligned enough"
msgstr ""
-#: mips-dis.c:845
+#: mips-dis.c:947
msgid "# internal error, incomplete extension sequence (+)"
msgstr ""
-#: mips-dis.c:1011
+#: mips-dis.c:1113
#, c-format
msgid "# internal error, undefined extension sequence (+%c)"
msgstr ""
-#: mips-dis.c:1371
+#: mips-dis.c:1485
#, c-format
msgid "# internal error, undefined modifier (%c)"
msgstr ""
-#: mips-dis.c:1975
+#: mips-dis.c:2089
#, c-format
msgid "# internal disassembler error, unrecognised modifier (%c)"
msgstr ""
-#: mips-dis.c:2213
+#: mips-dis.c:2664
+#, c-format
+msgid "# internal disassembler error, unrecognized modifier (+%c)"
+msgstr ""
+
+#: mips-dis.c:2894
+#, c-format
+msgid "# internal disassembler error, unrecognized modifier (m%c)"
+msgstr ""
+
+#: mips-dis.c:2904
+#, c-format
+msgid "# internal disassembler error, unrecognized modifier (%c)"
+msgstr ""
+
+#: mips-dis.c:3052
#, c-format
msgid ""
"\n"
"with the -M switch (multiple options should be separated by commas):\n"
msgstr ""
-#: mips-dis.c:2217
+#: mips-dis.c:3056
#, c-format
msgid ""
"\n"
" Default: based on binary being disassembled.\n"
msgstr ""
-#: mips-dis.c:2221
+#: mips-dis.c:3060
#, c-format
msgid ""
"\n"
" Default: numeric.\n"
msgstr ""
-#: mips-dis.c:2225
+#: mips-dis.c:3064
#, c-format
msgid ""
"\n"
" Default: based on binary being disassembled.\n"
msgstr ""
-#: mips-dis.c:2230
+#: mips-dis.c:3069
#, c-format
msgid ""
"\n"
" Default: based on binary being disassembled.\n"
msgstr ""
-#: mips-dis.c:2235
+#: mips-dis.c:3074
#, c-format
msgid ""
"\n"
" specified ABI.\n"
msgstr ""
-#: mips-dis.c:2239
+#: mips-dis.c:3078
#, c-format
msgid ""
"\n"
" specified architecture.\n"
msgstr ""
-#: mips-dis.c:2243
+#: mips-dis.c:3082
#, c-format
msgid ""
"\n"
" "
msgstr ""
-#: mips-dis.c:2248 mips-dis.c:2256 mips-dis.c:2258
+#: mips-dis.c:3087 mips-dis.c:3095 mips-dis.c:3097
#, c-format
msgid "\n"
msgstr ""
-#: mips-dis.c:2250
+#: mips-dis.c:3089
#, c-format
msgid ""
"\n"
"the -M switch:\n"
msgstr ""
-#: ppc-opc.c:879 ppc-opc.c:907
+#: ppc-opc.c:906 ppc-opc.c:936
msgid "invalid conditional option"
msgstr ""
-#: ppc-opc.c:909
+#: ppc-opc.c:908 ppc-opc.c:938
+msgid "invalid counter access"
+msgstr ""
+
+#: ppc-opc.c:940
msgid "attempt to set y bit when using + or - modifier"
msgstr ""
-#: ppc-opc.c:941
+#: ppc-opc.c:972
msgid "invalid mask field"
msgstr ""
-#: ppc-opc.c:967
+#: ppc-opc.c:998
msgid "ignoring invalid mfcr mask"
msgstr ""
-#: ppc-opc.c:1017 ppc-opc.c:1052
+#: ppc-opc.c:1048 ppc-opc.c:1083
msgid "illegal bitmask"
msgstr ""
-#: ppc-opc.c:1172
+#: ppc-opc.c:1170
+msgid "address register in load range"
+msgstr ""
+
+#: ppc-opc.c:1223
msgid "index register in load range"
msgstr ""
-#: ppc-opc.c:1188
+#: ppc-opc.c:1239 ppc-opc.c:1295
msgid "source and target register operands must be different"
msgstr ""
-#: ppc-opc.c:1203
+#: ppc-opc.c:1254
msgid "invalid register operand when updating"
msgstr ""
-#: ppc-opc.c:1282
+#: ppc-opc.c:1349
msgid "invalid sprg number"
msgstr ""
-#: ppc-opc.c:1452
+#: ppc-opc.c:1519
msgid "invalid constant"
msgstr ""
msgid "<illegal instruction>"
msgstr ""
-#: sparc-dis.c:283
+#: sparc-dis.c:285
#, c-format
msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
msgstr ""
-#: sparc-dis.c:294
+#: sparc-dis.c:296
#, c-format
msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
msgstr ""
-#: sparc-dis.c:344
+#: sparc-dis.c:346
#, c-format
msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
msgstr ""
#. Mark as non-valid instruction.
-#: sparc-dis.c:1015
+#: sparc-dis.c:1028
msgid "unknown"
msgstr ""
projects / binutils-gdb.git / commitdiff