arch: Make all register index flattening const

This patch makes all the register index flattening methods const for
all the ISAs. As part of this, readMiscRegNoEffect for ARM is also
made const.

diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index 35a26c108c42c3a88934412dcfc521773ef947ba..36515b520e1029fecfb88965ea46dba9e617229a 100644 (file)
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -96,26 +96,26 @@ namespace AlphaISA
         void unserialize(Checkpoint *cp, const std::string &section);
 
         int
-        flattenIntIndex(int reg)
+        flattenIntIndex(int reg) const
         {
             return reg;
         }
 
         int
-        flattenFloatIndex(int reg)
+        flattenFloatIndex(int reg) const
         {
             return reg;
         }
 
         // dummy
         int
-        flattenCCIndex(int reg)
+        flattenCCIndex(int reg) const
         {
             return reg;
         }
 
         int
-        flattenMiscIndex(int reg)
+        flattenMiscIndex(int reg) const
         {
             return reg;
         }

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 2b67e6cf611fc0c7e2226ec3a8332d95b39199e3..86be2803de594f561f9ca40327df34c1178ac6f0 100644 (file)
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -177,7 +177,7 @@ ISA::clear()
 }
 
 MiscReg
-ISA::readMiscRegNoEffect(int misc_reg)
+ISA::readMiscRegNoEffect(int misc_reg) const
 {
     assert(misc_reg < NumMiscRegs);
 

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 6fd57549ad96b22e149b40c076b99400bc648093..c747fc7704eb5b7114e587f3d55b87137f5828ed 100644 (file)
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -96,13 +96,13 @@ namespace ArmISA
       public:
         void clear();
 
-        MiscReg readMiscRegNoEffect(int misc_reg);
+        MiscReg readMiscRegNoEffect(int misc_reg) const;
         MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
         void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
         void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
 
         int
-        flattenIntIndex(int reg)
+        flattenIntIndex(int reg) const
         {
             assert(reg >= 0);
             if (reg < NUM_ARCH_INTREGS) {
@@ -135,20 +135,20 @@ namespace ArmISA
         }
 
         int
-        flattenFloatIndex(int reg)
+        flattenFloatIndex(int reg) const
         {
             return reg;
         }
 
         // dummy
         int
-        flattenCCIndex(int reg)
+        flattenCCIndex(int reg) const
         {
             return reg;
         }
 
         int
-        flattenMiscIndex(int reg)
+        flattenMiscIndex(int reg) const
         {
             if (reg == MISCREG_SPSR) {
                 int spsr_idx = NUM_MISCREGS;

diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index eddf75272915ed17919eb7f4afe2fa04e11bdcfc..d361d43711792c778a518038dcefd2863fdc4ab8 100644 (file)
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -167,26 +167,26 @@ namespace MipsISA
         ISA(Params *p);
 
         int
-        flattenIntIndex(int reg)
+        flattenIntIndex(int reg) const
         {
             return reg;
         }
 
         int
-        flattenFloatIndex(int reg)
+        flattenFloatIndex(int reg) const
         {
             return reg;
         }
 
         // dummy
         int
-        flattenCCIndex(int reg)
+        flattenCCIndex(int reg) const
         {
             return reg;
         }
 
         int
-        flattenMiscIndex(int reg)
+        flattenMiscIndex(int reg) const
         {
             return reg;
         }

diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 028142b5077cff5ebac488ba34bee9767adca8a8..d19410037d28b5efdf10bb0093f937d09b4fa2b6 100644 (file)
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -87,26 +87,26 @@ class ISA : public SimObject
     }
 
     int
-    flattenIntIndex(int reg)
+    flattenIntIndex(int reg) const
     {
         return reg;
     }
 
     int
-    flattenFloatIndex(int reg)
+    flattenFloatIndex(int reg) const
     {
         return reg;
     }
 
     // dummy
     int
-    flattenCCIndex(int reg)
+    flattenCCIndex(int reg) const
     {
         return reg;
     }
 
     int
-    flattenMiscIndex(int reg)
+    flattenMiscIndex(int reg) const
     {
         return reg;
     }

diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 31cb09c7eb42be813a534fa5c8c9b2b5602f00b1..536deb69c1b56d3393ccffeeace91c42c8d2f5d4 100644 (file)
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -191,7 +191,7 @@ class ISA : public SimObject
             ThreadContext *tc);
 
     int
-    flattenIntIndex(int reg)
+    flattenIntIndex(int reg) const
     {
         assert(reg < TotalInstIntRegs);
         RegIndex flatIndex = intRegMap[reg];
@@ -200,20 +200,20 @@ class ISA : public SimObject
     }
 
     int
-    flattenFloatIndex(int reg)
+    flattenFloatIndex(int reg) const
     {
         return reg;
     }
 
     // dummy
     int
-    flattenCCIndex(int reg)
+    flattenCCIndex(int reg) const
     {
         return reg;
     }
 
     int
-    flattenMiscIndex(int reg)
+    flattenMiscIndex(int reg) const
     {
         return reg;
     }

diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 14c8e98c9ff8901c5d830039611f4e74d0ac3f05..3ca771c61cdfda1771b2565ba1b7c0a42f308ca8 100644 (file)
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -70,13 +70,13 @@ namespace X86ISA
         void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
 
         int
-        flattenIntIndex(int reg)
+        flattenIntIndex(int reg) const
         {
             return reg & ~IntFoldBit;
         }
 
         int
-        flattenFloatIndex(int reg)
+        flattenFloatIndex(int reg) const
         {
             if (reg >= NUM_FLOATREGS) {
                 reg = FLOATREG_STACK(reg - NUM_FLOATREGS,
@@ -86,13 +86,13 @@ namespace X86ISA
         }
 
         int
-        flattenCCIndex(int reg)
+        flattenCCIndex(int reg) const
         {
             return reg;
         }
 
         int
-        flattenMiscIndex(int reg)
+        flattenMiscIndex(int reg) const
         {
             return reg;
         }