add /pi to LD/ST, temporarily. lose dz/sz replace with zz to compensate

this is related to bug #1047 and #1083

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index 54a4ead03664d10a539639fd88d68094c24c687d..0fd781a75fc95c5521f27e5f97467ccce35c0c2d 100644 (file)
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -2264,16 +2264,20 @@ class LDSTIdxBaseRM(PredicateWidthBaseRM):
     pass
 
 
-class LDSTIdxSimpleRM(SEABaseRM, ZZCombinedBaseRM, LDSTIdxBaseRM):
+class LDSTIdxSimpleRM(SEABaseRM, ZZBaseRM, LDSTIdxBaseRM):
     """ld/st index: simple mode (includes element-strided and Signed-EA)"""
+    pi: BaseRM.mode[2]  # Post-Increment Mode
     els: BaseRM.mode[0]
-    SEA: BaseRM.mode[2]
+    SEA: BaseRM.mode[4]
+    zz: BaseRM.mode[3]
     dz: BaseRM.mode[3]
-    sz: BaseRM.mode[4]
+    sz: BaseRM.mode[3]
 
     def specifiers(self, record):
         if self.els:
             yield "els"
+        if self.pi:
+            yield "pi"
 
         yield from super().specifiers(record=record)
 
@@ -3071,14 +3075,13 @@ class SpecifierPI(Specifier):
         if desc != "pi":
             return None
 
-        if record.svp64.mode is not _SVMode.LDST_IMM:
-            raise ValueError("only ld/st imm mode supported")
+        if record.svp64.mode not in [_SVMode.LDST_IMM, _SVMode.LDST_IDX]:
+            raise ValueError("only ld/st imm/idx mode supported")
 
         return cls(record=record)
 
     def assemble(self, insn):
         selector = insn.select(record=self.record)
-        selector.mode[1] = 0b0
         selector.mode[2] = 0b1
         selector.pi = 0b1
 
@@ -3119,6 +3122,7 @@ class SpecifierVLi(Specifier):
 
     def assemble(self, insn):
         selector = insn.select(record=self.record)
+        selector.mode[1] = 1
         selector.VLi = 1
 
 

diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py
index f92a4edd7c0c412a4604edbce2f214e27f4933d9..eeeede53e864787b70689b25be4e27e5f5bb9550 100644 (file)
--- a/src/openpower/decoder/power_svp64_rm.py
+++ b/src/openpower/decoder/power_svp64_rm.py
@@ -59,16 +59,14 @@ LD/ST immed:
 
 | 0 | 1 |  2  |  3   4  |  description               |
 |---|---| --- |---------|--------------------------- |
-| 0 | 0 | 0   |  zz els | simple mode                |
-| 0 | 0 | 1   | PI  LF  | post-increment and Fault-First  |
-| 1 | 0 |   N | zz  els |  sat mode: N=0/1 u/s       |
+|els| 0 | PI  |  zz LF | simple mode                |
 |VLi| 1 | inv | CR-bit  | ffirst CR sel             |
 
 LD/ST indexed:
 
 | 0 | 1 |  2  |  3   4  |  description               |
 |---|---| --- |---------|--------------------------- |
-|els| 0 | SEA |  dz  sz | simple mode        |
+|els| 0 | PI  |  zz SEA | simple mode        |
 |VLi| 1 | inv | CR-bit  | ffirst CR sel        |
 
 Arithmetic:

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 56828cb481bfe788ea39f154bab000f0a512eda6..f0a0542fae31ac8fc3cc335ef04faec87fbe2780 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -300,6 +300,7 @@ class SVSTATETestCase(unittest.TestCase):
     def test_18_sea(self):
         expected = [
                     "sv.ldux/sea 5,6,7",
+                    "sv.ldux/pi/sea 5,6,7",
                         ]
         self._do_tst(expected)