cpu: Remove default argument values for the update() method in bpreds.

These defaults are never used. There was an assert in the predictors
until recently which was asserting that one of the arguments didn't
have the default value, I think to verify that the default wasn't used
by accident(?), but it could be used purposefully. That would cause
gem5 to crash and has been removed.

Beyond that, there's no reason to have default values for those
arguments in the first place, so this change removes them. That makes
the code slightly simpler, and avoids them being used by accident.

Additionally, the defalt values of the arguments made the function
signatures inconsistent, even though they were supposed to override
each other.

JIRA: https://gem5.atlassian.net/browse/GEM5-483

Change-Id: I28f8d2048985c12ec9cac018a868a32bfa20dc6c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30375
Reviewed-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/cpu/pred/bpred_unit.hh b/src/cpu/pred/bpred_unit.hh
index c4dbad2b00fec2193472cbb1ddbca5d9874e1d6c..3ca6fa86a8114e066671ec0f1e03553f288c3b26 100644 (file)
--- a/src/cpu/pred/bpred_unit.hh
+++ b/src/cpu/pred/bpred_unit.hh
@@ -177,8 +177,7 @@ class BPredUnit : public SimObject
      */
     virtual void update(ThreadID tid, Addr instPC, bool taken,
                    void *bp_history, bool squashed,
-                   const StaticInstPtr & inst = StaticInst::nullStaticInstPtr,
-                   Addr corrTarget = MaxAddr) = 0;
+                   const StaticInstPtr &inst, Addr corrTarget) = 0;
     /**
      * Updates the BTB with the target of a branch.
      * @param inst_PC The branch's PC that will be updated.

diff --git a/src/cpu/pred/ltage.hh b/src/cpu/pred/ltage.hh
index 53081dae4180414d5034ee0236023314881fe0e3..0bbac81d15c4d02ef391e670a33d431647db93e3 100644 (file)
--- a/src/cpu/pred/ltage.hh
+++ b/src/cpu/pred/ltage.hh
@@ -66,7 +66,7 @@ class LTAGE : public TAGE
     void squash(ThreadID tid, void *bp_history) override;
     void update(ThreadID tid, Addr branch_addr, bool taken, void *bp_history,
                 bool squashed, const StaticInstPtr & inst,
-                Addr corrTarget = MaxAddr) override;
+                Addr corrTarget) override;
 
     void init() override;
     virtual void regStats() override;

diff --git a/src/cpu/pred/multiperspective_perceptron.hh b/src/cpu/pred/multiperspective_perceptron.hh
index 9d4503244355268a5f8d8652f5c881f5d1b4ae6a..c225aa4c338d63b379eb81ed20fc2e7e65840ee4 100644 (file)
--- a/src/cpu/pred/multiperspective_perceptron.hh
+++ b/src/cpu/pred/multiperspective_perceptron.hh
@@ -1029,7 +1029,7 @@ class MultiperspectivePerceptron : public BPredUnit
     void update(ThreadID tid, Addr instPC, bool taken,
             void *bp_history, bool squashed,
             const StaticInstPtr & inst,
-            Addr corrTarget = MaxAddr) override;
+            Addr corrTarget) override;
     void btbUpdate(ThreadID tid, Addr branch_addr, void* &bp_history) override;
 };
 #endif//__CPU_PRED_MULTIPERSPECTIVE_PERCEPTRON_HH__

diff --git a/src/cpu/pred/multiperspective_perceptron_tage.hh b/src/cpu/pred/multiperspective_perceptron_tage.hh
index b18774e54e165664ab2352b24f26284e48cc749c..366f7b8aae9445ced3a194c18760d6bc1464ff90 100644 (file)
--- a/src/cpu/pred/multiperspective_perceptron_tage.hh
+++ b/src/cpu/pred/multiperspective_perceptron_tage.hh
@@ -228,7 +228,7 @@ class MultiperspectivePerceptronTAGE : public MultiperspectivePerceptron
     void update(ThreadID tid, Addr instPC, bool taken,
             void *bp_history, bool squashed,
             const StaticInstPtr & inst,
-            Addr corrTarget = MaxAddr) override;
+            Addr corrTarget) override;
     void uncondBranch(ThreadID tid, Addr pc, void * &bp_history) override;
     void squash(ThreadID tid, void *bp_history) override;
 

diff --git a/src/cpu/pred/tage.hh b/src/cpu/pred/tage.hh
index a5857177395e304c1f05ffec9c3eb30f2451fcdf..b32ce6746db9b55273354dd16efe932d6290d2d7 100644 (file)
--- a/src/cpu/pred/tage.hh
+++ b/src/cpu/pred/tage.hh
@@ -85,7 +85,7 @@ class TAGE: public BPredUnit
     void btbUpdate(ThreadID tid, Addr branch_addr, void* &bp_history) override;
     void update(ThreadID tid, Addr branch_addr, bool taken, void *bp_history,
                 bool squashed, const StaticInstPtr & inst,
-                Addr corrTarget = MaxAddr) override;
+                Addr corrTarget) override;
     virtual void squash(ThreadID tid, void *bp_history) override;
 };
 

diff --git a/src/cpu/pred/tage_sc_l.hh b/src/cpu/pred/tage_sc_l.hh
index b3629ab7e9b76ff531c9d8908a01e646407a6e48..71f9c1766db39f2c4cfc3392109aebab61b55f6c 100644 (file)
--- a/src/cpu/pred/tage_sc_l.hh
+++ b/src/cpu/pred/tage_sc_l.hh
@@ -158,7 +158,7 @@ class TAGE_SC_L: public LTAGE
 
     void update(ThreadID tid, Addr branch_addr, bool taken, void *bp_history,
                 bool squashed, const StaticInstPtr & inst,
-                Addr corrTarget = MaxAddr) override;
+                Addr corrTarget) override;
 
   protected: