spelling and formatting

diff --git a/openpower/sv/rfc/ls004.mdwn b/openpower/sv/rfc/ls004.mdwn
index 8e6f9cb23f337457631fad5ff2c78b3870786054..e386aa36dca9d3aa5e6b41c72ad2f272948d9565 100644 (file)
--- a/openpower/sv/rfc/ls004.mdwn
+++ b/openpower/sv/rfc/ls004.mdwn
@@ -34,7 +34,7 @@
 ```
     Instructions added
     shadd - Shift and Add
-    shadduw - Shift and Add Unsigned Word 
+    shadduw - Shift and Add Unsigned Word
 ```
 
 **Submitter**: Luke Leighton (Libre-SOC)
@@ -57,7 +57,7 @@
 **Keywords**:
 
 ```
-    GPR, Big-manip, Shift, Arithmetic
+    GPR, Bit-manipulation, Shift, Arithmetic
 ```
 
 **Motivation**
@@ -168,19 +168,19 @@ reduction in binary size is not achieved.
 Pseudocode:
 
 ```
-    shift <- sm + 1                                # Shift is between 1-4
+    shift <- sm + 1                     # Shift is between 1-4
     sum[0:63] <- ((RB) << shift) + (RA) # Shift RB, add RA
-    RT <- sum                                      # Result stored in RT
+    RT <- sum                           # Result stored in RT
 ```
 
 When `sm` is zero, the contents of register RB are multiplied by 2,
 added to the contents of register RA, and the result stored in RT.
 
-`sm` is a 2-bit bitfield, and allows multiplication of RB by 2, 4, 8, 16.
+`sm` is a 2-bit bit-field, and allows multiplication of RB by 2, 4, 8, 16.
 
 Operands RA and RB, and the result RT are all 64-bit, unsigned integers.
 
-**NEED EXAMPLES (not sure how to embedd sm)!!!**
+**NEED EXAMPLES (not sure how to embed sm)!!!**
 Examples:
 
 ```
@@ -190,7 +190,7 @@ Examples:
 
 # Shift-and-Add Unsigned Word
 
-`shadd RT, RA, RB`
+`shadduw RT, RA, RB`
 
 |  0-5  | 6-10 | 11-15 | 16-20 | 21-22 | 23-30 | 31 | Form     |
 |-------|------|-------|-------|-------|-------|----|----------|
@@ -199,16 +199,16 @@ Examples:
 Pseudocode:
 
 ```
-    shift <- sm + 1                                    # Shift is between 1-4
-    n <- (RB)[32:63]                           # Only use lower 32-bits of RB
-    sum[0:63] <- (n << shift) + (RA)    # Shift n, add RA
-    RT <- sum                                      # Result stored in RT
+    shift <- sm + 1                  # Shift is between 1-4
+    n <- (RB)[32:63]                 # Only use lower 32-bits of RB
+    sum[0:63] <- (n << shift) + (RA) # Shift n, add RA
+    RT <- sum                        # Result stored in RT
 ```
 
 When `sm` is zero, the lower word contents of register RB are multiplied by 2,
 added to the contents of register RA, and the result stored in RT.
 
-`sm` is a 2-bit bitfield, and allows multiplication of RB by 2, 4, 8, 16.
+`sm` is a 2-bit bit-field, and allows multiplication of RB by 2, 4, 8, 16.
 
 Operands RA and RB, and the result RT are all 64-bit, unsigned integers.
 
@@ -219,11 +219,10 @@ address. RB is the offset into data structure limited to 32-bit.*
 Examples:
 
 ```
-# 
+#
 shadduw r4, r1, r2
 ```
 
-
 [[!tag opf_rfc]]
 
 # Appendices
@@ -237,4 +236,3 @@ shadduw r4, r1, r2
 |------|------|------|---------|----------|-------------|
 | Z23  | I    | #    | 3.0B    | shadd    | Shift-and-Add |
 | Z23  | I    | #    | 3.0B    | shadduw  | Shift-and-Add Unsigned Word |
-