rtlil: Dump empty connections when whole module is selected.

Without this, empty connections will be always skipped by `dump`, since
they contain no selected wires.  This makes debugging rather confusing.

diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc
index 68521d52d583cd29b1f1c9544b39d7e30f0c625a..1b11de5ec39454df7e759c8a9e111acc1b1984ef 100644 (file)
--- a/backends/rtlil/rtlil_backend.cc
+++ b/backends/rtlil/rtlil_backend.cc
@@ -358,8 +358,8 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
 
                bool first_conn_line = true;
                for (auto it = module->connections().begin(); it != module->connections().end(); ++it) {
-                       bool show_conn = !only_selected;
-                       if (only_selected) {
+                       bool show_conn = !only_selected || design->selected_whole_module(module->name);
+                       if (!show_conn) {
                                RTLIL::SigSpec sigs = it->first;
                                sigs.append(it->second);
                                for (auto &c : sigs.chunks()) {