radeonsi/gfx10: mask DCC tile swizzle by alignment

DCC alignment can be less than the alignment of the main surface. In that
case, the DCC tile swizzle needs to be masked accordingly. Should have no
impact on pre-gfx10.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 262f7e88c93bba1349e88bb27dfdd9f378f950c2..5a8c4acc53a94c45ee248f944c11cccfe8a5de68 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -351,7 +351,9 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
                                assert(base_level_info->mode == RADEON_SURF_MODE_2D);
                        }
 
-                       meta_va |= (uint32_t)tex->surface.tile_swizzle << 8;
+                       unsigned dcc_tile_swizzle = tex->surface.tile_swizzle << 8;
+                       dcc_tile_swizzle &= tex->surface.dcc_alignment - 1;
+                       meta_va |= dcc_tile_swizzle;
                } else if (vi_tc_compat_htile_enabled(tex, first_level)) {
                        meta_va = tex->buffer.gpu_address + tex->htile_offset;
                }

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 0044353fd66e93f029b2879d207f09610079f4c7..685ce697b3a19c1152f1f402426e63ba4b4a7397 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3194,7 +3194,10 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
 
                        cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
                                       tex->dcc_offset) >> 8;
-                       cb_dcc_base |= tex->surface.tile_swizzle;
+
+                       unsigned dcc_tile_swizzle = tex->surface.tile_swizzle;
+                       dcc_tile_swizzle &= (tex->surface.dcc_alignment - 1) >> 8;
+                       cb_dcc_base |= dcc_tile_swizzle;
                }
 
                if (sctx->chip_class >= GFX10) {