More stringent check for flop cells

diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index 643cf0215a77f24bd05c24c3d8164fc669bee6e1..8dd238bc77b76f40fe09673335f3a255c7409546 100644 (file)
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -222,7 +222,8 @@ struct OptMergeWorker
                        return true;
                }
 
-               if (cell1->type.begins_with("$") && conn1.count(ID(Q)) != 0) {
+               if (conn1.count(ID(Q)) != 0 && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") || cell1->type.in("$adff", "$sr", "$ff") ||
+                                       cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH"))) {
                        std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector();
                        std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector();
                        for (size_t i = 0; i < q1.size(); i++)
@@ -324,7 +325,8 @@ struct OptMergeWorker
                                                        module->connect(RTLIL::SigSig(it.second, other_sig));
                                                        assign_map.add(it.second, other_sig);
 
-                                                       if (cell->type.begins_with("$") && it.first == ID(Q)) {
+                                                       if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") || cell->type.in("$adff", "$sr", "$ff") ||
+                                                                               cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH"))) {
                                                                for (auto c : it.second.chunks()) {
                                                                        auto jt = c.wire->attributes.find(ID(init));
                                                                        if (jt == c.wire->attributes.end())