* ppc-opc.c (BH, XLBH_MASK): Define.

	(powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a4bd44d901d7be87d1009a4d991bb87ad0ac6f7b..bf176d7ca8fdf3122ae102bdd0dc37dfb7862682 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2004-06-26  Alan Modra  <amodra@bigpond.net.au>
+
+       * ppc-opc.c (BH, XLBH_MASK): Define.
+       (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
+
 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 
        * i386-dis.c (x_mode): Comment.

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 51fcfe25a6d2cdd9ddefd4ac26281c87b52eef81..f5ff9baf0d4aca291bf38fe741bda731ac065bfb 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -194,8 +194,11 @@ const struct powerpc_operand powerpc_operands[] =
 #define BOE BO + 1
   { 5, 21, insert_boe, extract_boe, 0 },
 
+#define BH BOE + 1
+  { 2, 11, 0, 0, PPC_OPERAND_OPTIONAL },
+
   /* The BT field in an X or XL form instruction.  */
-#define BT BOE + 1
+#define BT BH + 1
   { 5, 21, 0, 0, PPC_OPERAND_CR },
 
   /* The condition register number portion of the BI field in a B form
@@ -1656,6 +1659,9 @@ extract_tbr (unsigned long insn,
 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
 
+/* A mask for branch instructions using the BH field.  */
+#define XLBH_MASK (XL_MASK | (0x1c << 11))
+
 /* An XL_MASK with the BO and BB fields fixed.  */
 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
 
@@ -2883,12 +2889,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4,        { BI } },
 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bclr",    XLLK(19,16,0), XLYBB_MASK,        PPCCOM,         { BO, BI } },
-{ "bclrl",   XLLK(19,16,1), XLYBB_MASK,        PPCCOM,         { BO, BI } },
 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,     { BOE, BI } },
 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,     { BOE, BI } },
 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,     { BOE, BI } },
 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,     { BOE, BI } },
+{ "bclr",    XLLK(19,16,0), XLBH_MASK, PPCCOM,         { BO, BI, BH } },
+{ "bclrl",   XLLK(19,16,1), XLBH_MASK, PPCCOM,         { BO, BI, BH } },
 { "bcr",     XLLK(19,16,0), XLBB_MASK, PWRCOM,         { BO, BI } },
 { "bcrl",    XLLK(19,16,1), XLBB_MASK, PWRCOM,         { BO, BI } },
 { "bclre",   XLLK(19,17,0), XLBB_MASK, BOOKE64,        { BO, BI } },
@@ -3067,12 +3073,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
-{ "bcctr",   XLLK(19,528,0),     XLYBB_MASK,  PPCCOM,  { BO, BI } },
 { "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,  { BOE, BI } },
 { "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,  { BOE, BI } },
-{ "bcctrl",  XLLK(19,528,1),     XLYBB_MASK,  PPCCOM,  { BO, BI } },
 { "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,  { BOE, BI } },
 { "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,  { BOE, BI } },
+{ "bcctr",   XLLK(19,528,0),     XLBH_MASK,   PPCCOM,  { BO, BI, BH } },
+{ "bcctrl",  XLLK(19,528,1),     XLBH_MASK,   PPCCOM,  { BO, BI, BH } },
 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,  { BO, BI } },
 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,  { BO, BI } },
 { "bcctre",  XLLK(19,529,0),     XLYBB_MASK,  BOOKE64, { BO, BI } },