split out setvl from sv.setvl test in test_pysvp64dis.py

setvl. still failing (no idea why)

diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn
index ce4e1105a5d7a408326e97fc5f99c9d990a01a2b..8572d690cacd0991afc3fa658d991d56765b5be1 100644 (file)
--- a/openpower/isa/simplev.mdwn
+++ b/openpower/isa/simplev.mdwn
@@ -5,8 +5,8 @@
 
 SVL-Form
 
-* svstep RT,SVi,vf
-* svstep. RT,SVi,vf
+* svstep RT,SVi,vf (Rc=0)
+* svstep. RT,SVi,vf (Rc=1)
 
 Pseudo-code:
 
@@ -21,8 +21,8 @@ Special Registers Altered:
 
 SVL-Form
 
-* setvl RT,RA,SVi,vf,vs,ms
-* setvl. RT,RA,SVi,vf,vs,ms
+* setvl RT,RA,SVi,vf,vs,ms (Rc=0)
+* setvl. RT,RA,SVi,vf,vs,ms (Rc=1)
 
 Pseudo-code:
 

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index cc4922494f648792a1bc56fd85162c26978c8414..a27274d884b1e398b2db66000dde6f1d3d38f3e9 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -67,13 +67,19 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_5_sv_management(self):
+    def test_5_setvl(self):
         expected = [
                     "setvl 5,4,5,0,1,1",
                     "setvl. 5,4,5,0,1,1",
                         ]
         self._do_tst(expected)
 
+    def test_6_sv_setvl(self):
+        expected = [
+                    "sv.setvl 5,4,5,0,1,1",
+                        ]
+        self._do_tst(expected)
+
 if __name__ == "__main__":
     unittest.main()