struct nir_shader *const *shaders,
int shader_count,
struct radv_shader_variant_info *shader_info,
- const struct radv_nir_compiler_options *options,
- bool dump_shader)
+ const struct radv_nir_compiler_options *options)
{
struct radv_shader_context ctx = {0};
unsigned i;
if (shader_count == 1)
ac_nir_eliminate_const_vs_outputs(&ctx);
- if (dump_shader) {
+ if (options->dump_shader) {
ctx.shader_info->private_mem_vgprs =
ac_count_scratch_private_memory(ctx.main_function);
}
struct ac_shader_config *config,
struct radv_shader_variant_info *shader_info,
gl_shader_stage stage,
- bool dump_shader,
const struct radv_nir_compiler_options *options)
{
- if (dump_shader)
+ if (options->dump_shader)
ac_dump_module(llvm_module);
memset(binary, 0, sizeof(*binary));
fprintf(stderr, "compile failed\n");
}
- if (dump_shader)
+ if (options->dump_shader)
fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
ac_shader_binary_read_config(binary, config, 0, options->supports_spill);
struct radv_shader_variant_info *shader_info,
struct nir_shader *const *nir,
int nir_count,
- const struct radv_nir_compiler_options *options,
- bool dump_shader)
+ const struct radv_nir_compiler_options *options)
{
- LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
- options, dump_shader);
+ LLVMModuleRef llvm_module;
+
+ llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
+ options);
ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info,
- nir[0]->info.stage, dump_shader, options);
+ nir[0]->info.stage, options);
for (int i = 0; i < nir_count; ++i)
ac_fill_shader_info(shader_info, nir[i], options);
struct ac_shader_binary *binary,
struct ac_shader_config *config,
struct radv_shader_variant_info *shader_info,
- const struct radv_nir_compiler_options *options,
- bool dump_shader)
+ const struct radv_nir_compiler_options *options)
{
struct radv_shader_context ctx = {0};
ctx.context = LLVMContextCreate();
ac_llvm_finalize_module(&ctx);
ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
- MESA_SHADER_VERTEX, dump_shader, options);
+ MESA_SHADER_VERTEX, options);
}
struct ac_shader_binary *binary,
struct ac_shader_config *config,
struct radv_shader_variant_info *shader_info,
- const struct radv_nir_compiler_options *options,
- bool dump_shader);
+ const struct radv_nir_compiler_options *option);
void radv_compile_nir_shader(LLVMTargetMachineRef tm,
struct ac_shader_binary *binary,
struct radv_shader_variant_info *shader_info,
struct nir_shader *const *nir,
int nir_count,
- const struct radv_nir_compiler_options *options,
- bool dump_shader);
+ const struct radv_nir_compiler_options *options);
/* radv_shader_info.h */
struct radv_shader_info;
unsigned *code_size_out)
{
enum radeon_family chip_family = device->physical_device->rad_info.family;
- bool dump_shaders = radv_can_dump_shader(device, module);
enum ac_target_machine_options tm_options = 0;
struct radv_shader_variant *variant;
struct ac_shader_binary binary;
options->family = chip_family;
options->chip_class = device->physical_device->rad_info.chip_class;
- options->dump_preoptir = radv_can_dump_shader(device, module) &&
+ options->dump_shader = radv_can_dump_shader(device, module);
+ options->dump_preoptir = options->dump_shader &&
device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
if (options->supports_spill)
assert(shader_count == 1);
radv_compile_gs_copy_shader(tm, *shaders, &binary,
&variant->config, &variant->info,
- options, dump_shaders);
+ options);
} else {
radv_compile_nir_shader(tm, &binary, &variant->config,
&variant->info, shaders, shader_count,
- options, dump_shaders);
+ options);
}
LLVMDisposeTargetMachine(tm);