+++ /dev/null
-#===-- AMDGPUGenInstrEnums.pl - Script for generating instruction enums ----===#
-#
-# The LLVM Compiler Infrastructure
-#
-# This file is distributed under the University of Illinois Open Source
-# License. See LICENSE.TXT for details.
-#
-#===-----------------------------------------------------------------------===#
-#
-# This perl script is used to generate the following files:
-#
-# 1. perl AMDGPUGenInstrEnums.pl td > AMDGPUInstrEnums.td
-#
-# This file contains Tablegen constants used for matching hw instructions
-# from R600 and SI with functionally similar AMDIL instruction. It aslo
-# contains definitions of floating point constants like pi (in hex notation)
-# that are used in some of the shader patterns.
-#
-# 2. perl AMDGPUGenInstrEnums.pl h > AMDGPUInstrEnums.h
-#
-# This file contains cpp enums that match the constant values in
-# AMDGPUInstrEnums.td
-#
-# 3. perl AMDGPUGenInstrEnums.pl inc > AMDGPUInstrEnums.include
-#
-# This file contains a function called GetRealAMDILOpcode which maps the
-# constant values defined in AMDGPUInstrEnums.h to the corresponding AMDIL
-# instructions.
-#===-----------------------------------------------------------------------===#
-
-use warnings;
-use strict;
-
-my @GENERATION_ENUM = qw {
- R600_CAYMAN
- R600
- EG
- EG_CAYMAN
- CAYMAN
- SI
-};
-
-my $FILE_TYPE = $ARGV[0];
-
-open AMDIL, '<', 'AMDILInstructions.td';
-
-my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'LOG_f32', 'RSQ_f32', 'SIN_f32', 'COS_f32');
-
-while (<AMDIL>) {
- if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+)</) {
- } elsif ($_ =~ /def\s+([A-Z_]+)(_[fi]32)/) {
- push @INST_ENUMS, "$1$2";
- }
-}
-
-if ($FILE_TYPE eq 'td') {
-
- print_td_enum('AMDILInst', 'AMDILInstEnums', 'field bits<16>', @INST_ENUMS);
-
- print_td_enum('AMDGPUGen', 'AMDGPUGenEnums', 'field bits<3>', @GENERATION_ENUM);
-
- my %constants = (
- 'PI' => '0x40490fdb',
- 'TWO_PI' => '0x40c90fdb',
- 'TWO_PI_INV' => '0x3e22f983'
- );
-
- print "class Constants {\n";
- foreach (keys(%constants)) {
- print "int $_ = $constants{$_};\n";
- }
- print "}\n";
- print "def CONST : Constants;\n";
-
-} elsif ($FILE_TYPE eq 'h') {
-
- print "unsigned GetRealAMDILOpcode(unsigned internalOpcode) const;\n";
-
- print_h_enum('AMDILTblgenOpcode', @INST_ENUMS);
-
- print_h_enum('AMDGPUGen', @GENERATION_ENUM);
-
-} elsif ($FILE_TYPE eq 'inc') {
- print "unsigned AMDGPUInstrInfo::GetRealAMDILOpcode(unsigned internalOpcode) const\n{\n";
- print " switch(internalOpcode) {\n";
- #Start at 1 so we skip NONE
- for (my $i = 1; $i < scalar(@INST_ENUMS); $i++) {
- my $inst = $INST_ENUMS[$i];
- print " case AMDGPUInstrInfo::$inst: return AMDIL::$inst;\n";
- }
- print " default: abort();\n";
- print " }\n}\n";
-}
-
-
-sub print_td_enum {
- my ($instance, $class, $field, @values) = @_;
-
- print "class $class {\n";
-
- for (my $i = 0; $i < scalar(@values); $i++) {
- print " $field $values[$i] = $i;\n";
- }
- print "}\n";
-
- print "def $instance : $class;\n";
-}
-
-sub print_h_enum {
-
- my ($enum, @list) = @_;
- print "enum $enum {\n";
-
- for (my $i = 0; $i < scalar(@list); $i++) {
- print " $list[$i] = $i";
- if ($i != $#list) {
- print ',';
- }
- print "\n";
- }
- print "};\n";
-}
-
using namespace llvm;
AMDGPUInstrInfo::AMDGPUInstrInfo(AMDGPUTargetMachine &tm)
- : AMDILInstrInfo(tm), TM(tm)
-{
- const AMDILDevice * dev = TM.getSubtarget<AMDILSubtarget>().device();
- for (unsigned i = 0; i < AMDIL::INSTRUCTION_LIST_END; i++) {
- const MCInstrDesc & instDesc = get(i);
- uint32_t instGen = (instDesc.TSFlags >> 40) & 0x7;
- uint32_t inst = (instDesc.TSFlags >> 48) & 0xffff;
- if (inst == 0) {
- continue;
- }
- switch (instGen) {
- case AMDGPUInstrInfo::R600_CAYMAN:
- if (dev->getGeneration() > AMDILDeviceInfo::HD6XXX) {
- continue;
- }
- break;
- case AMDGPUInstrInfo::R600:
- if (dev->getGeneration() != AMDILDeviceInfo::HD4XXX) {
- continue;
- }
- break;
- case AMDGPUInstrInfo::EG_CAYMAN:
- if (dev->getGeneration() < AMDILDeviceInfo::HD5XXX
- || dev->getGeneration() > AMDILDeviceInfo::HD6XXX) {
- continue;
- }
- break;
- case AMDGPUInstrInfo::CAYMAN:
- if (dev->getDeviceFlag() != OCL_DEVICE_CAYMAN) {
- continue;
- }
- break;
- case AMDGPUInstrInfo::SI:
- if (dev->getGeneration() != AMDILDeviceInfo::HD7XXX) {
- continue;
- }
- break;
- default:
- abort();
- break;
- }
-
- unsigned amdilOpcode = GetRealAMDILOpcode(inst);
- amdilToISA[amdilOpcode] = instDesc.Opcode;
- }
-}
+ : AMDILInstrInfo(tm), TM(tm) { }
MachineInstr * AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF,
DebugLoc DL) const
return newInstr;
}
-
-unsigned AMDGPUInstrInfo::getISAOpcode(unsigned opcode) const
-{
- if (amdilToISA.count(opcode) == 0) {
- return opcode;
- } else {
- return amdilToISA.find(opcode)->second;
- }
-}
-
-#include "AMDGPUInstrEnums.include"
class AMDGPUInstrInfo : public AMDILInstrInfo {
private:
AMDGPUTargetMachine & TM;
- std::map<unsigned, unsigned> amdilToISA;
public:
explicit AMDGPUInstrInfo(AMDGPUTargetMachine &tm);
/// getISAOpcode - This function takes an AMDIL opcode as an argument and
/// returns an equivalent ISA opcode.
- virtual unsigned getISAOpcode(unsigned AMDILopcode) const;
+ virtual unsigned getISAOpcode(unsigned AMDILopcode) const = 0;
/// convertToISA - Convert the AMDIL MachineInstr to a supported ISA
/// MachineInstr
virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF,
DebugLoc DL) const;
- #include "AMDGPUInstrEnums.h.include"
};
} // End llvm namespace
//
//===----------------------------------------------------------------------===//
-include "AMDGPUInstrEnums.td"
-
class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
field bits<16> AMDILOp = 0;
field bits<3> Gen = 0;
}
+class Constants {
+int TWO_PI = 0x40c90fdb;
+int PI = 0x40490fdb;
+int TWO_PI_INV = 0x3e22f983;
+}
+def CONST : Constants;
+
let isCodeGenOnly = 1 in {
def MASK_WRITE : AMDGPUShaderInst <
switch(opcode) {
default: return false;
- case AMDIL::COS_f32:
case AMDIL::COS_r600:
case AMDIL::COS_eg:
case AMDIL::RSQ_f32:
case AMDIL::MULLIT:
case AMDIL::MUL_LIT_r600:
case AMDIL::MUL_LIT_eg:
- case AMDIL::SIN_f32:
case AMDIL::EXP_IEEE_r600:
case AMDIL::EXP_IEEE_eg:
case AMDIL::LOG_CLAMPED_r600:
case AMDIL::LOG_IEEE_r600:
case AMDIL::LOG_CLAMPED_eg:
case AMDIL::LOG_IEEE_eg:
- case AMDIL::LOG_f32:
return true;
}
}
defm ATAN : UnaryIntrinsicFloatScalar<IL_OP_ATAN, int_AMDIL_atan>;
defm ASIN : UnaryIntrinsicFloatScalar<IL_OP_ASIN, int_AMDIL_asin>;
defm TAN : UnaryIntrinsicFloatScalar<IL_OP_TAN, int_AMDIL_tan>;
-defm SIN : UnaryIntrinsicFloatScalar<IL_OP_SIN, int_AMDIL_sin>;
-defm COS : UnaryIntrinsicFloatScalar<IL_OP_COS, int_AMDIL_cos>;
defm SQRT : UnaryIntrinsicFloatScalar<IL_OP_SQRT, int_AMDIL_sqrt>;
defm SQRTVEC : UnaryIntrinsicFloat<IL_OP_SQRT_VEC, int_AMDIL_sqrt_vec>;
defm COSVEC : UnaryIntrinsicFloat<IL_OP_COS_VEC, int_AMDIL_cos_vec>;
let hasZeroOpFlag = 1 in {
let mayLoad = 0, mayStore=0 in {
defm LN : UnaryIntrinsicFloatScalar<IL_OP_LN, int_AMDIL_ln>;
-defm LOG : UnaryIntrinsicFloatScalar<IL_OP_LOG, int_AMDIL_log>;
defm RSQ : UnaryIntrinsicFloatScalar<IL_OP_RSQ, int_AMDIL_rsq>;
defm DIV : BinaryIntrinsicFloat<IL_OP_DIV, int_AMDIL_div>;
}
R600RegisterInfo.td: R600GenRegisterInfo.pl
$(PERL) $^ > $@
-AMDGPUInstrEnums.td: AMDGPUGenInstrEnums.pl
- $(PERL) $^ td > $@
-
-AMDGPUInstrEnums.h.include: AMDGPUGenInstrEnums.pl
- $(PERL) $^ h > $@
-
-AMDGPUInstrEnums.include: AMDGPUGenInstrEnums.pl
- $(PERL) $^ inc > $@
-
-
AMDILGenRegisterInfo.inc: *.td
$(call tablegen, -gen-register-info, AMDIL.td, $@)
GENERATED_SOURCES := \
R600Intrinsics.td \
R600RegisterInfo.td \
- AMDGPUInstrEnums.td \
SIRegisterInfo.td \
SIRegisterGetHWRegNum.inc \
AMDILGenRegisterInfo.inc \
AMDILGenSubtargetInfo.inc \
AMDILGenEDInfo.inc \
AMDILGenIntrinsics.inc \
- AMDILGenCodeEmitter.inc \
- AMDGPUInstrEnums.h.include \
- AMDGPUInstrEnums.include
+ AMDILGenCodeEmitter.inc
CPP_SOURCES := \
AMDIL7XXDevice.cpp \
unsigned R600InstrInfo::getISAOpcode(unsigned opcode) const
{
switch (opcode) {
- default: return AMDGPUInstrInfo::getISAOpcode(opcode);
+ default: return opcode;
case AMDIL::IEQ:
return AMDIL::SETE_INT;
case AMDIL::INE:
namespace llvm {
- struct InstrGroup {
- unsigned amdil;
- unsigned r600;
- unsigned eg;
- unsigned cayman;
- };
-
class AMDGPUTargetMachine;
class MachineFunction;
class MachineInstr;
/* ------------------------------------------- */
/* Common Instructions R600, R700, Evergreen, Cayman */
/* ------------------------------------------- */
-let Gen = AMDGPUGen.R600_CAYMAN in {
-
def ADD : R600_2OP <
0x0, "ADD",
[(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
(selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
COND_EQ))]
>;
-//let AMDILOp = AMDILInst.FEQ;
def SGT : R600_2OP <
0x09, "SETGT",
(selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
COND_GE))]
>;
-//let AMDILOp = AMDILInst.FGE;
def SNE : R600_2OP <
0xB, "SETNE",
COND_NE))]
>;
-// let AMDILOp = AMDILInst.FNE;
-
def FRACT : R600_1OP <
0x10, "FRACT",
[(set R600_Reg32:$dst, (AMDGPUfract R600_Reg32:$src))]
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
>;
-// let AMDILOp = AMDILInst.IEQ;
-
def SETGT_INT : R600_2OP <
0x3B, "SGT_INT",
[(set (i32 R600_Reg32:$dst),
[(set (i32 R600_Reg32:$dst),
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
>;
-// let AMDILOp = AMDILInst.IGE;
-
def SETNE_INT : R600_2OP <
0x3D, "SETNE_INT",
[(set (i32 R600_Reg32:$dst),
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
>;
-//let AMDILOp = AMDILInst.INE;
-
def SETGT_UINT : R600_2OP <
0x3E, "SETGT_UINT",
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
>;
-// let AMDILOp = AMDILInst.UGT;
-
def SETGE_UINT : R600_2OP <
0x3F, "SETGE_UINT",
[(set (i32 R600_Reg32:$dst),
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
>;
-// let AMDILOp = AMDILInst.UGE;
def CNDE_INT : R600_3OP <
0x1C, "CNDE_INT",
[]
>;
-} // End Gen R600_CAYMAN
-
def KILP : Pat <
(int_AMDGPU_kilp),
(MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
class LOG_IEEE_Common <bits<32> inst> : R600_1OP <
inst, "LOG_IEEE",
- []> {
- let AMDILOp = AMDILInst.LOG_f32;
-}
+ [(set R600_Reg32:$dst, (int_AMDIL_log R600_Reg32:$src))]
+>;
class LSHL_Common <bits<32> inst> : R600_2OP <
inst, "LSHL $dst, $src0, $src1",
class RECIP_IEEE_Common <bits<32> inst> : R600_1OP <
inst, "RECIP_IEEE",
- [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]> {
- let AMDILOp = AMDILInst.RSQ_f32;
-}
+ [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]
+>;
class RECIP_UINT_Common <bits<32> inst> : R600_1OP <
inst, "RECIP_INT $dst, $src",
class SIN_Common <bits<32> inst> : R600_1OP <
inst, "SIN",
- []>{
- let AMDILOp = AMDILInst.SIN_f32;
+ [(set R600_Reg32:$dst, (int_AMDIL_sin R600_Reg32:$src))]>{
let Trig = 1;
}
class COS_Common <bits<32> inst> : R600_1OP <
inst, "COS",
- []> {
- let AMDILOp = AMDILInst.COS_f32;
+ [(set R600_Reg32:$dst, (int_AMDIL_cos R600_Reg32:$src))]> {
let Trig = 1;
}
let Predicates = [isR600] in {
-let Gen = AMDGPUGen.R600 in {
-
def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
def MULADD_r600 : MULADD_Common<0x10>;
def CNDE_r600 : CNDE_Common<0x18>;
def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
def RECIP_UINT_r600 : RECIP_UINT_Common <0x77>;
-} // End AMDGPUGen.R600
-
def DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>;
def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>;
let Predicates = [isEG] in {
-let Gen = AMDGPUGen.EG in {
-
def RAT_WRITE_CACHELESS_eg :
EG_CF_RAT <0x57, 0x2, (outs), (ins R600_TReg32_X:$rw_gpr,
R600_TReg32_X:$index_gpr, i32imm:$rat_id), "">
*/
}
-
-
-} // End AMDGPUGen.EG
/* XXX: Need to convert PTR to rat_id */
/*
def : Pat <(store_global (f32 R600_Reg32:$value), node:$ptr),
(trig (MUL (MOV (LOADCONST_i32 CONST.TWO_PI_INV)), R600_Reg32:$src))
>;
-let Gen = AMDGPUGen.EG_CAYMAN in {
-
def MULADD_eg : MULADD_Common<0x14>;
def ASHR_eg : ASHR_Common<0x15>;
def LSHR_eg : LSHR_Common<0x16>;
def DOT4_eg : DOT4_Common<0xBE>;
def CUBE_eg : CUBE_Common<0xC0>;
-} // End AMDGPUGen.EG_CAYMAN
-
def DIV_eg : DIV_Common<RECIP_IEEE_eg>;
def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>;
def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>;
let Predicates = [isCayman] in {
-let Gen = AMDGPUGen.CAYMAN in {
-
/* XXX: I'm not sure if this opcode is correct. */
def RECIP_UINT_cm : RECIP_UINT_Common<0x77>;
-} // End AMDGPUGen.CAYMAN
-
} // End isCayman
/* Other Instructions */
op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
>;
-multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern,
- bits<16> amdil = AMDILInst.NONE> {
-
- let AMDILOp = amdil in {
- def _e32: VOP1_Helper <op, VReg_32, AllReg_32, opName, pattern>;
- }
-
- def _e64 : VOP3_32 <
- {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
- opName, []
+multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern> {
+ def _e32: VOP1_Helper <op, VReg_32, AllReg_32, opName, pattern>;
+ def _e64 : VOP3_32 <{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
+ opName, []
>;
}
op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
>;
-multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern,
- bits<16> amdil = AMDILInst.NONE> {
+multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern> {
- let AMDILOp = amdil in {
- def _e32 : VOP2_Helper <op, VReg_32, AllReg_32, opName, pattern>;
- }
+ def _e32 : VOP2_Helper <op, VReg_32, AllReg_32, opName, pattern>;
- def _e64 : VOP3_32 <
- {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
- opName, []
+ def _e64 : VOP3_32 <{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
+ opName, []
>;
}
switch (AMDILopcode) {
//XXX We need a better way of detecting end of program
case AMDIL::RETURN: return AMDIL::S_ENDPGM;
- default: return AMDGPUInstrInfo::getISAOpcode(AMDILopcode);
+ case AMDIL::MOVE_f32: return AMDIL::V_MOV_B32_e32;
+ default: return AMDILopcode;
}
}
"->getGeneration() == AMDILDeviceInfo::HD7XXX">;
let Predicates = [isSI] in {
-let Gen = AMDGPUGen.SI in {
def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
//def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
let neverHasSideEffects = 1 in {
-defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", [], AMDILInst.MOVE_f32>;
+defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>;
} // End neverHasSideEffects
defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>;
//defm V_CVT_I32_F64 : VOP1_32 <0x00000003, "V_CVT_I32_F64", []>;
} // end IsCodeGenOnly, isPseudo
-} // end Gen = AMDGPUGen.SI
-
/* int_SI_vs_load_input */
def : Pat<
(int_SI_vs_load_input SReg_64:$tlst_sgpr, IMM8bit:$t_offset, IMM12bit:$attr_offset,
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