tests.hdl.dsl: add tests for mis-nested Switch/Case and FSM/State statements

diff --git a/tests/test_hdl_dsl.py b/tests/test_hdl_dsl.py
index a2d0c96f7e679dddb34144c12a61b8dd14baa6f9..5156eab372225fd29ba4e62240d93d80d84b2da6 100644 (file)
--- a/tests/test_hdl_dsl.py
+++ b/tests/test_hdl_dsl.py
@@ -504,6 +504,15 @@ class DSLTestCase(FHDLTestCase):
                 with m.If(self.s2):
                     pass
 
+    def test_Case_wrong_nested(self):
+        m = Module()
+        with m.Switch(self.s1):
+            with m.Case(0):
+                with self.assertRaisesRegex(SyntaxError,
+                    r"^Case is not permitted outside of Switch$"):
+                    with m.Case(1):
+                        pass
+
     def test_FSM_basic(self):
         a = Signal()
         b = Signal()
@@ -660,6 +669,23 @@ class DSLTestCase(FHDLTestCase):
                 with m.If(self.s2):
                     pass
 
+    def test_State_outside_FSM_wrong(self):
+        m = Module()
+        with self.assertRaisesRegex(SyntaxError,
+            r"^FSM State is not permitted outside of FSM"):
+            with m.State("FOO"):
+                pass
+
+
+    def test_FSM_State_wrong_nested(self):
+        m = Module()
+        with m.FSM():
+            with m.State("FOO"):
+                with self.assertRaisesRegex(SyntaxError,
+                    r"^FSM State is not permitted outside of FSM"):
+                    with m.State("BAR"):
+                        pass
+
     def test_auto_pop_ctrl(self):
         m = Module()
         with m.If(self.w1):