Add "hdlname" attribute

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/README.md b/README.md
index c5cd4770701156129d6cbbdb5920e677a3aef1a8..4048ecbc7012fa1e6e2b7c60e9be5d0615d12798 100644 (file)
--- a/README.md
+++ b/README.md
@@ -315,6 +315,9 @@ Verilog Attributes and non-standard features
 - The ``dynports'' attribute is used by the Verilog front-end to mark modules
   that have ports with a width that depends on a parameter.
 
+- The ``hdlname'' attribute is used by some passes to document the original
+  (HDL) name of a module when renaming a module.
+
 - The ``keep`` attribute on cells and wires is used to mark objects that should
   never be removed by the optimizer. This is used for example for cells that
   have hidden connections that are not part of the netlist, such as IO pads.

diff --git a/passes/hierarchy/uniquify.cc b/passes/hierarchy/uniquify.cc
index c88ecd82ef89ea1f22fd3ed32305bc0f01b3b890..e6154e94f49e580293ddd4b6eec63bd4af0ccc97 100644 (file)
--- a/passes/hierarchy/uniquify.cc
+++ b/passes/hierarchy/uniquify.cc
@@ -87,6 +87,8 @@ struct UniquifyPass : public Pass {
                                        smod->name = newname;
                                        cell->type = newname;
                                        smod->set_bool_attribute("\\unique");
+                                       if (smod->attributes.count("\\hdlname") == 0)
+                                               smod->attributes["\\hdlname"] = string(log_id(tmod->name));
                                        design->add(smod);
 
                                        did_something = true;