uart2wishbone: share UARTRX and UARTTX with MiSoC

diff --git a/miscope/mila.py b/miscope/mila.py
index 5d74f3175c7f5acebad9c0272bfd7ee973404932..9fa3637ef4bb16ececcf3b17d2996e76b37fd189 100644 (file)
--- a/miscope/mila.py
+++ b/miscope/mila.py
@@ -1,9 +1,9 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.fhdl import verilog
 from migen.bank.description import *
+from migen.actorlib.fifo import AsyncFIFO
 
 from miscope.std import *
-from migen.actorlib.fifo import AsyncFIFO
 from miscope.trigger import Trigger
 from miscope.storage import Recorder, RunLengthEncoder
 
@@ -19,7 +19,7 @@ class MiLa(Module, AutoCSR):
                self.sink = Record(dat_layout(width))
 
                if clk_domain is not "sys":
-                       fifo = AsyncFIFO([("dat", width)], 32) # FIXME: reduce this
+                       fifo = AsyncFIFO([("dat", width)], 32)
                        self.submodules += RenameClockDomains(fifo, {"write": clk_domain, "read": "sys"})
                        self.comb += [
                                fifo.sink.stb.eq(self.sink.stb),

diff --git a/miscope/uart2wishbone.py b/miscope/uart2wishbone.py
index 0576b2581512363031ba90f8caf29d723728a378..f75a85743e384c02bd42606114ade812bbbce99f 100644 (file)
--- a/miscope/uart2wishbone.py
+++ b/miscope/uart2wishbone.py
@@ -1,111 +1,14 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import *
+from migen.fhdl.std import *
 from migen.genlib.record import *
-from migen.genlib.cdc import MultiReg
 from migen.genlib.fsm import FSM, NextState
-from migen.genlib.misc import split, displacer, chooser
+from migen.genlib.misc import chooser
 from migen.bank.description import *
 from migen.bus import wishbone
-from migen.flow.actor import Sink, Source
 
-class UARTRX(Module):
-       def __init__(self, pads, tuning_word):
-               self.source = Source([("d", 8)])
-
-               ###
-
-               uart_clk_rxen = Signal()
-               phase_accumulator_rx = Signal(32)
-
-               rx = Signal()
-               self.specials += MultiReg(pads.rx, rx)
-               rx_r = Signal()
-               rx_reg = Signal(8)
-               rx_bitcount = Signal(4)
-               rx_busy = Signal()
-               rx_done = self.source.stb
-               rx_data = self.source.payload.d
-               self.sync += [
-                       rx_done.eq(0),
-                       rx_r.eq(rx),
-                       If(~rx_busy,
-                               If(~rx & rx_r, # look for start bit
-                                       rx_busy.eq(1),
-                                       rx_bitcount.eq(0),
-                               )
-                       ).Else(
-                               If(uart_clk_rxen,
-                                       rx_bitcount.eq(rx_bitcount + 1),
-                                       If(rx_bitcount == 0,
-                                               If(rx, # verify start bit
-                                                       rx_busy.eq(0)
-                                               )
-                                       ).Elif(rx_bitcount == 9,
-                                               rx_busy.eq(0),
-                                               If(rx, # verify stop bit
-                                                       rx_data.eq(rx_reg),
-                                                       rx_done.eq(1)
-                                               )
-                                       ).Else(
-                                               rx_reg.eq(Cat(rx_reg[1:], rx))
-                                       )
-                               )
-                       )
-               ]
-               self.sync += \
-                               If(rx_busy,
-                                       Cat(phase_accumulator_rx, uart_clk_rxen).eq(phase_accumulator_rx + tuning_word)
-                               ).Else(
-                                       Cat(phase_accumulator_rx, uart_clk_rxen).eq(2**31)
-                               )
-
-class UARTTX(Module):
-       def __init__(self, pads, tuning_word):
-               self.sink = Sink([("d", 8)])
-
-               ###
-
-               uart_clk_txen = Signal()
-               phase_accumulator_tx = Signal(32)
-
-               pads.tx.reset = 1
-
-               tx_reg = Signal(8)
-               tx_bitcount = Signal(4)
-               tx_busy = Signal()
-               self.sync += [
-                       self.sink.ack.eq(0),
-                       If(self.sink.stb & ~tx_busy & ~self.sink.ack,
-                               tx_reg.eq(self.sink.payload.d),
-                               tx_bitcount.eq(0),
-                               tx_busy.eq(1),
-                               pads.tx.eq(0)
-                       ).Elif(uart_clk_txen & tx_busy,
-                               tx_bitcount.eq(tx_bitcount + 1),
-                               If(tx_bitcount == 8,
-                                       pads.tx.eq(1)
-                               ).Elif(tx_bitcount == 9,
-                                       pads.tx.eq(1),
-                                       tx_busy.eq(0),
-                                       self.sink.ack.eq(1),
-                               ).Else(
-                                       pads.tx.eq(tx_reg[0]),
-                                       tx_reg.eq(Cat(tx_reg[1:], 0))
-                               )
-                       )
-               ]
-               self.sync += [
-                               If(tx_busy,
-                                       Cat(phase_accumulator_tx, uart_clk_txen).eq(phase_accumulator_tx + tuning_word)
-                               ).Else(
-                                       Cat(phase_accumulator_tx, uart_clk_txen).eq(0)
-                               )
-               ]
+from misoclib.uart import UARTRX, UARTTX
 
 class UART(Module, AutoCSR):
        def __init__(self, pads, clk_freq, baud=115200):
-
-               # Tuning word value
                self._tuning_word = CSRStorage(32, reset=int((baud/clk_freq)*2**32))
                tuning_word = self._tuning_word.storage