-This is release 2.0 of the M5 simulator.
+This is release 2.0_beta of the M5 simulator.
-For information about building the simulator and getting started please refer
-to: http://m5.eecs.umich.edu/
+For detailed information about building the simulator and getting
+started please refer to http://www.m5sim.org.
-Specific Pages of Interest are:
-http://m5.eecs.umich.edu/wiki/index.php/Compiling_M5
-http://m5.eecs.umich.edu/wiki/index.php/Running_M5
+Specific pages of interest are:
+http://www.m5sim.org/wiki/index.php/Compiling_M5
+http://www.m5sim.org/wiki/index.php/Running_M5
+
+Short version:
+
+1. If you don't have SCons version 0.96.91 or newer, get it from
+http://wwww.scons.org.
+
+2. If you don't have SWIG version 0.96.91 or newer, get it from
+http://wwww.swig.org.
+
+3. In this directory, type 'scons build/ALPHA_SE/tests/debug/quick'. This
+will build the debug version of the m5 binary (m5.debug) for the Alpha
+syscall emulation target, and run the quick regression tests on it.
If you have questions, please send mail to m5sim-users@lists.sourceforge.net.
The basic source release includes these subdirectories:
- m5:
- src: source code of the m5 simulator
- - test: regression tests
+ - tests: regression tests
- ext: less-common external packages needed to build m5
- system/alpha: source for Alpha console and PALcode
To run full-system simulations, you will need compiled console,
PALcode, and kernel binaries and one or more disk images. These files
-are collected in a separate archive, m5_system_2.0.tar.bz2. This file
-is included on the CD release, or you can download it separately from
-Sourceforge.
+are collected in a separate archive, m5_system_1.1.tar.bz2. This file
+can he downloaded separately.
M5 supports Linux 2.4/2.6, FreeBSD, and the proprietary Compaq/HP
Tru64 version of Unix. We are able to distribute Linux and FreeBSD
bootdisks, but we are unable to distribute bootable disk images of
Tru64 Unix. If you have a Tru64 license and are interested in
obtaining disk images, contact us at m5-dev@eecs.umich.edu.
-
-The CD release includes a few extra goodies, such as a tar file
-containing doxygen-generated HTML documentation (html-docs.tar.gz), a
-set of Linux source patches (linux_m5-2.6.8.1.diff), and the scons
-program needed to build M5. If you do not have the CD, the same HTML
-documentation is available online at http://m5.eecs.umich.edu/docs,
-the Linux source patches are available at
-http://m5.eecs.umich.edu/dist/linux_m5-2.6.8.1.diff, the scons
-program is available from http://www.scons.org, and swig is available from
-http://www.swig.org.
-
-
-XXX. X, 2006: m5_2.0
+Aug. 15, 2006: m5_2.0_beta
--------------------
Major update to M5 including:
- New CPU model
-- Sew memory system
+- New memory system
- More extensive python integration
- Preliminary syscall emulation support for MIPS and SPARC
+This is a *beta* release, meaning that some features are not complete,
+and some features from M5 1.X aren't currently supported (e.g., MP
+coherence). We are working to address these limitations and hope to
+have a complete 2.0 release soon.
Oct. 8, 2005: m5_1.1
--------------------
# Non-sticky options only apply to the current build.
nonsticky_opts = Options(args=ARGUMENTS)
nonsticky_opts.AddOptions(
+ ListOption('TEST_CPU_MODELS', 'CPU models to test if regression is being run', '',
+ env['ALL_CPU_LIST']),
BoolOption('update_ref', 'Update test reference outputs', False)
)
exports = 'env')
# Set up the regression tests for each build.
-# for e in envList:
-# SConscript('m5-test/SConscript',
-# build_dir = os.path.join(build_dir, 'test', e.Label),
-# exports = { 'env' : e }, duplicate = False)
+ for e in envList:
+ SConscript('tests/SConscript',
+ build_dir = os.path.join(build_path, 'test', e.Label),
+ exports = { 'env' : e }, duplicate = False)
Help(help_text)
--- /dev/null
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Kevin Lim
+
+import m5
+from m5 import makeList
+from m5.objects import *
+from FullO3Config import *
+from SysPaths import *
+from Util import *
+
+script.dir = '/z/saidi/work/m5.newmem/configs/boot'
+linux_image = env.get('LINUX_IMAGE', disk('linux-latest.img'))
+
+class CowIdeDisk(IdeDisk):
+ image = CowDiskImage(child=RawDiskImage(read_only=True),
+ read_only=False)
+
+ def childImage(self, ci):
+ self.image.child.image_file = ci
+
+class BaseTsunami(Tsunami):
+ ethernet = NSGigE(configdata=NSGigEPciData(),
+ pci_bus=0, pci_dev=1, pci_func=0)
+ etherint = NSGigEInt(device=Parent.ethernet)
+ ide = IdeController(disks=[Parent.disk0, Parent.disk2],
+ pci_func=0, pci_dev=0, pci_bus=0)
+
+def makeLinuxAlphaSystem(cpu, mem_mode, linux_image, icache=None, dcache=None, l2cache=None):
+ self = LinuxAlphaSystem()
+ self.iobus = Bus(bus_id=0)
+ self.membus = Bus(bus_id=1)
+ self.bridge = Bridge()
+ self.physmem = PhysicalMemory(range = AddrRange('128MB'))
+ self.bridge.side_a = self.iobus.port
+ self.bridge.side_b = self.membus.port
+ self.physmem.port = self.membus.port
+ self.disk0 = CowIdeDisk(driveID='master')
+ self.disk2 = CowIdeDisk(driveID='master')
+ self.disk0.childImage(linux_image)
+ self.disk2.childImage(disk('linux-bigswap2.img'))
+ self.tsunami = BaseTsunami()
+ self.tsunami.attachIO(self.iobus)
+ self.tsunami.ide.pio = self.iobus.port
+ self.tsunami.ide.dma = self.iobus.port
+ self.tsunami.ide.config = self.iobus.port
+ self.tsunami.ethernet.pio = self.iobus.port
+ self.tsunami.ethernet.dma = self.iobus.port
+ self.tsunami.ethernet.config = self.iobus.port
+ self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = linux_image,
+ read_only = True))
+ self.intrctrl = IntrControl()
+ self.cpu = cpu
+ self.mem_mode = mem_mode
+ connectCpu(self.cpu, self.membus, icache, dcache, l2cache)
+ for each_cpu in makeList(self.cpu):
+ each_cpu.itb = AlphaITB()
+ each_cpu.dtb = AlphaDTB()
+ self.cpu.clock = '2GHz'
+ self.sim_console = SimConsole(listener=ConsoleListener(port=3456))
+ self.kernel = binary('vmlinux')
+ self.pal = binary('ts_osfpal')
+ self.console = binary('console')
+ self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
+
+ return self
+
+def makeDualRoot(clientSystem, serverSystem):
+ self = Root()
+ self.client = clientSystem
+ self.server = serverSystem
+
+ self.etherdump = EtherDump(file='ethertrace')
+ self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0],
+ int2 = Parent.server.tsunami.etherint[0],
+ dump = Parent.etherdump)
+ self.clock = '1THz'
+ return self
--- /dev/null
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ali Saidi
+
+import os, sys
+from os.path import isdir, join as joinpath
+from os import environ as env
+
+def disk(file):
+ system()
+ return joinpath(disk.dir, file)
+
+def binary(file):
+ system()
+ return joinpath(binary.dir, file)
+
+def script(file):
+ system()
+ return joinpath(script.dir, file)
+
+def system():
+ if not system.dir:
+ try:
+ path = env['M5_PATH'].split(':')
+ except KeyError:
+ path = [ '/dist/m5/system', '/n/poolfs/z/dist/m5/system' ]
+
+ for system.dir in path:
+ if os.path.isdir(system.dir):
+ break
+ else:
+ raise ImportError, "Can't find a path to system files."
+
+ if not binary.dir:
+ binary.dir = joinpath(system.dir, 'binaries')
+ if not disk.dir:
+ disk.dir = joinpath(system.dir, 'disks')
+ if not script.dir:
+ script.dir = joinpath(system.dir, 'boot')
+
+system.dir = None
+binary.dir = None
+disk.dir = None
+script.dir = None
+++ /dev/null
-import os, sys
-from os.path import isdir, join as joinpath
-from os import environ as env
-
-systemdir = None
-bindir = None
-diskdir = None
-scriptdir = None
-
-def load_defaults():
- global systemdir, bindir, diskdir, scriptdir
- if not systemdir:
- try:
- path = env['M5_PATH'].split(':')
- except KeyError:
- path = [ '/dist/m5/system', '/n/poolfs/z/dist/m5/system' ]
-
- for systemdir in path:
- if os.path.isdir(systemdir):
- break
- else:
- raise ImportError, "Can't find a path to system files."
-
- if not bindir:
- bindir = joinpath(systemdir, 'binaries')
- if not diskdir:
- diskdir = joinpath(systemdir, 'disks')
- if not scriptdir:
- scriptdir = joinpath(systemdir, 'boot')
-
-def disk(file):
- load_defaults()
- return joinpath(diskdir, file)
-
-def binary(file):
- load_defaults()
- return joinpath(bindir, file)
-
-def script(file):
- load_defaults()
- return joinpath(scriptdir, file)
-
import m5
from m5.objects import *
+m5.AddToPath('../common')
+from FSConfig import *
from SysPaths import *
+from Util import *
parser = optparse.OptionParser()
+parser.add_option("-d", "--detailed", action="store_true")
parser.add_option("-t", "--timing", action="store_true")
+parser.add_option("-m", "--maxtick", type="int")
+parser.add_option("--maxtime", type="float")
+parser.add_option("--dual", help="Run full system using dual systems",
+ action="store_true")
(options, args) = parser.parse_args()
print "Error: script doesn't take any positional arguments"
sys.exit(1)
-# Base for tests is directory containing this file.
-test_base = os.path.dirname(__file__)
-
-linux_image = env.get('LINUX_IMAGE', disk('linux-latest.img'))
-
-class IdeControllerPciData(PciConfigData):
- VendorID = 0x8086
- DeviceID = 0x7111
- Command = 0x0
- Status = 0x280
- Revision = 0x0
- ClassCode = 0x01
- SubClassCode = 0x01
- ProgIF = 0x85
- BAR0 = 0x00000001
- BAR1 = 0x00000001
- BAR2 = 0x00000001
- BAR3 = 0x00000001
- BAR4 = 0x00000001
- BAR5 = 0x00000001
- InterruptLine = 0x1f
- InterruptPin = 0x01
- BAR0Size = '8B'
- BAR1Size = '4B'
- BAR2Size = '8B'
- BAR3Size = '4B'
- BAR4Size = '16B'
-
-class SinicPciData(PciConfigData):
- VendorID = 0x1291
- DeviceID = 0x1293
- Status = 0x0290
- SubClassCode = 0x00
- ClassCode = 0x02
- ProgIF = 0x00
- BAR0 = 0x00000000
- BAR1 = 0x00000000
- BAR2 = 0x00000000
- BAR3 = 0x00000000
- BAR4 = 0x00000000
- BAR5 = 0x00000000
- MaximumLatency = 0x34
- MinimumGrant = 0xb0
- InterruptLine = 0x1e
- InterruptPin = 0x01
- BAR0Size = '64kB'
-
-class NSGigEPciData(PciConfigData):
- VendorID = 0x100B
- DeviceID = 0x0022
- Status = 0x0290
- SubClassCode = 0x00
- ClassCode = 0x02
- ProgIF = 0x00
- BAR0 = 0x00000001
- BAR1 = 0x00000000
- BAR2 = 0x00000000
- BAR3 = 0x00000000
- BAR4 = 0x00000000
- BAR5 = 0x00000000
- MaximumLatency = 0x34
- MinimumGrant = 0xb0
- InterruptLine = 0x1e
- InterruptPin = 0x01
- BAR0Size = '256B'
- BAR1Size = '4kB'
-
-class LinuxRootDisk(IdeDisk):
- raw_image = RawDiskImage(image_file=linux_image, read_only=True)
- image = CowDiskImage(child=Parent.raw_image, read_only=False)
-
-class LinuxSwapDisk(IdeDisk):
- raw_image = RawDiskImage(image_file = disk('linux-bigswap2.img'),
- read_only=True)
- image = CowDiskImage(child = Parent.raw_image, read_only=False)
-
-class SpecwebFilesetDisk(IdeDisk):
- raw_image = RawDiskImage(image_file = disk('specweb-fileset.img'),
- read_only=True)
- image = CowDiskImage(child = Parent.raw_image, read_only=False)
-
-class BaseTsunami(Tsunami):
- cchip = TsunamiCChip(pio_addr=0x801a0000000)
- pchip = TsunamiPChip(pio_addr=0x80180000000)
- pciconfig = PciConfigAll()
- fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
-
- fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
- fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
- fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
- fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
-
- fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
-
- fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
-
- fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
- fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
- fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
- fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
- fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
- fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
- fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
- fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
- fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
- fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
-
- fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
- fake_ata1 = IsaFake(pio_addr=0x801fc000170)
-
- fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
- io = TsunamiIO(pio_addr=0x801fc000000)
- uart = Uart8250(pio_addr=0x801fc0003f8)
- ethernet = NSGigE(configdata=NSGigEPciData(),
- pci_bus=0, pci_dev=1, pci_func=0)
- etherint = NSGigEInt(device=Parent.ethernet)
- console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
-
-class LinuxTsunami(BaseTsunami):
- disk0 = LinuxRootDisk(driveID='master')
- disk1 = SpecwebFilesetDisk(driveID='slave')
- disk2 = LinuxSwapDisk(driveID='master')
- ide = IdeController(disks=[Parent.disk0, Parent.disk1, Parent.disk2],
- configdata=IdeControllerPciData(),
- pci_func=0, pci_dev=0, pci_bus=0)
-
-class MyLinuxAlphaSystem(LinuxAlphaSystem):
- magicbus = Bus(bus_id=0)
- magicbus2 = Bus(bus_id=1)
- bridge = Bridge()
- physmem = PhysicalMemory(range = AddrRange('128MB'))
- bridge.side_a = magicbus.port
- bridge.side_b = magicbus2.port
- physmem.port = magicbus2.port
- tsunami = LinuxTsunami()
- tsunami.cchip.pio = magicbus.port
- tsunami.pchip.pio = magicbus.port
- tsunami.pciconfig.pio = magicbus.default
- tsunami.fake_sm_chip.pio = magicbus.port
- tsunami.ethernet.pio = magicbus.port
- tsunami.ethernet.dma = magicbus.port
- tsunami.ethernet.config = magicbus.port
- tsunami.fake_uart1.pio = magicbus.port
- tsunami.fake_uart2.pio = magicbus.port
- tsunami.fake_uart3.pio = magicbus.port
- tsunami.fake_uart4.pio = magicbus.port
- tsunami.ide.pio = magicbus.port
- tsunami.ide.dma = magicbus.port
- tsunami.ide.config = magicbus.port
- tsunami.fake_ppc.pio = magicbus.port
- tsunami.fake_OROM.pio = magicbus.port
- tsunami.fake_pnp_addr.pio = magicbus.port
- tsunami.fake_pnp_write.pio = magicbus.port
- tsunami.fake_pnp_read0.pio = magicbus.port
- tsunami.fake_pnp_read1.pio = magicbus.port
- tsunami.fake_pnp_read2.pio = magicbus.port
- tsunami.fake_pnp_read3.pio = magicbus.port
- tsunami.fake_pnp_read4.pio = magicbus.port
- tsunami.fake_pnp_read5.pio = magicbus.port
- tsunami.fake_pnp_read6.pio = magicbus.port
- tsunami.fake_pnp_read7.pio = magicbus.port
- tsunami.fake_ata0.pio = magicbus.port
- tsunami.fake_ata1.pio = magicbus.port
- tsunami.fb.pio = magicbus.port
- tsunami.io.pio = magicbus.port
- tsunami.uart.pio = magicbus.port
- tsunami.console.pio = magicbus.port
- raw_image = RawDiskImage(image_file=disk('linux-latest.img'),
- read_only=True)
- simple_disk = SimpleDisk(disk=Parent.raw_image)
- intrctrl = IntrControl()
- if options.timing:
- cpu = TimingSimpleCPU()
- else:
- cpu = AtomicSimpleCPU()
- cpu.mem = magicbus2
- cpu.icache_port = magicbus2.port
- cpu.dcache_port = magicbus2.port
- cpu.itb = AlphaITB()
- cpu.dtb = AlphaDTB()
- sim_console = SimConsole(listener=ConsoleListener(port=3456))
- kernel = binary('vmlinux')
- pal = binary('ts_osfpal')
- console = binary('console')
- boot_osflags = 'root=/dev/hda1 console=ttyS0'
-# readfile = os.path.join(test_base, 'halt.sh')
-
-
-
-class TsunamiRoot(System):
- pass
-
-
-def DualRoot(clientSystem, serverSystem):
- self = Root()
- self.client = clientSystem
- self.server = serverSystem
-
- self.etherdump = EtherDump(file='ethertrace')
- self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0],
- int2 = Parent.server.tsunami.etherint[0],
- dump = Parent.etherdump)
- self.clock = '5GHz'
- return self
-
-root = DualRoot(
- MyLinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')),
- MyLinuxAlphaSystem(readfile=script('netperf-server.rcS')))
+if options.detailed:
+ cpu = DetailedO3CPU()
+ cpu2 = DetailedO3CPU()
+ mem_mode = 'timing'
+elif options.timing:
+ cpu = TimingSimpleCPU()
+ cpu2 = TimingSimpleCPU()
+ mem_mode = 'timing'
+else:
+ cpu = AtomicSimpleCPU()
+ cpu2 = AtomicSimpleCPU()
+ mem_mode = 'atomic'
+
+if options.dual:
+ root = makeDualRoot(
+ makeLinuxAlphaSystem(cpu, mem_mode, linux_image),
+ makeLinuxAlphaSystem(cpu2, mem_mode, linux_image))
+ root.client.readfile = script('netperf-stream-nt-client.rcS')
+ root.server.readfile = script('netperf-server.rcS')
+else:
+ root = Root(clock = '1THz',
+ system = makeLinuxAlphaSystem(cpu, mem_mode, linux_image))
m5.instantiate(root)
-exit_event = m5.simulate()
+#exit_event = m5.simulate(2600000000000)
+#if exit_event.getCause() != "user interrupt received":
+# m5.checkpoint(root, 'cpt')
+# exit_event = m5.simulate(300000000000)
+# if exit_event.getCause() != "user interrupt received":
+# m5.checkpoint(root, 'cptA')
+
+
+if options.maxtick:
+ exit_event = m5.simulate(options.maxtick)
+elif options.maxtime:
+ simtime = int(options.maxtime * root.clock.value)
+ print "simulating for: ", simtime
+ exit_event = m5.simulate(simtime)
+else:
+ exit_event = m5.simulate()
print 'Exiting @ cycle', m5.curTick(), 'because', exit_event.getCause()
# Simple test script
#
# Alpha: "m5 test.py"
-# MIPS: "m5 test.py -a Mips -c hello_mips"
-
-import os, optparse, sys
+# MIPS: "m5 test.py -c hello_mips"
import m5
-from m5.objects import *
+import os, optparse, sys
+m5.AddToPath('../common')
+from SEConfig import *
from FullO3Config import *
+from m5.objects import *
-# parse command-line arguments
parser = optparse.OptionParser()
parser.add_option("-c", "--cmd", default="hello",
- help="The binary to run in syscall emulation mode.")
+ help="The binary to run in syscall emulation mode.")
parser.add_option("-o", "--options", default="",
- help="The options to pass to the binary, use \" \" around the entire\
- string.")
+ help="The options to pass to the binary, use \" \" around the entire\
+ string.")
parser.add_option("-i", "--input", default="",
- help="A file of input to give to the binary.")
-parser.add_option("-t", "--timing", action="store_true",
- help="Use simple timing CPU.")
-parser.add_option("-d", "--detailed", action="store_true",
- help="Use detailed CPU.")
-parser.add_option("-m", "--maxtick", type="int",
- help="Set the maximum number of ticks to run for")
+ help="A file of input to give to the binary.")
+parser.add_option("-d", "--detailed", action="store_true")
+parser.add_option("-t", "--timing", action="store_true")
+parser.add_option("-m", "--maxtick", type="int")
(options, args) = parser.parse_args()
print "Error: script doesn't take any positional arguments"
sys.exit(1)
-# build configuration
this_dir = os.path.dirname(__file__)
process = LiveProcess()
if options.input != "":
process.input = options.input
-magicbus = Bus()
-mem = PhysicalMemory()
-
-if options.timing and options.detailed:
- print "Error: you may only specify one cpu model";
- sys.exit(1)
-
-if options.timing:
- cpu = TimingSimpleCPU()
-elif options.detailed:
+if options.detailed:
#check for SMT workload
workloads = options.cmd.split(';')
if len(workloads) > 1:
process += [smt_process, ]
smt_idx += 1
+
+if options.timing:
+ cpu = TimingSimpleCPU()
+elif options.detailed:
cpu = DetailedO3CPU()
else:
cpu = AtomicSimpleCPU()
-cpu.workload = process
-cpu.mem = magicbus
-cpu.icache_port=magicbus.port
-cpu.dcache_port=magicbus.port
-
-system = System(physmem = mem, cpu = cpu)
-mem.port = magicbus.port
-root = Root(system = system)
+
+root = MySESystem(cpu, process)
+
+if options.timing or options.detailed:
+ root.system.mem_mode = 'timing'
# instantiate configuration
m5.instantiate(root)
+++ /dev/null
-<hr size="1"><address style="align: right;"><small>
-Generated on $datetime for $projectname by <a href="http://www.doxygen.org/index.html"> doxygen</a> $doxygenversion</small></address>
-
-</body>
-</html>
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Erik Hallnor
- * Nathan Binkert
- */
-
-/**
- * @file
- * Dummy definitions of STL classes to pick up relationships in doxygen.
- */
-
-namespace std {
-
-/** STL vector class*/
-template <class T> class vector {
- public:
- /** Dummy Item */
- T item;
-};
-
-/** STL deque class */
-template <class T> class deque {
- public:
- /** Dummy Item */
- T item;
-};
-
-/** STL list class */
-template <class T> class list {
- public:
- /** Dummy Item */
- T item;
-};
-
-/** STL pair class */
-template <class X, class Y> class pair {
- public:
- /** Dummy Item */
- X item1;
- /** Dummy Item */
- Y item2;
-};
-
-}
# If a relative path is entered, it will be relative to the location
# where doxygen was started. If left blank the current directory will be used.
-OUTPUT_DIRECTORY = docs/doxygen
+OUTPUT_DIRECTORY = doxygen
# The OUTPUT_LANGUAGE tag is used to specify the language in which all
# documentation generated by doxygen is written. Doxygen will use this
# each generated HTML page. If it is left blank doxygen will generate a
# standard footer.
-HTML_FOOTER = docs/footer.html
+HTML_FOOTER = doxygen/footer.html
# The HTML_STYLESHEET tag can be used to specify a user-defined cascading
# style sheet that is used by each HTML page. It can be used to
mem/packet.cc
mem/physical.cc
mem/port.cc
+ mem/tport.cc
mem/cache/base_cache.cc
mem/cache/cache.cc
encumbered/eio/eio.cc
''')
-if env['TARGET_ISA'] == 'ALPHA_ISA':
+if env['TARGET_ISA'] == 'alpha':
syscall_emulation_sources += alpha_eio_sources
memtest_sources = Split('''
# List of headers to generate
isa_switch_hdrs = Split('''
arguments.hh
- constants.hh
faults.hh
isa_traits.hh
process.hh
regfile.hh
stacktrace.hh
+ syscallreturn.hh
tlb.hh
types.hh
utility.hh
# Pieces are in place, so create the builder.
python = sys.executable # use same Python binary used to run scons
-isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS',
- emitter = isa_desc_emitter)
+
+# Also include the CheckerCPU as one of the models if it is being
+# enabled via command line.
+if env['USE_CHECKER']:
+ isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS CheckerCPU',
+ emitter = isa_desc_emitter)
+else:
+ isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS',
+ emitter = isa_desc_emitter)
env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
* Nathan Binkert
*/
-#include "arch/alpha/tlb.hh"
+#include "arch/alpha/faults.hh"
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/osfpal.hh"
+#include "arch/alpha/tlb.hh"
#include "base/kgdb.h"
#include "base/remote_gdb.hh"
#include "base/stats/events.hh"
#ifndef __ALPHA_FAULTS_HH__
#define __ALPHA_FAULTS_HH__
-#include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/pagetable.hh"
#include "sim/faults.hh"
// The design of the "name" and "vect" functions is in sim/faults.hh
Param<Tick> boot_cpu_frequency;
SimObjectParam<PhysicalMemory *> physmem;
+ SimpleEnumParam<System::MemoryMode> mem_mode;
Param<string> kernel;
Param<string> console;
INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
INIT_PARAM(physmem, "phsyical memory"),
+ INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
+ System::MemoryModeStrings),
INIT_PARAM(kernel, "file that contains the kernel code"),
INIT_PARAM(console, "file that contains the console code"),
INIT_PARAM(pal, "file that contains palcode"),
p->name = getInstanceName();
p->boot_cpu_frequency = boot_cpu_frequency;
p->physmem = physmem;
+ p->mem_mode = mem_mode;
p->kernel_path = kernel;
p->console_path = console;
p->palcode = pal;
+ completeAccTemplate.subst(completeacc_iop))
}};
-
def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
namespace LittleEndianGuest {}
#include "arch/alpha/types.hh"
-#include "arch/alpha/constants.hh"
-#include "arch/alpha/regfile.hh"
#include "config/full_system.hh"
#include "sim/host.hh"
class StaticInstPtr;
-#if !FULL_SYSTEM
-class SyscallReturn {
- public:
- template <class T>
- SyscallReturn(T v, bool s)
- {
- retval = (uint64_t)v;
- success = s;
- }
-
- template <class T>
- SyscallReturn(T v)
- {
- success = (v >= 0);
- retval = (uint64_t)v;
- }
-
- ~SyscallReturn() {}
-
- SyscallReturn& operator=(const SyscallReturn& s) {
- retval = s.retval;
- success = s.success;
- return *this;
- }
-
- bool successful() { return success; }
- uint64_t value() { return retval; }
-
-
- private:
- uint64_t retval;
- bool success;
-};
+namespace AlphaISA
+{
+
+ using namespace LittleEndianGuest;
+
+ // These enumerate all the registers for dependence tracking.
+ enum DependenceTags {
+ // 0..31 are the integer regs 0..31
+ // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
+ FP_Base_DepTag = 40,
+ Ctrl_Base_DepTag = 72,
+ Fpcr_DepTag = 72, // floating point control register
+ Uniq_DepTag = 73,
+ Lock_Flag_DepTag = 74,
+ Lock_Addr_DepTag = 75,
+ IPR_Base_DepTag = 76
+ };
+
+ StaticInstPtr decodeInst(ExtMachInst);
+
+ const Addr PageShift = 13;
+ const Addr PageBytes = ULL(1) << PageShift;
+ const Addr PageMask = ~(PageBytes - 1);
+ const Addr PageOffset = PageBytes - 1;
-#endif
#if FULL_SYSTEM
-#include "arch/alpha/isa_fullsys_traits.hh"
-#endif
+ ////////////////////////////////////////////////////////////////////////
+ //
+ // Translation stuff
+ //
-namespace AlphaISA
-{
+ const Addr PteShift = 3;
+ const Addr NPtePageShift = PageShift - PteShift;
+ const Addr NPtePage = ULL(1) << NPtePageShift;
+ const Addr PteMask = NPtePage - 1;
-using namespace LittleEndianGuest;
+ // User Virtual
+ const Addr USegBase = ULL(0x0);
+ const Addr USegEnd = ULL(0x000003ffffffffff);
-// redirected register map, really only used for the full system case.
-extern const int reg_redir[NumIntRegs];
+ // Kernel Direct Mapped
+ const Addr K0SegBase = ULL(0xfffffc0000000000);
+ const Addr K0SegEnd = ULL(0xfffffdffffffffff);
- StaticInstPtr decodeInst(ExtMachInst);
+ // Kernel Virtual
+ const Addr K1SegBase = ULL(0xfffffe0000000000);
+ const Addr K1SegEnd = ULL(0xffffffffffffffff);
+
+ // For loading... XXX This maybe could be USegEnd?? --ali
+ const Addr LoadAddrMask = ULL(0xffffffffff);
+
+ ////////////////////////////////////////////////////////////////////////
+ //
+ // Interrupt levels
+ //
+ enum InterruptLevels
+ {
+ INTLEVEL_SOFTWARE_MIN = 4,
+ INTLEVEL_SOFTWARE_MAX = 19,
+
+ INTLEVEL_EXTERNAL_MIN = 20,
+ INTLEVEL_EXTERNAL_MAX = 34,
+
+ INTLEVEL_IRQ0 = 20,
+ INTLEVEL_IRQ1 = 21,
+ INTINDEX_ETHERNET = 0,
+ INTINDEX_SCSI = 1,
+ INTLEVEL_IRQ2 = 22,
+ INTLEVEL_IRQ3 = 23,
+
+ INTLEVEL_SERIAL = 33,
+
+ NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
+ };
+
+
+ // EV5 modes
+ enum mode_type
+ {
+ mode_kernel = 0, // kernel
+ mode_executive = 1, // executive (unused by unix)
+ mode_supervisor = 2, // supervisor (unused by unix)
+ mode_user = 3, // user mode
+ mode_number // number of modes
+ };
+
+#endif
-#if !FULL_SYSTEM
- static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
+#if FULL_SYSTEM
+ ////////////////////////////////////////////////////////////////////////
+ //
+ // Internal Processor Reigsters
+ //
+ enum md_ipr_names
{
- // check for error condition. Alpha syscall convention is to
- // indicate success/failure in reg a3 (r19) and put the
- // return value itself in the standard return value reg (v0).
- if (return_value.successful()) {
- // no error
- regs->setIntReg(SyscallSuccessReg, 0);
- regs->setIntReg(ReturnValueReg, return_value.value());
- } else {
- // got an error, return details
- regs->setIntReg(SyscallSuccessReg, (IntReg)-1);
- regs->setIntReg(ReturnValueReg, -return_value.value());
- }
- }
+ IPR_ISR = 0x100, // interrupt summary register
+ IPR_ITB_TAG = 0x101, // ITLB tag register
+ IPR_ITB_PTE = 0x102, // ITLB page table entry register
+ IPR_ITB_ASN = 0x103, // ITLB address space register
+ IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register
+ IPR_ITB_IA = 0x105, // ITLB invalidate all register
+ IPR_ITB_IAP = 0x106, // ITLB invalidate all process register
+ IPR_ITB_IS = 0x107, // ITLB invalidate select register
+ IPR_SIRR = 0x108, // software interrupt request register
+ IPR_ASTRR = 0x109, // asynchronous system trap request register
+ IPR_ASTER = 0x10a, // asynchronous system trap enable register
+ IPR_EXC_ADDR = 0x10b, // exception address register
+ IPR_EXC_SUM = 0x10c, // exception summary register
+ IPR_EXC_MASK = 0x10d, // exception mask register
+ IPR_PAL_BASE = 0x10e, // PAL base address register
+ IPR_ICM = 0x10f, // instruction current mode
+ IPR_IPLR = 0x110, // interrupt priority level register
+ IPR_INTID = 0x111, // interrupt ID register
+ IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register
+ IPR_IVPTBR = 0x113, // virtual page table base register
+ IPR_HWINT_CLR = 0x115, // H/W interrupt clear register
+ IPR_SL_XMIT = 0x116, // serial line transmit register
+ IPR_SL_RCV = 0x117, // serial line receive register
+ IPR_ICSR = 0x118, // instruction control and status register
+ IPR_IC_FLUSH = 0x119, // instruction cache flush control
+ IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register
+ IPR_PMCTR = 0x11c, // performance counter register
+
+ // PAL temporary registers...
+ // register meanings gleaned from osfpal.s source code
+ IPR_PALtemp0 = 0x140, // local scratch
+ IPR_PALtemp1 = 0x141, // local scratch
+ IPR_PALtemp2 = 0x142, // entUna
+ IPR_PALtemp3 = 0x143, // CPU specific impure area pointer
+ IPR_PALtemp4 = 0x144, // memory management temp
+ IPR_PALtemp5 = 0x145, // memory management temp
+ IPR_PALtemp6 = 0x146, // memory management temp
+ IPR_PALtemp7 = 0x147, // entIF
+ IPR_PALtemp8 = 0x148, // intmask
+ IPR_PALtemp9 = 0x149, // entSys
+ IPR_PALtemp10 = 0x14a, // ??
+ IPR_PALtemp11 = 0x14b, // entInt
+ IPR_PALtemp12 = 0x14c, // entArith
+ IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL
+ IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL
+ IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL
+ IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0>
+ IPR_PALtemp17 = 0x151, // sysval
+ IPR_PALtemp18 = 0x152, // usp
+ IPR_PALtemp19 = 0x153, // ksp
+ IPR_PALtemp20 = 0x154, // PTBR
+ IPR_PALtemp21 = 0x155, // entMM
+ IPR_PALtemp22 = 0x156, // kgp
+ IPR_PALtemp23 = 0x157, // PCBB
+
+ IPR_DTB_ASN = 0x200, // DTLB address space number register
+ IPR_DTB_CM = 0x201, // DTLB current mode register
+ IPR_DTB_TAG = 0x202, // DTLB tag register
+ IPR_DTB_PTE = 0x203, // DTLB page table entry register
+ IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register
+
+ IPR_MM_STAT = 0x205, // data MMU fault status register
+ IPR_VA = 0x206, // fault virtual address register
+ IPR_VA_FORM = 0x207, // formatted virtual address register
+ IPR_MVPTBR = 0x208, // MTU virtual page table base register
+ IPR_DTB_IAP = 0x209, // DTLB invalidate all process register
+ IPR_DTB_IA = 0x20a, // DTLB invalidate all register
+ IPR_DTB_IS = 0x20b, // DTLB invalidate single register
+ IPR_ALT_MODE = 0x20c, // alternate mode register
+ IPR_CC = 0x20d, // cycle counter register
+ IPR_CC_CTL = 0x20e, // cycle counter control register
+ IPR_MCSR = 0x20f, // MTU control register
+
+ IPR_DC_FLUSH = 0x210,
+ IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register
+ IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register
+ IPR_DC_TEST_TAG = 0x214, // Dcache test tag register
+ IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register
+ IPR_DC_MODE = 0x216, // Dcache mode register
+ IPR_MAF_MODE = 0x217, // miss address file mode register
+
+ NumInternalProcRegs // number of IPR registers
+ };
+#else
+ const int NumInternalProcRegs = 0;
#endif
+
+ // Constants Related to the number of registers
+
+ const int NumIntArchRegs = 32;
+ const int NumPALShadowRegs = 8;
+ const int NumFloatArchRegs = 32;
+ // @todo: Figure out what this number really should be.
+ const int NumMiscArchRegs = 32;
+
+ const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
+ const int NumFloatRegs = NumFloatArchRegs;
+ const int NumMiscRegs = NumMiscArchRegs;
+
+ const int TotalNumRegs = NumIntRegs + NumFloatRegs +
+ NumMiscRegs + NumInternalProcRegs;
+
+ const int TotalDataRegs = NumIntRegs + NumFloatRegs;
+
+ // Static instruction parameters
+ const int MaxInstSrcRegs = 3;
+ const int MaxInstDestRegs = 2;
+
+ // semantically meaningful register indices
+ const int ZeroReg = 31; // architecturally meaningful
+ // the rest of these depend on the ABI
+ const int StackPointerReg = 30;
+ const int GlobalPointerReg = 29;
+ const int ProcedureValueReg = 27;
+ const int ReturnAddressReg = 26;
+ const int ReturnValueReg = 0;
+ const int FramePointerReg = 15;
+ const int ArgumentReg0 = 16;
+ const int ArgumentReg1 = 17;
+ const int ArgumentReg2 = 18;
+ const int ArgumentReg3 = 19;
+ const int ArgumentReg4 = 20;
+ const int ArgumentReg5 = 21;
+ const int SyscallNumReg = ReturnValueReg;
+ const int SyscallPseudoReturnReg = ArgumentReg4;
+ const int SyscallSuccessReg = 19;
+
+ const int LogVMPageSize = 13; // 8K bytes
+ const int VMPageSize = (1 << LogVMPageSize);
+
+ const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
+
+ const int MachineBytes = 8;
+ const int WordBytes = 4;
+ const int HalfwordBytes = 2;
+ const int ByteBytes = 1;
+
+ // return a no-op instruction... used for instruction fetch faults
+ // Alpha UNOP (ldq_u r31,0(r0))
+ const ExtMachInst NoopMachInst = 0x2ffe0000;
+
+ // redirected register map, really only used for the full system case.
+ extern const int reg_redir[NumIntRegs];
+
};
#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
#include "arch/alpha/linux/linux.hh"
+#include <fcntl.h>
+
// open(2) flags translation table
OpenFlagTransTable AlphaLinux::openFlagTable[] = {
#ifdef _MSC_VER
Param<Tick> boot_cpu_frequency;
SimObjectParam<PhysicalMemory *> physmem;
+ SimpleEnumParam<System::MemoryMode> mem_mode;
Param<string> kernel;
Param<string> console;
INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
INIT_PARAM(physmem, "phsyical memory"),
+ INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
+ System::MemoryModeStrings),
INIT_PARAM(kernel, "file that contains the kernel code"),
INIT_PARAM(console, "file that contains the console code"),
INIT_PARAM(pal, "file that contains palcode"),
p->name = getInstanceName();
p->boot_cpu_frequency = boot_cpu_frequency;
p->physmem = physmem;
+ p->mem_mode = mem_mode;
p->kernel_path = kernel;
p->console_path = console;
p->palcode = pal;
--- /dev/null
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Steve Reinhardt
+ */
+
+#ifndef __ARCH_ALPHA_PAGETABLE_H__
+#define __ARCH_ALPHA_PAGETABLE_H__
+
+#include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/utility.hh"
+#include "config/full_system.hh"
+
+namespace AlphaISA {
+
+#if FULL_SYSTEM
+ struct VAddr
+ {
+ static const int ImplBits = 43;
+ static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
+ static const Addr UnImplMask = ~ImplMask;
+
+ VAddr(Addr a) : addr(a) {}
+ Addr addr;
+ operator Addr() const { return addr; }
+ const VAddr &operator=(Addr a) { addr = a; return *this; }
+
+ Addr vpn() const { return (addr & ImplMask) >> PageShift; }
+ Addr page() const { return addr & PageMask; }
+ Addr offset() const { return addr & PageOffset; }
+
+ Addr level3() const
+ { return AlphaISA::PteAddr(addr >> PageShift); }
+ Addr level2() const
+ { return AlphaISA::PteAddr(addr >> NPtePageShift + PageShift); }
+ Addr level1() const
+ { return AlphaISA::PteAddr(addr >> 2 * NPtePageShift + PageShift); }
+ };
+
+ struct PageTableEntry
+ {
+ PageTableEntry(uint64_t e) : entry(e) {}
+ uint64_t entry;
+ operator uint64_t() const { return entry; }
+ const PageTableEntry &operator=(uint64_t e) { entry = e; return *this; }
+ const PageTableEntry &operator=(const PageTableEntry &e)
+ { entry = e.entry; return *this; }
+
+ Addr _pfn() const { return (entry >> 32) & 0xffffffff; }
+ Addr _sw() const { return (entry >> 16) & 0xffff; }
+ int _rsv0() const { return (entry >> 14) & 0x3; }
+ bool _uwe() const { return (entry >> 13) & 0x1; }
+ bool _kwe() const { return (entry >> 12) & 0x1; }
+ int _rsv1() const { return (entry >> 10) & 0x3; }
+ bool _ure() const { return (entry >> 9) & 0x1; }
+ bool _kre() const { return (entry >> 8) & 0x1; }
+ bool _nomb() const { return (entry >> 7) & 0x1; }
+ int _gh() const { return (entry >> 5) & 0x3; }
+ bool _asm() const { return (entry >> 4) & 0x1; }
+ bool _foe() const { return (entry >> 3) & 0x1; }
+ bool _fow() const { return (entry >> 2) & 0x1; }
+ bool _for() const { return (entry >> 1) & 0x1; }
+ bool valid() const { return (entry >> 0) & 0x1; }
+
+ Addr paddr() const { return _pfn() << PageShift; }
+ };
+
+ // ITB/DTB page table entry
+ struct PTE
+ {
+ Addr tag; // virtual page number tag
+ Addr ppn; // physical page number
+ uint8_t xre; // read permissions - VMEM_PERM_* mask
+ uint8_t xwe; // write permissions - VMEM_PERM_* mask
+ uint8_t asn; // address space number
+ bool asma; // address space match
+ bool fonr; // fault on read
+ bool fonw; // fault on write
+ bool valid; // valid page table entry
+
+ void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string §ion);
+ };
+#endif
+};
+#endif // __ARCH_ALPHA_PAGETABLE_H__
+
* Ali Saidi
*/
-#include "arch/alpha/constants.hh"
+#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/process.hh"
#include "base/loader/object_file.hh"
#include "base/misc.hh"
#define __ARCH_ALPHA_REGFILE_HH__
#include "arch/alpha/types.hh"
-#include "arch/alpha/constants.hh"
+#include "arch/alpha/isa_traits.hh"
#include "sim/faults.hh"
+#include <string>
+
+//XXX These should be implemented by someone who knows the alpha stuff better
+
class Checkpoint;
class ThreadContext;
namespace AlphaISA
{
+
+ static inline std::string getIntRegName(RegIndex)
+ {
+ return "";
+ }
+
+ static inline std::string getFloatRegName(RegIndex)
+ {
+ return "";
+ }
+
+ static inline std::string getMiscRegName(RegIndex)
+ {
+ return "";
+ }
+
class IntRegFile
{
protected:
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string §ion);
- enum ContextParam
- {
- CONTEXT_PALMODE
- };
-
- typedef bool ContextVal;
-
- void changeContext(ContextParam param, ContextVal val)
+ void changeContext(RegContextParam param, RegContextVal val)
{
//This would be an alternative place to call/implement
//the swapPALShadow function
--- /dev/null
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ * Gabe Black
+ */
+
+#ifndef __ARCH_ALPHA_SYSCALLRETURN_HH__
+#define __ARCH_ALPHA_SYSCALLRETURN_HH__
+
+class SyscallReturn {
+ public:
+ template <class T>
+ SyscallReturn(T v, bool s)
+ {
+ retval = (uint64_t)v;
+ success = s;
+ }
+
+ template <class T>
+ SyscallReturn(T v)
+ {
+ success = (v >= 0);
+ retval = (uint64_t)v;
+ }
+
+ ~SyscallReturn() {}
+
+ SyscallReturn& operator=(const SyscallReturn& s) {
+ retval = s.retval;
+ success = s.success;
+ return *this;
+ }
+
+ bool successful() { return success; }
+ uint64_t value() { return retval; }
+
+
+ private:
+ uint64_t retval;
+ bool success;
+};
+
+namespace AlphaISA
+{
+ static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
+ {
+ // check for error condition. Alpha syscall convention is to
+ // indicate success/failure in reg a3 (r19) and put the
+ // return value itself in the standard return value reg (v0).
+ if (return_value.successful()) {
+ // no error
+ regs->setIntReg(SyscallSuccessReg, 0);
+ regs->setIntReg(ReturnValueReg, return_value.value());
+ } else {
+ // got an error, return details
+ regs->setIntReg(SyscallSuccessReg, (IntReg)-1);
+ regs->setIntReg(ReturnValueReg, -return_value.value());
+ }
+ }
+}
+
+#endif
Param<Tick> boot_cpu_frequency;
SimObjectParam<PhysicalMemory *> physmem;
+ SimpleEnumParam<System::MemoryMode> mem_mode;
Param<std::string> kernel;
Param<std::string> console;
INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
INIT_PARAM(physmem, "phsyical memory"),
+ INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
+ System::MemoryModeStrings),
INIT_PARAM(kernel, "file that contains the kernel code"),
INIT_PARAM(console, "file that contains the console code"),
INIT_PARAM(pal, "file that contains palcode"),
p->name = getInstanceName();
p->boot_cpu_frequency = boot_cpu_frequency;
p->physmem = physmem;
+ p->mem_mode = mem_mode;
p->kernel_path = kernel;
p->console_path = console;
p->palcode = pal;
#include <string>
#include <vector>
+#include "arch/alpha/pagetable.hh"
#include "arch/alpha/tlb.hh"
+#include "arch/alpha/faults.hh"
#include "base/inifile.hh"
#include "base/str.hh"
#include "base/trace.hh"
#include "arch/alpha/ev5.hh"
#include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/faults.hh"
+#include "arch/alpha/utility.hh"
+#include "arch/alpha/vtophys.hh"
#include "base/statistics.hh"
#include "mem/request.hh"
+#include "sim/faults.hh"
#include "sim/sim_object.hh"
class ThreadContext;
Param<Tick> boot_cpu_frequency;
SimObjectParam<PhysicalMemory *> physmem;
+ SimpleEnumParam<System::MemoryMode> mem_mode;
Param<string> kernel;
Param<string> console;
INIT_PARAM(boot_cpu_frequency, "frequency of the boot cpu"),
INIT_PARAM(physmem, "phsyical memory"),
+ INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
+ System::MemoryModeStrings),
INIT_PARAM(kernel, "file that contains the kernel code"),
INIT_PARAM(console, "file that contains the console code"),
INIT_PARAM(pal, "file that contains palcode"),
p->name = getInstanceName();
p->boot_cpu_frequency = boot_cpu_frequency;
p->physmem = physmem;
+ p->mem_mode = mem_mode;
p->kernel_path = kernel;
p->console_path = console;
p->palcode = pal;
#ifndef __ARCH_ALPHA_TYPES_HH__
#define __ARCH_ALPHA_TYPES_HH__
-#include "sim/host.hh"
+#include <inttypes.h>
namespace AlphaISA
{
MiscReg ctrlreg;
} AnyReg;
+ enum RegContextParam
+ {
+ CONTEXT_PALMODE
+ };
+
+ typedef bool RegContextVal;
+
enum annotes {
ANNOTE_NONE = 0,
// An impossible number for instruction annotations
#include "config/full_system.hh"
#include "arch/alpha/types.hh"
-#include "arch/alpha/constants.hh"
+#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/regfile.hh"
#include "base/misc.hh"
#define __ARCH_ALPHA_VTOPHYS_H__
#include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/pagetable.hh"
+#include "arch/alpha/utility.hh"
class ThreadContext;
class FunctionalPort;
namespace AlphaISA {
-PageTableEntry
-kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr);
+ PageTableEntry
+ kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr);
-Addr vtophys(Addr vaddr);
-Addr vtophys(ThreadContext *tc, Addr vaddr);
+ Addr vtophys(Addr vaddr);
+ Addr vtophys(ThreadContext *tc, Addr vaddr);
-void CopyOut(ThreadContext *tc, void *dst, Addr src, size_t len);
-void CopyIn(ThreadContext *tc, Addr dst, void *src, size_t len);
-void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen);
-void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr);
+ void CopyOut(ThreadContext *tc, void *dst, Addr src, size_t len);
+ void CopyIn(ThreadContext *tc, Addr dst, void *src, size_t len);
+ void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen);
+ void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr);
};
#endif // __ARCH_ALPHA_VTOPHYS_H__
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Korey Sewell
+ * Authors: Gabe Black
+ * Korey Sewell
*/
#include "arch/mips/faults.hh"
#include "cpu/thread_context.hh"
#include "cpu/base.hh"
#include "base/trace.hh"
+
#if !FULL_SYSTEM
#include "sim/process.hh"
#include "mem/page_table.hh"
FaultVect IntegerOverflowFault::_vect = 0x0501;
FaultStat IntegerOverflowFault::_count;
-#if FULL_SYSTEM
-
-void MipsFault::invoke(ThreadContext * tc)
-{
- FaultBase::invoke(tc);
- countStat()++;
-
- // exception restart address
- if (setRestartAddress() || !tc->inPalMode())
- tc->setMiscReg(MipsISA::IPR_EXC_ADDR, tc->readPC());
-
- if (skipFaultingInstruction()) {
- // traps... skip faulting instruction.
- tc->setMiscReg(MipsISA::IPR_EXC_ADDR,
- tc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4);
- }
-
- tc->setPC(tc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect());
- tc->setNextPC(tc->readPC() + sizeof(MachInst));
-}
-
-void ArithmeticFault::invoke(ThreadContext * tc)
-{
- FaultBase::invoke(tc);
- panic("Arithmetic traps are unimplemented!");
-}
-
-#else //!FULL_SYSTEM
-
void PageTableFault::invoke(ThreadContext *tc)
{
Process *p = tc->getProcessPtr();
}
}
-#endif
} // namespace MipsISA
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Korey Sewell
+ * Authors: Gabe Black
+ * Korey Sewell
*/
#ifndef __MIPS_FAULTS_HH__
ccprintf(ss, "%-10s ", mnemonic);
- if(_numDestRegs > 0){
- printReg(ss, _destRegIdx[0]);
+ // Need to find standard way to not print
+ // this info. Maybe add bool variable to
+ // class?
+ if (mnemonic != "syscall") {
+ if(_numDestRegs > 0){
+ printReg(ss, _destRegIdx[0]);
+ }
+
+ if(_numSrcRegs > 0) {
+ ss << ", ";
+ printReg(ss, _srcRegIdx[0]);
+ }
+
+ if(_numSrcRegs > 1) {
+ ss << ", ";
+ printReg(ss, _srcRegIdx[1]);
+ }
}
- if(_numSrcRegs > 0) {
- ss << ", ";
- printReg(ss, _srcRegIdx[0]);
- }
-
- if(_numSrcRegs > 1) {
- ss << ", ";
- printReg(ss, _srcRegIdx[1]);
- }
-
-
+ // Should we define a separate inst. class
+ // just for two insts?
if(mnemonic == "sll" || mnemonic == "sra"){
ccprintf(ss,", %d",SA);
}
format BasicOp {
0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
- 0x4: syscall({{ xc->syscall(R2); }}, IsNonSpeculative);
+ 0x4: syscall({{ xc->syscall(R2); }},
+ IsSerializeAfter, IsNonSpeculative);
0x7: sync({{ ; }}, IsMemBarrier);
}
0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
{{ uint64_t tmp = write_result;
Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
- }}, mem_flags=LOCKED);
+ }}, mem_flags=LOCKED, inst_flags = IsStoreConditional);
format StoreMemory {
0x1: swc1({{ Mem.uw = Ft.uw; }});
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
-// Authors: Korey Sewell
+// Authors: Steve Reinhardt
+// Korey Sewell
// Declarations for execute() methods.
def template BasicExecDeclare {{
return new %(class_name)s("%(mnemonic)s", machInst);
}};
-// The most basic instruction format... used only for a few misc. insts
+// The most basic instruction format...
def format BasicOp(code, *flags) {{
iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
output header {{
#include <iostream>
- using namespace std;
/**
* Base class for instructions whose disassembly is not purely a
else:
inst_flags += (x, )
+ #Take into account uncond. branch instruction
if 'cond == 1' in code:
- inst_flags += ('IsCondControl', )
+ inst_flags += ('IsUnCondControl', )
else:
- inst_flags += ('IsUncondControl', )
+ inst_flags += ('IsCondControl', )
#Condition code
code = 'bool cond;\n' + code
//
output header {{
#include <iostream>
- using namespace std;
/**
* Base class for integer operations.
*/
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
-// Authors: Gabe Black
+// Authors: Steve Reinhardt
// Korey Sewell
////////////////////////////////////////////////////////////////////
def template CompleteAccDeclare {{
- Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
+ Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
def template LoadCompleteAcc {{
- Fault %(class_name)s::completeAcc(uint8_t *data,
+ Fault %(class_name)s::completeAcc(Packet *pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
%(fp_enable_check)s;
%(op_decl)s;
- memcpy(&Mem, data, sizeof(Mem));
+ Mem = pkt->get<typeof(Mem)>();
if (fault == NoFault) {
%(memacc_code)s;
{
Addr EA;
Fault fault = NoFault;
- uint64_t write_result = 0;
%(fp_enable_check)s;
%(op_decl)s;
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, &write_result);
+ memAccessFlags, NULL);
if (traceData) { traceData->setData(Mem); }
}
def template StoreCompleteAcc {{
- Fault %(class_name)s::completeAcc(uint8_t *data,
+ Fault %(class_name)s::completeAcc(Packet *pkt,
+ %(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(fp_enable_check)s;
+ %(op_dest_decl)s;
+
+ if (fault == NoFault) {
+ %(postacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+
+ return fault;
+ }
+}};
+
+def template StoreCondCompleteAcc {{
+ Fault %(class_name)s::completeAcc(Packet *pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
- uint64_t write_result = 0;
%(fp_enable_check)s;
%(op_dest_decl)s;
- memcpy(&write_result, data, sizeof(write_result));
+ uint64_t write_result = pkt->req->getScResult();
if (fault == NoFault) {
%(postacc_code)s;
def template MiscCompleteAcc {{
- Fault %(class_name)s::completeAcc(uint8_t *data,
+ Fault %(class_name)s::completeAcc(Packet *pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
- postacc_code, exec_template_base = 'Store')
+ postacc_code, exec_template_base = 'StoreCond')
}};
if (exec_template_base == 'Load'):
initiateacc_cblk = CodeBlock(ea_code + memacc_code)
completeacc_cblk = CodeBlock(memacc_code + postacc_code)
- elif (exec_template_base == 'Store'):
+ elif (exec_template_base.startswith('Store')):
initiateacc_cblk = CodeBlock(ea_code + memacc_code)
completeacc_cblk = CodeBlock(postacc_code)
else:
initiateacc_iop.memacc_code = memacc_cblk.code
completeacc_iop.memacc_code = memacc_cblk.code
completeacc_iop.postacc_code = postacc_cblk.code
- elif (exec_template_base == 'Store'):
+ elif (exec_template_base.startswith('Store')):
initiateacc_iop.ea_code = ea_cblk.code
initiateacc_iop.memacc_code = memacc_cblk.code
completeacc_iop.postacc_code = postacc_cblk.code
memacc_iop.constructor += s
# select templates
+
+ # define aliases... most StoreCond templates are the same as the
+ # corresponding Store templates (only CompleteAcc is different).
+ StoreCondMemAccExecute = StoreMemAccExecute
+ StoreCondExecute = StoreExecute
+ StoreCondInitiateAcc = StoreInitiateAcc
+
memAccExecTemplate = eval(exec_template_base + 'MemAccExecute')
fullExecTemplate = eval(exec_template_base + 'Execute')
initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
+ initiateAccTemplate.subst(initiateacc_iop)
+ completeAccTemplate.subst(completeacc_iop))
}};
-
output header {{
std::string inst2string(MachInst machInst);
}};
std::string inst2string(MachInst machInst)
{
- string str = "";
+ std::string str = "";
uint32_t mask = 0x80000000;
for(int i=0; i < 32; i++) {
*/
#include "arch/mips/isa_traits.hh"
-//#include "config/full_system.hh"
-#include "cpu/static_inst.hh"
+#include "arch/mips/regfile/regfile.hh"
#include "sim/serialize.hh"
#include "base/bitfield.hh"
using namespace MipsISA;
using namespace std;
-
void
MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
{
panic("Copy Regs Not Implemented Yet\n");
}
+void
+MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+ panic("Copy Misc. Regs Not Implemented Yet\n");
+}
+
void
MipsISA::MiscRegFile::copyMiscRegs(ThreadContext *tc)
{
RegFile::serialize(std::ostream &os)
{
intRegFile.serialize(os);
- //SERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs);
+ //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
+ //SERIALZE_ARRAY(miscRegFile);
//SERIALIZE_SCALAR(miscRegs.fpcr);
- //SERIALIZE_SCALAR(miscRegs.uniq);
//SERIALIZE_SCALAR(miscRegs.lock_flag);
//SERIALIZE_SCALAR(miscRegs.lock_addr);
SERIALIZE_SCALAR(pc);
RegFile::unserialize(Checkpoint *cp, const std::string §ion)
{
intRegFile.unserialize(cp, section);
- //UNSERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs);
+ //UNSERIALIZE_ARRAY(floatRegFile);
+ //UNSERIALZE_ARRAY(miscRegFile);
//UNSERIALIZE_SCALAR(miscRegs.fpcr);
- //UNSERIALIZE_SCALAR(miscRegs.uniq);
//UNSERIALIZE_SCALAR(miscRegs.lock_flag);
//UNSERIALIZE_SCALAR(miscRegs.lock_addr);
UNSERIALIZE_SCALAR(pc);
#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
#define __ARCH_MIPS_ISA_TRAITS_HH__
-#include "arch/mips/constants.hh"
#include "arch/mips/types.hh"
-#include "arch/mips/regfile/regfile.hh"
-#include "arch/mips/faults.hh"
-#include "arch/mips/utility.hh"
-#include "base/misc.hh"
-#include "config/full_system.hh"
-#include "sim/byteswap.hh"
#include "sim/host.hh"
-#include "sim/faults.hh"
-
-#include <vector>
-
-class FastCPU;
-class FullCPU;
-class Checkpoint;
-class ThreadContext;
namespace LittleEndianGuest {};
#define TARGET_MIPS
-class StaticInst;
class StaticInstPtr;
-class SyscallReturn {
- public:
- template <class T>
- SyscallReturn(T v, bool s)
- {
- retval = (uint32_t)v;
- success = s;
- }
-
- template <class T>
- SyscallReturn(T v)
- {
- success = (v >= 0);
- retval = (uint32_t)v;
- }
-
- ~SyscallReturn() {}
-
- SyscallReturn& operator=(const SyscallReturn& s) {
- retval = s.retval;
- success = s.success;
- return *this;
- }
-
- bool successful() { return success; }
- uint64_t value() { return retval; }
-
-
- private:
- uint64_t retval;
- bool success;
-};
-
namespace MipsISA
{
using namespace LittleEndianGuest;
- static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
- {
- if (return_value.successful()) {
- // no error
- regs->setIntReg(SyscallSuccessReg, 0);
- regs->setIntReg(ReturnValueReg1, return_value.value());
- } else {
- // got an error, return details
- regs->setIntReg(SyscallSuccessReg, (IntReg) -1);
- regs->setIntReg(ReturnValueReg1, -return_value.value());
- }
- }
-
StaticInstPtr decodeInst(ExtMachInst);
- static inline ExtMachInst
- makeExtMI(MachInst inst, const uint64_t &pc) {
-#if FULL_SYSTEM
- ExtMachInst ext_inst = inst;
- if (pc && 0x1)
- return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
- else
- return ext_inst;
-#else
- return ExtMachInst(inst);
-#endif
- }
-
- /**
- * Function to insure ISA semantics about 0 registers.
- * @param tc The thread context.
- */
- template <class TC>
- void zeroRegisters(TC *tc);
-
- const Addr MaxAddr = (Addr)-1;
-
- void copyRegs(ThreadContext *src, ThreadContext *dest);
-
- // Machine operations
-
- void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
- int regnum);
-
- void restoreMachineReg(RegFile ®s, const AnyReg ®,
- int regnum);
-
-#if 0
- static void serializeSpecialRegs(const Serializable::Proxy &proxy,
- const RegFile ®s);
-
- static void unserializeSpecialRegs(const IniFile *db,
- const std::string &category,
- ConfigNode *node,
- RegFile ®s);
-#endif
-
- static inline Addr alignAddress(const Addr &addr,
- unsigned int nbytes) {
- return (addr & ~(nbytes - 1));
- }
-
- // Instruction address compression hooks
- static inline Addr realPCToFetchPC(const Addr &addr) {
- return addr;
- }
-
- static inline Addr fetchPCToRealPC(const Addr &addr) {
- return addr;
- }
-
- // the size of "fetched" instructions (not necessarily the size
- // of real instructions for PISA)
- static inline size_t fetchInstSize() {
- return sizeof(MachInst);
- }
-
- static inline MachInst makeRegisterCopy(int dest, int src) {
- panic("makeRegisterCopy not implemented");
- return 0;
- }
+ const Addr PageShift = 13;
+ const Addr PageBytes = ULL(1) << PageShift;
+ const Addr PageMask = ~(PageBytes - 1);
+ const Addr PageOffset = PageBytes - 1;
+
+ // return a no-op instruction... used for instruction fetch faults
+ const ExtMachInst NoopMachInst = 0x00000000;
+
+ // Constants Related to the number of registers
+ const int NumIntArchRegs = 32;
+ const int NumIntSpecialRegs = 2;
+ const int NumFloatArchRegs = 32;
+ const int NumFloatSpecialRegs = 5;
+ const int NumControlRegs = 265;
+ const int NumInternalProcRegs = 0;
+
+ const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
+ const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
+ const int NumMiscRegs = NumControlRegs;
+
+ const int TotalNumRegs = NumIntRegs + NumFloatRegs +
+ NumMiscRegs + 0/*NumInternalProcRegs*/;
+
+ const int TotalDataRegs = NumIntRegs + NumFloatRegs;
+
+ // Static instruction parameters
+ const int MaxInstSrcRegs = 3;
+ const int MaxInstDestRegs = 2;
+
+ // semantically meaningful register indices
+ const int ZeroReg = 0;
+ const int AssemblerReg = 1;
+ const int ReturnValueReg = 2;
+ const int ReturnValueReg1 = 2;
+ const int ReturnValueReg2 = 3;
+ const int ArgumentReg0 = 4;
+ const int ArgumentReg1 = 5;
+ const int ArgumentReg2 = 6;
+ const int ArgumentReg3 = 7;
+ const int KernelReg0 = 26;
+ const int KernelReg1 = 27;
+ const int GlobalPointerReg = 28;
+ const int StackPointerReg = 29;
+ const int FramePointerReg = 30;
+ const int ReturnAddressReg = 31;
+
+ const int SyscallNumReg = ReturnValueReg1;
+ const int SyscallPseudoReturnReg = ReturnValueReg1;
+ const int SyscallSuccessReg = ArgumentReg3;
+
+ const int LogVMPageSize = 13; // 8K bytes
+ const int VMPageSize = (1 << LogVMPageSize);
+
+ const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
+
+ const int MachineBytes = 4;
+ const int WordBytes = 4;
+ const int HalfwordBytes = 2;
+ const int ByteBytes = 1;
+
+ // These help enumerate all the registers for dependence tracking.
+ const int FP_Base_DepTag = 34;
+ const int Ctrl_Base_DepTag = 257;
+
+ const int ANNOTE_NONE = 0;
+ const uint32_t ITOUCH_ANNOTE = 0xffffffff;
};
#include "arch/mips/linux/linux.hh"
+#include <fcntl.h>
+
// open(2) flags translation table
OpenFlagTransTable MipsLinux::openFlagTable[] = {
#ifdef _MSC_VER
std::vector<std::string> &envp);
void startup();
+
};
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
+ */
+
+#ifndef __ARCH_MIPS_REGFILE_HH__
+#define __ARCH_MIPS_REGFILE_HH__
+
+#include "arch/mips/regfile/regfile.hh"
+
+#endif
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __ARCH_MIPS_FLOAT_REGFILE_HH__
-#define __ARCH_MIPS_FLOAT_REGFILE_HH__
+#ifndef __ARCH_MIPS_REGFILE_FLOAT_REGFILE_HH__
+#define __ARCH_MIPS_REGFILE_FLOAT_REGFILE_HH__
#include "arch/mips/types.hh"
-#include "arch/mips/constants.hh"
+#include "arch/mips/isa_traits.hh"
#include "base/misc.hh"
#include "base/bitfield.hh"
-#include "config/full_system.hh"
-#include "sim/byteswap.hh"
#include "sim/faults.hh"
-#include "sim/host.hh"
+
+#include <string>
class Checkpoint;
-class ExecContext;
-class Regfile;
namespace MipsISA
{
+ static inline std::string getFloatRegName(RegIndex)
+ {
+ return "";
+ }
+
+ const uint32_t MIPS32_QNAN = 0x7fbfffff;
+ const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff);
+
+ enum FPControlRegNums {
+ FIR = NumFloatArchRegs,
+ FCCR,
+ FEXR,
+ FENR,
+ FCSR
+ };
+
+ enum FCSRBits {
+ Inexact = 1,
+ Underflow,
+ Overflow,
+ DivideByZero,
+ Invalid,
+ Unimplemented
+ };
+
+ enum FCSRFields {
+ Flag_Field = 1,
+ Enable_Field = 6,
+ Cause_Field = 11
+ };
+
+ const int SingleWidth = 32;
+ const int SingleBytes = SingleWidth / 4;
+
+ const int DoubleWidth = 64;
+ const int DoubleBytes = DoubleWidth / 4;
+
+ const int QuadWidth = 128;
+ const int QuadBytes = QuadWidth / 4;
+
class FloatRegFile
{
protected:
Fault setReg(int floatReg, const FloatRegVal &val, int width)
{
- using namespace std;
switch(width)
{
case SingleWidth:
Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
{
- using namespace std;
switch(width)
{
* Authors: Korey Sewell
*/
-#ifndef __ARCH_MIPS_INT_REGFILE_HH__
-#define __ARCH_MIPS_INT_REGFILE_HH__
+#ifndef __ARCH_MIPS_REGFILE_INT_REGFILE_HH__
+#define __ARCH_MIPS_REGFILE_INT_REGFILE_HH__
#include "arch/mips/types.hh"
-#include "arch/mips/constants.hh"
+#include "arch/mips/isa_traits.hh"
#include "base/misc.hh"
#include "sim/faults.hh"
class Checkpoint;
class ThreadContext;
-class Regfile;
namespace MipsISA
{
+ static inline std::string getIntRegName(RegIndex)
+ {
+ return "";
+ }
+
+ enum MiscIntRegNums {
+ HI = NumIntArchRegs,
+ LO
+ };
+
class IntRegFile
{
protected:
* Authors: Korey Sewell
*/
-#ifndef __ARCH_MIPS_MISC_REGFILE_HH__
-#define __ARCH_MIPS_MISC_REGFILE_HH__
+#ifndef __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__
+#define __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__
#include "arch/mips/types.hh"
-#include "arch/mips/constants.hh"
#include "sim/faults.hh"
-class Checkpoint;
class ThreadContext;
-class Regfile;
namespace MipsISA
{
+ static inline std::string getMiscRegName(RegIndex)
+ {
+ return "";
+ }
+
+ //Coprocessor 0 Register Names
+ enum MiscRegTags {
+ //Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
+ //(Register Number-Register Select) Summary of Register
+ //------------------------------------------------------
+ Index = 0, //Bank 0: 0 - 3
+ MVPControl,
+ MVPConf0,
+ MVPConf1,
+
+ Random = 8, //Bank 1: 8 - 15
+ VPEControl,
+ VPEConf0,
+ VPEConf1,
+ YQMask,
+ VPESchedule,
+ VPEScheFBack,
+ VPEOpt,
+
+ EntryLo0 = 16, //Bank 2: 16 - 23
+ TCStatus,
+ TCBind,
+ TCRestart,
+ TCHalt,
+ TCContext,
+ TCSchedule,
+ TCScheFBack,
+
+ EntryLo1 = 24, // Bank 3: 24
+
+ Context = 32, // Bank 4: 32 - 33
+ ContextConfig,
+
+ //PageMask = 40, //Bank 5: 40 - 41
+ PageGrain = 41,
+
+ Wired = 48, //Bank 6: 48 - 55
+ SRSConf0,
+ SRSConf1,
+ SRSConf2,
+ SRSConf3,
+ SRSConf4,
+
+ HWRena = 56, //Bank 7: 56
+
+ BadVAddr = 63, //Bank 8: 63
+
+ Count = 64, //Bank 9: 64
+
+ EntryHi = 72, //Bank 10:72 - 79
+
+ Compare = 80, //Bank 10:80 - 87
+
+ Status = 88, //Bank 12:88 - 96
+ IntCtl = 89,
+ SRSCtl = 90,
+ SRSMap = 91,
+
+ Cause = 97, //97-104
+
+ EPC = 105, //105-112
+
+ PRId = 113, //113-120,
+ EBase = 114,
+
+ Config = 121, //Bank 16: 121-128
+ Config1 = 122,
+ Config2 = 123,
+ Config3 = 124,
+ Config6 = 127,
+ Config7 = 128,
+
+
+ LLAddr = 129, //Bank 17: 129-136
+
+ WatchLo0 = 137, //Bank 18: 137-144
+ WatchLo1 = 138,
+ WatchLo2 = 139,
+ WatchLo3 = 140,
+ WatchLo4 = 141,
+ WatchLo5 = 142,
+ WatchLo6 = 143,
+ WatchLo7 = 144,
+
+ WatchHi0 = 145,//Bank 19: 145-152
+ WatchHi1 = 146,
+ WatchHi2 = 147,
+ WatchHi3 = 148,
+ WatchHi4 = 149,
+ WatchHi5 = 150,
+ WatchHi6 = 151,
+ WatchHi7 = 152,
+
+ XCContext64 = 153, //Bank 20: 153-160
+
+ //Bank 21: 161-168
+
+ //Bank 22: 169-176
+
+ Debug = 177, //Bank 23: 177-184
+ TraceControl1 = 178,
+ TraceControl2 = 179,
+ UserTraceData = 180,
+ TraceBPC = 181,
+
+ DEPC = 185,//Bank 24: 185-192
+
+ PerfCnt0 = 193,//Bank 25: 193 - 200
+ PerfCnt1 = 194,
+ PerfCnt2 = 195,
+ PerfCnt3 = 196,
+ PerfCnt4 = 197,
+ PerfCnt5 = 198,
+ PerfCnt6 = 199,
+ PerfCnt7 = 200,
+
+ ErrCtl = 201, //Bank 26: 201 - 208
+
+ CacheErr0 = 209, //Bank 27: 209 - 216
+ CacheErr1 = 210,
+ CacheErr2 = 211,
+ CacheErr3 = 212,
+
+ TagLo0 = 217,//Bank 28: 217 - 224
+ DataLo1 = 218,
+ TagLo2 = 219,
+ DataLo3 = 220,
+ TagLo4 = 221,
+ DataLo5 = 222,
+ TagLo6 = 223,
+ DataLo7 = 234,
+
+ TagHi0 = 233,//Bank 29: 233 - 240
+ DataHi1 = 234,
+ TagHi2 = 235,
+ DataHi3 = 236,
+ TagHi4 = 237,
+ DataHi5 = 238,
+ TagHi6 = 239,
+ DataHi7 = 240,
+
+
+ ErrorEPC = 249,//Bank 30: 241 - 248
+
+ DESAVE = 257//Bank 31: 249-256
+ };
+
class MiscRegFile {
protected:
uint64_t fpcr; // floating point condition codes
+ // FPCR is not used in MIPS. Condition
+ // codes are kept as part of the FloatRegFile
+
bool lock_flag; // lock flag for LL/SC
+ // use LL reg. in the future
+
Addr lock_addr; // lock address for LL/SC
+ // use LLAddr reg. in the future
MiscReg miscRegFile[NumMiscRegs];
public:
+ void clear()
+ {
+ fpcr = 0;
+ lock_flag = 0;
+ lock_addr = 0;
+ }
+
void copyMiscRegs(ThreadContext *tc);
MiscReg readReg(int misc_reg)
* Authors: Korey Sewell
*/
-#ifndef __ARCH_MIPS_REGFILE_HH__
-#define __ARCH_MIPS_REGFILE_HH__
+#ifndef __ARCH_MIPS_REGFILE_REGFILE_HH__
+#define __ARCH_MIPS_REGFILE_REGFILE_HH__
#include "arch/mips/types.hh"
-#include "arch/mips/constants.hh"
#include "arch/mips/regfile/int_regfile.hh"
#include "arch/mips/regfile/float_regfile.hh"
#include "arch/mips/regfile/misc_regfile.hh"
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string §ion);
- typedef int ContextParam;
- typedef int ContextVal;
-
- void changeContext(ContextParam param, ContextVal val)
+ void changeContext(RegContextParam param, RegContextVal val)
{
}
};
--- /dev/null
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ * Korey Sewell
+ */
+
+#ifndef __ARCH_MIPS_SYSCALLRETURN_HH__
+#define __ARCH_MIPS_SYSCALLRETURN_HH__
+
+class SyscallReturn {
+ public:
+ template <class T>
+ SyscallReturn(T v, bool s)
+ {
+ retval = (uint32_t)v;
+ success = s;
+ }
+
+ template <class T>
+ SyscallReturn(T v)
+ {
+ success = (v >= 0);
+ retval = (uint32_t)v;
+ }
+
+ ~SyscallReturn() {}
+
+ SyscallReturn& operator=(const SyscallReturn& s) {
+ retval = s.retval;
+ success = s.success;
+ return *this;
+ }
+
+ bool successful() { return success; }
+ uint64_t value() { return retval; }
+
+
+ private:
+ uint64_t retval;
+ bool success;
+};
+
+namespace MipsISA
+{
+ static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
+ {
+ if (return_value.successful()) {
+ // no error
+ regs->setIntReg(SyscallSuccessReg, 0);
+ regs->setIntReg(ReturnValueReg1, return_value.value());
+ } else {
+ // got an error, return details
+ regs->setIntReg(SyscallSuccessReg, (IntReg) -1);
+ regs->setIntReg(ReturnValueReg1, -return_value.value());
+ }
+ }
+}
+
+#endif
MiscReg ctrlreg;
} AnyReg;
+ typedef int RegContextParam;
+ typedef int RegContextVal;
+
//used in FP convert & round function
enum ConvertType{
SINGLE_TO_DOUBLE,
* Authors: Korey Sewell
*/
-#include "arch/mips/isa_traits.hh"
+#include "arch/mips/regfile.hh"
#include "arch/mips/utility.hh"
-#include "config/full_system.hh"
-#include "cpu/static_inst.hh"
-#include "sim/serialize.hh"
+#include "base/misc.hh"
#include "base/bitfield.hh"
using namespace MipsISA;
-using namespace std;
uint64_t
MipsISA::fpConvert(ConvertType cvt_type, double fp_val)
#define __ARCH_MIPS_UTILITY_HH__
#include "arch/mips/types.hh"
-#include "arch/mips/constants.hh"
#include "base/misc.hh"
+#include "config/full_system.hh"
+//XXX This is needed for size_t. We should use something other than size_t
+//#include "kern/linux/linux.hh"
#include "sim/host.hh"
+class ThreadContext;
+
namespace MipsISA {
//Floating Point Utility Functions
bool isNan(void *val_ptr, int size);
bool isQnan(void *val_ptr, int size);
bool isSnan(void *val_ptr, int size);
+
+ /**
+ * Function to insure ISA semantics about 0 registers.
+ * @param tc The thread context.
+ */
+ template <class TC>
+ void zeroRegisters(TC *tc);
+
+ void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+ // Instruction address compression hooks
+ static inline Addr realPCToFetchPC(const Addr &addr) {
+ return addr;
+ }
+
+ static inline Addr fetchPCToRealPC(const Addr &addr) {
+ return addr;
+ }
+
+ // the size of "fetched" instructions (not necessarily the size
+ // of real instructions for PISA)
+ static inline size_t fetchInstSize() {
+ return sizeof(MachInst);
+ }
+
+ static inline MachInst makeRegisterCopy(int dest, int src) {
+ panic("makeRegisterCopy not implemented");
+ return 0;
+ }
+
+ static inline ExtMachInst
+ makeExtMI(MachInst inst, const uint64_t &pc) {
+#if FULL_SYSTEM
+ ExtMachInst ext_inst = inst;
+ if (pc && 0x1)
+ return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
+ else
+ return ext_inst;
+#else
+ return ExtMachInst(inst);
+#endif
+ }
};
# Base sources used by all configurations.
base_sources = Split('''
faults.cc
- isa_traits.cc
+ floatregfile.cc
+ intregfile.cc
+ miscregfile.cc
+ regfile.cc
''')
# Full-system sources
full_system_sources = Split('''
- vtophys.cc
ua2005.cc
+ vtophys.cc
''')
# Syscall emulation (non-full-system) sources
syscall_emulation_sources = Split('''
linux/linux.cc
linux/process.cc
- solaris/solaris.cc
- solaris/process.cc
process.cc
+ solaris/process.cc
+ solaris/solaris.cc
''')
sources = base_sources
--- /dev/null
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ * Ali Saidi
+ */
+
+#include "arch/sparc/floatregfile.hh"
+#include "base/trace.hh"
+#include "sim/byteswap.hh"
+#include "sim/serialize.hh"
+
+using namespace SparcISA;
+using namespace std;
+
+class Checkpoint;
+
+string SparcISA::getFloatRegName(RegIndex index)
+{
+ static std::string floatRegName[NumFloatRegs] =
+ {"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+ "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
+ "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
+ "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
+ "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63"};
+ return floatRegName[index];
+}
+
+void FloatRegFile::clear()
+{
+ bzero(regSpace, sizeof(regSpace));
+}
+
+FloatReg FloatRegFile::readReg(int floatReg, int width)
+{
+ //In each of these cases, we have to copy the value into a temporary
+ //variable. This is because we may otherwise try to access an
+ //unaligned portion of memory.
+ switch(width)
+ {
+ case SingleWidth:
+ float32_t result32;
+ memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32));
+ return htog(result32);
+ case DoubleWidth:
+ float64_t result64;
+ memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64));
+ return htog(result64);
+ case QuadWidth:
+ float128_t result128;
+ memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128));
+ return htog(result128);
+ default:
+ panic("Attempted to read a %d bit floating point register!", width);
+ }
+}
+
+FloatRegBits FloatRegFile::readRegBits(int floatReg, int width)
+{
+ //In each of these cases, we have to copy the value into a temporary
+ //variable. This is because we may otherwise try to access an
+ //unaligned portion of memory.
+ switch(width)
+ {
+ case SingleWidth:
+ uint32_t result32;
+ memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32));
+ return htog(result32);
+ case DoubleWidth:
+ uint64_t result64;
+ memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64));
+ return htog(result64);
+ case QuadWidth:
+ uint64_t result128;
+ memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128));
+ return htog(result128);
+ default:
+ panic("Attempted to read a %d bit floating point register!", width);
+ }
+}
+
+Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width)
+{
+ //In each of these cases, we have to copy the value into a temporary
+ //variable. This is because we may otherwise try to access an
+ //unaligned portion of memory.
+
+ uint32_t result32;
+ uint64_t result64;
+ DPRINTF(Sparc, "Setting floating point register %d\n", floatReg);
+ switch(width)
+ {
+ case SingleWidth:
+ result32 = gtoh((uint32_t)val);
+ memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
+ break;
+ case DoubleWidth:
+ result64 = gtoh((uint64_t)val);
+ memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
+ break;
+ case QuadWidth:
+ panic("Quad width FP not implemented.");
+ break;
+ default:
+ panic("Attempted to read a %d bit floating point register!", width);
+ }
+ return NoFault;
+}
+
+Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width)
+{
+ //In each of these cases, we have to copy the value into a temporary
+ //variable. This is because we may otherwise try to access an
+ //unaligned portion of memory.
+ uint32_t result32;
+ uint64_t result64;
+ switch(width)
+ {
+ case SingleWidth:
+ result32 = gtoh((uint32_t)val);
+ memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
+ break;
+ case DoubleWidth:
+ result64 = gtoh((uint64_t)val);
+ memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
+ break;
+ case QuadWidth:
+ panic("Quad width FP not implemented.");
+ break;
+ default:
+ panic("Attempted to read a %d bit floating point register!", width);
+ }
+ return NoFault;
+}
+
+void FloatRegFile::serialize(std::ostream &os)
+{
+ SERIALIZE_ARRAY((unsigned char *)regSpace,
+ SingleWidth / 8 * NumFloatRegs);
+}
+
+void FloatRegFile::unserialize(Checkpoint *cp, const std::string §ion)
+{
+ UNSERIALIZE_ARRAY((unsigned char *)regSpace,
+ SingleWidth / 8 * NumFloatRegs);
+}
+
--- /dev/null
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ * Ali Saidi
+ */
+
+#ifndef __ARCH_SPARC_FLOATREGFILE_HH__
+#define __ARCH_SPARC_FLOATREGFILE_HH__
+
+#include "arch/sparc/faults.hh"
+#include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/types.hh"
+
+#include <string>
+
+namespace SparcISA
+{
+ std::string getFloatRegName(RegIndex);
+
+ typedef float float32_t;
+ typedef double float64_t;
+ //FIXME long double refers to a 10 byte float, rather than a
+ //16 byte float as required. This data type may have to be emulated.
+ typedef double float128_t;
+
+ class FloatRegFile
+ {
+ public:
+ static const int SingleWidth = 32;
+ static const int DoubleWidth = 64;
+ static const int QuadWidth = 128;
+
+ protected:
+
+ //Since the floating point registers overlap each other,
+ //A generic storage space is used. The float to be returned is
+ //pulled from the appropriate section of this region.
+ char regSpace[(SingleWidth / 8) * NumFloatRegs];
+
+ public:
+
+ void clear();
+
+ FloatReg readReg(int floatReg, int width);
+
+ FloatRegBits readRegBits(int floatReg, int width);
+
+ Fault setReg(int floatReg, const FloatReg &val, int width);
+
+ Fault setRegBits(int floatReg, const FloatRegBits &val, int width);
+
+ void serialize(std::ostream &os);
+
+ void unserialize(Checkpoint *cp, const std::string §ion);
+ };
+}
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ * Ali Saidi
+ */
+
+#include "arch/sparc/intregfile.hh"
+#include "base/trace.hh"
+#include "sim/serialize.hh"
+
+using namespace SparcISA;
+using namespace std;
+
+class Checkpoint;
+
+string SparcISA::getIntRegName(RegIndex index)
+{
+ static std::string intRegName[NumIntRegs] =
+ {"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+ "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
+ "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
+ "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7"};
+ return intRegName[index];
+}
+
+int IntRegFile::flattenIndex(int reg)
+{
+ int flatIndex = offset[reg >> FrameOffsetBits]
+ | (reg & FrameOffsetMask);
+ DPRINTF(Sparc, "Flattened index %d into %d.\n", reg, flatIndex);
+ return flatIndex;
+}
+
+void IntRegFile::clear()
+{
+ int x;
+ for (x = 0; x < MaxGL; x++)
+ memset(regGlobals[x], 0, sizeof(regGlobals[x]));
+ for(int x = 0; x < 2 * NWindows; x++)
+ bzero(regSegments[x], sizeof(regSegments[x]));
+}
+
+IntRegFile::IntRegFile()
+{
+ offset[Globals] = 0;
+ regView[Globals] = regGlobals[0];
+ setCWP(0);
+ clear();
+}
+
+IntReg IntRegFile::readReg(int intReg)
+{
+ IntReg val =
+ regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask];
+ DPRINTF(Sparc, "Read register %d = 0x%x\n", intReg, val);
+ return val;
+}
+
+Fault IntRegFile::setReg(int intReg, const IntReg &val)
+{
+ if(intReg)
+ DPRINTF(Sparc, "Wrote register %d = 0x%x\n", intReg, val);
+ regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask] = val;
+ return NoFault;
+}
+
+//This doesn't effect the actual CWP register.
+//It's purpose is to adjust the view of the register file
+//to what it would be if CWP = cwp.
+void IntRegFile::setCWP(int cwp)
+{
+ int index = ((NWindows - cwp) % NWindows) * 2;
+ offset[Outputs] = FrameOffset + (index * RegsPerFrame);
+ offset[Locals] = FrameOffset + ((index+1) * RegsPerFrame);
+ offset[Inputs] = FrameOffset +
+ (((index+2) % (NWindows * 2)) * RegsPerFrame);
+ regView[Outputs] = regSegments[index];
+ regView[Locals] = regSegments[index+1];
+ regView[Inputs] = regSegments[(index+2) % (NWindows * 2)];
+
+ DPRINTF(Sparc, "Changed the CWP value to %d\n", cwp);
+}
+
+void IntRegFile::setGlobals(int gl)
+{
+ DPRINTF(Sparc, "Now using %d globals", gl);
+
+ regView[Globals] = regGlobals[gl];
+ offset[Globals] = RegGlobalOffset + gl * RegsPerFrame;
+}
+
+void IntRegFile::serialize(std::ostream &os)
+{
+ unsigned int x;
+ for(x = 0; x < MaxGL; x++)
+ SERIALIZE_ARRAY(regGlobals[x], RegsPerFrame);
+ for(x = 0; x < 2 * NWindows; x++)
+ SERIALIZE_ARRAY(regSegments[x], RegsPerFrame);
+}
+
+void IntRegFile::unserialize(Checkpoint *cp, const std::string §ion)
+{
+ unsigned int x;
+ for(x = 0; x < MaxGL; x++)
+ UNSERIALIZE_ARRAY(regGlobals[x], RegsPerFrame);
+ for(unsigned int x = 0; x < 2 * NWindows; x++)
+ UNSERIALIZE_ARRAY(regSegments[x], RegsPerFrame);
+}
--- /dev/null
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ * Ali Saidi
+ */
+
+#ifndef __ARCH_SPARC_INTREGFILE_HH__
+#define __ARCH_SPARC_INTREGFILE_HH__
+
+#include "arch/sparc/faults.hh"
+#include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/types.hh"
+
+#include <string>
+
+namespace SparcISA
+{
+ class RegFile;
+
+ //This function translates integer register file indices into names
+ std::string getIntRegName(RegIndex);
+
+ class IntRegFile
+ {
+ private:
+ friend class RegFile;
+ protected:
+ static const int FrameOffsetBits = 3;
+ static const int FrameNumBits = 2;
+
+ static const int RegsPerFrame = 1 << FrameOffsetBits;
+ static const int FrameNumMask =
+ (FrameNumBits == sizeof(int)) ?
+ (unsigned int)(-1) :
+ (1 << FrameNumBits) - 1;
+ static const int FrameOffsetMask =
+ (FrameOffsetBits == sizeof(int)) ?
+ (unsigned int)(-1) :
+ (1 << FrameOffsetBits) - 1;
+
+ IntReg regGlobals[MaxGL][RegsPerFrame];
+ IntReg regSegments[2 * NWindows][RegsPerFrame];
+
+ enum regFrame {Globals, Outputs, Locals, Inputs, NumFrames};
+
+ IntReg * regView[NumFrames];
+
+ static const int RegGlobalOffset = 0;
+ static const int FrameOffset = MaxGL * RegsPerFrame;
+ int offset[NumFrames];
+
+ public:
+
+ int flattenIndex(int reg);
+
+ void clear();
+
+ IntRegFile();
+
+ IntReg readReg(int intReg);
+
+ Fault setReg(int intReg, const IntReg &val);
+
+ void serialize(std::ostream &os);
+
+ void unserialize(Checkpoint *cp, const std::string §ion);
+
+ protected:
+ //This doesn't effect the actual CWP register.
+ //It's purpose is to adjust the view of the register file
+ //to what it would be if CWP = cwp.
+ void setCWP(int cwp);
+
+ void setGlobals(int gl);
+ };
+}
+
+#endif
const SymbolTable *symtab) const;
void printReg(std::ostream &os, int reg) const;
+ void printSrcReg(std::ostream &os, int reg) const;
+ void printDestReg(std::ostream &os, int reg) const;
+
+ void printRegArray(std::ostream &os,
+ const RegIndex indexArray[], int num) const;
};
bool passesCondition(uint32_t codes, uint32_t condition);
ccprintf(os, "\t%s ", mnemonic);
}
+ void SparcStaticInst::printRegArray(std::ostream &os,
+ const RegIndex indexArray[], int num) const
+ {
+ if(num <= 0)
+ return;
+ printReg(os, indexArray[0]);
+ for(int x = 1; x < num; x++)
+ {
+ os << ", ";
+ printReg(os, indexArray[x]);
+ }
+ }
+
+ void
+ SparcStaticInst::printSrcReg(std::ostream &os, int reg) const
+ {
+ if(_numSrcRegs > reg)
+ printReg(os, _srcRegIdx[reg]);
+ }
+
+ void
+ SparcStaticInst::printDestReg(std::ostream &os, int reg) const
+ {
+ if(_numDestRegs > reg)
+ printReg(os, _destRegIdx[reg]);
+ }
+
void
SparcStaticInst::printReg(std::ostream &os, int reg) const
{
{
//Throw an illegal instruction acception
0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
- 0x1: decode BPCC
+ format BranchN
{
- format Branch19
+ 0x1: decode BPCC
{
- 0x0: bpcci({{
+ 0x0: bpcci(19, {{
if(passesCondition(Ccr<3:0>, COND2))
NNPC = xc->readPC() + disp;
else
handle_annul
}});
- 0x2: bpccx({{
+ 0x2: bpccx(19, {{
if(passesCondition(Ccr<7:4>, COND2))
NNPC = xc->readPC() + disp;
else
handle_annul
}});
}
+ 0x2: bicc(22, {{
+ if(passesCondition(Ccr<3:0>, COND2))
+ NNPC = xc->readPC() + disp;
+ else
+ handle_annul
+ }});
}
- 0x2: Branch22::bicc({{
- if(passesCondition(Ccr<3:0>, COND2))
- NNPC = xc->readPC() + disp;
- else
- handle_annul
- }});
0x3: decode RCOND2
{
format BranchSplit
0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
0x6: Trap::fbfcc({{fault = new FpDisabled;}});
}
- 0x1: Branch30::call({{
+ 0x1: BranchN::call(30, {{
R15 = xc->readPC();
NNPC = R15 + disp;
}});
0x2: decode OP3 {
format IntOp {
0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
- 0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}});
- 0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}});
- 0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}});
+ 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
+ 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
+ 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
- 0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}});
- 0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}});
- 0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}});
+ 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
+ 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
+ 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
- 0x09: mulx({{Rd = Rs1 * Rs2_or_imm13;}});
+ 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
0x0A: umul({{
Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
Y = Rd<63:32>;
Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
Y = Rd.sdw;
}});
- 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + Ccr<0:0>}});
+ 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
0x0D: udivx({{
if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
else Rd.udw = Rs1.udw / Rs2_or_imm13;
0x1C: subccc({{
int64_t resTemp, val2 = Rs2_or_imm13;
int64_t carryin = Ccr<0:0>;
- Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
+ Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
{{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
{{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
);
0x22: taddcctv({{
int64_t resTemp, val2 = Rs2_or_imm13;
- Rd = resTemp = Rs1 + val2;
- int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
+ Rd = Rs1 + val2;
+ int32_t overflow = Rs1<1:0> || val2<1:0> ||
+ (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
if(overflow) fault = new TagOverflow;}},
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
{{overflow}},
0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
}
// XXX might want a format rdipr thing here
- 0x28: rdasr({{
+ 0x28: decode RS1 {
+ 0xF: decode I {
+ 0x0: Nop::stbar({{/*stuff*/}});
+ 0x1: Nop::membar({{/*stuff*/}});
+ }
+ default: rdasr({{
Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault);
- }});
- 0x29: rdhpr({{
+ }});
+ }
+ 0x29: HPriv::rdhpr({{
// XXX Need to protect with format that traps non-priv/priv
// access
Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
}});
- 0x2A: rdpr({{
+ 0x2A: Priv::rdpr({{
// XXX Need to protect with format that traps non-priv
// access
Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
}
- 0x32: wrpr({{
+ 0x32: Priv::wrpr({{
// XXX Need to protect with format that traps non-priv
// access
- xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
+ fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
}});
- 0x33: wrhpr({{
+ 0x33: HPriv::wrhpr({{
// XXX Need to protect with format that traps non-priv/priv
// access
- xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
+ fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
}});
- 0x34: Trap::fpop1({{fault = new FpDisabled;}});
+ 0x34: decode OPF{
+ format BasicOperate{
+ 0x01: fmovs({{
+ Frd.sf = Frs2.sf;
+ //fsr.ftt = fsr.cexc = 0
+ Fsr &= ~(7 << 14);
+ Fsr &= ~(0x1F);
+ }});
+ 0x02: fmovd({{
+ Frd.df = Frs2.df;
+ //fsr.ftt = fsr.cexc = 0
+ Fsr &= ~(7 << 14);
+ Fsr &= ~(0x1F);
+ }});
+ 0x03: Trap::fmovq({{fault = new FpDisabled;}});
+ 0x05: fnegs({{
+ //XXX might want to explicitly flip the sign bit
+ //So cases with Nan and +/-0 don't do weird things
+ Frd.sf = -Frs2.sf;
+ //fsr.ftt = fsr.cexc = 0
+ Fsr &= ~(7 << 14);
+ Fsr &= ~(0x1F);
+ }});
+ 0x06: fnegd({{
+ //XXX might want to explicitly flip the sign bit
+ //So cases with Nan and +/-0 don't do weird things
+ Frd.df = -Frs2.df;
+ //fsr.ftt = fsr.cexc = 0
+ Fsr &= ~(7 << 14);
+ Fsr &= ~(0x1F);
+ }});
+ 0x07: Trap::fnegq({{fault = new FpDisabled;}});
+ 0x09: fabss({{
+ //XXX this instruction should be tested individually
+ //Clear the sign bit
+ Frd.sf = (float)(~(1 << 31) & ((uint32_t)Frs2.sf));
+ //fsr.ftt = fsr.cexc = 0
+ Fsr &= ~(7 << 14);
+ Fsr &= ~(0x1F);
+ }});
+ 0x0A: fabsd({{
+ //XXX this instruction should be tested individually
+ //Clear the sign bit
+ Frd.df = (float)(~((uint64_t)1 << 63) & ((uint64_t)Frs2.df));
+ //fsr.ftt = fsr.cexc = 0
+ Fsr &= ~(7 << 14);
+ Fsr &= ~(0x1F);
+ }});
+ 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
+ 0x29: fsqrts({{Frd.sf = sqrt(Frs2.sf);}});
+ 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
+ 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
+ 0x41: fadds({{Frd.sf = Frs1.sf + Frs2.sf;}});
+ 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
+ 0x43: Trap::faddq({{fault = new FpDisabled;}});
+ 0x45: fsubs({{Frd.sf = Frs1.sf - Frs2.sf;}});
+ 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
+ 0x47: Trap::fsubq({{fault = new FpDisabled;}});
+ 0x49: fmuls({{Frd.sf = Frs1.sf * Frs2.sf;}});
+ 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
+ 0x4B: Trap::fmulq({{fault = new FpDisabled;}});
+ 0x4D: fdivs({{Frd.sf = Frs1.sf / Frs2.sf;}});
+ 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
+ 0x4F: Trap::fdivq({{fault = new FpDisabled;}});
+ 0x69: fsmuld({{Frd.df = Frs1.sf * Frs2.sf;}});
+ 0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
+ 0x81: fstox({{
+ Frd.df = (double)static_cast<int64_t>(Frs2.sf);
+ }});
+ 0x82: fdtox({{
+ Frd.df = (double)static_cast<int64_t>(Frs2.df);
+ }});
+ 0x83: Trap::fqtox({{fault = new FpDisabled;}});
+ 0x84: fxtos({{
+ Frd.sf = static_cast<float>((int64_t)Frs2.df);
+ }});
+ 0x88: fxtod({{
+ Frd.df = static_cast<double>((int64_t)Frs2.df);
+ }});
+ 0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
+ 0xC4: fitos({{
+ Frd.sf = static_cast<float>((int32_t)Frs2.sf);
+ }});
+ 0xC6: fdtos({{Frd.sf = Frs2.df;}});
+ 0xC7: Trap::fqtos({{fault = new FpDisabled;}});
+ 0xC8: fitod({{
+ Frd.df = static_cast<double>((int32_t)Frs2.sf);
+ }});
+ 0xC9: fstod({{Frd.df = Frs2.sf;}});
+ 0xCB: Trap::fqtod({{fault = new FpDisabled;}});
+ 0xCC: Trap::fitoq({{fault = new FpDisabled;}});
+ 0xCD: Trap::fstoq({{fault = new FpDisabled;}});
+ 0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
+ 0xD1: fstoi({{
+ Frd.sf = (float)static_cast<int32_t>(Frs2.sf);
+ }});
+ 0xD2: fdtoi({{
+ Frd.sf = (float)static_cast<int32_t>(Frs2.df);
+ }});
+ 0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
+ default: Trap::fpop1({{fault = new FpDisabled;}});
+ }
+ }
0x35: Trap::fpop2({{fault = new FpDisabled;}});
+ //This used to be just impdep1, but now it's a whole bunch
+ //of instructions
+ 0x36: decode OPF{
+ 0x00: Trap::edge8({{fault = new IllegalInstruction;}});
+ 0x01: Trap::edge8n({{fault = new IllegalInstruction;}});
+ 0x02: Trap::edge8l({{fault = new IllegalInstruction;}});
+ 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}});
+ 0x04: Trap::edge16({{fault = new IllegalInstruction;}});
+ 0x05: Trap::edge16n({{fault = new IllegalInstruction;}});
+ 0x06: Trap::edge16l({{fault = new IllegalInstruction;}});
+ 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}});
+ 0x08: Trap::edge32({{fault = new IllegalInstruction;}});
+ 0x09: Trap::edge32n({{fault = new IllegalInstruction;}});
+ 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}});
+ 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}});
+ 0x10: Trap::array8({{fault = new IllegalInstruction;}});
+ 0x12: Trap::array16({{fault = new IllegalInstruction;}});
+ 0x14: Trap::array32({{fault = new IllegalInstruction;}});
+ 0x18: BasicOperate::alignaddress({{
+ uint64_t sum = Rs1 + Rs2;
+ Frd = sum & ~7;
+ Gsr = (Gsr & ~7) | (sum & 7);
+ }});
+ 0x19: Trap::bmask({{fault = new IllegalInstruction;}});
+ 0x1A: BasicOperate::alignaddresslittle({{
+ uint64_t sum = Rs1 + Rs2;
+ Frd = sum & ~7;
+ Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
+ }});
+ 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}});
+ 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}});
+ 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}});
+ 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}});
+ 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}});
+ 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}});
+ 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}});
+ 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}});
+ 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}});
+ 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}});
+ 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}});
+ 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}});
+ 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
+ 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
+ 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
+ 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
+ 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
+ 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
+ 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
+ 0x48: BasicOperate::faligndata({{
+ uint64_t msbX = (uint64_t)Frs1;
+ uint64_t lsbX = (uint64_t)Frs2;
+ uint64_t msbShift = Gsr<2:0> * 8;
+ uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
+ uint64_t msbMask = ((uint64_t)(-1)) << msbShift;
+ uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
+ Frd = ((msbX << msbShift) & msbMask) |
+ ((lsbX << lsbShift) & lsbMask);
+ }});
+ 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
+ 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
+ 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
+ 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
+ 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
+ 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
+ 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});
+ 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}});
+ 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}});
+ 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
+ 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
+ 0x60: BasicOperate::fzero({{Frd.df = 0;}});
+ 0x61: BasicOperate::fzeros({{Frd.sf = 0;}});
+ 0x62: Trap::fnor({{fault = new IllegalInstruction;}});
+ 0x63: Trap::fnors({{fault = new IllegalInstruction;}});
+ 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
+ 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}});
+ 0x66: BasicOperate::fnot2({{
+ Frd.df = (double)(~((uint64_t)Frs2.df));
+ }});
+ 0x67: BasicOperate::fnot2s({{
+ Frd.sf = (float)(~((uint32_t)Frs2.sf));
+ }});
+ 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
+ 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
+ 0x6A: BasicOperate::fnot1({{
+ Frd.df = (double)(~((uint64_t)Frs1.df));
+ }});
+ 0x6B: BasicOperate::fnot1s({{
+ Frd.sf = (float)(~((uint32_t)Frs1.sf));
+ }});
+ 0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
+ 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
+ 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
+ 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
+ 0x70: Trap::fand({{fault = new IllegalInstruction;}});
+ 0x71: Trap::fands({{fault = new IllegalInstruction;}});
+ 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
+ 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
+ 0x74: BasicOperate::fsrc1({{Frd.df = Frs1.df;}});
+ 0x75: BasicOperate::fsrc1s({{Frd.sf = Frs1.sf;}});
+ 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
+ 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
+ 0x78: BasicOperate::fsrc2({{Frd.df = Frs2.df;}});
+ 0x79: BasicOperate::fsrc2s({{Frd.sf = Frs2.sf;}});
+ 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
+ 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
+ 0x7C: Trap::for({{fault = new IllegalInstruction;}});
+ 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
+ 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
+ 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
+ 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
+ 0x81: Trap::siam({{fault = new IllegalInstruction;}});
+ }
+ 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
0x38: Branch::jmpl({{
Addr target = Rs1 + Rs2_or_imm13;
if(target & 0x3)
NNPC = Tnpc + 4;
Tl = Tl - 1;
}});
- 0x1: BasicOperate::retry({{
+ 0x1: Priv::retry({{
if(Tl == 0)
return new IllegalInstruction;
Cwp = Tstate<4:0>;
Mem = temp;
}}, {{32}});
format Trap {
- 0x20: ldf({{fault = new FpDisabled;}});
+ 0x20: Load::ldf({{Frd.sf = ((float)Mem);}}, {{32}});
0x21: decode X {
0x0: Load::ldfsr({{Fsr = Mem<31:0> | Fsr<63:32>;}}, {{32}});
0x1: Load::ldxfsr({{Fsr = Mem;}}, {{64}});
}
0x22: ldqf({{fault = new FpDisabled;}});
- 0x23: lddf({{fault = new FpDisabled;}});
- 0x24: stf({{fault = new FpDisabled;}});
+ 0x23: Load::lddf({{Frd.df = ((double)Mem);}}, {{64}});
+ 0x24: Store::stf({{Mem = ((int32_t)Frd.sf);}}, {{32}});
0x25: decode X {
0x0: Store::stfsr({{Mem = Fsr<31:0>;}}, {{32}});
0x1: Store::stxfsr({{Mem = Fsr;}}, {{64}});
}
0x26: stqf({{fault = new FpDisabled;}});
- 0x27: stdf({{fault = new FpDisabled;}});
+ 0x27: Store::stdf({{Mem = ((int64_t)Frd.df);}}, {{64}});
0x2D: Nop::prefetch({{ }});
- 0x30: ldfa({{return new FpDisabled;}});
+ 0x30: Load::ldfa({{Frd.sf = ((float)Mem);}}, {{32}});
0x32: ldqfa({{fault = new FpDisabled;}});
- 0x33: lddfa({{fault = new FpDisabled;}});
- 0x34: stfa({{fault = new FpDisabled;}});
- 0x35: stqfa({{fault = new FpDisabled;}});
- 0x36: stdfa({{fault = new FpDisabled;}});
+ 0x33: Load::lddfa({{Frd.df = ((double)Mem);}}, {{64}});
+ 0x34: Store::stfa({{Mem = ((int32_t)Frd.sf);}}, {{32}});
+ 0x36: stqfa({{fault = new FpDisabled;}});
+ //XXX need to work in the ASI thing
+ 0x37: Store::stdfa({{Mem = ((uint64_t)Frd.df);}}, {{64}});
0x3C: Cas::casa({{
uint64_t val = Mem.uw;
if(Rs2.uw == val)
{
Fault fault = NoFault;
- %(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(code)s;
return new %(class_name)s(machInst);
}};
-// Basic decode template, passing mnemonic in as string arg to constructor.
-def template BasicDecodeWithMnemonic {{
- return new %(class_name)s("%(mnemonic)s", machInst);
-}};
-
// The most basic instruction format... used only for a few misc. insts
def format BasicOperate(code, *flags) {{
iop = InstObjParams(name, Name, 'SparcStaticInst',
};
/**
- * Base class for branches with 19 bit displacements.
+ * Base class for branches with n bit displacements.
*/
- class Branch19 : public BranchDisp
+ template<int bits>
+ class BranchNBits : public BranchDisp
{
protected:
// Constructor
- Branch19(const char *mnem, MachInst _machInst,
+ BranchNBits(const char *mnem, MachInst _machInst,
OpClass __opClass) :
BranchDisp(mnem, _machInst, __opClass)
{
- disp = sign_ext(DISP19 << 2, 21);
- }
- };
-
- /**
- * Base class for branches with 22 bit displacements.
- */
- class Branch22 : public BranchDisp
- {
- protected:
- // Constructor
- Branch22(const char *mnem, MachInst _machInst,
- OpClass __opClass) :
- BranchDisp(mnem, _machInst, __opClass)
- {
- disp = sign_ext(DISP22 << 2, 24);
- }
- };
-
- /**
- * Base class for branches with 30 bit displacements.
- */
- class Branch30 : public BranchDisp
- {
- protected:
- // Constructor
- Branch30(const char *mnem, MachInst _machInst,
- OpClass __opClass) :
- BranchDisp(mnem, _machInst, __opClass)
- {
- disp = sign_ext(DISP30 << 2, 32);
+ disp = sign_ext(_machInst << 2, bits + 2);
}
};
}};
output decoder {{
+
+ template class BranchNBits<19>;
+
+ template class BranchNBits<22>;
+
+ template class BranchNBits<30>;
+
std::string Branch::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, mnemonic);
-
- if (_numSrcRegs > 0)
- {
- printReg(response, _srcRegIdx[0]);
- for(int x = 1; x < _numSrcRegs; x++)
- {
+ printRegArray(response, _srcRegIdx, _numSrcRegs);
+ if(_numDestRegs && _numSrcRegs)
response << ", ";
- printReg(response, _srcRegIdx[x]);
- }
- }
-
- if (_numDestRegs > 0)
- {
- if(_numSrcRegs > 0)
- response << ", ";
- printReg(response, _destRegIdx[0]);
- }
+ printDestReg(response, 0);
return response.str();
}
std::stringstream response;
printMnemonic(response, mnemonic);
-
- if (_numSrcRegs > 0)
- {
- printReg(response, _srcRegIdx[0]);
- for(int x = 1; x < _numSrcRegs; x++)
- {
- response << ", ";
- printReg(response, _srcRegIdx[x]);
- }
- }
-
+ printRegArray(response, _srcRegIdx, _numSrcRegs);
if(_numSrcRegs > 0)
response << ", ";
-
ccprintf(response, "0x%x", imm);
-
if (_numDestRegs > 0)
- {
response << ", ";
- printReg(response, _destRegIdx[0]);
- }
+ printDestReg(response, 0);
return response.str();
}
}};
// Primary format for branch instructions:
-def format Branch19(code, *opt_flags) {{
- code = re.sub(r'handle_annul', handle_annul, code)
- codeBlk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'Branch19', codeBlk, opt_flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- exec_output = BranchExecute.subst(iop)
- decode_block = BasicDecode.subst(iop)
-}};
-
-// Primary format for branch instructions:
-def format Branch22(code, *opt_flags) {{
- code = re.sub(r'handle_annul', handle_annul, code)
- codeBlk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'Branch22', codeBlk, opt_flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- exec_output = BranchExecute.subst(iop)
- decode_block = BasicDecode.subst(iop)
-}};
-
-// Primary format for branch instructions:
-def format Branch30(code, *opt_flags) {{
+def format BranchN(bits, code, *opt_flags) {{
code = re.sub(r'handle_annul', handle_annul, code)
codeBlk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'Branch30', codeBlk, opt_flags)
+ iop = InstObjParams(name, Name, "BranchNBits<%d>" % bits, codeBlk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = BranchExecute.subst(iop)
OpClass __opClass) :
IntOpImm(mnem, _machInst, __opClass)
{
- imm = (IMM22 << 10) & 0xFFFFFC00;
+ imm = (IMM22 & 0x3FFFFF) << 10;
}
std::string generateDisassembly(Addr pc,
if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0)
{
printMnemonic(os, "mov");
- if(_numSrcRegs > 0)
- printReg(os, _srcRegIdx[1]);
+ printSrcReg(os, 1);
ccprintf(os, ", ");
- if(_numDestRegs > 0)
- printReg(os, _destRegIdx[0]);
-
+ printDestReg(os, 0);
return true;
}
return false;
{
if(!strcmp(mnemonic, "or"))
{
- if(_srcRegIdx[0] == 0)
+ if(_numSrcRegs > 0 && _srcRegIdx[0] == 0)
{
if(imm == 0)
- {
printMnemonic(os, "clr");
- if(_numDestRegs > 0)
- printReg(os, _destRegIdx[0]);
- return true;
- }
else
{
printMnemonic(os, "mov");
- ccprintf(os, ", 0x%x, ", imm);
- if(_numDestRegs > 0)
- printReg(os, _destRegIdx[0]);
- return true;
+ ccprintf(os, " 0x%x, ", imm);
}
+ printDestReg(os, 0);
+ return true;
}
else if(imm == 0)
{
printMnemonic(os, "mov");
- if(_numSrcRegs > 0)
- printReg(os, _srcRegIdx[0]);
+ printSrcReg(os, 0);
ccprintf(os, ", ");
- if(_numDestRegs > 0)
- printReg(os, _destRegIdx[0]);
+ printDestReg(os, 0);
return true;
}
}
{
std::stringstream response;
- if(!printPseudoOps(response, pc, symtab))
- {
- printMnemonic(response, mnemonic);
- if (_numSrcRegs > 0)
- {
- printReg(response, _srcRegIdx[0]);
- for(int x = 1; x < _numSrcRegs; x++)
- {
- response << ", ";
- printReg(response, _srcRegIdx[x]);
- }
- }
- if (_numDestRegs > 0)
- {
- if(_numSrcRegs > 0)
- response << ", ";
- printReg(response, _destRegIdx[0]);
- }
- }
+ if(printPseudoOps(response, pc, symtab))
+ return response.str();
+ printMnemonic(response, mnemonic);
+ printRegArray(response, _srcRegIdx, _numSrcRegs);
+ if(_numDestRegs && _numSrcRegs)
+ response << ", ";
+ printDestReg(response, 0);
return response.str();
}
{
std::stringstream response;
- if(!printPseudoOps(response, pc, symtab))
- {
- printMnemonic(response, mnemonic);
- if (_numSrcRegs > 0)
- {
- printReg(response, _srcRegIdx[0]);
- for(int x = 1; x < _numSrcRegs - 1; x++)
- {
- response << ", ";
- printReg(response, _srcRegIdx[x]);
- }
- }
- if(_numSrcRegs > 0)
- response << ", ";
- ccprintf(response, "0x%x", imm);
- if (_numDestRegs > 0)
- {
- response << ", ";
- printReg(response, _destRegIdx[0]);
- }
- }
+ if(printPseudoOps(response, pc, symtab))
+ return response.str();
+ printMnemonic(response, mnemonic);
+ printRegArray(response, _srcRegIdx, _numSrcRegs);
+ if(_numSrcRegs > 0)
+ response << ", ";
+ ccprintf(response, "0x%x", imm);
+ if(_numDestRegs > 0)
+ response << ", ";
+ printDestReg(response, 0);
return response.str();
}
std::stringstream response;
printMnemonic(response, mnemonic);
- if(_numSrcRegs > 0)
- response << ", ";
ccprintf(response, "%%hi(0x%x), ", imm);
- printReg(response, _destRegIdx[0]);
+ printDestReg(response, 0);
return response.str();
}
}};
return (header_output, decoder_output, exec_output, decode_block)
calcCcCode = '''
- uint8_t tmp_ccriccc;
- uint8_t tmp_ccriccv;
- uint8_t tmp_ccriccz;
- uint8_t tmp_ccriccn;
- uint8_t tmp_ccrxccc;
- uint8_t tmp_ccrxccv;
- uint8_t tmp_ccrxccz;
- uint8_t tmp_ccrxccn;
-
- tmp_ccriccn = (Rd >> 31) & 1;
- tmp_ccriccz = ((Rd & 0xFFFFFFFF) == 0);
- tmp_ccrxccn = (Rd >> 63) & 1;
- tmp_ccrxccz = (Rd == 0);
- tmp_ccriccv = %(ivValue)s & 1;
- tmp_ccriccc = %(icValue)s & 1;
- tmp_ccrxccv = %(xvValue)s & 1;
- tmp_ccrxccc = %(xcValue)s & 1;
-
- Ccr = tmp_ccriccc | tmp_ccriccv << 1 |
- tmp_ccriccz << 2 | tmp_ccriccn << 3|
- tmp_ccrxccc << 4 | tmp_ccrxccv << 5|
- tmp_ccrxccz << 6| tmp_ccrxccn << 7;
-
-
- DPRINTF(Sparc, "in = %%d\\n", (uint16_t)tmp_ccriccn);
- DPRINTF(Sparc, "iz = %%d\\n", (uint16_t)tmp_ccriccz);
- DPRINTF(Sparc, "xn = %%d\\n", (uint16_t)tmp_ccrxccn);
- DPRINTF(Sparc, "xz = %%d\\n", (uint16_t)tmp_ccrxccz);
- DPRINTF(Sparc, "iv = %%d\\n", (uint16_t)tmp_ccriccv);
- DPRINTF(Sparc, "ic = %%d\\n", (uint16_t)tmp_ccriccc);
- DPRINTF(Sparc, "xv = %%d\\n", (uint16_t)tmp_ccrxccv);
- DPRINTF(Sparc, "xc = %%d\\n", (uint16_t)tmp_ccrxccc);
+ uint16_t _ic, _iv, _iz, _in, _xc, _xv, _xz, _xn;
+
+ _in = (Rd >> 31) & 1;
+ _iz = ((Rd & 0xFFFFFFFF) == 0);
+ _xn = (Rd >> 63) & 1;
+ _xz = (Rd == 0);
+ _iv = %(ivValue)s & 1;
+ _ic = %(icValue)s & 1;
+ _xv = %(xvValue)s & 1;
+ _xc = %(xcValue)s & 1;
+
+ Ccr = _ic << 0 | _iv << 1 | _iz << 2 | _in << 3 |
+ _xc << 4 | _xv << 5 | _xz << 6 | _xn << 7;
+
+
+ DPRINTF(Sparc, "in = %%d\\n", _in);
+ DPRINTF(Sparc, "iz = %%d\\n", _iz);
+ DPRINTF(Sparc, "xn = %%d\\n", _xn);
+ DPRINTF(Sparc, "xz = %%d\\n", _xz);
+ DPRINTF(Sparc, "iv = %%d\\n", _iv);
+ DPRINTF(Sparc, "ic = %%d\\n", _ic);
+ DPRINTF(Sparc, "xv = %%d\\n", _xv);
+ DPRINTF(Sparc, "xc = %%d\\n", _xc);
'''
}};
std::string Priv::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
- return "Privileged Instruction";
+ std::stringstream response;
+
+ printMnemonic(response, mnemonic);
+
+ return response.str();
}
}};
if(%(check)s)
return new PrivilegedAction;
+ Fault fault = NoFault;
%(code)s;
%(op_wb)s;
- return NoFault;
+ return fault;
}
}};
// Primary format for integer operate instructions:
def format Priv(code, *opt_flags) {{
- checkCode = "((xc->readMiscReg(PrStart + MISCREG_PSTATE))<2:2>)"
+ checkCode = '''((xc->readMiscReg(PrStart + MISCREG_PSTATE))<2:2>) ||
+ ((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)'''
(header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code,
- checkCode, name, Name, opt_flags)
+ checkCode, name, Name, opt_flags + ('IprAccessOp',))
}};
+def format HPriv(code, *opt_flags) {{
+ checkCode = "((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)"
+ (header_output, decoder_output,
+ exec_output, decode_block) = doPrivFormat(code,
+ checkCode, name, Name, opt_flags + ('IprAccessOp',))
+}};
output header {{
#include <sstream>
#include <iostream>
-#include <iomanip>
#include "cpu/static_inst.hh"
#include "arch/sparc/faults.hh"
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh" // for Jump::branchTarget()
-#include <math.h>
#if defined(linux)
#include <fenv.h>
#endif
}};
output exec {{
-#include <math.h>
#if defined(linux)
#include <fenv.h>
#endif
-#ifdef FULL_SYSTEM
-//#include "sim/pseudo_inst.hh"
-#endif
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "sim/sim_exit.hh"
'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
- #'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
- #'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
- #'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
- 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
- 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 4),
- 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 4),
+ 'Frd': ('FloatReg', 'df', 'RD', 'IsFloating', 10),
+ 'Frs1': ('FloatReg', 'df', 'RS1', 'IsFloating', 11),
+ 'Frs2': ('FloatReg', 'df', 'RS2', 'IsFloating', 12),
+ 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20),
+ 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
+ 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
'R0': ('IntReg', 'udw', '0', None, 6),
'R16': ('IntReg', 'udw', '16', None, 9),
# Control registers
- 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 12),
- 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 17),
- 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 26),
+ 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
+ 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
+ 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
- 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 28),
- 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 28),
- 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 28),
- 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1),
- 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 27),
+ 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 43),
+ 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44),
+ 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45),
+ 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46),
+ 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 47),
- 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 15),
- 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 34),
- 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 35),
- 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 37),
- 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 36),
- 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 38),
- 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 12),
+ 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 48),
+ 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49),
+ 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50),
+ 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51),
+ 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52),
+ 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53),
+ 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54),
- 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 47)
+ 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55),
+ 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56)
}};
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Korey Sewell
- * Gabe Black
+ * Authors: Gabe Black
*/
#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
#define __ARCH_SPARC_ISA_TRAITS_HH__
+#include "arch/sparc/types.hh"
#include "base/misc.hh"
#include "config/full_system.hh"
#include "sim/host.hh"
namespace BigEndianGuest {}
-#if !FULL_SYSTEM
-class SyscallReturn
-{
- public:
- template <class T>
- SyscallReturn(T v, bool s)
- {
- retval = (uint64_t)v;
- success = s;
- }
-
- template <class T>
- SyscallReturn(T v)
- {
- success = (v >= 0);
- retval = (uint64_t)v;
- }
-
- ~SyscallReturn() {}
-
- SyscallReturn& operator=(const SyscallReturn& s)
- {
- retval = s.retval;
- success = s.success;
- return *this;
- }
-
- bool successful() { return success; }
- uint64_t value() { return retval; }
-
- private:
- uint64_t retval;
- bool success;
-};
-
-#endif
-
#if FULL_SYSTEM
#include "arch/sparc/isa_fullsys_traits.hh"
#endif
namespace SparcISA
{
+ class RegFile;
+
+ //This makes sure the big endian versions of certain functions are used.
+ using namespace BigEndianGuest;
+
+ //TODO this needs to be a SPARC Noop
+ // Alpha UNOP (ldq_u r31,0(r0))
+ const MachInst NoopMachInst = 0x2ffe0000;
+
+ const int NumIntRegs = 32;
+ const int NumFloatRegs = 64;
+ const int NumMiscRegs = 40;
// These enumerate all the registers for dependence tracking.
enum DependenceTags {
// 0..31 are the integer regs 0..31
- // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
- FP_Base_DepTag = 32,
- Ctrl_Base_DepTag = 96,
+ // 32..95 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
+ FP_Base_DepTag = NumIntRegs,
+ Ctrl_Base_DepTag = NumIntRegs + NumFloatRegs,
//XXX These are here solely to get compilation and won't work
Fpcr_DepTag = 0,
Uniq_DepTag = 0
};
- //This makes sure the big endian versions of certain functions are used.
- using namespace BigEndianGuest;
- typedef uint32_t MachInst;
- typedef uint64_t ExtMachInst;
+ // MAXTL - maximum trap level
+ const int MaxPTL = 2;
+ const int MaxTL = 6;
+ const int MaxGL = 3;
+ const int MaxPGL = 2;
- const int NumIntRegs = 32;
- const int NumFloatRegs = 64;
- const int NumMiscRegs = 32;
+ // NWINDOWS - number of register windows, can be 3 to 32
+ const int NWindows = 32;
// semantically meaningful register indices
const int ZeroReg = 0; // architecturally meaningful
const int MaxInstSrcRegs = 8;
const int MaxInstDestRegs = 9;
- typedef uint64_t IntReg;
-
- // control register file contents
- typedef uint64_t MiscReg;
-
- typedef double FloatReg;
- typedef uint64_t FloatRegBits;
-
//8K. This value is implmentation specific; and should probably
//be somewhere else.
const int LogVMPageSize = 13;
extern const MachInst NoopMachInst;
}
-#include "arch/sparc/regfile.hh"
-
-namespace SparcISA
-{
-
-#if !FULL_SYSTEM
- static inline void setSyscallReturn(SyscallReturn return_value,
- RegFile *regs)
- {
- // check for error condition. SPARC syscall convention is to
- // indicate success/failure in reg the carry bit of the ccr
- // and put the return value itself in the standard return value reg ().
- if (return_value.successful()) {
- // no error, clear XCC.C
- regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) & 0xEF);
- regs->setIntReg(ReturnValueReg, return_value.value());
- } else {
- // got an error, set XCC.C
- regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) | 0x10);
- regs->setIntReg(ReturnValueReg, return_value.value());
- }
- }
-#endif
-};
-
#endif // __ARCH_SPARC_ISA_TRAITS_HH__
*/
#include "arch/sparc/linux/linux.hh"
+#include <fcntl.h>
// open(2) flags translation table
OpenFlagTransTable SparcLinux::openFlagTable[] = {
/* 99 */ SyscallDesc("accept", unimplementedFunc),
/* 100 */ SyscallDesc("getpriority", unimplementedFunc),
/* 101 */ SyscallDesc("rt_sigreturn", unimplementedFunc),
- /* 102 */ SyscallDesc("rt_sigaction", unimplementedFunc),
+ /* 102 */ SyscallDesc("rt_sigaction", ignoreFunc),
/* 103 */ SyscallDesc("rt_sigprocmask", unimplementedFunc),
/* 104 */ SyscallDesc("rt_sigpending", unimplementedFunc),
/* 105 */ SyscallDesc("rt_sigtimedwait", unimplementedFunc),
/* 195 */ SyscallDesc("epoll_wait", unimplementedFunc),
/* 196 */ SyscallDesc("ioprio_set", unimplementedFunc),
/* 197 */ SyscallDesc("getppid", getppidFunc),
- /* 198 */ SyscallDesc("sigaction", unimplementedFunc),
+ /* 198 */ SyscallDesc("sigaction", ignoreFunc),
/* 199 */ SyscallDesc("sgetmask", unimplementedFunc),
/* 200 */ SyscallDesc("ssetmask", unimplementedFunc),
/* 201 */ SyscallDesc("sigsuspend", unimplementedFunc),
#define __SPARC_LINUX_PROCESS_HH__
#include "arch/sparc/linux/linux.hh"
+#include "arch/sparc/syscallreturn.hh"
#include "arch/sparc/process.hh"
#include "sim/process.hh"
--- /dev/null
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ * Ali Saidi
+ */
+
+#include "arch/sparc/miscregfile.hh"
+#include "base/trace.hh"
+#include "cpu/base.hh"
+#include "cpu/thread_context.hh"
+
+using namespace SparcISA;
+using namespace std;
+
+class Checkpoint;
+
+//These functions map register indices to names
+string SparcISA::getMiscRegName(RegIndex index)
+{
+ static::string miscRegName[NumMiscRegs] =
+ {"y", "ccr", "asi", "tick", "pc", "fprs", "pcr", "pic",
+ "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
+ "stick", "stick_cmpr",
+ "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
+ "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
+ "wstate", "gl",
+ "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
+ "hstick_cmpr",
+ "fsr"};
+ return miscRegName[index];
+}
+
+#if FULL_SYSTEM
+
+//XXX These need an implementation someplace
+/** Fullsystem only register version of ReadRegWithEffect() */
+MiscReg MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
+/** Fullsystem only register version of SetRegWithEffect() */
+Fault MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
+ ThreadContext * tc);
+#endif
+
+void MiscRegFile::reset()
+{
+ pstateFields.pef = 0; //No FPU
+ //pstateFields.pef = 1; //FPU
+#if FULL_SYSTEM
+ //For SPARC, when a system is first started, there is a power
+ //on reset Trap which sets the processor into the following state.
+ //Bits that aren't set aren't defined on startup.
+ tl = MaxTL;
+ gl = MaxGL;
+
+ tickFields.counter = 0; //The TICK register is unreadable bya
+ tickFields.npt = 1; //The TICK register is unreadable by by !priv
+
+ softint = 0; // Clear all the soft interrupt bits
+ tick_cmprFields.int_dis = 1; // disable timer compare interrupts
+ tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
+ stickFields.npt = 1; //The TICK register is unreadable by by !priv
+ stick_cmprFields.int_dis = 1; // disable timer compare interrupts
+ stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
+
+
+ tt[tl] = power_on_reset;
+ pstate = 0; // fields 0 but pef
+ pstateFields.pef = 1;
+
+ hpstate = 0;
+ hpstateFields.red = 1;
+ hpstateFields.hpriv = 1;
+ hpstateFields.tlz = 0; // this is a guess
+ hintp = 0; // no interrupts pending
+ hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
+ hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
+#else
+/* //This sets up the initial state of the processor for usermode processes
+ pstateFields.priv = 0; //Process runs in user mode
+ pstateFields.ie = 1; //Interrupts are enabled
+ fsrFields.rd = 0; //Round to nearest
+ fsrFields.tem = 0; //Floating point traps not enabled
+ fsrFields.ns = 0; //Non standard mode off
+ fsrFields.qne = 0; //Floating point queue is empty
+ fsrFields.aexc = 0; //No accrued exceptions
+ fsrFields.cexc = 0; //No current exceptions
+
+ //Register window management registers
+ otherwin = 0; //No windows contain info from other programs
+ canrestore = 0; //There are no windows to pop
+ cansave = MaxTL - 2; //All windows are available to save into
+ cleanwin = MaxTL;*/
+#endif
+}
+
+MiscReg MiscRegFile::readReg(int miscReg)
+{
+ switch (miscReg) {
+ case MISCREG_Y:
+ return y;
+ case MISCREG_CCR:
+ return ccr;
+ case MISCREG_ASI:
+ return asi;
+ case MISCREG_FPRS:
+ return fprs;
+ case MISCREG_TICK:
+ return tick;
+ case MISCREG_PCR:
+ case MISCREG_PIC:
+ panic("ASR number %d not implemented\n", miscReg - AsrStart);
+ case MISCREG_GSR:
+ return gsr;
+ case MISCREG_SOFTINT:
+ return softint;
+ case MISCREG_TICK_CMPR:
+ return tick_cmpr;
+ case MISCREG_STICK:
+ return stick;
+ case MISCREG_STICK_CMPR:
+ return stick_cmpr;
+
+ /** Privilged Registers */
+ case MISCREG_TPC:
+ return tpc[tl-1];
+ case MISCREG_TNPC:
+ return tnpc[tl-1];
+ case MISCREG_TSTATE:
+ return tstate[tl-1];
+ case MISCREG_TT:
+ return tt[tl-1];
+ case MISCREG_PRIVTICK:
+ panic("Priviliged access to tick registers not implemented\n");
+ case MISCREG_TBA:
+ return tba;
+ case MISCREG_PSTATE:
+ return pstate;
+ case MISCREG_TL:
+ return tl;
+ case MISCREG_PIL:
+ return pil;
+ case MISCREG_CWP:
+ return cwp;
+ case MISCREG_CANSAVE:
+ return cansave;
+ case MISCREG_CANRESTORE:
+ return canrestore;
+ case MISCREG_CLEANWIN:
+ return cleanwin;
+ case MISCREG_OTHERWIN:
+ return otherwin;
+ case MISCREG_WSTATE:
+ return wstate;
+ case MISCREG_GL:
+ return gl;
+
+ /** Hyper privileged registers */
+ case MISCREG_HPSTATE:
+ return hpstate;
+ case MISCREG_HTSTATE:
+ return htstate[tl-1];
+ case MISCREG_HINTP:
+ panic("HINTP not implemented\n");
+ case MISCREG_HTBA:
+ return htba;
+ case MISCREG_HVER:
+ return NWindows | MaxTL << 8 | MaxGL << 16;
+ case MISCREG_STRAND_STS_REG:
+ return strandStatusReg;
+ case MISCREG_HSTICK_CMPR:
+ return hstick_cmpr;
+
+ /** Floating Point Status Register */
+ case MISCREG_FSR:
+ return fsr;
+ default:
+ panic("Miscellaneous register %d not implemented\n", miscReg);
+ }
+}
+
+MiscReg MiscRegFile::readRegWithEffect(int miscReg,
+ Fault &fault, ThreadContext * tc)
+{
+ fault = NoFault;
+ switch (miscReg) {
+ case MISCREG_Y:
+ case MISCREG_CCR:
+ case MISCREG_ASI:
+ return readReg(miscReg);
+
+ case MISCREG_TICK:
+ case MISCREG_PRIVTICK:
+ // Check for reading privilege
+ if (tickFields.npt && !isNonPriv()) {
+ fault = new PrivilegedAction;
+ return 0;
+ }
+ return tc->getCpuPtr()->curCycle() - tickFields.counter |
+ tickFields.npt << 63;
+ case MISCREG_PC:
+ return tc->readPC();
+ case MISCREG_FPRS:
+ fault = new UnimpFault("FPU not implemented\n");
+ return 0;
+ case MISCREG_PCR:
+ fault = new UnimpFault("Performance Instrumentation not impl\n");
+ return 0;
+ case MISCREG_PIC:
+ fault = new UnimpFault("Performance Instrumentation not impl\n");
+ return 0;
+ case MISCREG_GSR:
+ return readReg(miscReg);
+
+ /** Privilged Registers */
+ case MISCREG_TPC:
+ case MISCREG_TNPC:
+ case MISCREG_TSTATE:
+ case MISCREG_TT:
+ if (tl == 0) {
+ fault = new IllegalInstruction;
+ return 0;
+ } // NOTE THE FALL THROUGH!
+ case MISCREG_PSTATE:
+ case MISCREG_TL:
+ return readReg(miscReg);
+
+ case MISCREG_TBA:
+ return readReg(miscReg) & ULL(~0x7FFF);
+
+ case MISCREG_PIL:
+
+ case MISCREG_CWP:
+ case MISCREG_CANSAVE:
+ case MISCREG_CANRESTORE:
+ case MISCREG_CLEANWIN:
+ case MISCREG_OTHERWIN:
+ case MISCREG_WSTATE:
+ case MISCREG_GL:
+ return readReg(miscReg);
+
+ /** Floating Point Status Register */
+ case MISCREG_FSR:
+ panic("Floating Point not implemented\n");
+ default:
+#if FULL_SYSTEM
+ return readFSRegWithEffect(miscReg, fault, tc);
+#else
+ fault = new IllegalInstruction;
+ return 0;
+#endif
+ }
+}
+
+Fault MiscRegFile::setReg(int miscReg, const MiscReg &val)
+{
+ switch (miscReg) {
+ case MISCREG_Y:
+ y = val;
+ return NoFault;
+ case MISCREG_CCR:
+ ccr = val;
+ return NoFault;
+ case MISCREG_ASI:
+ asi = val;
+ return NoFault;
+ case MISCREG_FPRS:
+ fprs = val;
+ return NoFault;
+ case MISCREG_TICK:
+ tick = val;
+ return NoFault;
+ case MISCREG_PCR:
+ case MISCREG_PIC:
+ panic("ASR number %d not implemented\n", miscReg - AsrStart);
+ case MISCREG_GSR:
+ gsr = val;
+ case MISCREG_SOFTINT:
+ softint = val;
+ return NoFault;
+ case MISCREG_TICK_CMPR:
+ tick_cmpr = val;
+ return NoFault;
+ case MISCREG_STICK:
+ stick = val;
+ return NoFault;
+ case MISCREG_STICK_CMPR:
+ stick_cmpr = val;
+ return NoFault;
+
+ /** Privilged Registers */
+ case MISCREG_TPC:
+ tpc[tl-1] = val;
+ return NoFault;
+ case MISCREG_TNPC:
+ tnpc[tl-1] = val;
+ return NoFault;
+ case MISCREG_TSTATE:
+ tstate[tl-1] = val;
+ return NoFault;
+ case MISCREG_TT:
+ tt[tl-1] = val;
+ return NoFault;
+ case MISCREG_PRIVTICK:
+ panic("Priviliged access to tick regesiters not implemented\n");
+ case MISCREG_TBA:
+ tba = val;
+ return NoFault;
+ case MISCREG_PSTATE:
+ pstate = val;
+ return NoFault;
+ case MISCREG_TL:
+ tl = val;
+ return NoFault;
+ case MISCREG_PIL:
+ pil = val;
+ return NoFault;
+ case MISCREG_CWP:
+ cwp = val;
+ return NoFault;
+ case MISCREG_CANSAVE:
+ cansave = val;
+ return NoFault;
+ case MISCREG_CANRESTORE:
+ canrestore = val;
+ return NoFault;
+ case MISCREG_CLEANWIN:
+ cleanwin = val;
+ return NoFault;
+ case MISCREG_OTHERWIN:
+ otherwin = val;
+ return NoFault;
+ case MISCREG_WSTATE:
+ wstate = val;
+ return NoFault;
+ case MISCREG_GL:
+ gl = val;
+ return NoFault;
+
+ /** Hyper privileged registers */
+ case MISCREG_HPSTATE:
+ hpstate = val;
+ return NoFault;
+ case MISCREG_HTSTATE:
+ htstate[tl-1] = val;
+ return NoFault;
+ case MISCREG_HINTP:
+ panic("HINTP not implemented\n");
+ case MISCREG_HTBA:
+ htba = val;
+ return NoFault;
+ case MISCREG_STRAND_STS_REG:
+ strandStatusReg = val;
+ return NoFault;
+ case MISCREG_HSTICK_CMPR:
+ hstick_cmpr = val;
+ return NoFault;
+
+ /** Floating Point Status Register */
+ case MISCREG_FSR:
+ fsr = val;
+ return NoFault;
+ default:
+ panic("Miscellaneous register %d not implemented\n", miscReg);
+ }
+}
+
+Fault MiscRegFile::setRegWithEffect(int miscReg,
+ const MiscReg &val, ThreadContext * tc)
+{
+ const uint64_t Bit64 = (1ULL << 63);
+ switch (miscReg) {
+ case MISCREG_Y:
+ case MISCREG_CCR:
+ case MISCREG_ASI:
+ setReg(miscReg, val);
+ return NoFault;
+ case MISCREG_PRIVTICK:
+ case MISCREG_TICK:
+ if (isNonPriv())
+ return new PrivilegedOpcode;
+ if (isPriv())
+ return new PrivilegedAction;
+ tickFields.counter = tc->getCpuPtr()->curCycle() - val & ~Bit64;
+ tickFields.npt = val & Bit64 ? 1 : 0;
+ return NoFault;
+ case MISCREG_PC:
+ return new IllegalInstruction;
+ case MISCREG_FPRS:
+ return new UnimpFault("FPU not implemented\n");
+ case MISCREG_PCR:
+ return new UnimpFault("Performance Instrumentation not impl\n");
+ case MISCREG_PIC:
+ return new UnimpFault("Performance Instrumentation not impl\n");
+ case MISCREG_GSR:
+ return setReg(miscReg, val);
+
+ /** Privilged Registers */
+ case MISCREG_TPC:
+ case MISCREG_TNPC:
+ case MISCREG_TSTATE:
+ case MISCREG_TT:
+ if (tl == 0)
+ return new IllegalInstruction;
+ setReg(miscReg, val);
+ return NoFault;
+
+ case MISCREG_TBA:
+ // clear lower 7 bits on writes.
+ setReg(miscReg, val & ULL(~0x7FFF));
+ return NoFault;
+
+ case MISCREG_PSTATE:
+ setReg(miscReg, val);
+ return NoFault;
+
+ case MISCREG_TL:
+ if (isHyperPriv() && val > MaxTL)
+ setReg(miscReg, MaxTL);
+ else if (isPriv() && !isHyperPriv() && val > MaxPTL)
+ setReg(miscReg, MaxPTL);
+ else
+ setReg(miscReg, val);
+ return NoFault;
+
+ case MISCREG_CWP:
+ tc->changeRegFileContext(CONTEXT_CWP, val);
+ case MISCREG_CANSAVE:
+ case MISCREG_CANRESTORE:
+ case MISCREG_CLEANWIN:
+ case MISCREG_OTHERWIN:
+ case MISCREG_WSTATE:
+ setReg(miscReg, val);
+ return NoFault;
+
+ case MISCREG_GL:
+ int newval;
+ if (isHyperPriv() && val > MaxGL)
+ newval = MaxGL;
+ else if (isPriv() && !isHyperPriv() && val > MaxPGL)
+ newval = MaxPGL;
+ else
+ newval = val;
+ tc->changeRegFileContext(CONTEXT_GLOBALS, newval);
+ setReg(miscReg, newval);
+ return NoFault;
+
+ /** Floating Point Status Register */
+ case MISCREG_FSR:
+ panic("Floating Point not implemented\n");
+ default:
+#if FULL_SYSTEM
+ setFSRegWithEffect(miscReg, val, tc);
+#else
+ return new IllegalInstruction;
+#endif
+ }
+}
+
+void MiscRegFile::serialize(std::ostream & os)
+{
+ SERIALIZE_SCALAR(pstate);
+ SERIALIZE_SCALAR(tba);
+ SERIALIZE_SCALAR(y);
+ SERIALIZE_SCALAR(pil);
+ SERIALIZE_SCALAR(gl);
+ SERIALIZE_SCALAR(cwp);
+ SERIALIZE_ARRAY(tt, MaxTL);
+ SERIALIZE_SCALAR(ccr);
+ SERIALIZE_SCALAR(asi);
+ SERIALIZE_SCALAR(tl);
+ SERIALIZE_ARRAY(tpc, MaxTL);
+ SERIALIZE_ARRAY(tnpc, MaxTL);
+ SERIALIZE_ARRAY(tstate, MaxTL);
+ SERIALIZE_SCALAR(tick);
+ SERIALIZE_SCALAR(cansave);
+ SERIALIZE_SCALAR(canrestore);
+ SERIALIZE_SCALAR(otherwin);
+ SERIALIZE_SCALAR(cleanwin);
+ SERIALIZE_SCALAR(wstate);
+ SERIALIZE_SCALAR(fsr);
+ SERIALIZE_SCALAR(fprs);
+ SERIALIZE_SCALAR(hpstate);
+ SERIALIZE_ARRAY(htstate, MaxTL);
+ SERIALIZE_SCALAR(htba);
+ SERIALIZE_SCALAR(hstick_cmpr);
+}
+
+void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
+{
+ UNSERIALIZE_SCALAR(pstate);
+ UNSERIALIZE_SCALAR(tba);
+ UNSERIALIZE_SCALAR(y);
+ UNSERIALIZE_SCALAR(pil);
+ UNSERIALIZE_SCALAR(gl);
+ UNSERIALIZE_SCALAR(cwp);
+ UNSERIALIZE_ARRAY(tt, MaxTL);
+ UNSERIALIZE_SCALAR(ccr);
+ UNSERIALIZE_SCALAR(asi);
+ UNSERIALIZE_SCALAR(tl);
+ UNSERIALIZE_ARRAY(tpc, MaxTL);
+ UNSERIALIZE_ARRAY(tnpc, MaxTL);
+ UNSERIALIZE_ARRAY(tstate, MaxTL);
+ UNSERIALIZE_SCALAR(tick);
+ UNSERIALIZE_SCALAR(cansave);
+ UNSERIALIZE_SCALAR(canrestore);
+ UNSERIALIZE_SCALAR(otherwin);
+ UNSERIALIZE_SCALAR(cleanwin);
+ UNSERIALIZE_SCALAR(wstate);
+ UNSERIALIZE_SCALAR(fsr);
+ UNSERIALIZE_SCALAR(fprs);
+ UNSERIALIZE_SCALAR(hpstate);
+ UNSERIALIZE_ARRAY(htstate, MaxTL);
+ UNSERIALIZE_SCALAR(htba);
+ UNSERIALIZE_SCALAR(hstick_cmpr);
+}
+
--- /dev/null
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ * Ali Saidi
+ */
+
+#ifndef __ARCH_SPARC_MISCREGFILE_HH__
+#define __ARCH_SPARC_MISCREGFILE_HH__
+
+#include "arch/sparc/faults.hh"
+#include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/types.hh"
+
+#include <string>
+
+namespace SparcISA
+{
+
+ //These functions map register indices to names
+ std::string getMiscRegName(RegIndex);
+
+ const int AsrStart = 0;
+ const int PrStart = 32;
+ const int HprStart = 64;
+ const int MiscStart = 96;
+
+ enum MiscRegIndex
+ {
+ /** Ancillary State Registers */
+ MISCREG_Y = AsrStart + 0,
+ MISCREG_CCR = AsrStart + 2,
+ MISCREG_ASI = AsrStart + 3,
+ MISCREG_TICK = AsrStart + 4,
+ MISCREG_PC = AsrStart + 5,
+ MISCREG_FPRS = AsrStart + 6,
+ MISCREG_PCR = AsrStart + 16,
+ MISCREG_PIC = AsrStart + 17,
+ MISCREG_GSR = AsrStart + 19,
+ MISCREG_SOFTINT_SET = AsrStart + 20,
+ MISCREG_SOFTINT_CLR = AsrStart + 21,
+ MISCREG_SOFTINT = AsrStart + 22,
+ MISCREG_TICK_CMPR = AsrStart + 23,
+ MISCREG_STICK = AsrStart + 24,
+ MISCREG_STICK_CMPR = AsrStart + 25,
+
+ /** Privilged Registers */
+ MISCREG_TPC = PrStart + 0,
+ MISCREG_TNPC = PrStart + 1,
+ MISCREG_TSTATE = PrStart + 2,
+ MISCREG_TT = PrStart + 3,
+ MISCREG_PRIVTICK = PrStart + 4,
+ MISCREG_TBA = PrStart + 5,
+ MISCREG_PSTATE = PrStart + 6,
+ MISCREG_TL = PrStart + 7,
+ MISCREG_PIL = PrStart + 8,
+ MISCREG_CWP = PrStart + 9,
+ MISCREG_CANSAVE = PrStart + 10,
+ MISCREG_CANRESTORE = PrStart + 11,
+ MISCREG_CLEANWIN = PrStart + 12,
+ MISCREG_OTHERWIN = PrStart + 13,
+ MISCREG_WSTATE = PrStart + 14,
+ MISCREG_GL = PrStart + 16,
+
+ /** Hyper privileged registers */
+ MISCREG_HPSTATE = HprStart + 0,
+ MISCREG_HTSTATE = HprStart + 1,
+ MISCREG_HINTP = HprStart + 3,
+ MISCREG_HTBA = HprStart + 5,
+ MISCREG_HVER = HprStart + 6,
+ MISCREG_STRAND_STS_REG = HprStart + 16,
+ MISCREG_HSTICK_CMPR = HprStart + 31,
+
+ /** Floating Point Status Register */
+ MISCREG_FSR = MiscStart + 0
+
+ };
+
+ // The control registers, broken out into fields
+ class MiscRegFile
+ {
+ private:
+
+ /* ASR Registers */
+ union {
+ uint64_t y; // Y (used in obsolete multiplication)
+ struct {
+ uint64_t value:32; // The actual value stored in y
+ uint64_t :32; // reserved bits
+ } yFields;
+ };
+ union {
+ uint8_t ccr; // Condition Code Register
+ struct {
+ union {
+ uint8_t icc:4; // 32-bit condition codes
+ struct {
+ uint8_t c:1; // Carry
+ uint8_t v:1; // Overflow
+ uint8_t z:1; // Zero
+ uint8_t n:1; // Negative
+ } iccFields;
+ };
+ union {
+ uint8_t xcc:4; // 64-bit condition codes
+ struct {
+ uint8_t c:1; // Carry
+ uint8_t v:1; // Overflow
+ uint8_t z:1; // Zero
+ uint8_t n:1; // Negative
+ } xccFields;
+ };
+ } ccrFields;
+ };
+ uint8_t asi; // Address Space Identifier
+ union {
+ uint64_t tick; // Hardware clock-tick counter
+ struct {
+ int64_t counter:63; // Clock-tick count
+ uint64_t npt:1; // Non-priveleged trap
+ } tickFields;
+ };
+ union {
+ uint8_t fprs; // Floating-Point Register State
+ struct {
+ uint8_t dl:1; // Dirty lower
+ uint8_t du:1; // Dirty upper
+ uint8_t fef:1; // FPRS enable floating-Point
+ } fprsFields;
+ };
+ union {
+ uint64_t gsr; //General Status Register
+ struct {
+ uint64_t mask:32;
+ uint64_t :4;
+ uint64_t im:1;
+ uint64_t irnd:2;
+ uint64_t :17;
+ uint64_t scale:5;
+ uint64_t align:3;
+ } gsrFields;
+ };
+ union {
+ uint64_t softint;
+ struct {
+ uint64_t tm:1;
+ uint64_t int_level:14;
+ uint64_t sm:1;
+ } softintFields;
+ };
+ union {
+ uint64_t tick_cmpr; // Hardware tick compare registers
+ struct {
+ uint64_t tick_cmpr:63; // Clock-tick count
+ uint64_t int_dis:1; // Non-priveleged trap
+ } tick_cmprFields;
+ };
+ union {
+ uint64_t stick; // Hardware clock-tick counter
+ struct {
+ int64_t :63; // Not used, storage in SparcSystem
+ uint64_t npt:1; // Non-priveleged trap
+ } stickFields;
+ };
+ union {
+ uint64_t stick_cmpr; // Hardware tick compare registers
+ struct {
+ uint64_t tick_cmpr:63; // Clock-tick count
+ uint64_t int_dis:1; // Non-priveleged trap
+ } stick_cmprFields;
+ };
+
+
+ /* Privileged Registers */
+ uint64_t tpc[MaxTL]; // Trap Program Counter (value from
+ // previous trap level)
+ uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
+ // previous trap level)
+ union {
+ uint64_t tstate[MaxTL]; // Trap State
+ struct {
+ //Values are from previous trap level
+ uint64_t cwp:5; // Current Window Pointer
+ uint64_t :3; // Reserved bits
+ uint64_t pstate:13; // Process State
+ uint64_t :3; // Reserved bits
+ uint64_t asi:8; // Address Space Identifier
+ uint64_t ccr:8; // Condition Code Register
+ uint64_t gl:8; // Global level
+ } tstateFields[MaxTL];
+ };
+ uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
+ // on the previous level)
+ uint64_t tba; // Trap Base Address
+
+ union {
+ uint16_t pstate; // Process State Register
+ struct {
+ uint16_t :1; // reserved
+ uint16_t ie:1; // Interrupt enable
+ uint16_t priv:1; // Privelege mode
+ uint16_t am:1; // Address mask
+ uint16_t pef:1; // PSTATE enable floating-point
+ uint16_t :1; // reserved2
+ uint16_t mm:2; // Memory Model
+ uint16_t tle:1; // Trap little-endian
+ uint16_t cle:1; // Current little-endian
+ } pstateFields;
+ };
+ uint8_t tl; // Trap Level
+ uint8_t pil; // Process Interrupt Register
+ uint8_t cwp; // Current Window Pointer
+ uint8_t cansave; // Savable windows
+ uint8_t canrestore; // Restorable windows
+ uint8_t cleanwin; // Clean windows
+ uint8_t otherwin; // Other windows
+ union {
+ uint8_t wstate; // Window State
+ struct {
+ uint8_t normal:3; // Bits TT<4:2> are set to on a normal
+ // register window trap
+ uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin"
+ // register window trap
+ } wstateFields;
+ };
+ uint8_t gl; // Global level register
+
+
+ /** Hyperprivileged Registers */
+ union {
+ uint64_t hpstate; // Hyperprivileged State Register
+ struct {
+ uint8_t tlz: 1;
+ uint8_t :1;
+ uint8_t hpriv:1;
+ uint8_t :2;
+ uint8_t red:1;
+ uint8_t :4;
+ uint8_t ibe:1;
+ uint8_t id:1;
+ } hpstateFields;
+ };
+
+ uint64_t htstate[MaxTL]; // Hyperprivileged Trap State Register
+ uint64_t hintp;
+ uint64_t htba; // Hyperprivileged Trap Base Address register
+ union {
+ uint64_t hstick_cmpr; // Hardware tick compare registers
+ struct {
+ uint64_t tick_cmpr:63; // Clock-tick count
+ uint64_t int_dis:1; // Non-priveleged trap
+ } hstick_cmprFields;
+ };
+
+ uint64_t strandStatusReg; // Per strand status register
+
+
+ /** Floating point misc registers. */
+ union {
+ uint64_t fsr; // Floating-Point State Register
+ struct {
+ union {
+ uint64_t cexc:5; // Current excpetion
+ struct {
+ uint64_t nxc:1; // Inexact
+ uint64_t dzc:1; // Divide by zero
+ uint64_t ufc:1; // Underflow
+ uint64_t ofc:1; // Overflow
+ uint64_t nvc:1; // Invalid operand
+ } cexcFields;
+ };
+ union {
+ uint64_t aexc:5; // Accrued exception
+ struct {
+ uint64_t nxc:1; // Inexact
+ uint64_t dzc:1; // Divide by zero
+ uint64_t ufc:1; // Underflow
+ uint64_t ofc:1; // Overflow
+ uint64_t nvc:1; // Invalid operand
+ } aexcFields;
+ };
+ uint64_t fcc0:2; // Floating-Point condtion codes
+ uint64_t :1; // Reserved bits
+ uint64_t qne:1; // Deferred trap queue not empty
+ // with no queue, it should read 0
+ uint64_t ftt:3; // Floating-Point trap type
+ uint64_t ver:3; // Version (of the FPU)
+ uint64_t :2; // Reserved bits
+ uint64_t ns:1; // Nonstandard floating point
+ union {
+ uint64_t tem:5; // Trap Enable Mask
+ struct {
+ uint64_t nxm:1; // Inexact
+ uint64_t dzm:1; // Divide by zero
+ uint64_t ufm:1; // Underflow
+ uint64_t ofm:1; // Overflow
+ uint64_t nvm:1; // Invalid operand
+ } temFields;
+ };
+ uint64_t :2; // Reserved bits
+ uint64_t rd:2; // Rounding direction
+ uint64_t fcc1:2; // Floating-Point condition codes
+ uint64_t fcc2:2; // Floating-Point condition codes
+ uint64_t fcc3:2; // Floating-Point condition codes
+ uint64_t :26; // Reserved bits
+ } fsrFields;
+ };
+
+ // These need to check the int_dis field and if 0 then
+ // set appropriate bit in softint and checkinterrutps on the cpu
+#if FULL_SYSTEM
+ /** Process a tick compare event and generate an interrupt on the cpu if
+ * appropriate. */
+ void processTickCompare(ThreadContext *tc);
+ void processSTickCompare(ThreadContext *tc);
+ void processHSTickCompare(ThreadContext *tc);
+
+ typedef CpuEventWrapper<MiscRegFile,
+ &MiscRegFile::processTickCompare> TickCompareEvent;
+ TickCompareEvent *tickCompare;
+
+ typedef CpuEventWrapper<MiscRegFile,
+ &MiscRegFile::processSTickCompare> STickCompareEvent;
+ STickCompareEvent *sTickCompare;
+
+ typedef CpuEventWrapper<MiscRegFile,
+ &MiscRegFile::processHSTickCompare> HSTickCompareEvent;
+ HSTickCompareEvent *hSTickCompare;
+
+ /** Fullsystem only register version of ReadRegWithEffect() */
+ MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
+ /** Fullsystem only register version of SetRegWithEffect() */
+ Fault setFSRegWithEffect(int miscReg, const MiscReg &val,
+ ThreadContext * tc);
+#endif
+ public:
+
+ void reset();
+
+ MiscRegFile()
+ {
+ reset();
+ }
+
+ /** read a value out of an either an SE or FS IPR. No checking is done
+ * about SE vs. FS as this is mostly used to copy the regfile. Thus more
+ * register are copied that are necessary for FS. However this prevents
+ * a bunch of ifdefs and is rarely called so is not performance
+ * criticial. */
+ MiscReg readReg(int miscReg);
+
+ /** Read a value from an IPR. Only the SE iprs are here and the rest
+ * are are readFSRegWithEffect (which is called by readRegWithEffect()).
+ * Checking is done for permission based on state bits in the miscreg
+ * file. */
+ MiscReg readRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
+
+ /** write a value into an either an SE or FS IPR. No checking is done
+ * about SE vs. FS as this is mostly used to copy the regfile. Thus more
+ * register are copied that are necessary for FS. However this prevents
+ * a bunch of ifdefs and is rarely called so is not performance
+ * criticial.*/
+ Fault setReg(int miscReg, const MiscReg &val);
+
+ /** Write a value into an IPR. Only the SE iprs are here and the rest
+ * are are setFSRegWithEffect (which is called by setRegWithEffect()).
+ * Checking is done for permission based on state bits in the miscreg
+ * file. */
+ Fault setRegWithEffect(int miscReg,
+ const MiscReg &val, ThreadContext * tc);
+
+ void serialize(std::ostream & os);
+
+ void unserialize(Checkpoint * cp, const std::string & section);
+
+ void copyMiscRegs(ThreadContext * tc);
+
+ protected:
+
+ bool isHyperPriv() { return hpstateFields.hpriv; }
+ bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; }
+ bool isNonPriv() { return !isPriv(); }
+ };
+}
+
+#endif
#include "arch/sparc/isa_traits.hh"
#include "arch/sparc/process.hh"
#include "base/loader/object_file.hh"
+#include "base/loader/elf_object.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
#include "mem/page_table.hh"
SPARC_AT_UID = 11,
SPARC_AT_EUID = 12,
SPARC_AT_GID = 13,
- SPARC_AT_EGID = 14
+ SPARC_AT_EGID = 14,
+ SPARC_AT_SECURE = 23
};
enum hardwareCaps
M5_HWCAP_SPARC_V9 |
M5_HWCAP_SPARC_ULTRA3;
- //Setup the auxilliary vectors. These will already have
- //endian conversion.
- auxv.push_back(buildAuxVect(SPARC_AT_EGID, 100));
- auxv.push_back(buildAuxVect(SPARC_AT_GID, 100));
- auxv.push_back(buildAuxVect(SPARC_AT_EUID, 100));
- auxv.push_back(buildAuxVect(SPARC_AT_UID, 100));
- //This would work, but the entry point is a protected member
- //auxv.push_back(buildAuxVect(SPARC_AT_ENTRY, objFile->entry));
- auxv.push_back(buildAuxVect(SPARC_AT_FLAGS, 0));
- //This is the address of the elf "interpreter", which I don't
- //think we currently set up. It should be set to 0 (I think)
- //auxv.push_back(buildAuxVect(SPARC_AT_BASE, 0));
- //This is the number of headers which were in the original elf
- //file. This information isn't avaibale by this point.
- //auxv.push_back(buildAuxVect(SPARC_AT_PHNUM, 3));
- //This is the size of a program header entry. This isn't easy
- //to compute here.
- //auxv.push_back(buildAuxVect(SPARC_AT_PHENT, blah));
- //This is should be set to load_addr (whatever that is) +
- //e_phoff. I think it's a pointer to the program headers.
- //auxv.push_back(buildAuxVect(SPARC_AT_PHDR, blah));
- //This should be easy to get right, but I won't set it for now
- //auxv.push_back(buildAuxVect(SPARC_AT_CLKTCK, blah));
- auxv.push_back(buildAuxVect(SPARC_AT_PAGESZ, SparcISA::VMPageSize));
- auxv.push_back(buildAuxVect(SPARC_AT_HWCAP, hwcap));
+
+ //Setup the auxilliary vectors. These will already have endian conversion.
+ //Auxilliary vectors are loaded only for elf formatted executables.
+ ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
+ if(elfObject)
+ {
+ //Bits which describe the system hardware capabilities
+ auxv.push_back(buildAuxVect(SPARC_AT_HWCAP, hwcap));
+ //The system page size
+ auxv.push_back(buildAuxVect(SPARC_AT_PAGESZ, SparcISA::VMPageSize));
+ //Defined to be 100 in the kernel source.
+ //Frequency at which times() increments
+ auxv.push_back(buildAuxVect(SPARC_AT_CLKTCK, 100));
+ // For statically linked executables, this is the virtual address of the
+ // program header tables if they appear in the executable image
+ auxv.push_back(buildAuxVect(SPARC_AT_PHDR, elfObject->programHeaderTable()));
+ // This is the size of a program header entry from the elf file.
+ auxv.push_back(buildAuxVect(SPARC_AT_PHENT, elfObject->programHeaderSize()));
+ // This is the number of program headers from the original elf file.
+ auxv.push_back(buildAuxVect(SPARC_AT_PHNUM, elfObject->programHeaderCount()));
+ //This is the address of the elf "interpreter", It should be set
+ //to 0 for regular executables. It should be something else
+ //(not sure what) for dynamic libraries.
+ auxv.push_back(buildAuxVect(SPARC_AT_BASE, 0));
+ //This is hardwired to 0 in the elf loading code in the kernel
+ auxv.push_back(buildAuxVect(SPARC_AT_FLAGS, 0));
+ //The entry point to the program
+ auxv.push_back(buildAuxVect(SPARC_AT_ENTRY, objFile->entryPoint()));
+ //Different user and group IDs
+ auxv.push_back(buildAuxVect(SPARC_AT_UID, 100));
+ auxv.push_back(buildAuxVect(SPARC_AT_EUID, 100));
+ auxv.push_back(buildAuxVect(SPARC_AT_GID, 100));
+ auxv.push_back(buildAuxVect(SPARC_AT_EGID, 100));
+ //Whether to enable "secure mode" in the executable
+ auxv.push_back(buildAuxVect(SPARC_AT_SECURE, 0));
+ }
//Figure out how big the initial stack needs to be
--- /dev/null
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ * Ali Saidi
+ */
+
+#include "arch/sparc/regfile.hh"
+#include "cpu/thread_context.hh"
+
+class Checkpoint;
+
+using namespace SparcISA;
+using namespace std;
+
+//RegFile class methods
+Addr RegFile::readPC()
+{
+ return pc;
+}
+
+void RegFile::setPC(Addr val)
+{
+ pc = val;
+}
+
+Addr RegFile::readNextPC()
+{
+ return npc;
+}
+
+void RegFile::setNextPC(Addr val)
+{
+ npc = val;
+}
+
+Addr RegFile::readNextNPC()
+{
+ return nnpc;
+}
+
+void RegFile::setNextNPC(Addr val)
+{
+ nnpc = val;
+}
+
+void RegFile::clear()
+{
+ intRegFile.clear();
+ floatRegFile.clear();
+}
+
+MiscReg RegFile::readMiscReg(int miscReg)
+{
+ return miscRegFile.readReg(miscReg);
+}
+
+MiscReg RegFile::readMiscRegWithEffect(int miscReg,
+ Fault &fault, ThreadContext *tc)
+{
+ return miscRegFile.readRegWithEffect(miscReg, fault, tc);
+}
+
+Fault RegFile::setMiscReg(int miscReg, const MiscReg &val)
+{
+ return miscRegFile.setReg(miscReg, val);
+}
+
+Fault RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val,
+ ThreadContext * tc)
+{
+ return miscRegFile.setRegWithEffect(miscReg, val, tc);
+}
+
+FloatReg RegFile::readFloatReg(int floatReg, int width)
+{
+ return floatRegFile.readReg(floatReg, width);
+}
+
+FloatReg RegFile::readFloatReg(int floatReg)
+{
+ //Use the "natural" width of a single float
+ return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth);
+}
+
+FloatRegBits RegFile::readFloatRegBits(int floatReg, int width)
+{
+ return floatRegFile.readRegBits(floatReg, width);
+}
+
+FloatRegBits RegFile::readFloatRegBits(int floatReg)
+{
+ //Use the "natural" width of a single float
+ return floatRegFile.readRegBits(floatReg,
+ FloatRegFile::SingleWidth);
+}
+
+Fault RegFile::setFloatReg(int floatReg, const FloatReg &val, int width)
+{
+ return floatRegFile.setReg(floatReg, val, width);
+}
+
+Fault RegFile::setFloatReg(int floatReg, const FloatReg &val)
+{
+ //Use the "natural" width of a single float
+ return setFloatReg(floatReg, val, FloatRegFile::SingleWidth);
+}
+
+Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
+{
+ return floatRegFile.setRegBits(floatReg, val, width);
+}
+
+Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
+{
+ //Use the "natural" width of a single float
+ return floatRegFile.setRegBits(floatReg, val,
+ FloatRegFile::SingleWidth);
+}
+
+IntReg RegFile::readIntReg(int intReg)
+{
+ return intRegFile.readReg(intReg);
+}
+
+Fault RegFile::setIntReg(int intReg, const IntReg &val)
+{
+ return intRegFile.setReg(intReg, val);
+}
+
+void RegFile::serialize(std::ostream &os)
+{
+ intRegFile.serialize(os);
+ floatRegFile.serialize(os);
+ miscRegFile.serialize(os);
+ SERIALIZE_SCALAR(pc);
+ SERIALIZE_SCALAR(npc);
+}
+
+void RegFile::unserialize(Checkpoint *cp, const std::string §ion)
+{
+ intRegFile.unserialize(cp, section);
+ floatRegFile.unserialize(cp, section);
+ miscRegFile.unserialize(cp, section);
+ UNSERIALIZE_SCALAR(pc);
+ UNSERIALIZE_SCALAR(npc);
+}
+
+void RegFile::changeContext(RegContextParam param, RegContextVal val)
+{
+ switch(param)
+ {
+ case CONTEXT_CWP:
+ intRegFile.setCWP(val);
+ break;
+ case CONTEXT_GLOBALS:
+ intRegFile.setGlobals(val);
+ break;
+ default:
+ panic("Tried to set illegal context parameter in the SPARC regfile.\n");
+ }
+}
+
+int SparcISA::InterruptLevel(uint64_t softint)
+{
+ if (softint & 0x10000 || softint & 0x1)
+ return 14;
+
+ int level = 14;
+ while (level >= 0 && !(1 << (level + 1) & softint))
+ level--;
+ if (1 << (level + 1) & softint)
+ return level;
+ return 0;
+}
+
+void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+
+ uint8_t tl = src->readMiscReg(MISCREG_TL);
+
+ // Read all the trap level dependent registers and save them off
+ for(int i = 1; i <= MaxTL; i++)
+ {
+ src->setMiscReg(MISCREG_TL, i);
+ dest->setMiscReg(MISCREG_TL, i);
+
+ dest->setMiscReg(MISCREG_TT, src->readMiscReg(MISCREG_TT));
+ dest->setMiscReg(MISCREG_TPC, src->readMiscReg(MISCREG_TPC));
+ dest->setMiscReg(MISCREG_TNPC, src->readMiscReg(MISCREG_TNPC));
+ dest->setMiscReg(MISCREG_TSTATE, src->readMiscReg(MISCREG_TSTATE));
+ }
+
+ // Save off the traplevel
+ dest->setMiscReg(MISCREG_TL, tl);
+ src->setMiscReg(MISCREG_TL, tl);
+
+
+ // ASRs
+ dest->setMiscReg(MISCREG_Y, src->readMiscReg(MISCREG_Y));
+ dest->setMiscReg(MISCREG_CCR, src->readMiscReg(MISCREG_CCR));
+ dest->setMiscReg(MISCREG_ASI, src->readMiscReg(MISCREG_ASI));
+ dest->setMiscReg(MISCREG_TICK, src->readMiscReg(MISCREG_TICK));
+ dest->setMiscReg(MISCREG_FPRS, src->readMiscReg(MISCREG_FPRS));
+ dest->setMiscReg(MISCREG_SOFTINT, src->readMiscReg(MISCREG_SOFTINT));
+ dest->setMiscReg(MISCREG_TICK_CMPR, src->readMiscReg(MISCREG_TICK_CMPR));
+ dest->setMiscReg(MISCREG_STICK, src->readMiscReg(MISCREG_STICK));
+ dest->setMiscReg(MISCREG_STICK_CMPR, src->readMiscReg(MISCREG_STICK_CMPR));
+
+ // Priv Registers
+ dest->setMiscReg(MISCREG_TICK, src->readMiscReg(MISCREG_TICK));
+ dest->setMiscReg(MISCREG_TBA, src->readMiscReg(MISCREG_TBA));
+ dest->setMiscReg(MISCREG_PSTATE, src->readMiscReg(MISCREG_PSTATE));
+ dest->setMiscReg(MISCREG_PIL, src->readMiscReg(MISCREG_PIL));
+ dest->setMiscReg(MISCREG_CWP, src->readMiscReg(MISCREG_CWP));
+ dest->setMiscReg(MISCREG_CANSAVE, src->readMiscReg(MISCREG_CANSAVE));
+ dest->setMiscReg(MISCREG_CANRESTORE, src->readMiscReg(MISCREG_CANRESTORE));
+ dest->setMiscReg(MISCREG_OTHERWIN, src->readMiscReg(MISCREG_OTHERWIN));
+ dest->setMiscReg(MISCREG_CLEANWIN, src->readMiscReg(MISCREG_CLEANWIN));
+ dest->setMiscReg(MISCREG_WSTATE, src->readMiscReg(MISCREG_WSTATE));
+ dest->setMiscReg(MISCREG_GL, src->readMiscReg(MISCREG_GL));
+
+ // Hyperprivilged registers
+ dest->setMiscReg(MISCREG_HPSTATE, src->readMiscReg(MISCREG_HPSTATE));
+ dest->setMiscReg(MISCREG_HINTP, src->readMiscReg(MISCREG_HINTP));
+ dest->setMiscReg(MISCREG_HTBA, src->readMiscReg(MISCREG_HTBA));
+ dest->setMiscReg(MISCREG_STRAND_STS_REG,
+ src->readMiscReg(MISCREG_STRAND_STS_REG));
+ dest->setMiscReg(MISCREG_HSTICK_CMPR,
+ src->readMiscReg(MISCREG_HSTICK_CMPR));
+
+ // FSR
+ dest->setMiscReg(MISCREG_FSR, src->readMiscReg(MISCREG_FSR));
+}
+
+void SparcISA::copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+ // First loop through the integer registers.
+ for (int i = 0; i < TheISA::NumIntRegs; ++i) {
+ dest->setIntReg(i, src->readIntReg(i));
+ }
+
+ // Then loop through the floating point registers.
+ for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
+ dest->setFloatRegBits(i, src->readFloatRegBits(i));
+ }
+
+ // Copy misc. registers
+ copyMiscRegs(src, dest);
+
+ // Lastly copy PC/NPC
+ dest->setPC(src->readPC());
+ dest->setNextPC(src->readNextPC());
+ dest->setNextNPC(src->readNextNPC());
+}
#ifndef __ARCH_SPARC_REGFILE_HH__
#define __ARCH_SPARC_REGFILE_HH__
-#include "arch/sparc/exceptions.hh"
#include "arch/sparc/faults.hh"
-#include "base/trace.hh"
-#include "sim/byteswap.hh"
-#include "cpu/cpuevent.hh"
+#include "arch/sparc/floatregfile.hh"
+#include "arch/sparc/intregfile.hh"
+#include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/miscregfile.hh"
+#include "arch/sparc/types.hh"
#include "sim/host.hh"
+#include <string>
+
class Checkpoint;
namespace SparcISA
{
-
- typedef uint8_t RegIndex;
-
- // MAXTL - maximum trap level
- const int MaxPTL = 2;
- const int MaxTL = 6;
- const int MaxGL = 3;
- const int MaxPGL = 2;
-
- // NWINDOWS - number of register windows, can be 3 to 32
- const int NWindows = 32;
-
-
- const int AsrStart = 0;
- const int PrStart = 32;
- const int HprStart = 64;
- const int MiscStart = 96;
-
- const uint64_t Bit64 = (1ULL << 63);
-
- class IntRegFile
+ class RegFile
{
protected:
- static const int FrameOffsetBits = 3;
- static const int FrameNumBits = 2;
-
- static const int RegsPerFrame = 1 << FrameOffsetBits;
- static const int FrameNumMask =
- (FrameNumBits == sizeof(int)) ?
- (unsigned int)(-1) :
- (1 << FrameNumBits) - 1;
- static const int FrameOffsetMask =
- (FrameOffsetBits == sizeof(int)) ?
- (unsigned int)(-1) :
- (1 << FrameOffsetBits) - 1;
-
- IntReg regGlobals[MaxGL][RegsPerFrame];
- IntReg regSegments[2 * NWindows][RegsPerFrame];
-
- enum regFrame {Globals, Outputs, Locals, Inputs, NumFrames};
-
- IntReg * regView[NumFrames];
-
- static const int RegGlobalOffset = 0;
- static const int FrameOffset = MaxGL * RegsPerFrame;
- int offset[NumFrames];
+ Addr pc; // Program Counter
+ Addr npc; // Next Program Counter
+ Addr nnpc;
public:
+ Addr readPC();
+ void setPC(Addr val);
- int flattenIndex(int reg)
- {
- int flatIndex = offset[reg >> FrameOffsetBits]
- | (reg & FrameOffsetMask);
- DPRINTF(Sparc, "Flattened index %d into %d.\n", reg, flatIndex);
- return flatIndex;
- }
-
- void clear()
- {
- int x;
- for (x = 0; x < MaxGL; x++)
- memset(regGlobals[x], 0, sizeof(regGlobals[x]));
- for(int x = 0; x < 2 * NWindows; x++)
- bzero(regSegments[x], sizeof(regSegments[x]));
- }
-
- IntRegFile()
- {
- offset[Globals] = 0;
- regView[Globals] = regGlobals[0];
- setCWP(0);
- clear();
- }
-
- IntReg readReg(int intReg)
- {
- IntReg val =
- regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask];
- DPRINTF(Sparc, "Read register %d = 0x%x\n", intReg, val);
- return val;
- }
-
- Fault setReg(int intReg, const IntReg &val)
- {
- if(intReg)
- DPRINTF(Sparc, "Wrote register %d = 0x%x\n", intReg, val);
- regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask] = val;
- return NoFault;
- }
-
- //This doesn't effect the actual CWP register.
- //It's purpose is to adjust the view of the register file
- //to what it would be if CWP = cwp.
- void setCWP(int cwp)
- {
- int index = ((NWindows - cwp) % NWindows) * 2;
- offset[Outputs] = FrameOffset + (index * RegsPerFrame);
- offset[Locals] = FrameOffset + ((index+1) * RegsPerFrame);
- offset[Inputs] = FrameOffset +
- (((index+2) % (NWindows * 2)) * RegsPerFrame);
- regView[Outputs] = regSegments[index];
- regView[Locals] = regSegments[index+1];
- regView[Inputs] = regSegments[(index+2) % (NWindows * 2)];
-
- DPRINTF(Sparc, "Changed the CWP value to %d\n", cwp);
- }
-
- void setGlobals(int gl)
- {
-
- DPRINTF(Sparc, "Now using %d globals", gl);
-
- regView[Globals] = regGlobals[gl];
- offset[Globals] = RegGlobalOffset + gl * RegsPerFrame;
- }
-
- void serialize(std::ostream &os);
-
- void unserialize(Checkpoint *cp, const std::string §ion);
- };
-
- typedef float float32_t;
- typedef double float64_t;
- //FIXME long double refers to a 10 byte float, rather than a
- //16 byte float as required. This data type may have to be emulated.
- typedef double float128_t;
+ Addr readNextPC();
+ void setNextPC(Addr val);
- class FloatRegFile
- {
- public:
- static const int SingleWidth = 32;
- static const int DoubleWidth = 64;
- static const int QuadWidth = 128;
+ Addr readNextNPC();
+ void setNextNPC(Addr val);
protected:
-
- //Since the floating point registers overlap each other,
- //A generic storage space is used. The float to be returned is
- //pulled from the appropriate section of this region.
- char regSpace[SingleWidth / 8 * NumFloatRegs];
+ IntRegFile intRegFile; // integer register file
+ FloatRegFile floatRegFile; // floating point register file
+ MiscRegFile miscRegFile; // control register file
public:
- void clear()
- {
- bzero(regSpace, sizeof(regSpace));
- }
-
- FloatReg readReg(int floatReg, int width)
- {
- //In each of these cases, we have to copy the value into a temporary
- //variable. This is because we may otherwise try to access an
- //unaligned portion of memory.
- switch(width)
- {
- case SingleWidth:
- float32_t result32;
- memcpy(&result32, regSpace + 4 * floatReg, width);
- return htog(result32);
- case DoubleWidth:
- float64_t result64;
- memcpy(&result64, regSpace + 4 * floatReg, width);
- return htog(result64);
- case QuadWidth:
- float128_t result128;
- memcpy(&result128, regSpace + 4 * floatReg, width);
- return htog(result128);
- default:
- panic("Attempted to read a %d bit floating point register!", width);
- }
- }
-
- FloatRegBits readRegBits(int floatReg, int width)
- {
- //In each of these cases, we have to copy the value into a temporary
- //variable. This is because we may otherwise try to access an
- //unaligned portion of memory.
- switch(width)
- {
- case SingleWidth:
- uint32_t result32;
- memcpy(&result32, regSpace + 4 * floatReg, width);
- return htog(result32);
- case DoubleWidth:
- uint64_t result64;
- memcpy(&result64, regSpace + 4 * floatReg, width);
- return htog(result64);
- case QuadWidth:
- uint64_t result128;
- memcpy(&result128, regSpace + 4 * floatReg, width);
- return htog(result128);
- default:
- panic("Attempted to read a %d bit floating point register!", width);
- }
- }
-
- Fault setReg(int floatReg, const FloatReg &val, int width)
- {
- //In each of these cases, we have to copy the value into a temporary
- //variable. This is because we may otherwise try to access an
- //unaligned portion of memory.
-
- uint32_t result32;
- uint64_t result64;
- switch(width)
- {
- case SingleWidth:
- result32 = gtoh((uint32_t)val);
- memcpy(regSpace + 4 * floatReg, &result32, width);
- break;
- case DoubleWidth:
- result64 = gtoh((uint64_t)val);
- memcpy(regSpace + 4 * floatReg, &result64, width);
- break;
- case QuadWidth:
- panic("Quad width FP not implemented.");
- break;
- default:
- panic("Attempted to read a %d bit floating point register!", width);
- }
- return NoFault;
- }
-
- Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
- {
- //In each of these cases, we have to copy the value into a temporary
- //variable. This is because we may otherwise try to access an
- //unaligned portion of memory.
- uint32_t result32;
- uint64_t result64;
- switch(width)
- {
- case SingleWidth:
- result32 = gtoh((uint32_t)val);
- memcpy(regSpace + 4 * floatReg, &result32, width);
- break;
- case DoubleWidth:
- result64 = gtoh((uint64_t)val);
- memcpy(regSpace + 4 * floatReg, &result64, width);
- break;
- case QuadWidth:
- panic("Quad width FP not implemented.");
- break;
- default:
- panic("Attempted to read a %d bit floating point register!", width);
- }
- return NoFault;
- }
+ void clear();
- void serialize(std::ostream &os);
+ int FlattenIntIndex(int reg);
- void unserialize(Checkpoint *cp, const std::string §ion);
- };
+ MiscReg readMiscReg(int miscReg);
- enum MiscRegIndex
- {
- /** Ancillary State Registers */
- MISCREG_Y = AsrStart + 0,
- MISCREG_CCR = AsrStart + 2,
- MISCREG_ASI = AsrStart + 3,
- MISCREG_TICK = AsrStart + 4,
- MISCREG_PC = AsrStart + 5,
- MISCREG_FPRS = AsrStart + 6,
- MISCREG_PCR = AsrStart + 16,
- MISCREG_PIC = AsrStart + 17,
- MISCREG_GSR = AsrStart + 19,
- MISCREG_SOFTINT_SET = AsrStart + 20,
- MISCREG_SOFTINT_CLR = AsrStart + 21,
- MISCREG_SOFTINT = AsrStart + 22,
- MISCREG_TICK_CMPR = AsrStart + 23,
- MISCREG_STICK = AsrStart + 24,
- MISCREG_STICK_CMPR = AsrStart + 25,
-
- /** Privilged Registers */
- MISCREG_TPC = PrStart + 0,
- MISCREG_TNPC = PrStart + 1,
- MISCREG_TSTATE = PrStart + 2,
- MISCREG_TT = PrStart + 3,
- MISCREG_PRIVTICK = PrStart + 4,
- MISCREG_TBA = PrStart + 5,
- MISCREG_PSTATE = PrStart + 6,
- MISCREG_TL = PrStart + 7,
- MISCREG_PIL = PrStart + 8,
- MISCREG_CWP = PrStart + 9,
- MISCREG_CANSAVE = PrStart + 10,
- MISCREG_CANRESTORE = PrStart + 11,
- MISCREG_CLEANWIN = PrStart + 12,
- MISCREG_OTHERWIN = PrStart + 13,
- MISCREG_WSTATE = PrStart + 14,
- MISCREG_GL = PrStart + 16,
-
- /** Hyper privileged registers */
- MISCREG_HPSTATE = HprStart + 0,
- MISCREG_HTSTATE = HprStart + 1,
- MISCREG_HINTP = HprStart + 3,
- MISCREG_HTBA = HprStart + 5,
- MISCREG_HVER = HprStart + 6,
- MISCREG_STRAND_STS_REG = HprStart + 16,
- MISCREG_HSTICK_CMPR = HprStart + 31,
-
- /** Floating Point Status Register */
- MISCREG_FSR = MiscStart + 0
+ MiscReg readMiscRegWithEffect(int miscReg,
+ Fault &fault, ThreadContext *tc);
- };
+ Fault setMiscReg(int miscReg, const MiscReg &val);
- // The control registers, broken out into fields
- class MiscRegFile
- {
- private:
-
- /* ASR Registers */
- union {
- uint64_t y; // Y (used in obsolete multiplication)
- struct {
- uint64_t value:32; // The actual value stored in y
- uint64_t :32; // reserved bits
- } yFields;
- };
- union {
- uint8_t ccr; // Condition Code Register
- struct {
- union {
- uint8_t icc:4; // 32-bit condition codes
- struct {
- uint8_t c:1; // Carry
- uint8_t v:1; // Overflow
- uint8_t z:1; // Zero
- uint8_t n:1; // Negative
- } iccFields;
- };
- union {
- uint8_t xcc:4; // 64-bit condition codes
- struct {
- uint8_t c:1; // Carry
- uint8_t v:1; // Overflow
- uint8_t z:1; // Zero
- uint8_t n:1; // Negative
- } xccFields;
- };
- } ccrFields;
- };
- uint8_t asi; // Address Space Identifier
- union {
- uint64_t tick; // Hardware clock-tick counter
- struct {
- int64_t counter:63; // Clock-tick count
- uint64_t npt:1; // Non-priveleged trap
- } tickFields;
- };
- union {
- uint8_t fprs; // Floating-Point Register State
- struct {
- uint8_t dl:1; // Dirty lower
- uint8_t du:1; // Dirty upper
- uint8_t fef:1; // FPRS enable floating-Point
- } fprsFields;
- };
- union {
- uint64_t softint;
- struct {
- uint64_t tm:1;
- uint64_t int_level:14;
- uint64_t sm:1;
- } softintFields;
- };
- union {
- uint64_t tick_cmpr; // Hardware tick compare registers
- struct {
- uint64_t tick_cmpr:63; // Clock-tick count
- uint64_t int_dis:1; // Non-priveleged trap
- } tick_cmprFields;
- };
- union {
- uint64_t stick; // Hardware clock-tick counter
- struct {
- int64_t :63; // Not used, storage in SparcSystem
- uint64_t npt:1; // Non-priveleged trap
- } stickFields;
- };
- union {
- uint64_t stick_cmpr; // Hardware tick compare registers
- struct {
- uint64_t tick_cmpr:63; // Clock-tick count
- uint64_t int_dis:1; // Non-priveleged trap
- } stick_cmprFields;
- };
-
-
- /* Privileged Registers */
- uint64_t tpc[MaxTL]; // Trap Program Counter (value from
- // previous trap level)
- uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
- // previous trap level)
- union {
- uint64_t tstate[MaxTL]; // Trap State
- struct {
- //Values are from previous trap level
- uint64_t cwp:5; // Current Window Pointer
- uint64_t :3; // Reserved bits
- uint64_t pstate:13; // Process State
- uint64_t :3; // Reserved bits
- uint64_t asi:8; // Address Space Identifier
- uint64_t ccr:8; // Condition Code Register
- uint64_t gl:8; // Global level
- } tstateFields[MaxTL];
- };
- uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
- // on the previous level)
- uint64_t tba; // Trap Base Address
-
- union {
- uint16_t pstate; // Process State Register
- struct {
- uint16_t :1; // reserved
- uint16_t ie:1; // Interrupt enable
- uint16_t priv:1; // Privelege mode
- uint16_t am:1; // Address mask
- uint16_t pef:1; // PSTATE enable floating-point
- uint16_t :1; // reserved2
- uint16_t mm:2; // Memory Model
- uint16_t tle:1; // Trap little-endian
- uint16_t cle:1; // Current little-endian
- } pstateFields;
- };
- uint8_t tl; // Trap Level
- uint8_t pil; // Process Interrupt Register
- uint8_t cwp; // Current Window Pointer
- uint8_t cansave; // Savable windows
- uint8_t canrestore; // Restorable windows
- uint8_t cleanwin; // Clean windows
- uint8_t otherwin; // Other windows
- union {
- uint8_t wstate; // Window State
- struct {
- uint8_t normal:3; // Bits TT<4:2> are set to on a normal
- // register window trap
- uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin"
- // register window trap
- } wstateFields;
- };
- uint8_t gl; // Global level register
-
-
- /** Hyperprivileged Registers */
- union {
- uint64_t hpstate; // Hyperprivileged State Register
- struct {
- uint8_t tlz: 1;
- uint8_t :1;
- uint8_t hpriv:1;
- uint8_t :2;
- uint8_t red:1;
- uint8_t :4;
- uint8_t ibe:1;
- uint8_t id:1;
- } hpstateFields;
- };
-
- uint64_t htstate[MaxTL]; // Hyperprivileged Trap State Register
- uint64_t hintp;
- uint64_t htba; // Hyperprivileged Trap Base Address register
- union {
- uint64_t hstick_cmpr; // Hardware tick compare registers
- struct {
- uint64_t tick_cmpr:63; // Clock-tick count
- uint64_t int_dis:1; // Non-priveleged trap
- } hstick_cmprFields;
- };
-
- uint64_t strandStatusReg; // Per strand status register
-
-
- /** Floating point misc registers. */
- union {
- uint64_t fsr; // Floating-Point State Register
- struct {
- union {
- uint64_t cexc:5; // Current excpetion
- struct {
- uint64_t nxc:1; // Inexact
- uint64_t dzc:1; // Divide by zero
- uint64_t ufc:1; // Underflow
- uint64_t ofc:1; // Overflow
- uint64_t nvc:1; // Invalid operand
- } cexcFields;
- };
- union {
- uint64_t aexc:5; // Accrued exception
- struct {
- uint64_t nxc:1; // Inexact
- uint64_t dzc:1; // Divide by zero
- uint64_t ufc:1; // Underflow
- uint64_t ofc:1; // Overflow
- uint64_t nvc:1; // Invalid operand
- } aexcFields;
- };
- uint64_t fcc0:2; // Floating-Point condtion codes
- uint64_t :1; // Reserved bits
- uint64_t qne:1; // Deferred trap queue not empty
- // with no queue, it should read 0
- uint64_t ftt:3; // Floating-Point trap type
- uint64_t ver:3; // Version (of the FPU)
- uint64_t :2; // Reserved bits
- uint64_t ns:1; // Nonstandard floating point
- union {
- uint64_t tem:5; // Trap Enable Mask
- struct {
- uint64_t nxm:1; // Inexact
- uint64_t dzm:1; // Divide by zero
- uint64_t ufm:1; // Underflow
- uint64_t ofm:1; // Overflow
- uint64_t nvm:1; // Invalid operand
- } temFields;
- };
- uint64_t :2; // Reserved bits
- uint64_t rd:2; // Rounding direction
- uint64_t fcc1:2; // Floating-Point condition codes
- uint64_t fcc2:2; // Floating-Point condition codes
- uint64_t fcc3:2; // Floating-Point condition codes
- uint64_t :26; // Reserved bits
- } fsrFields;
- };
-
- // These need to check the int_dis field and if 0 then
- // set appropriate bit in softint and checkinterrutps on the cpu
-#if FULL_SYSTEM
- /** Process a tick compare event and generate an interrupt on the cpu if
- * appropriate. */
- void processTickCompare(ThreadContext *tc);
- void processSTickCompare(ThreadContext *tc);
- void processHSTickCompare(ThreadContext *tc);
-
- typedef CpuEventWrapper<MiscRegFile,
- &MiscRegFile::processTickCompare> TickCompareEvent;
- TickCompareEvent *tickCompare;
-
- typedef CpuEventWrapper<MiscRegFile,
- &MiscRegFile::processSTickCompare> STickCompareEvent;
- STickCompareEvent *sTickCompare;
-
- typedef CpuEventWrapper<MiscRegFile,
- &MiscRegFile::processHSTickCompare> HSTickCompareEvent;
- HSTickCompareEvent *hSTickCompare;
-
- /** Fullsystem only register version of ReadRegWithEffect() */
- MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
- /** Fullsystem only register version of SetRegWithEffect() */
- Fault setFSRegWithEffect(int miscReg, const MiscReg &val,
+ Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
ThreadContext * tc);
-#endif
- public:
- void reset()
- {
- pstateFields.pef = 0; //No FPU
- //pstateFields.pef = 1; //FPU
-#if FULL_SYSTEM
- //For SPARC, when a system is first started, there is a power
- //on reset Trap which sets the processor into the following state.
- //Bits that aren't set aren't defined on startup.
- tl = MaxTL;
- gl = MaxGL;
-
- tickFields.counter = 0; //The TICK register is unreadable bya
- tickFields.npt = 1; //The TICK register is unreadable by by !priv
-
- softint = 0; // Clear all the soft interrupt bits
- tick_cmprFields.int_dis = 1; // disable timer compare interrupts
- tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
- stickFields.npt = 1; //The TICK register is unreadable by by !priv
- stick_cmprFields.int_dis = 1; // disable timer compare interrupts
- stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
-
-
- tt[tl] = power_on_reset;
- pstate = 0; // fields 0 but pef
- pstateFields.pef = 1;
-
- hpstate = 0;
- hpstateFields.red = 1;
- hpstateFields.hpriv = 1;
- hpstateFields.tlz = 0; // this is a guess
-
- hintp = 0; // no interrupts pending
- hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
- hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
-
-#else
-/* //This sets up the initial state of the processor for usermode processes
- pstateFields.priv = 0; //Process runs in user mode
- pstateFields.ie = 1; //Interrupts are enabled
- fsrFields.rd = 0; //Round to nearest
- fsrFields.tem = 0; //Floating point traps not enabled
- fsrFields.ns = 0; //Non standard mode off
- fsrFields.qne = 0; //Floating point queue is empty
- fsrFields.aexc = 0; //No accrued exceptions
- fsrFields.cexc = 0; //No current exceptions
-
- //Register window management registers
- otherwin = 0; //No windows contain info from other programs
- canrestore = 0; //There are no windows to pop
- cansave = MaxTL - 2; //All windows are available to save into
- cleanwin = MaxTL;*/
-#endif
- }
-
- MiscRegFile()
- {
- reset();
- }
-
- /** read a value out of an either an SE or FS IPR. No checking is done
- * about SE vs. FS as this is mostly used to copy the regfile. Thus more
- * register are copied that are necessary for FS. However this prevents
- * a bunch of ifdefs and is rarely called so is not performance
- * criticial. */
- MiscReg readReg(int miscReg);
-
- /** Read a value from an IPR. Only the SE iprs are here and the rest
- * are are readFSRegWithEffect (which is called by readRegWithEffect()).
- * Checking is done for permission based on state bits in the miscreg
- * file. */
- MiscReg readRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
-
- /** write a value into an either an SE or FS IPR. No checking is done
- * about SE vs. FS as this is mostly used to copy the regfile. Thus more
- * register are copied that are necessary for FS. However this prevents
- * a bunch of ifdefs and is rarely called so is not performance
- * criticial.*/
- Fault setReg(int miscReg, const MiscReg &val);
-
- /** Write a value into an IPR. Only the SE iprs are here and the rest
- * are are setFSRegWithEffect (which is called by setRegWithEffect()).
- * Checking is done for permission based on state bits in the miscreg
- * file. */
- Fault setRegWithEffect(int miscReg,
- const MiscReg &val, ThreadContext * tc);
-
- void serialize(std::ostream & os);
-
- void unserialize(Checkpoint * cp, const std::string & section);
-
- void copyMiscRegs(ThreadContext * tc);
-
- bool isHyperPriv() { return hpstateFields.hpriv; }
- bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; }
- bool isNonPriv() { return !isPriv(); }
- };
+ FloatReg readFloatReg(int floatReg, int width);
- typedef union
- {
- IntReg intreg;
- FloatReg fpreg;
- MiscReg ctrlreg;
- } AnyReg;
+ FloatReg readFloatReg(int floatReg);
- class RegFile
- {
- protected:
- Addr pc; // Program Counter
- Addr npc; // Next Program Counter
- Addr nnpc;
-
- public:
- Addr readPC()
- {
- return pc;
- }
-
- void setPC(Addr val)
- {
- pc = val;
- }
-
- Addr readNextPC()
- {
- return npc;
- }
-
- void setNextPC(Addr val)
- {
- npc = val;
- }
-
- Addr readNextNPC()
- {
- return nnpc;
- }
-
- void setNextNPC(Addr val)
- {
- nnpc = val;
- }
-
- protected:
- IntRegFile intRegFile; // integer register file
- FloatRegFile floatRegFile; // floating point register file
- MiscRegFile miscRegFile; // control register file
+ FloatRegBits readFloatRegBits(int floatReg, int width);
- public:
+ FloatRegBits readFloatRegBits(int floatReg);
- void clear()
- {
- intRegFile.clear();
- floatRegFile.clear();
- }
+ Fault setFloatReg(int floatReg, const FloatReg &val, int width);
- int FlattenIntIndex(int reg)
- {
- return intRegFile.flattenIndex(reg);
- }
+ Fault setFloatReg(int floatReg, const FloatReg &val);
- MiscReg readMiscReg(int miscReg)
- {
- return miscRegFile.readReg(miscReg);
- }
+ Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width);
- MiscReg readMiscRegWithEffect(int miscReg,
- Fault &fault, ThreadContext *tc)
- {
- return miscRegFile.readRegWithEffect(miscReg, fault, tc);
- }
+ Fault setFloatRegBits(int floatReg, const FloatRegBits &val);
- Fault setMiscReg(int miscReg, const MiscReg &val)
- {
- return miscRegFile.setReg(miscReg, val);
- }
+ IntReg readIntReg(int intReg);
- Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
- ThreadContext * tc)
- {
- return miscRegFile.setRegWithEffect(miscReg, val, tc);
- }
-
- FloatReg readFloatReg(int floatReg, int width)
- {
- return floatRegFile.readReg(floatReg, width);
- }
-
- FloatReg readFloatReg(int floatReg)
- {
- //Use the "natural" width of a single float
- return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth);
- }
-
- FloatRegBits readFloatRegBits(int floatReg, int width)
- {
- return floatRegFile.readRegBits(floatReg, width);
- }
-
- FloatRegBits readFloatRegBits(int floatReg)
- {
- //Use the "natural" width of a single float
- return floatRegFile.readRegBits(floatReg,
- FloatRegFile::SingleWidth);
- }
-
- Fault setFloatReg(int floatReg, const FloatReg &val, int width)
- {
- return floatRegFile.setReg(floatReg, val, width);
- }
-
- Fault setFloatReg(int floatReg, const FloatReg &val)
- {
- //Use the "natural" width of a single float
- return setFloatReg(floatReg, val, FloatRegFile::SingleWidth);
- }
-
- Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
- {
- return floatRegFile.setRegBits(floatReg, val, width);
- }
-
- Fault setFloatRegBits(int floatReg, const FloatRegBits &val)
- {
- //Use the "natural" width of a single float
- return floatRegFile.setRegBits(floatReg, val,
- FloatRegFile::SingleWidth);
- }
-
- IntReg readIntReg(int intReg)
- {
- return intRegFile.readReg(intReg);
- }
-
- Fault setIntReg(int intReg, const IntReg &val)
- {
- return intRegFile.setReg(intReg, val);
- }
+ Fault setIntReg(int intReg, const IntReg &val);
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string §ion);
public:
- enum ContextParam
- {
- CONTEXT_CWP,
- CONTEXT_GLOBALS
- };
- typedef int ContextVal;
-
- void changeContext(ContextParam param, ContextVal val)
- {
- switch(param)
- {
- case CONTEXT_CWP:
- intRegFile.setCWP(val);
- break;
- case CONTEXT_GLOBALS:
- intRegFile.setGlobals(val);
- break;
- default:
- panic("Tried to set illegal context parameter in the SPARC regfile.\n");
- }
- }
+ void changeContext(RegContextParam param, RegContextVal val);
};
void copyRegs(ThreadContext *src, ThreadContext *dest);
#include "arch/sparc/solaris/solaris.hh"
+#include <fcntl.h>
+
// open(2) flags translation table
OpenFlagTransTable SparcSolaris::openFlagTable[] = {
#ifdef _MSC_VER
* Authors: Nathan Binkert
*/
-#ifndef __ARCH_ALPHA_STACKTRACE_HH__
-#define __ARCH_ALPHA_STACKTRACE_HH__
+#ifndef __ARCH_SPARC_STACKTRACE_HH__
+#define __ARCH_SPARC_STACKTRACE_HH__
#include "base/trace.hh"
#include "cpu/static_inst.hh"
return true;
}
-#endif // __ARCH_ALPHA_STACKTRACE_HH__
+#endif // __ARCH_SPARC_STACKTRACE_HH__
--- /dev/null
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_SPARC_SYSCALLRETURN_HH__
+#define __ARCH_SPARC_SYSCALLRETURN_HH__
+
+#include <inttypes.h>
+
+#include "arch/sparc/regfile.hh"
+
+class SyscallReturn
+{
+ public:
+ template <class T>
+ SyscallReturn(T v, bool s)
+ {
+ retval = (uint64_t)v;
+ success = s;
+ }
+
+ template <class T>
+ SyscallReturn(T v)
+ {
+ success = (v >= 0);
+ retval = (uint64_t)v;
+ }
+
+ ~SyscallReturn() {}
+
+ SyscallReturn& operator=(const SyscallReturn& s)
+ {
+ retval = s.retval;
+ success = s.success;
+ return *this;
+ }
+
+ bool successful() { return success; }
+ uint64_t value() { return retval; }
+
+ private:
+ uint64_t retval;
+ bool success;
+};
+
+namespace SparcISA
+{
+ static inline void setSyscallReturn(SyscallReturn return_value,
+ RegFile *regs)
+ {
+ // check for error condition. SPARC syscall convention is to
+ // indicate success/failure in reg the carry bit of the ccr
+ // and put the return value itself in the standard return value reg ().
+ if (return_value.successful()) {
+ // no error, clear XCC.C
+ regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) & 0xEF);
+ regs->setIntReg(ReturnValueReg, return_value.value());
+ } else {
+ // got an error, set XCC.C
+ regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) | 0x10);
+ regs->setIntReg(ReturnValueReg, return_value.value());
+ }
+ }
+};
+
+#endif
BEGIN_DECLARE_SIM_OBJECT_PARAMS(SparcSystem)
SimObjectParam<PhysicalMemory *> physmem;
+ SimpleEnumParam<System::MemoryMode> mem_mode;
Param<std::string> kernel;
Param<std::string> reset_bin;
INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
INIT_PARAM(physmem, "phsyical memory"),
+ INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
+ System::MemoryModeStrings),
INIT_PARAM(kernel, "file that contains the kernel code"),
INIT_PARAM(reset_bin, "file that contains the reset code"),
INIT_PARAM(hypervisor_bin, "file that contains the hypervisor code"),
p->name = getInstanceName();
p->boot_cpu_frequency = boot_cpu_frequency;
p->physmem = physmem;
+ p->mem_mode = mem_mode;
p->kernel_path = kernel;
p->reset_bin = reset_bin;
p->hypervisor_bin = hypervisor_bin;
--- /dev/null
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_SPARC_TYPES_HH__
+#define __ARCH_SPARC_TYPES_HH__
+
+#include <inttypes.h>
+
+namespace SparcISA
+{
+ typedef uint32_t MachInst;
+ typedef uint64_t ExtMachInst;
+
+ typedef uint64_t IntReg;
+ typedef uint64_t MiscReg;
+ typedef double FloatReg;
+ typedef uint64_t FloatRegBits;
+ typedef union
+ {
+ IntReg intReg;
+ FloatReg fpreg;
+ MiscReg ctrlreg;
+ } AnyReg;
+
+ enum RegContextParam
+ {
+ CONTEXT_CWP,
+ CONTEXT_GLOBALS
+ };
+
+ typedef int RegContextVal;
+
+ typedef uint8_t RegIndex;
+}
+
+#endif
int64_t time;
SparcSystem *sys;
switch (miscReg) {
- /** Full system only ASRs */
+ /* Full system only ASRs */
case MISCREG_SOFTINT:
if (isNonPriv())
return new PrivilegedOpcode;
sTickCompare.schedule(time * Clock::Int::ns);
return NoFault;
- /** Fullsystem only Priv registers. */
+ /* Fullsystem only Priv registers. */
case MISCREG_PIL:
if (FULL_SYSTEM) {
setReg(miscReg, val);
} else
panic("PIL not implemented for syscall emulation\n");
- /** Hyper privileged registers */
+ /* Hyper privileged registers */
case MISCREG_HPSTATE:
case MISCREG_HINTP:
setReg(miscReg, val);
{
switch (miscReg) {
- /** Privileged registers. */
+ /* Privileged registers. */
case MISCREG_SOFTINT:
if (isNonPriv()) {
fault = new PrivilegedOpcode;
return readReg(miscReg);
- /** Hyper privileged registers */
+ /* Hyper privileged registers */
case MISCREG_HPSTATE:
case MISCREG_HINTP:
return readReg(miscReg);
public:
/**
* Constructor.
- * @param startAddr The starting address of the region.
+ * @param _startAddr The starting address of the region.
* @param totalSize The total size of the region.
* @param _chunkSize The size/alignment of chunks into which
* the region should be decomposed.
} // while sections
}
+ ElfObject * result = new ElfObject(fname, fd, len, data, arch, opSys);
+
+ //The number of headers in the file
+ result->_programHeaderCount = ehdr.e_phnum;
+ //Record the size of each entry
+ result->_programHeaderSize = ehdr.e_phentsize;
+ if(result->_programHeaderCount) //If there is a program header table
+ {
+ //Figure out the virtual address of the header table in the
+ //final memory image. We use the program headers themselves
+ //to translate from a file offset to the address in the image.
+ GElf_Phdr phdr;
+ uint64_t e_phoff = ehdr.e_phoff;
+ result->_programHeaderTable = 0;
+ for(int hdrnum = 0; hdrnum < result->_programHeaderCount; hdrnum++)
+ {
+ gelf_getphdr(elf, hdrnum, &phdr);
+ //Check if we've found the segment with the headers in it
+ if(phdr.p_offset <= e_phoff &&
+ phdr.p_offset + phdr.p_filesz > e_phoff)
+ {
+ result->_programHeaderTable = phdr.p_vaddr + e_phoff;
+ break;
+ }
+ }
+ }
+ else
+ result->_programHeaderTable = 0;
+
+
elf_end(elf);
- return new ElfObject(fname, fd, len, data, arch, opSys);
+ return result;
}
}
{
protected:
+ //These values are provided to a linux process by the kernel, so we
+ //need to keep them around.
+ Addr _programHeaderTable;
+ uint16_t _programHeaderSize;
+ uint16_t _programHeaderCount;
+
/// Helper functions for loadGlobalSymbols() and loadLocalSymbols().
bool loadSomeSymbols(SymbolTable *symtab, int binding);
static ObjectFile *tryFile(const std::string &fname, int fd,
size_t len, uint8_t *data);
+ Addr programHeaderTable() {return _programHeaderTable;}
+ uint16_t programHeaderSize() {return _programHeaderSize;}
+ uint16_t programHeaderCount() {return _programHeaderCount;}
};
#endif // __ELF_OBJECT_HH__
/// Find the nearest symbol equal to or less than the supplied
/// address (e.g., the label for the enclosing function).
- /// @param address The address to look up.
- /// @param symbol Return reference for symbol string.
- /// @param sym_address Return reference for symbol address.
- /// @param next_sym_address Address of following symbol (for
- /// determining valid range of symbol).
+ /// @param addr The address to look up.
+ /// @param symbol Return reference for symbol string.
+ /// @param symaddr Return reference for symbol address.
+ /// @param nextaddr Address of following symbol (for
+ /// determining valid range of symbol).
/// @retval True if a symbol was found.
bool
findNearestSymbol(Addr addr, std::string &symbol, Addr &symaddr,
}
/// Overload for findNearestSymbol() for callers who don't care
- /// about next_sym_address.
+ /// about nextaddr.
bool
findNearestSymbol(Addr addr, std::string &symbol, Addr &symaddr) const
{
#include <map>
+#include "arch/types.hh"
#include "base/kgdb.h"
#include "cpu/pc_event.hh"
#include "base/pollevent.hh"
# Generate a temporary CPU list, including the CheckerCPU if
# it's enabled. This isn't used for anything else other than StaticInst
# headers.
-temp_cpu_list = env['CPU_MODELS']
+temp_cpu_list = env['CPU_MODELS'][:]
+
if env['USE_CHECKER']:
temp_cpu_list.append('CheckerCPU')
#
#################################################################
+# Keep a list of CPU models that support SMT
+env['SMT_CPU_MODELS'] = []
+
sources = []
need_simple_base = False
''')
if env['USE_CHECKER']:
sources += Split('o3/checker_builder.cc')
+ else:
+ env['SMT_CPU_MODELS'].append('O3CPU') # Checker doesn't support SMT right now
if 'OzoneCPU' in env['CPU_MODELS']:
need_bp_unit = True
*/
Addr nextPC;
+ /** Next non-speculative NPC. Target PC for Mips or Sparc. */
+ Addr nextNPC;
+
/** Predicted next PC. */
Addr predPC;
*/
Addr readNextPC() { return nextPC; }
+ /** Returns the next NPC. This could be the speculative next NPC if it is
+ * called prior to the actual branch target being calculated.
+ */
+ Addr readNextNPC() { return nextNPC; }
+
/** Set the predicted target of this current instruction. */
void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
Addr readPredTarg() { return predPC; }
/** Returns whether the instruction was predicted taken or not. */
- bool predTaken() { return predPC != (PC + sizeof(MachInst)); }
+ bool predTaken()
+#if THE_ISA == ALPHA_ISA
+ { return predPC != (PC + sizeof(MachInst)); }
+#else
+ { return predPC != (nextPC + sizeof(MachInst)); }
+#endif
/** Returns whether the instruction mispredicted. */
- bool mispredicted() { return predPC != nextPC; }
-
+ bool mispredicted()
+#if THE_ISA == ALPHA_ISA
+ { return predPC != nextPC; }
+#else
+ { return predPC != nextNPC; }
+#endif
//
// Instruction types. Forward checks to StaticInst object.
//
bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
bool isCondCtrl() const { return staticInst->isCondCtrl(); }
bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
+ bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
bool isThreadSync() const { return staticInst->isThreadSync(); }
bool isSerializing() const { return staticInst->isSerializing(); }
bool isSerializeBefore() const
nextPC = val;
}
+ /** Set the next NPC of this instruction (the target in Mips or Sparc).*/
+ void setNextNPC(uint64_t val)
+ {
+ nextNPC = val;
+ }
+
/** Sets the ASID. */
void setASID(short addr_space_id) { asid = addr_space_id; }
#include "base/cprintf.hh"
#include "base/trace.hh"
-#include "arch/faults.hh"
+#include "sim/faults.hh"
#include "cpu/exetrace.hh"
#include "mem/request.hh"
#include "cpu/base_dyn_inst.hh"
-using namespace std;
-using namespace TheISA;
-
#define NOHASH
#ifndef NOHASH
#endif
template <class Impl>
-BaseDynInst<Impl>::BaseDynInst(ExtMachInst machInst, Addr inst_PC,
+BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst machInst, Addr inst_PC,
Addr pred_PC, InstSeqNum seq_num,
ImplCPU *cpu)
: staticInst(machInst), traceData(NULL), cpu(cpu)
seqNum = seq_num;
PC = inst_PC;
- nextPC = PC + sizeof(MachInst);
+ nextPC = PC + sizeof(TheISA::MachInst);
+ nextNPC = nextPC + sizeof(TheISA::MachInst);
predPC = pred_PC;
initVars();
BaseDynInst<Impl>::dump()
{
cprintf("T%d : %#08d `", threadNumber, PC);
- cout << staticInst->disassemble(PC);
+ std::cout << staticInst->disassemble(PC);
cprintf("'\n");
}
virtual Counter totalInstructions() const
{
- return numInst - startNumInst;
+ return 0;
}
// number of simulated loads
#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
#define __CPU_CHECKER_THREAD_CONTEXT_HH__
+#include "arch/types.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
#endif
- void changeRegFileContext(RegFile::ContextParam param,
- RegFile::ContextVal val)
+ void changeRegFileContext(TheISA::RegContextParam param,
+ TheISA::RegContextVal val)
{
actualTC->changeRegFileContext(param, val);
checkerTC->changeRegFileContext(param, val);
#include <fstream>
#include <iomanip>
+#include "arch/regfile.hh"
#include "base/loader/symtab.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "sim/system.hh"
using namespace std;
-
+using namespace TheISA;
////////////////////////////////////////////////////////////////////////
//
void
Trace::InstRecord::dump(ostream &outs)
{
- if (flags[INTEL_FORMAT]) {
+ if (flags[PRINT_REG_DELTA])
+ {
+ outs << "PC = 0x" << setbase(16)
+ << setfill('0')
+ << setw(16) << PC << endl;
+ outs << setbase(10)
+ << setfill(' ')
+ << setw(0);
+ /*
+ int numSources = staticInst->numSrcRegs();
+ int numDests = staticInst->numDestRegs();
+ outs << "Sources:";
+ for(int x = 0; x < numSources; x++)
+ {
+ int sourceNum = staticInst->srcRegIdx(x);
+ if(sourceNum < FP_Base_DepTag)
+ outs << " " << getIntRegName(sourceNum);
+ else if(sourceNum < Ctrl_Base_DepTag)
+ outs << " " << getFloatRegName(sourceNum - FP_Base_DepTag);
+ else
+ outs << " " << getMiscRegName(sourceNum - Ctrl_Base_DepTag);
+ }
+ outs << endl;
+ outs << "Destinations:";
+ for(int x = 0; x < numDests; x++)
+ {
+ int destNum = staticInst->destRegIdx(x);
+ if(destNum < FP_Base_DepTag)
+ outs << " " << getIntRegName(destNum);
+ else if(destNum < Ctrl_Base_DepTag)
+ outs << " " << getFloatRegName(destNum - FP_Base_DepTag);
+ else
+ outs << " " << getMiscRegName(destNum - Ctrl_Base_DepTag);
+ }
+ outs << endl;*/
+ }
+ else if (flags[INTEL_FORMAT]) {
#if FULL_SYSTEM
bool is_trace_system = (cpu->system->name() == trace_system);
#else
"print fetch sequence number", false);
Param<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq",
"print correct-path sequence number", false);
+Param<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta",
+ "print which registers changed to what", false);
Param<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol",
"Use symbols for the PC if available", true);
Param<bool> exe_trace_intel_format(&exeTraceParams, "intel_format",
flags[PRINT_INT_REGS] = exe_trace_print_iregs;
flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq;
flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq;
+ flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta;
flags[PC_SYMBOL] = exe_trace_pc_symbol;
flags[INTEL_FORMAT] = exe_trace_intel_format;
trace_system = exe_trace_system;
PRINT_INT_REGS,
PRINT_FETCH_SEQ,
PRINT_CP_SEQ,
+ PRINT_REG_DELTA,
PC_SYMBOL,
INTEL_FORMAT,
NUM_BITS
#ifndef __CPU_O3_2BIT_LOCAL_PRED_HH__
#define __CPU_O3_2BIT_LOCAL_PRED_HH__
-// For Addr type.
-#include "arch/isa_traits.hh"
#include "cpu/o3/sat_counter.hh"
+#include "sim/host.hh"
#include <vector>
alpha/cpu_builder.cc
''')
elif env['TARGET_ISA'] == 'mips':
- sys.exit('O3 CPU does not support MIPS')
- #sources += Split('''
- # mips/dyn_inst.cc
- # mips/cpu.cc
- # mips/thread_context.cc
- # mips/cpu_builder.cc
- # ''')
+ sources += Split('''
+ mips/dyn_inst.cc
+ mips/cpu.cc
+ mips/thread_context.cc
+ mips/cpu_builder.cc
+ ''')
elif env['TARGET_ISA'] == 'sparc':
- sys.exit('O3 CPU does not support MIPS')
- #sources += Split('''
- # sparc/dyn_inst.cc
- # sparc/cpu.cc
- # sparc/thread_context.cc
- # sparc/cpu_builder.cc
- # ''')
+ sources += Split('''
+ sparc/dyn_inst.cc
+ sparc/cpu.cc
+ sparc/thread_context.cc
+ sparc/cpu_builder.cc
+ ''')
else:
sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
#ifndef __CPU_O3_ALPHA_CPU_HH__
#define __CPU_O3_ALPHA_CPU_HH__
-#include "arch/isa_traits.hh"
+#include "arch/regfile.hh"
+#include "arch/types.hh"
#include "cpu/thread_context.hh"
#include "cpu/o3/cpu.hh"
#include "sim/byteswap.hh"
#include "config/use_checker.hh"
#include "arch/alpha/faults.hh"
+#include "arch/alpha/isa_traits.hh"
#include "base/cprintf.hh"
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "sim/system.hh"
#endif
-using namespace TheISA;
-
template <class Impl>
AlphaO3CPU<Impl>::AlphaO3CPU(Params *params)
#if FULL_SYSTEM
template <class Impl>
-MiscReg
+TheISA::MiscReg
AlphaO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
{
return this->regFile.readMiscReg(misc_reg, tid);
}
template <class Impl>
-MiscReg
+TheISA::MiscReg
AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault,
unsigned tid)
{
void
AlphaO3CPU<Impl>::processInterrupts()
{
+ using namespace TheISA;
// Check for interrupts here. For now can copy the code that
// exists within isa_fullsys_traits.hh. Also assume that thread 0
// is the one that handles the interrupts.
// return value itself in the standard return value reg (v0).
if (return_value.successful()) {
// no error
- this->setArchIntReg(SyscallSuccessReg, 0, tid);
- this->setArchIntReg(ReturnValueReg, return_value.value(), tid);
+ this->setArchIntReg(TheISA::SyscallSuccessReg, 0, tid);
+ this->setArchIntReg(TheISA::ReturnValueReg, return_value.value(), tid);
} else {
// got an error, return details
- this->setArchIntReg(SyscallSuccessReg, (IntReg) -1, tid);
- this->setArchIntReg(ReturnValueReg, -return_value.value(), tid);
+ this->setArchIntReg(TheISA::SyscallSuccessReg, (IntReg) -1, tid);
+ this->setArchIntReg(TheISA::ReturnValueReg, -return_value.value(), tid);
}
}
#endif
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
- * Korey Sewell
*/
+#include "arch/alpha/types.hh"
#include "cpu/o3/thread_context.hh"
template <class Impl>
panic("Alpha has no NextNPC!");
}
- virtual void changeRegFileContext(TheISA::RegFile::ContextParam param,
- TheISA::RegFile::ContextVal val)
+ virtual void changeRegFileContext(TheISA::RegContextParam param,
+ TheISA::RegContextVal val)
{ panic("Not supported on Alpha!"); }
#ifndef __CPU_O3_BPRED_UNIT_HH__
#define __CPU_O3_BPRED_UNIT_HH__
-// For Addr type.
-#include "arch/isa_traits.hh"
#include "base/statistics.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/ras.hh"
#include "cpu/o3/tournament_pred.hh"
+#include "sim/host.hh"
+
#include <list>
/**
* Authors: Kevin Lim
*/
-#include <list>
-#include <vector>
-
+#include "arch/types.hh"
#include "base/trace.hh"
#include "base/traceflags.hh"
#include "cpu/o3/bpred_unit.hh"
-using namespace std;
-
template<class Impl>
BPredUnit<Impl>::BPredUnit(Params *params)
: BTB(params->BTBEntries,
void *bp_history = NULL;
if (inst->isUncondCtrl()) {
- DPRINTF(Fetch, "BranchPred: [tid:%i] Unconditional control.\n", tid);
+ DPRINTF(Fetch, "BranchPred: [tid:%i]: Unconditional control.\n", tid);
pred_taken = true;
// Tell the BP there was an unconditional branch.
BPUncond(bp_history);
++BTBLookups;
if (inst->isCall()) {
- RAS[tid].push(PC + sizeof(MachInst));
+#if THE_ISA == ALPHA_ISA
+ Addr ras_pc = PC + sizeof(MachInst); // Next PC
+#else
+ Addr ras_pc = PC + (2 * sizeof(MachInst)); // Next Next PC
+#endif
+ RAS[tid].push(ras_pc);
// Record that it was a call so that the top RAS entry can
// be popped off if the speculation is incorrect.
predict_record.wasCall = true;
- DPRINTF(Fetch, "BranchPred: [tid:%i] Instruction %#x was a call"
+ DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %#x was a call"
", adding %#x to the RAS.\n",
- tid, inst->readPC(), PC + sizeof(MachInst));
+ tid, inst->readPC(), ras_pc);
}
if (BTB.valid(PC, tid)) {
predHist[tid].push_front(predict_record);
- DPRINTF(Fetch, "[tid:%i] predHist.size(): %i\n", tid, predHist[tid].size());
+ DPRINTF(Fetch, "[tid:%i]: predHist.size(): %i\n", tid, predHist[tid].size());
return pred_taken;
}
void
BPredUnit<Impl>::update(const InstSeqNum &done_sn, unsigned tid)
{
- DPRINTF(Fetch, "BranchPred: [tid:%i]: Commiting branches until sequence"
- "number %lli.\n", tid, done_sn);
+ DPRINTF(Fetch, "BranchPred: [tid:%i]: Commiting branches until "
+ "[sn:%lli].\n", tid, done_sn);
while (!predHist[tid].empty() &&
predHist[tid].back().seqNum <= done_sn) {
#include "base/trace.hh"
#include "cpu/o3/btb.hh"
-using namespace TheISA;
-
DefaultBTB::DefaultBTB(unsigned _numEntries,
unsigned _tagBits,
unsigned _instShiftAmt)
#ifndef __CPU_O3_BTB_HH__
#define __CPU_O3_BTB_HH__
-// For Addr type.
-#include "arch/isa_traits.hh"
#include "base/misc.hh"
+#include "sim/host.hh"
class DefaultBTB
{
#include <vector>
-#include "arch/faults.hh"
-#include "arch/isa_traits.hh"
+#include "sim/faults.hh"
#include "cpu/inst_seq.hh"
#include "sim/host.hh"
bool squash[Impl::MaxThreads];
bool branchMispredict[Impl::MaxThreads];
bool branchTaken[Impl::MaxThreads];
+ bool condDelaySlotBranch[Impl::MaxThreads];
uint64_t mispredPC[Impl::MaxThreads];
uint64_t nextPC[Impl::MaxThreads];
InstSeqNum squashedSeqNum[Impl::MaxThreads];
uint64_t branchAddr;
InstSeqNum doneSeqNum;
+ InstSeqNum bdelayDoneSeqNum;
// @todo: Might want to package this kind of branch stuff into a single
// struct as it is used pretty frequently.
// retired or squashed sequence number.
InstSeqNum doneSeqNum;
+ InstSeqNum bdelayDoneSeqNum;
+ bool squashDelaySlot;
+
//Just in case we want to do a commit/squash on a cycle
//(necessary for multiple ROBs?)
bool commitInsts;
#ifndef __CPU_O3_COMMIT_HH__
#define __CPU_O3_COMMIT_HH__
-#include "arch/faults.hh"
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "cpu/exetrace.hh"
/** Sets the pointer to the IEW stage. */
void setIEWStage(IEW *iew_stage);
+ /** Skid buffer between rename and commit. */
+ std::queue<DynInstPtr> skidBuffer;
+
/** The pointer to the IEW stage. Used solely to ensure that
* various events (traps, interrupts, syscalls) do not occur until
* all stores have written back.
/** Gets instructions from rename and inserts them into the ROB. */
void getInsts();
+ /** Insert all instructions from rename into skidBuffer */
+ void skidInsert();
+
/** Marks completed instructions using information sent from IEW. */
void markCompletedInsts();
/** Sets the next PC of a specific thread. */
void setNextPC(uint64_t val, unsigned tid) { nextPC[tid] = val; }
-#if THE_ISA != ALPHA_ISA
/** Reads the next NPC of a specific thread. */
- uint64_t readNextPC(unsigned tid) { return nextNPC[tid]; }
+ uint64_t readNextNPC(unsigned tid) { return nextNPC[tid]; }
/** Sets the next NPC of a specific thread. */
- void setNextPC(uint64_t val, unsigned tid) { nextNPC[tid] = val; }
-#endif
+ void setNextNPC(uint64_t val, unsigned tid) { nextNPC[tid] = val; }
private:
/** Time buffer interface. */
/** The next PC of each thread. */
Addr nextPC[Impl::MaxThreads];
-#if THE_ISA != ALPHA_ISA
/** The next NPC of each thread. */
Addr nextNPC[Impl::MaxThreads];
-#endif
/** The sequence number of the youngest valid instruction in the ROB. */
InstSeqNum youngestSeqNum[Impl::MaxThreads];
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
+ * Korey Sewell
*/
#include "config/full_system.hh"
#include "cpu/checker/cpu.hh"
#endif
-using namespace std;
-
template <class Impl>
DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
unsigned _tid)
{
_status = Active;
_nextStatus = Inactive;
- string policy = params->smtCommitPolicy;
+ std::string policy = params->smtCommitPolicy;
//Convert string to lowercase
std::transform(policy.begin(), policy.end(), policy.begin(),
changedROBNumEntries[i] = false;
trapSquash[i] = false;
tcSquash[i] = false;
- PC[i] = nextPC[i] = 0;
+ PC[i] = nextPC[i] = nextNPC[i] = 0;
}
}
template <class Impl>
void
-DefaultCommit<Impl>::setThreads(vector<Thread *> &threads)
+DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
{
thread = threads;
}
template<class Impl>
void
-DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
{
DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
activeThreads = at_ptr;
DefaultCommit<Impl>::updateStatus()
{
// reset ROB changed variable
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
changedROBNumEntries[tid] = false;
{
int squashes = 0;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
bool
DefaultCommit<Impl>::changedROBEntries()
{
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
if ((*activeThreads).size() <= 0)
return;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
// Check if any of the threads are done squashing. Change the
// status if they are done.
// Check for any possible squashes, handle them first
////////////////////////////////////
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
// then use one older sequence number.
InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
- if (fromIEW->includeSquashInst[tid] == true)
- squashed_inst--;
+#if THE_ISA != ALPHA_ISA
+ InstSeqNum bdelay_done_seq_num;
+ bool squash_bdelay_slot;
+
+ if (fromIEW->branchMispredict[tid]) {
+ if (fromIEW->branchTaken[tid] &&
+ fromIEW->condDelaySlotBranch[tid]) {
+ DPRINTF(Commit, "[tid:%i]: Cond. delay slot branch"
+ "mispredicted as taken. Squashing after previous "
+ "inst, [sn:%i]\n",
+ tid, squashed_inst);
+ bdelay_done_seq_num = squashed_inst;
+ squash_bdelay_slot = true;
+ } else {
+ DPRINTF(Commit, "[tid:%i]: Branch Mispredict. Squashing "
+ "after delay slot [sn:%i]\n", tid, squashed_inst+1);
+ bdelay_done_seq_num = squashed_inst + 1;
+ squash_bdelay_slot = false;
+ }
+ } else {
+ bdelay_done_seq_num = squashed_inst;
+ }
+#endif
+ if (fromIEW->includeSquashInst[tid] == true) {
+ squashed_inst--;
+#if THE_ISA != ALPHA_ISA
+ bdelay_done_seq_num--;
+#endif
+ }
// All younger instructions will be squashed. Set the sequence
// number as the youngest instruction in the ROB.
youngestSeqNum[tid] = squashed_inst;
+#if THE_ISA == ALPHA_ISA
rob->squash(squashed_inst, tid);
+ toIEW->commitInfo[tid].squashDelaySlot = true;
+#else
+ rob->squash(bdelay_done_seq_num, tid);
+ toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
+ toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
+#endif
changedROBNumEntries[tid] = true;
toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
// Try to commit any instructions.
commitInsts();
+ } else {
+#if THE_ISA != ALPHA_ISA
+ skidInsert();
+#endif
}
//Check for any activity
} else {
PC[tid] = head_inst->readPC();
nextPC[tid] = head_inst->readNextPC();
+ nextNPC[tid] = head_inst->readNextNPC();
// Increment the total number of non-speculative instructions
// executed.
}
PC[tid] = nextPC[tid];
+#if THE_ISA == ALPHA_ISA
nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
+#else
+ nextPC[tid] = nextNPC[tid];
+ nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
+#endif
+
#if FULL_SYSTEM
int count = 0;
Addr oldpc;
// Check if the instruction caused a fault. If so, trap.
Fault inst_fault = head_inst->getFault();
+ // DTB will sometimes need the machine instruction for when
+ // faults happen. So we will set it here, prior to the DTB
+ // possibly needing it for its fault.
+ thread[tid]->setInst(
+ static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
+
if (inst_fault != NoFault) {
head_inst->setCompleted();
DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
// execution doesn't generate extra squashes.
thread[tid]->inSyscall = true;
- // DTB will sometimes need the machine instruction for when
- // faults happen. So we will set it here, prior to the DTB
- // possibly needing it for its fault.
- thread[tid]->setInst(
- static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
-
// Execute the trap. Although it's slightly unrealistic in
// terms of timing (as it doesn't wait for the full timing of
// the trap event to complete before updating state), it's
void
DefaultCommit<Impl>::getInsts()
{
+ DPRINTF(Commit, "Getting instructions from Rename stage.\n");
+
+#if THE_ISA == ALPHA_ISA
+ // Read any renamed instructions and place them into the ROB.
+ int insts_to_process = std::min((int)renameWidth, fromRename->size);
+#else
// Read any renamed instructions and place them into the ROB.
- int insts_to_process = min((int)renameWidth, fromRename->size);
+ int insts_to_process = std::min((int)renameWidth,
+ (int)(fromRename->size + skidBuffer.size()));
+ int rename_idx = 0;
- for (int inst_num = 0; inst_num < insts_to_process; ++inst_num)
- {
- DynInstPtr inst = fromRename->insts[inst_num];
+ DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
+ "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
+ skidBuffer.size());
+#endif
+
+
+ for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
+ DynInstPtr inst;
+
+#if THE_ISA == ALPHA_ISA
+ inst = fromRename->insts[inst_num];
+#else
+ // Get insts from skidBuffer or from Rename
+ if (skidBuffer.size() > 0) {
+ DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
+ inst = skidBuffer.front();
+ skidBuffer.pop();
+ } else {
+ DPRINTF(Commit, "Grabbing rename inst.\n");
+ inst = fromRename->insts[rename_idx++];
+ }
+#endif
int tid = inst->threadNumber;
if (!inst->isSquashed() &&
inst->readPC(), inst->seqNum, tid);
}
}
+
+#if THE_ISA != ALPHA_ISA
+ if (rename_idx < fromRename->size) {
+ DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
+
+ for (;
+ rename_idx < fromRename->size;
+ rename_idx++) {
+ DynInstPtr inst = fromRename->insts[rename_idx];
+ int tid = inst->threadNumber;
+
+ if (!inst->isSquashed()) {
+ DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
+ "skidBuffer.\n", inst->readPC(), inst->seqNum, tid);
+ skidBuffer.push(inst);
+ } else {
+ DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
+ "squashed, skipping.\n",
+ inst->readPC(), inst->seqNum, tid);
+ }
+ }
+ }
+#endif
+
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::skidInsert()
+{
+ DPRINTF(Commit, "Attempting to any instructions from rename into "
+ "skidBuffer.\n");
+
+ for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
+ DynInstPtr inst = fromRename->insts[inst_num];
+ int tid = inst->threadNumber;
+
+ if (!inst->isSquashed()) {
+ DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
+ "skidBuffer.\n", inst->readPC(), inst->seqNum, tid);
+ skidBuffer.push(inst);
+ } else {
+ DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
+ "squashed, skipping.\n",
+ inst->readPC(), inst->seqNum, tid);
+ }
+ }
}
template <class Impl>
bool
DefaultCommit<Impl>::robDoneSquashing()
{
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
int
DefaultCommit<Impl>::roundRobin()
{
- list<unsigned>::iterator pri_iter = priority_list.begin();
- list<unsigned>::iterator end = priority_list.end();
+ std::list<unsigned>::iterator pri_iter = priority_list.begin();
+ std::list<unsigned>::iterator end = priority_list.end();
while (pri_iter != end) {
unsigned tid = *pri_iter;
unsigned oldest = 0;
bool first = true;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
if (!tickEvent.scheduled()) {
if (_status == SwitchedOut ||
- getState() == SimObject::DrainedTiming) {
+ getState() == SimObject::Drained) {
// increment stat
lastRunningCycle = curTick;
} else if (!activityRec.active()) {
FullO3CPU<Impl>::suspendContext(int tid)
{
DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
- unscheduleTickEvent();
+ deactivateThread(tid);
+ if (activeThreads.size() == 0)
+ unscheduleTickEvent();
_status = Idle;
-/*
- //Remove From Active List, if Active
- list<unsigned>::iterator isActive = find(
- activeThreads.begin(), activeThreads.end(), tid);
-
- if (isActive != activeThreads.end()) {
- DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
- tid);
- activeThreads.erase(isActive);
- }
-*/
}
template <class Impl>
void
FullO3CPU<Impl>::haltContext(int tid)
{
- DPRINTF(O3CPU,"[tid:%i]: Halting Thread Context", tid);
-/*
- //Remove From Active List, if Active
- list<unsigned>::iterator isActive = find(
- activeThreads.begin(), activeThreads.end(), tid);
-
- if (isActive != activeThreads.end()) {
- DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
- tid);
- activeThreads.erase(isActive);
-
- removeThread(tid);
- }
-*/
+ //For now, this is the same as deallocate
+ DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
+ deallocateContext(tid, 1);
}
template <class Impl>
}
// Squash Throughout Pipeline
- fetch.squash(0,tid);
+ InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
+ fetch.squash(0, squash_seq_num, true, tid);
decode.squash(tid);
- rename.squash(tid);
+ rename.squash(squash_seq_num, tid);
iew.squash(tid);
- commit.rob->squash(commit.rob->readHeadInst(tid)->seqNum, tid);
+ commit.rob->squash(squash_seq_num, tid);
assert(iew.ldstQueue.getCount(tid) == 0);
void
FullO3CPU<Impl>::serialize(std::ostream &os)
{
- SERIALIZE_ENUM(_status);
+ SimObject::State so_state = SimObject::getState();
+ SERIALIZE_ENUM(so_state);
BaseCPU::serialize(os);
nameOut(os, csprintf("%s.tickEvent", name()));
tickEvent.serialize(os);
void
FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
{
- UNSERIALIZE_ENUM(_status);
+ SimObject::State so_state;
+ UNSERIALIZE_ENUM(so_state);
BaseCPU::unserialize(cp, section);
tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
}
template <class Impl>
-bool
+unsigned int
FullO3CPU<Impl>::drain(Event *drain_event)
{
drainCount = 0;
// Wake the CPU and record activity so everything can drain out if
// the CPU was not able to immediately drain.
- if (getState() != SimObject::DrainedTiming) {
+ if (getState() != SimObject::Drained) {
// A bit of a hack...set the drainEvent after all the drain()
// calls have been made, that way if all of the stages drain
// immediately, the signalDrained() function knows not to call
wakeCPU();
activityRec.activity();
- return false;
+ return 1;
} else {
- return true;
+ return 0;
}
}
void
FullO3CPU<Impl>::resume()
{
+ assert(system->getMemoryMode() == System::Timing);
fetch.resume();
decode.resume();
rename.resume();
iew.resume();
commit.resume();
+ changeState(SimObject::Running);
+
if (_status == SwitchedOut || _status == Idle)
return;
if (!tickEvent.scheduled())
tickEvent.schedule(curTick);
_status = Running;
- changeState(SimObject::Timing);
}
template <class Impl>
if (tickEvent.scheduled())
tickEvent.squash();
- changeState(SimObject::DrainedTiming);
+ changeState(SimObject::Drained);
if (drainEvent) {
drainEvent->process();
void
FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
{
- PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
+ int idx = reg_idx + TheISA::FP_Base_DepTag;
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
regFile.setFloatReg(phys_reg, val);
}
void
FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
{
- PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
+ int idx = reg_idx + TheISA::FP_Base_DepTag;
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
regFile.setFloatReg(phys_reg, val, 64);
}
void
FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
{
- PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
+ int idx = reg_idx + TheISA::FP_Base_DepTag;
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
regFile.setFloatRegBits(phys_reg, val);
}
commit.setNextPC(val, tid);
}
-#if THE_ISA != ALPHA_ISA
template <class Impl>
uint64_t
FullO3CPU<Impl>::readNextNPC(unsigned tid)
template <class Impl>
void
-FullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid)
+FullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid)
{
commit.setNextNPC(val, tid);
}
-#endif
template <class Impl>
typename FullO3CPU<Impl>::ListIt
template <class Impl>
void
-FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
+FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid,
+ bool squash_delay_slot,
+ const InstSeqNum &delay_slot_seq_num)
{
DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
" list.\n", tid);
while (inst_it != end_it) {
assert(!instList.empty());
+#if THE_ISA != ALPHA_ISA
+ if(!squash_delay_slot &&
+ delay_slot_seq_num >= (*inst_it)->seqNum) {
+ break;
+ }
+#endif
squashInstIt(inst_it, tid);
inst_it--;
#include <set>
#include <vector>
-#include "arch/isa_traits.hh"
+#include "arch/types.hh"
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "config/full_system.hh"
/** Starts draining the CPU's pipeline of all instructions in
* order to stop all memory accesses. */
- virtual bool drain(Event *drain_event);
+ virtual unsigned int drain(Event *drain_event);
/** Resumes execution after a drain. */
virtual void resume();
*/
void removeFrontInst(DynInstPtr &inst);
- /** Remove all instructions that are not currently in the ROB. */
- void removeInstsNotInROB(unsigned tid);
+ /** Remove all instructions that are not currently in the ROB.
+ * There's also an option to not squash delay slot instructions.*/
+ void removeInstsNotInROB(unsigned tid, bool squash_delay_slot,
+ const InstSeqNum &delay_slot_seq_num);
/** Remove all instructions younger than the given sequence number. */
void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
/** Maximum size of the skid buffer. */
unsigned skidBufferMax;
+ /** SeqNum of Squashing Branch Delay Instruction (used for MIPS)*/
+ Addr bdelayDoneSeqNum[Impl::MaxThreads];
+
+ /** Instruction used for squashing branch (used for MIPS)*/
+ DynInstPtr squashInst[Impl::MaxThreads];
+
+ /** Tells when their is a pending delay slot inst. to send
+ * to rename. If there is, then wait squash after the next
+ * instruction (used for MIPS).
+ */
+ bool squashAfterDelaySlot[Impl::MaxThreads];
+
+
/** Stat for total number of idle cycles. */
Stats::Scalar<> decodeIdleCycles;
/** Stat for total number of blocked cycles. */
#include "cpu/o3/decode.hh"
-using namespace std;
-
template<class Impl>
DefaultDecode<Impl>::DefaultDecode(Params *params)
: renameToDecodeDelay(params->renameToDecodeDelay),
stalls[i].rename = false;
stalls[i].iew = false;
stalls[i].commit = false;
+
+ squashAfterDelaySlot[i] = false;
}
// @todo: Make into a parameter
template<class Impl>
void
-DefaultDecode<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+DefaultDecode<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
{
DPRINTF(Decode, "Setting active threads list pointer.\n");
activeThreads = at_ptr;
// Send back mispredict information.
toFetch->decodeInfo[tid].branchMispredict = true;
- toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
toFetch->decodeInfo[tid].predIncorrect = true;
+ toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
toFetch->decodeInfo[tid].squash = true;
toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
+#if THE_ISA == ALPHA_ISA
toFetch->decodeInfo[tid].branchTaken =
inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst));
+ InstSeqNum squash_seq_num = inst->seqNum;
+#else
+ toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() !=
+ (inst->readNextPC() + sizeof(TheISA::MachInst));
+
+ toFetch->decodeInfo[tid].bdelayDoneSeqNum = bdelayDoneSeqNum[tid];
+ squashAfterDelaySlot[tid] = false;
+
+ InstSeqNum squash_seq_num = bdelayDoneSeqNum[tid];
+#endif
+
// Might have to tell fetch to unblock.
if (decodeStatus[tid] == Blocked ||
decodeStatus[tid] == Unblocking) {
for (int i=0; i<fromFetch->size; i++) {
if (fromFetch->insts[i]->threadNumber == tid &&
- fromFetch->insts[i]->seqNum > inst->seqNum) {
+ fromFetch->insts[i]->seqNum > squash_seq_num) {
fromFetch->insts[i]->setSquashed();
}
}
// Clear the instruction list and skid buffer in case they have any
// insts in them.
while (!insts[tid].empty()) {
+
+#if THE_ISA != ALPHA_ISA
+ if (insts[tid].front()->seqNum <= squash_seq_num) {
+ DPRINTF(Decode, "[tid:%i]: Cannot remove incoming decode "
+ "instructions before delay slot [sn:%i]. %i insts"
+ "left in decode.\n", tid, squash_seq_num,
+ insts[tid].size());
+ break;
+ }
+#endif
insts[tid].pop();
}
while (!skidBuffer[tid].empty()) {
+
+#if THE_ISA != ALPHA_ISA
+ if (skidBuffer[tid].front()->seqNum <= squash_seq_num) {
+ DPRINTF(Decode, "[tid:%i]: Cannot remove skidBuffer "
+ "instructions before delay slot [sn:%i]. %i insts"
+ "left in decode.\n", tid, squash_seq_num,
+ insts[tid].size());
+ break;
+ }
+#endif
skidBuffer[tid].pop();
}
// Squash instructions up until this one
- cpu->removeInstsUntil(inst->seqNum, tid);
+ cpu->removeInstsUntil(squash_seq_num, tid);
}
template<class Impl>
bool
DefaultDecode<Impl>::skidsEmpty()
{
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
if (!skidBuffer[*threads++].empty())
{
bool any_unblocking = false;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
threads = (*activeThreads).begin();
toRenameIndex = 0;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
sortInsts();
// will allow, as long as it is not currently blocked.
if (decodeStatus[tid] == Running ||
decodeStatus[tid] == Idle) {
- DPRINTF(Decode, "[tid:%u] Not blocked, so attempting to run "
+ DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run "
"stage.\n",tid);
decodeInsts(tid);
// Ensure that if it was predicted as a branch, it really is a
// branch.
if (inst->predTaken() && !inst->isControl()) {
+ DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n",inst->predPC,
+ inst->nextPC + 4);
+
panic("Instruction predicted as a branch!");
++decodeControlMispred;
// Might want to set some sort of boolean and just do
// a check at the end
+#if THE_ISA == ALPHA_ISA
squash(inst, inst->threadNumber);
inst->setPredTarg(inst->branchTarget());
-
break;
+#else
+ // If mispredicted as taken, then ignore delay slot
+ // instruction... else keep delay slot and squash
+ // after it is sent to rename
+ if (inst->predTaken() && inst->isCondDelaySlot()) {
+ DPRINTF(Decode, "[tid:%i]: Conditional delay slot inst."
+ "[sn:%i] PC %#x mispredicted as taken.\n", tid,
+ inst->seqNum, inst->PC);
+ bdelayDoneSeqNum[tid] = inst->seqNum;
+ squash(inst, inst->threadNumber);
+ inst->setPredTarg(inst->branchTarget());
+ break;
+ } else {
+ DPRINTF(Decode, "[tid:%i]: Misprediction detected at "
+ "[sn:%i] PC %#x, will squash after delay slot "
+ "inst. is sent to Rename\n",
+ tid, inst->seqNum, inst->PC);
+ bdelayDoneSeqNum[tid] = inst->seqNum + 1;
+ squashAfterDelaySlot[tid] = true;
+ squashInst[tid] = inst;
+ continue;
+ }
+#endif
}
}
+
+ if (squashAfterDelaySlot[tid]) {
+ assert(!inst->isSquashed());
+ squash(squashInst[tid], squashInst[tid]->threadNumber);
+ squashInst[tid]->setPredTarg(squashInst[tid]->branchTarget());
+ assert(!inst->isSquashed());
+ break;
+ }
}
// If we didn't process all instructions, then we will need to block
#include "arch/isa_specific.hh"
#if THE_ISA == ALPHA_ISA
-template <class Impl>
-class AlphaDynInst;
-
-struct AlphaSimpleImpl;
-
-typedef AlphaDynInst<AlphaSimpleImpl> O3DynInst;
+ template <class Impl> class AlphaDynInst;
+ struct AlphaSimpleImpl;
+ typedef AlphaDynInst<AlphaSimpleImpl> O3DynInst;
+#elif THE_ISA == MIPS_ISA
+ template <class Impl> class MipsDynInst;
+ struct MipsSimpleImpl;
+ typedef MipsDynInst<MipsSimpleImpl> O3DynInst;
+#elif THE_ISA == SPARC_ISA
+ template <class Impl> class SparcDynInst;
+ struct SparcSimpleImpl;
+ typedef SparcDynInst<SparcSimpleImpl> O3DynInst;
+#else
+ #error "O3DynInst not defined for this ISA"
#endif
#endif // __CPU_O3_DYN_INST_HH__
virtual void recvRetry();
};
+
public:
/** Overall fetch status. Used to determine if the CPU can
* deschedule itsef due to a lack of activity.
* @param next_PC Next PC variable passed in by reference. It is
* expected to be set to the current PC; it will be updated with what
* the next PC will be.
+ * @param next_NPC Used for ISAs which use delay slots.
* @return Whether or not a branch was predicted as taken.
*/
- bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC);
+ bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, Addr &next_NPC);
/**
* Fetches the cache line that contains fetch_PC. Returns any
* remove any instructions that are not in the ROB. The source of this
* squash should be the commit stage.
*/
- void squash(const Addr &new_PC, unsigned tid);
+ void squash(const Addr &new_PC, const InstSeqNum &seq_num,
+ bool squash_delay_slot, unsigned tid);
/** Ticks the fetch stage, processing all inputs signals and fetching
* as many instructions as possible.
/** Per-thread next PC. */
Addr nextPC[Impl::MaxThreads];
-#if THE_ISA != ALPHA_ISA
/** Per-thread next Next PC.
* This is not a real register but is used for
* architectures that use a branch-delay slot.
* (such as MIPS or Sparc)
*/
Addr nextNPC[Impl::MaxThreads];
-#endif
/** Memory request used to access cache. */
RequestPtr memReq[Impl::MaxThreads];
/** Tracks how many instructions has been fetched this cycle. */
int numInst;
+ /** Tracks delay slot information for threads in ISAs which use
+ * delay slots;
+ */
+ struct DelaySlotInfo {
+ InstSeqNum delaySlotSeqNum;
+ InstSeqNum branchSeqNum;
+ int numInsts;
+ Addr targetAddr;
+ bool targetReady;
+ };
+
+ DelaySlotInfo delaySlotInfo[Impl::MaxThreads];
+
/** Source of possible stalls. */
struct Stalls {
bool decode;
/** The cache line being fetched. */
uint8_t *cacheData[Impl::MaxThreads];
+ /** The PC of the cacheline that has been loaded. */
+ Addr cacheDataPC[Impl::MaxThreads];
+
+ /** Whether or not the cache data is valid. */
+ bool cacheDataValid[Impl::MaxThreads];
+
/** Size of instructions. */
int instSize;
#include <algorithm>
-using namespace std;
-using namespace TheISA;
-
template<class Impl>
Tick
DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
// Set fetch stage's status to inactive.
_status = Inactive;
- string policy = params->smtFetchPolicy;
+ std::string policy = params->smtFetchPolicy;
// Convert string to lowercase
std::transform(policy.begin(), policy.end(), policy.begin(),
// Create space to store a cache line.
cacheData[tid] = new uint8_t[cacheBlkSize];
+ cacheDataPC[tid] = 0;
+ cacheDataValid[tid] = false;
+
+ delaySlotInfo[tid].branchSeqNum = -1;
+ delaySlotInfo[tid].numInsts = 0;
+ delaySlotInfo[tid].targetAddr = 0;
+ delaySlotInfo[tid].targetReady = false;
- stalls[tid].decode = 0;
- stalls[tid].rename = 0;
- stalls[tid].iew = 0;
- stalls[tid].commit = 0;
+ stalls[tid].decode = false;
+ stalls[tid].rename = false;
+ stalls[tid].iew = false;
+ stalls[tid].commit = false;
}
// Get the size of an instruction.
- instSize = sizeof(MachInst);
+ instSize = sizeof(TheISA::MachInst);
}
template <class Impl>
}
#endif
+ // Schedule fetch to get the correct PC from the CPU
+ // scheduleFetchStartupEvent(1);
+
// Fetch needs to start fetching instructions at the very beginning,
// so it must start up in active state.
switchToActive();
template<class Impl>
void
-DefaultFetch<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
{
DPRINTF(Fetch, "Setting active threads list pointer.\n");
activeThreads = at_ptr;
}
memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
+ cacheDataValid[tid] = true;
if (!drainPending) {
// Wake up the CPU (if it went to sleep and was waiting on
nextPC[i] = cpu->readNextPC(i);
#if THE_ISA != ALPHA_ISA
nextNPC[i] = cpu->readNextNPC(i);
+ delaySlotInfo[i].branchSeqNum = -1;
+ delaySlotInfo[i].numInsts = 0;
+ delaySlotInfo[i].targetAddr = 0;
+ delaySlotInfo[i].targetReady = false;
#endif
fetchStatus[i] = Running;
}
template <class Impl>
bool
-DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
+DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
+ Addr &next_NPC)
{
// Do branch prediction check here.
// A bit of a misnomer...next_PC is actually the current PC until
bool predict_taken;
if (!inst->isControl()) {
+#if THE_ISA == ALPHA_ISA
next_PC = next_PC + instSize;
inst->setPredTarg(next_PC);
+#else
+ Addr cur_PC = next_PC;
+ next_PC = cur_PC + instSize; //next_NPC;
+ next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize;
+ inst->setPredTarg(next_NPC);
+#endif
return false;
}
- predict_taken = branchPred.predict(inst, next_PC, inst->threadNumber);
+ int tid = inst->threadNumber;
+#if THE_ISA == ALPHA_ISA
+ predict_taken = branchPred.predict(inst, next_PC, tid);
+#else
+ Addr pred_PC = next_PC;
+ predict_taken = branchPred.predict(inst, pred_PC, tid);
+
+ if (predict_taken) {
+ DPRINTF(Fetch, "[tid:%i]: Branch predicted to be true.\n", tid);
+ } else {
+ DPRINTF(Fetch, "[tid:%i]: Branch predicted to be false.\n", tid);
+ }
+
+ if (predict_taken) {
+ next_PC = next_NPC;
+ next_NPC = pred_PC;
+
+ // Update delay slot info
+ ++delaySlotInfo[tid].numInsts;
+ delaySlotInfo[tid].targetAddr = pred_PC;
+ DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) to process.\n", tid,
+ delaySlotInfo[tid].numInsts);
+ } else { // !predict_taken
+ if (inst->isCondDelaySlot()) {
+ next_PC = pred_PC;
+ // The delay slot is skipped here if there is on
+ // prediction
+ } else {
+ next_PC = next_NPC;
+ // No need to declare a delay slot here since
+ // there is no for the pred. target to jump
+ }
+
+ next_NPC = next_NPC + instSize;
+ }
+#endif
++fetchedBranches;
// Align the fetch PC so it's at the start of a cache block.
fetch_PC = icacheBlockAlignPC(fetch_PC);
+ // If we've already got the block, no need to try to fetch it again.
+ if (cacheDataValid[tid] && fetch_PC == cacheDataPC[tid]) {
+ return true;
+ }
+
// Setup the memReq to do a read of the first instruction's address.
// Set the appropriate read size and flags as well.
// Build request here.
// Build packet here.
PacketPtr data_pkt = new Packet(mem_req,
Packet::ReadReq, Packet::Broadcast);
- data_pkt->dataDynamic(new uint8_t[cacheBlkSize]);
+ data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
+
+ cacheDataPC[tid] = fetch_PC;
+ cacheDataValid[tid] = false;
DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
PC[tid] = new_PC;
nextPC[tid] = new_PC + instSize;
+ nextNPC[tid] = new_PC + (2 * instSize);
// Clear the icache miss if it's outstanding.
if (fetchStatus[tid] == IcacheWaitResponse) {
doSquash(new_PC, tid);
+#if THE_ISA != ALPHA_ISA
+ if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
+ delaySlotInfo[tid].numInsts = 0;
+ delaySlotInfo[tid].targetAddr = 0;
+ delaySlotInfo[tid].targetReady = false;
+ }
+#endif
+
// Tell the CPU to remove any instructions that are in flight between
// fetch and decode.
cpu->removeInstsUntil(seq_num, tid);
DefaultFetch<Impl>::updateFetchStatus()
{
//Check Running
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
template <class Impl>
void
-DefaultFetch<Impl>::squash(const Addr &new_PC, unsigned tid)
+DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num,
+ bool squash_delay_slot, unsigned tid)
{
DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
doSquash(new_PC, tid);
+#if THE_ISA == ALPHA_ISA
+ // Tell the CPU to remove any instructions that are not in the ROB.
+ cpu->removeInstsNotInROB(tid, true, 0);
+#else
+ if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
+ delaySlotInfo[tid].numInsts = 0;
+ delaySlotInfo[tid].targetAddr = 0;
+ delaySlotInfo[tid].targetReady = false;
+ }
+
// Tell the CPU to remove any instructions that are not in the ROB.
- cpu->removeInstsNotInROB(tid);
+ cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
+#endif
}
template <class Impl>
void
DefaultFetch<Impl>::tick()
{
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
bool status_change = false;
wroteToTimeBuffer = false;
DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
"from commit.\n",tid);
+#if THE_ISA == ALPHA_ISA
+ InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
+#else
+ InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
+#endif
// In any case, squash.
- squash(fromCommit->commitInfo[tid].nextPC,tid);
+ squash(fromCommit->commitInfo[tid].nextPC,
+ doneSeqNum,
+ fromCommit->commitInfo[tid].squashDelaySlot,
+ tid);
// Also check if there's a mispredict that happened.
if (fromCommit->commitInfo[tid].branchMispredict) {
}
if (fetchStatus[tid] != Squashing) {
+
+#if THE_ISA == ALPHA_ISA
+ InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
+#else
+ InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
+#endif
// Squash unless we're already squashing
squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
- fromDecode->decodeInfo[tid].doneSeqNum,
+ doneSeqNum,
tid);
return true;
}
Addr next_PC = fetch_PC;
+ Addr next_NPC = next_PC + instSize;
InstSeqNum inst_seq;
MachInst inst;
ExtMachInst ext_inst;
// ended this fetch block.
bool predicted_branch = false;
+ // Need to keep track of whether or not a delay slot
+ // instruction has been fetched
+
for (;
offset < cacheBlkSize &&
numInst < fetchWidth &&
- !predicted_branch;
+ (!predicted_branch || delaySlotInfo[tid].numInsts > 0);
++numInst) {
// Get a sequence number.
assert(offset <= cacheBlkSize - instSize);
// Get the instruction from the array of the cache line.
- inst = gtoh(*reinterpret_cast<MachInst *>
+ inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
(&cacheData[tid][offset]));
ext_inst = TheISA::makeExtMI(inst, fetch_PC);
instruction->staticInst,
instruction->readPC(),tid);
- predicted_branch = lookupAndUpdateNextPC(instruction, next_PC);
+ predicted_branch = lookupAndUpdateNextPC(instruction, next_PC,
+ next_NPC);
// Add instruction to the CPU's list of instructions.
instruction->setInstListIt(cpu->addInst(instruction));
break;
}
- offset+= instSize;
+ offset += instSize;
+
+#if THE_ISA != ALPHA_ISA
+ if (predicted_branch) {
+ delaySlotInfo[tid].branchSeqNum = inst_seq;
+
+ DPRINTF(Fetch, "[tid:%i]: Delay slot branch set to [sn:%i]\n",
+ tid, inst_seq);
+ continue;
+ } else if (delaySlotInfo[tid].numInsts > 0) {
+ --delaySlotInfo[tid].numInsts;
+
+ // It's OK to set PC to target of branch
+ if (delaySlotInfo[tid].numInsts == 0) {
+ delaySlotInfo[tid].targetReady = true;
+
+ // Break the looping condition
+ predicted_branch = true;
+ }
+
+ DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) left to"
+ " process.\n", tid, delaySlotInfo[tid].numInsts);
+ }
+#endif
+ }
+
+ if (offset >= cacheBlkSize) {
+ DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
+ "block.\n", tid);
+ } else if (numInst >= fetchWidth) {
+ DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
+ "for this cycle.\n", tid);
+ } else if (predicted_branch && delaySlotInfo[tid].numInsts <= 0) {
+ DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
+ "instruction encountered.\n", tid);
}
}
// Now that fetching is completed, update the PC to signify what the next
// cycle will be.
if (fault == NoFault) {
- DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
-
#if THE_ISA == ALPHA_ISA
+ DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
PC[tid] = next_PC;
nextPC[tid] = next_PC + instSize;
#else
- PC[tid] = next_PC;
- nextPC[tid] = next_PC + instSize;
- nextPC[tid] = next_PC + instSize;
+ if (delaySlotInfo[tid].targetReady &&
+ delaySlotInfo[tid].numInsts == 0) {
+ // Set PC to target
+ PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
+ nextPC[tid] = next_PC + instSize; //next_NPC
+ nextNPC[tid] = next_PC + (2 * instSize);
+
+ delaySlotInfo[tid].targetReady = false;
+ } else {
+ PC[tid] = next_PC;
+ nextPC[tid] = next_NPC;
+ nextNPC[tid] = next_NPC + instSize;
+ }
- thread->setNextPC(thread->readNextNPC());
- thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
+ DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
#endif
} else {
// We shouldn't be in an icache miss and also have a fault (an ITB
fetchStatus[tid] = TrapPending;
status_change = true;
- warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
+ warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]);
#else // !FULL_SYSTEM
- warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
+ warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]);
#endif // FULL_SYSTEM
}
}
int
DefaultFetch<Impl>::roundRobin()
{
- list<unsigned>::iterator pri_iter = priorityList.begin();
- list<unsigned>::iterator end = priorityList.end();
+ std::list<unsigned>::iterator pri_iter = priorityList.begin();
+ std::list<unsigned>::iterator end = priorityList.end();
int high_pri;
int
DefaultFetch<Impl>::iqCount()
{
- priority_queue<unsigned> PQ;
+ std::priority_queue<unsigned> PQ;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
int
DefaultFetch<Impl>::lsqCount()
{
- priority_queue<unsigned> PQ;
+ std::priority_queue<unsigned> PQ;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
int
DefaultFetch<Impl>::branchCount()
{
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
panic("Branch Count Fetch policy unimplemented\n");
return *threads;
}
#ifndef __CPU_O3_IEW_HH__
#define __CPU_O3_IEW_HH__
+#include "config/full_system.hh"
+
#include <queue>
#include "base/statistics.hh"
#include "base/timebuf.hh"
-#include "config/full_system.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/scoreboard.hh"
#include "cpu/o3/lsq.hh"
if (++wbOutstanding == wbMax)
ableToIssue = false;
DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
-#if DEBUG
+#ifdef DEBUG
wbList.insert(sn);
#endif
}
if (wbOutstanding-- == wbMax)
ableToIssue = true;
DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
-#if DEBUG
+#ifdef DEBUG
assert(wbList.find(sn) != wbList.end());
wbList.erase(sn);
#endif
}
-#if DEBUG
+#ifdef DEBUG
std::set<InstSeqNum> wbList;
void dumpWb()
/** Records if there is a fetch redirect on this cycle for each thread. */
bool fetchRedirect[Impl::MaxThreads];
+ /** Keeps track of the last valid branch delay slot instss for threads */
+ InstSeqNum bdelayDoneSeqNum[Impl::MaxThreads];
+
/** Used to track if all instructions have been dispatched this cycle.
* If they have not, then blocking must have occurred, and the instructions
* would already be added to the skid buffer.
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/iew.hh"
-using namespace std;
-
template<class Impl>
DefaultIEW<Impl>::DefaultIEW(Params *params)
: issueToExecQueue(params->backComSize, params->forwardComSize),
dispatchStatus[i] = Running;
stalls[i].commit = false;
fetchRedirect[i] = false;
+ bdelayDoneSeqNum[i] = 0;
}
wbMax = wbWidth * params->wbDepth;
template<class Impl>
void
-DefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+DefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
{
DPRINTF(IEW, "Setting active threads list pointer.\n");
activeThreads = at_ptr;
instQueue.squash(tid);
// Tell the LDSTQ to start squashing.
+#if THE_ISA == ALPHA_ISA
ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
-
+#else
+ ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
+#endif
updatedQueues = true;
// Clear the skid buffer in case it has any data in it.
- while (!skidBuffer[tid].empty()) {
+ DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
+ tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
+ while (!skidBuffer[tid].empty()) {
+#if THE_ISA != ALPHA_ISA
+ if (skidBuffer[tid].front()->seqNum <=
+ fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
+ DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
+ "that occur before delay slot [sn:%i].\n",
+ fromCommit->commitInfo[tid].bdelayDoneSeqNum,
+ tid);
+ break;
+ } else {
+ DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from "
+ "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum);
+ }
+#endif
if (skidBuffer[tid].front()->isLoad() ||
skidBuffer[tid].front()->isStore() ) {
toRename->iewInfo[tid].dispatchedToLSQ++;
skidBuffer[tid].pop();
}
+ bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
+
emptyRenameInsts(tid);
}
toCommit->squash[tid] = true;
toCommit->squashedSeqNum[tid] = inst->seqNum;
toCommit->mispredPC[tid] = inst->readPC();
- toCommit->nextPC[tid] = inst->readNextPC();
toCommit->branchMispredict[tid] = true;
+
+#if THE_ISA == ALPHA_ISA
toCommit->branchTaken[tid] = inst->readNextPC() !=
(inst->readPC() + sizeof(TheISA::MachInst));
+ toCommit->nextPC[tid] = inst->readNextPC();
+#else
+ bool branch_taken = inst->readNextNPC() !=
+ (inst->readNextPC() + sizeof(TheISA::MachInst));
+
+ toCommit->branchTaken[tid] = branch_taken;
+
+ toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot();
+
+ if (inst->isCondDelaySlot() && branch_taken) {
+ toCommit->nextPC[tid] = inst->readNextPC();
+ } else {
+ toCommit->nextPC[tid] = inst->readNextNPC();
+ }
+#endif
toCommit->includeSquashInst[tid] = false;
{
int max=0;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned thread_count = skidBuffer[*threads++].size();
bool
DefaultIEW<Impl>::skidsEmpty()
{
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
if (!skidBuffer[*threads++].empty())
{
bool any_unblocking = false;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
threads = (*activeThreads).begin();
{
int insts_from_rename = fromRename->size;
#ifdef DEBUG
+#if THE_ISA == ALPHA_ISA
for (int i = 0; i < numThreads; i++)
assert(insts[i].empty());
+#endif
#endif
for (int i = 0; i < insts_from_rename; ++i) {
insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
void
DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
{
+ DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until "
+ "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
+
while (!insts[tid].empty()) {
+
+#if THE_ISA != ALPHA_ISA
+ if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
+ DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
+ " that occurs at or before delay slot [sn:%i].\n",
+ tid, bdelayDoneSeqNum[tid]);
+ break;
+ } else {
+ DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction "
+ "[sn:%i].\n", tid, insts[tid].front()->seqNum);
+ }
+#endif
+
if (insts[tid].front()->isLoad() ||
insts[tid].front()->isStore() ) {
toRename->iewInfo[tid].dispatchedToLSQ++;
}
if (!insts_to_dispatch.empty()) {
- DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n");
+ DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
block(tid);
toRename->iewUnblock[tid] = false;
}
{
int inst = 0;
- cout << "Available Instructions: ";
+ std::cout << "Available Instructions: ";
while (fromIssue->insts[inst]) {
- if (inst%3==0) cout << "\n\t";
+ if (inst%3==0) std::cout << "\n\t";
- cout << "PC: " << fromIssue->insts[inst]->readPC()
+ std::cout << "PC: " << fromIssue->insts[inst]->readPC()
<< " TN: " << fromIssue->insts[inst]->threadNumber
<< " SN: " << fromIssue->insts[inst]->seqNum << " | ";
}
- cout << "\n";
+ std::cout << "\n";
}
template <class Impl>
wbNumInst = 0;
wbCycle = 0;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
fetchRedirect[tid] = true;
DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
+#if THE_ISA == ALPHA_ISA
DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
inst->nextPC);
-
+#else
+ DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
+ inst->nextNPC);
+#endif
// If incorrect, then signal the ROB that it must be squashed.
squashDueToBranch(inst, tid);
// Free function units marked as being freed this cycle.
fuPool->processFreeUnits();
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
// Check stall and squash signals, dispatch any instructions.
while (threads != (*activeThreads).end()) {
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
- * Korey Sewell
*/
#ifndef __CPU_O3_INST_QUEUE_HH__
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/inst_queue.hh"
-using namespace std;
-
template <class Impl>
InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
int fu_idx,
resetState();
- string policy = params->smtIQPolicy;
+ std::string policy = params->smtIQPolicy;
//Convert string to lowercase
std::transform(policy.begin(), policy.end(), policy.begin(),
;
for (int i=0; i<Num_OpClasses; ++i) {
- stringstream subname;
+ std::stringstream subname;
subname << opClassStrings[i] << "_delay";
issueDelayDist.subname(i, subname.str());
}
template <class Impl>
void
-InstructionQueue<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+InstructionQueue<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
{
DPRINTF(IQ, "Setting active threads list pointer.\n");
activeThreads = at_ptr;
if (iqPolicy != Dynamic || numThreads > 1) {
int active_threads = (*activeThreads).size();
- list<unsigned>::iterator threads = (*activeThreads).begin();
- list<unsigned>::iterator list_end = (*activeThreads).end();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator list_end = (*activeThreads).end();
while (threads != list_end) {
if (iqPolicy == Partitioned) {
// Read instruction sequence number of last instruction out of the
// time buffer.
+#if THE_ISA == ALPHA_ISA
squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
+#else
+ squashedSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
+#endif
// Call doSquash if there are insts in the IQ
if (count[tid] > 0) {
#include "cpu/o3/alpha/impl.hh"
#include "cpu/o3/alpha/params.hh"
#include "cpu/o3/alpha/dyn_inst.hh"
+#elif THE_ISA == MIPS_ISA
+ #include "cpu/o3/mips/cpu.hh"
+ #include "cpu/o3/mips/impl.hh"
+ #include "cpu/o3/mips/params.hh"
+ #include "cpu/o3/mips/dyn_inst.hh"
#else
- #error "O3CPU doesnt support this ISA"
+ #error "ISA-specific header files O3CPU not defined ISA"
#endif
* to work. For now it just returns the port from one of the
* threads.
*/
- Port *getDcachePort() { return thread[0].getDcachePort(); }
+ Port *getDcachePort() { return &dcachePort; }
/** Sets the pointer to the list of active threads. */
void setActiveThreads(std::list<unsigned> *at_ptr);
bool willWB(unsigned tid)
{ return thread[tid].willWB(); }
+ /** Returns if the cache is currently blocked. */
+ bool cacheBlocked()
+ { return retryTid != -1; }
+
+ /** Sets the retry thread id, indicating that one of the LSQUnits
+ * tried to access the cache but the cache was blocked. */
+ void setRetryTid(int tid)
+ { retryTid = tid; }
+
/** Debugging function to print out all instructions. */
void dumpInsts();
/** Debugging function to print out instructions from a specific thread. */
template <class T>
Fault write(RequestPtr req, T &data, int store_idx);
- private:
+ /** DcachePort class for this LSQ. Handles doing the
+ * communication with the cache/memory.
+ */
+ class DcachePort : public Port
+ {
+ protected:
+ /** Pointer to LSQ. */
+ LSQ *lsq;
+
+ public:
+ /** Default constructor. */
+ DcachePort(LSQ *_lsq)
+ : lsq(_lsq)
+ { }
+
+ protected:
+ /** Atomic version of receive. Panics. */
+ virtual Tick recvAtomic(PacketPtr pkt);
+
+ /** Functional version of receive. Panics. */
+ virtual void recvFunctional(PacketPtr pkt);
+
+ /** Receives status change. Other than range changing, panics. */
+ virtual void recvStatusChange(Status status);
+
+ /** Returns the address ranges of this device. */
+ virtual void getDeviceAddressRanges(AddrRangeList &resp,
+ AddrRangeList &snoop)
+ { resp.clear(); snoop.clear(); }
+
+ /** Timing version of receive. Handles writing back and
+ * completing the load or store that has returned from
+ * memory. */
+ virtual bool recvTiming(PacketPtr pkt);
+
+ /** Handles doing a retry of the previous send. */
+ virtual void recvRetry();
+ };
+
+ /** D-cache port. */
+ DcachePort dcachePort;
+
+ protected:
/** The LSQ policy for SMT mode. */
LSQPolicy lsqPolicy;
/** Number of Threads. */
unsigned numThreads;
+
+ /** The thread id of the LSQ Unit that is currently waiting for a
+ * retry. */
+ int retryTid;
};
template <class Impl>
*/
#include <algorithm>
+#include <list>
#include <string>
#include "cpu/o3/lsq.hh"
-using namespace std;
+template <class Impl>
+Tick
+LSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
+{
+ panic("O3CPU model does not work with atomic mode!");
+ return curTick;
+}
+
+template <class Impl>
+void
+LSQ<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
+{
+ panic("O3CPU doesn't expect recvFunctional callback!");
+}
+
+template <class Impl>
+void
+LSQ<Impl>::DcachePort::recvStatusChange(Status status)
+{
+ if (status == RangeChange)
+ return;
+
+ panic("O3CPU doesn't expect recvStatusChange callback!");
+}
+
+template <class Impl>
+bool
+LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
+{
+ lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt);
+ return true;
+}
+
+template <class Impl>
+void
+LSQ<Impl>::DcachePort::recvRetry()
+{
+ lsq->thread[lsq->retryTid].recvRetry();
+ // Speculatively clear the retry Tid. This will get set again if
+ // the LSQUnit was unable to complete its access.
+ lsq->retryTid = -1;
+}
template <class Impl>
LSQ<Impl>::LSQ(Params *params)
- : LQEntries(params->LQEntries), SQEntries(params->SQEntries),
- numThreads(params->numberOfThreads)
+ : dcachePort(this), LQEntries(params->LQEntries),
+ SQEntries(params->SQEntries), numThreads(params->numberOfThreads),
+ retryTid(-1)
{
DPRINTF(LSQ, "Creating LSQ object.\n");
//**********************************************/
//************ Handle SMT Parameters ***********/
//**********************************************/
- string policy = params->smtLSQPolicy;
+ std::string policy = params->smtLSQPolicy;
//Convert string to lowercase
std::transform(policy.begin(), policy.end(), policy.begin(),
//Initialize LSQs
for (int tid=0; tid < numThreads; tid++) {
- thread[tid].init(params, maxLQEntries, maxSQEntries, tid);
+ thread[tid].init(params, this, maxLQEntries, maxSQEntries, tid);
+ thread[tid].setDcachePort(&dcachePort);
}
}
template<class Impl>
void
-LSQ<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+LSQ<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
{
activeThreads = at_ptr;
assert(activeThreads != 0);
{
cpu = cpu_ptr;
+ dcachePort.setName(name());
+
for (int tid=0; tid < numThreads; tid++) {
thread[tid].setCPU(cpu_ptr);
}
if (lsqPolicy != Dynamic || numThreads > 1) {
int active_threads = (*activeThreads).size();
- list<unsigned>::iterator threads = (*activeThreads).begin();
- list<unsigned>::iterator list_end = (*activeThreads).end();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator list_end = (*activeThreads).end();
int maxEntries;
void
LSQ<Impl>::tick()
{
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
void
LSQ<Impl>::writebackStores()
{
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
LSQ<Impl>::violation()
{
/* Answers: Does Anybody Have a Violation?*/
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
{
unsigned total = 0;
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
{
unsigned total = 0;
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
{
unsigned total = 0;
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
{
unsigned total = 0;
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
{
unsigned total = 0;
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
bool
LSQ<Impl>::isFull()
{
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
bool
LSQ<Impl>::lqFull()
{
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
bool
LSQ<Impl>::sqFull()
{
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
bool
LSQ<Impl>::isStalled()
{
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
bool
LSQ<Impl>::hasStoresToWB()
{
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
if ((*activeThreads).empty())
return false;
bool
LSQ<Impl>::willWB()
{
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
void
LSQ<Impl>::dumpInsts()
{
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::CPUPol::IEW IEW;
+ typedef typename Impl::CPUPol::LSQ LSQ;
typedef typename Impl::CPUPol::IssueStruct IssueStruct;
public:
LSQUnit();
/** Initializes the LSQ unit with the specified number of entries. */
- void init(Params *params, unsigned maxLQEntries,
+ void init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
unsigned maxSQEntries, unsigned id);
/** Returns the name of the LSQ unit. */
std::string name() const;
- /** Returns the dcache port.
- * @todo: Remove this once the port moves up to the LSQ level.
- */
- Port *getDcachePort() { return dcachePort; }
-
/** Registers statistics. */
void regStats();
void setIEW(IEW *iew_ptr)
{ iewStage = iew_ptr; }
+ /** Sets the pointer to the dcache port. */
+ void setDcachePort(Port *dcache_port)
+ { dcachePort = dcache_port; }
+
/** Switches out LSQ unit. */
void switchOut();
!storeQueue[storeWBIdx].completed &&
!isStoreBlocked; }
+ /** Handles doing the retry. */
+ void recvRetry();
+
private:
/** Writes back the instruction, sending it to IEW. */
void writeback(DynInstPtr &inst, PacketPtr pkt);
/** Completes the store at the specified index. */
void completeStore(int store_idx);
- /** Handles doing the retry. */
- void recvRetry();
-
/** Increments the given store index (circular queue). */
inline void incrStIdx(int &store_idx);
/** Decrements the given store index (circular queue). */
/** Pointer to the IEW stage. */
IEW *iewStage;
- /** Pointer to memory object. */
- MemObject *mem;
+ /** Pointer to the LSQ. */
+ LSQ *lsq;
- /** DcachePort class for this LSQ Unit. Handles doing the
- * communication with the cache/memory.
- * @todo: Needs to be moved to the LSQ level and have some sort
- * of arbitration.
- */
- class DcachePort : public Port
- {
- protected:
- /** Pointer to CPU. */
- O3CPU *cpu;
- /** Pointer to LSQ. */
- LSQUnit *lsq;
-
- public:
- /** Default constructor. */
- DcachePort(O3CPU *_cpu, LSQUnit *_lsq)
- : Port(_lsq->name() + "-dport"), cpu(_cpu), lsq(_lsq)
- { }
-
- protected:
- /** Atomic version of receive. Panics. */
- virtual Tick recvAtomic(PacketPtr pkt);
-
- /** Functional version of receive. Panics. */
- virtual void recvFunctional(PacketPtr pkt);
-
- /** Receives status change. Other than range changing, panics. */
- virtual void recvStatusChange(Status status);
-
- /** Returns the address ranges of this device. */
- virtual void getDeviceAddressRanges(AddrRangeList &resp,
- AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); }
-
- /** Timing version of receive. Handles writing back and
- * completing the load or store that has returned from
- * memory. */
- virtual bool recvTiming(PacketPtr pkt);
-
- /** Handles doing a retry of the previous send. */
- virtual void recvRetry();
- };
-
- /** Pointer to the D-cache. */
- DcachePort *dcachePort;
+ /** Pointer to the dcache port. Used only for sending. */
+ Port *dcachePort;
/** Derived class to hold any sender state the LSQ needs. */
class LSQSenderState : public Packet::SenderState
// Tell IQ/mem dep unit that this instruction will need to be
// rescheduled eventually
iewStage->rescheduleMemInst(load_inst);
+ iewStage->decrWb(load_inst->seqNum);
++lsqRescheduledLoads;
// Do not generate a writeback event as this instruction is not
}
// If there's no forwarding case, then go access memory
- DPRINTF(LSQUnit, "Doing functional access for inst [sn:%lli] PC %#x\n",
+ DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %#x\n",
load_inst->seqNum, load_inst->readPC());
assert(!load_inst->memData);
++usedPorts;
- DPRINTF(LSQUnit, "Doing timing access for inst PC %#x\n",
- load_inst->readPC());
-
PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
data_pkt->dataStatic(load_inst->memData);
state->inst = load_inst;
data_pkt->senderState = state;
- // if we have a cache, do cache access too
- if (!dcachePort->sendTiming(data_pkt)) {
+ // if we the cache is not blocked, do cache access
+ if (!lsq->cacheBlocked()) {
+ if (!dcachePort->sendTiming(data_pkt)) {
+ // If the access didn't succeed, tell the LSQ by setting
+ // the retry thread id.
+ lsq->setRetryTid(lsqID);
+ }
+ }
+
+ // If the cache was blocked, or has become blocked due to the access,
+ // handle it.
+ if (lsq->cacheBlocked()) {
++lsqCacheBlocked;
// There's an older load that's already going to squash.
if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
#include "config/use_checker.hh"
+#include "cpu/o3/lsq.hh"
#include "cpu/o3/lsq_unit.hh"
#include "base/str.hh"
#include "mem/packet.hh"
delete pkt;
}
-template <class Impl>
-Tick
-LSQUnit<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
-{
- panic("O3CPU model does not work with atomic mode!");
- return curTick;
-}
-
-template <class Impl>
-void
-LSQUnit<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
-{
- panic("O3CPU doesn't expect recvFunctional callback!");
-}
-
-template <class Impl>
-void
-LSQUnit<Impl>::DcachePort::recvStatusChange(Status status)
-{
- if (status == RangeChange)
- return;
-
- panic("O3CPU doesn't expect recvStatusChange callback!");
-}
-
-template <class Impl>
-bool
-LSQUnit<Impl>::DcachePort::recvTiming(PacketPtr pkt)
-{
- lsq->completeDataAccess(pkt);
- return true;
-}
-
-template <class Impl>
-void
-LSQUnit<Impl>::DcachePort::recvRetry()
-{
- lsq->recvRetry();
-}
-
template <class Impl>
LSQUnit<Impl>::LSQUnit()
: loads(0), stores(0), storesToWB(0), stalled(false),
template<class Impl>
void
-LSQUnit<Impl>::init(Params *params, unsigned maxLQEntries,
+LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
unsigned maxSQEntries, unsigned id)
{
DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
switchedOut = false;
+ lsq = lsq_ptr;
+
lsqID = id;
// Add 1 for the sentinel entry (they are circular queues).
usedPorts = 0;
cachePorts = params->cachePorts;
- mem = params->mem;
-
memDepViolator = NULL;
blockedLoadSeqNum = 0;
LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr)
{
cpu = cpu_ptr;
- dcachePort = new DcachePort(cpu, this);
#if USE_CHECKER
if (cpu->checker) {
storeQueue[storeWBIdx].canWB &&
usedPorts < cachePorts) {
- if (isStoreBlocked) {
+ if (isStoreBlocked || lsq->cacheBlocked()) {
DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
" is blocked!\n");
break;
// Squashed instructions do not need to complete their access.
if (inst->isSquashed()) {
+ iewStage->decrWb(inst->seqNum);
assert(!inst->isStore());
++lsqIgnoredResponses;
return;
} else {
// Still blocked!
++lsqCacheBlocked;
+ lsq->setRetryTid(lsqID);
}
} else if (isLoadBlocked) {
DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ * Korey Sewell
+ */
+
+#include "cpu/o3/mips/impl.hh"
+#include "cpu/o3/mips/cpu_impl.hh"
+#include "cpu/o3/mips/dyn_inst.hh"
+
+// Force instantiation of MipsO3CPU for all the implemntations that are
+// needed. Consider merging this and mips_dyn_inst.cc, and maybe all
+// classes that depend on a certain impl, into one file (mips_impl.cc?).
+template class MipsO3CPU<MipsSimpleImpl>;
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ * Korey Sewell
+ */
+
+#ifndef __CPU_O3_MIPS_CPU_HH__
+#define __CPU_O3_MIPS_CPU_HH__
+
+#include "arch/mips/regfile.hh"
+#include "arch/mips/syscallreturn.hh"
+#include "cpu/thread_context.hh"
+#include "cpu/o3/cpu.hh"
+#include "sim/byteswap.hh"
+#include "sim/faults.hh"
+
+class EndQuiesceEvent;
+namespace Kernel {
+ class Statistics;
+};
+
+class TranslatingPort;
+
+/**
+ * MipsO3CPU class. Derives from the FullO3CPU class, and
+ * implements all ISA and implementation specific functions of the
+ * CPU. This is the CPU class that is used for the SimObjects, and is
+ * what is given to the DynInsts. Most of its state exists in the
+ * FullO3CPU; the state is has is mainly for ISA specific
+ * functionality.
+ */
+template <class Impl>
+class MipsO3CPU : public FullO3CPU<Impl>
+{
+ public:
+ typedef O3ThreadState<Impl> ImplState;
+ typedef O3ThreadState<Impl> Thread;
+ typedef typename Impl::Params Params;
+
+ /** Constructs an MipsO3CPU with the given parameters. */
+ MipsO3CPU(Params *params);
+
+ /** Registers statistics. */
+ void regStats();
+
+ /** Translates instruction requestion in syscall emulation mode. */
+ Fault translateInstReq(RequestPtr &req, Thread *thread)
+ {
+ return thread->getProcessPtr()->pTable->translate(req);
+ }
+
+ /** Translates data read request in syscall emulation mode. */
+ Fault translateDataReadReq(RequestPtr &req, Thread *thread)
+ {
+ return thread->getProcessPtr()->pTable->translate(req);
+ }
+
+ /** Translates data write request in syscall emulation mode. */
+ Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
+ {
+ return thread->getProcessPtr()->pTable->translate(req);
+ }
+
+ /** Reads a miscellaneous register. */
+ TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
+
+ /** Reads a misc. register, including any side effects the read
+ * might have as defined by the architecture.
+ */
+ TheISA::MiscReg readMiscRegWithEffect(int misc_reg,
+ Fault &fault, unsigned tid);
+
+ /** Sets a miscellaneous register. */
+ Fault setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
+
+ /** Sets a misc. register, including any side effects the write
+ * might have as defined by the architecture.
+ */
+ Fault setMiscRegWithEffect(int misc_reg,
+ const TheISA::MiscReg &val, unsigned tid);
+
+ /** Initiates a squash of all in-flight instructions for a given
+ * thread. The source of the squash is an external update of
+ * state through the TC.
+ */
+ void squashFromTC(unsigned tid);
+
+ /** Traps to handle given fault. */
+ void trap(Fault fault, unsigned tid);
+
+ /** Executes a syscall.
+ * @todo: Determine if this needs to be virtual.
+ */
+ void syscall(int64_t callnum, int tid);
+ /** Gets a syscall argument. */
+ TheISA::IntReg getSyscallArg(int i, int tid);
+
+ /** Used to shift args for indirect syscall. */
+ void setSyscallArg(int i, TheISA::IntReg val, int tid);
+
+ /** Sets the return value of a syscall. */
+ void setSyscallReturn(SyscallReturn return_value, int tid);
+
+ /** CPU read function, forwards read to LSQ. */
+ template <class T>
+ Fault read(RequestPtr &req, T &data, int load_idx)
+ {
+ return this->iew.ldstQueue.read(req, data, load_idx);
+ }
+
+ /** CPU write function, forwards write to LSQ. */
+ template <class T>
+ Fault write(RequestPtr &req, T &data, int store_idx)
+ {
+ return this->iew.ldstQueue.write(req, data, store_idx);
+ }
+
+ Addr lockAddr;
+
+ /** Temporary fix for the lock flag, works in the UP case. */
+ bool lockFlag;
+};
+
+#endif // __CPU_O3_MIPS_CPU_HH__
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ * Korey Sewell
+ */
+
+#include <string>
+
+#include "cpu/base.hh"
+#include "cpu/o3/mips/cpu.hh"
+#include "cpu/o3/mips/impl.hh"
+#include "cpu/o3/mips/params.hh"
+#include "cpu/o3/fu_pool.hh"
+#include "sim/builder.hh"
+
+class DerivO3CPU : public MipsO3CPU<MipsSimpleImpl>
+{
+ public:
+ DerivO3CPU(MipsSimpleParams *p)
+ : MipsO3CPU<MipsSimpleImpl>(p)
+ { }
+};
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
+
+Param<int> clock;
+Param<int> numThreads;
+Param<int> activity;
+
+SimObjectVectorParam<Process *> workload;
+
+SimObjectParam<MemObject *> mem;
+
+SimObjectParam<BaseCPU *> checker;
+
+Param<Counter> max_insts_any_thread;
+Param<Counter> max_insts_all_threads;
+Param<Counter> max_loads_any_thread;
+Param<Counter> max_loads_all_threads;
+
+Param<unsigned> cachePorts;
+
+Param<unsigned> decodeToFetchDelay;
+Param<unsigned> renameToFetchDelay;
+Param<unsigned> iewToFetchDelay;
+Param<unsigned> commitToFetchDelay;
+Param<unsigned> fetchWidth;
+
+Param<unsigned> renameToDecodeDelay;
+Param<unsigned> iewToDecodeDelay;
+Param<unsigned> commitToDecodeDelay;
+Param<unsigned> fetchToDecodeDelay;
+Param<unsigned> decodeWidth;
+
+Param<unsigned> iewToRenameDelay;
+Param<unsigned> commitToRenameDelay;
+Param<unsigned> decodeToRenameDelay;
+Param<unsigned> renameWidth;
+
+Param<unsigned> commitToIEWDelay;
+Param<unsigned> renameToIEWDelay;
+Param<unsigned> issueToExecuteDelay;
+Param<unsigned> dispatchWidth;
+Param<unsigned> issueWidth;
+Param<unsigned> wbWidth;
+Param<unsigned> wbDepth;
+SimObjectParam<FUPool *> fuPool;
+
+Param<unsigned> iewToCommitDelay;
+Param<unsigned> renameToROBDelay;
+Param<unsigned> commitWidth;
+Param<unsigned> squashWidth;
+Param<Tick> trapLatency;
+
+Param<unsigned> backComSize;
+Param<unsigned> forwardComSize;
+
+Param<std::string> predType;
+Param<unsigned> localPredictorSize;
+Param<unsigned> localCtrBits;
+Param<unsigned> localHistoryTableSize;
+Param<unsigned> localHistoryBits;
+Param<unsigned> globalPredictorSize;
+Param<unsigned> globalCtrBits;
+Param<unsigned> globalHistoryBits;
+Param<unsigned> choicePredictorSize;
+Param<unsigned> choiceCtrBits;
+
+Param<unsigned> BTBEntries;
+Param<unsigned> BTBTagSize;
+
+Param<unsigned> RASSize;
+
+Param<unsigned> LQEntries;
+Param<unsigned> SQEntries;
+Param<unsigned> LFSTSize;
+Param<unsigned> SSITSize;
+
+Param<unsigned> numPhysIntRegs;
+Param<unsigned> numPhysFloatRegs;
+Param<unsigned> numIQEntries;
+Param<unsigned> numROBEntries;
+
+Param<unsigned> smtNumFetchingThreads;
+Param<std::string> smtFetchPolicy;
+Param<std::string> smtLSQPolicy;
+Param<unsigned> smtLSQThreshold;
+Param<std::string> smtIQPolicy;
+Param<unsigned> smtIQThreshold;
+Param<std::string> smtROBPolicy;
+Param<unsigned> smtROBThreshold;
+Param<std::string> smtCommitPolicy;
+
+Param<unsigned> instShiftAmt;
+
+Param<bool> defer_registration;
+
+Param<bool> function_trace;
+Param<Tick> function_trace_start;
+
+END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
+
+ INIT_PARAM(clock, "clock speed"),
+ INIT_PARAM(numThreads, "number of HW thread contexts"),
+ INIT_PARAM_DFLT(activity, "Initial activity count", 0),
+
+ INIT_PARAM(workload, "Processes to run"),
+
+ INIT_PARAM(mem, "Memory"),
+
+ INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
+
+ INIT_PARAM_DFLT(max_insts_any_thread,
+ "Terminate when any thread reaches this inst count",
+ 0),
+ INIT_PARAM_DFLT(max_insts_all_threads,
+ "Terminate when all threads have reached"
+ "this inst count",
+ 0),
+ INIT_PARAM_DFLT(max_loads_any_thread,
+ "Terminate when any thread reaches this load count",
+ 0),
+ INIT_PARAM_DFLT(max_loads_all_threads,
+ "Terminate when all threads have reached this load"
+ "count",
+ 0),
+
+ INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
+
+ INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
+ INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
+ INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
+ "delay"),
+ INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
+ INIT_PARAM(fetchWidth, "Fetch width"),
+ INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
+ INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
+ "delay"),
+ INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
+ INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
+ INIT_PARAM(decodeWidth, "Decode width"),
+
+ INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
+ "delay"),
+ INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
+ INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
+ INIT_PARAM(renameWidth, "Rename width"),
+
+ INIT_PARAM(commitToIEWDelay, "Commit to "
+ "Issue/Execute/Writeback delay"),
+ INIT_PARAM(renameToIEWDelay, "Rename to "
+ "Issue/Execute/Writeback delay"),
+ INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
+ "to the IEW stage)"),
+ INIT_PARAM(dispatchWidth, "Dispatch width"),
+ INIT_PARAM(issueWidth, "Issue width"),
+ INIT_PARAM(wbWidth, "Writeback width"),
+ INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
+ INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
+
+ INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
+ "delay"),
+ INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
+ INIT_PARAM(commitWidth, "Commit width"),
+ INIT_PARAM(squashWidth, "Squash width"),
+ INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
+
+ INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
+ INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
+
+ INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
+ INIT_PARAM(localPredictorSize, "Size of local predictor"),
+ INIT_PARAM(localCtrBits, "Bits per counter"),
+ INIT_PARAM(localHistoryTableSize, "Size of local history table"),
+ INIT_PARAM(localHistoryBits, "Bits for the local history"),
+ INIT_PARAM(globalPredictorSize, "Size of global predictor"),
+ INIT_PARAM(globalCtrBits, "Bits per counter"),
+ INIT_PARAM(globalHistoryBits, "Bits of history"),
+ INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
+ INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
+
+ INIT_PARAM(BTBEntries, "Number of BTB entries"),
+ INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
+
+ INIT_PARAM(RASSize, "RAS size"),
+
+ INIT_PARAM(LQEntries, "Number of load queue entries"),
+ INIT_PARAM(SQEntries, "Number of store queue entries"),
+ INIT_PARAM(LFSTSize, "Last fetched store table size"),
+ INIT_PARAM(SSITSize, "Store set ID table size"),
+
+ INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
+ INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
+ "registers"),
+ INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
+ INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
+
+ INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
+ INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
+ INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
+ INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
+ INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
+ INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
+ INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
+ INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
+ INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
+
+ INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
+ INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
+
+ INIT_PARAM(function_trace, "Enable function trace"),
+ INIT_PARAM(function_trace_start, "Cycle to start function trace")
+
+END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
+
+CREATE_SIM_OBJECT(DerivO3CPU)
+{
+ DerivO3CPU *cpu;
+
+ // In non-full-system mode, we infer the number of threads from
+ // the workload if it's not explicitly specified.
+ int actual_num_threads =
+ (numThreads.isValid() && numThreads >= workload.size()) ?
+ numThreads : workload.size();
+
+ if (workload.size() == 0) {
+ fatal("Must specify at least one workload!");
+ }
+
+ MipsSimpleParams *params = new MipsSimpleParams;
+
+ params->clock = clock;
+
+ params->name = getInstanceName();
+ params->numberOfThreads = actual_num_threads;
+ params->activity = activity;
+
+ params->workload = workload;
+
+ params->mem = mem;
+
+ params->checker = checker;
+
+ params->max_insts_any_thread = max_insts_any_thread;
+ params->max_insts_all_threads = max_insts_all_threads;
+ params->max_loads_any_thread = max_loads_any_thread;
+ params->max_loads_all_threads = max_loads_all_threads;
+
+ //
+ // Caches
+ //
+ params->cachePorts = cachePorts;
+
+ params->decodeToFetchDelay = decodeToFetchDelay;
+ params->renameToFetchDelay = renameToFetchDelay;
+ params->iewToFetchDelay = iewToFetchDelay;
+ params->commitToFetchDelay = commitToFetchDelay;
+ params->fetchWidth = fetchWidth;
+
+ params->renameToDecodeDelay = renameToDecodeDelay;
+ params->iewToDecodeDelay = iewToDecodeDelay;
+ params->commitToDecodeDelay = commitToDecodeDelay;
+ params->fetchToDecodeDelay = fetchToDecodeDelay;
+ params->decodeWidth = decodeWidth;
+
+ params->iewToRenameDelay = iewToRenameDelay;
+ params->commitToRenameDelay = commitToRenameDelay;
+ params->decodeToRenameDelay = decodeToRenameDelay;
+ params->renameWidth = renameWidth;
+
+ params->commitToIEWDelay = commitToIEWDelay;
+ params->renameToIEWDelay = renameToIEWDelay;
+ params->issueToExecuteDelay = issueToExecuteDelay;
+ params->dispatchWidth = dispatchWidth;
+ params->issueWidth = issueWidth;
+ params->wbWidth = wbWidth;
+ params->wbDepth = wbDepth;
+ params->fuPool = fuPool;
+
+ params->iewToCommitDelay = iewToCommitDelay;
+ params->renameToROBDelay = renameToROBDelay;
+ params->commitWidth = commitWidth;
+ params->squashWidth = squashWidth;
+ params->trapLatency = trapLatency;
+
+ params->backComSize = backComSize;
+ params->forwardComSize = forwardComSize;
+
+ params->predType = predType;
+ params->localPredictorSize = localPredictorSize;
+ params->localCtrBits = localCtrBits;
+ params->localHistoryTableSize = localHistoryTableSize;
+ params->localHistoryBits = localHistoryBits;
+ params->globalPredictorSize = globalPredictorSize;
+ params->globalCtrBits = globalCtrBits;
+ params->globalHistoryBits = globalHistoryBits;
+ params->choicePredictorSize = choicePredictorSize;
+ params->choiceCtrBits = choiceCtrBits;
+
+ params->BTBEntries = BTBEntries;
+ params->BTBTagSize = BTBTagSize;
+
+ params->RASSize = RASSize;
+
+ params->LQEntries = LQEntries;
+ params->SQEntries = SQEntries;
+
+ params->SSITSize = SSITSize;
+ params->LFSTSize = LFSTSize;
+
+ params->numPhysIntRegs = numPhysIntRegs;
+ params->numPhysFloatRegs = numPhysFloatRegs;
+ params->numIQEntries = numIQEntries;
+ params->numROBEntries = numROBEntries;
+
+ params->smtNumFetchingThreads = smtNumFetchingThreads;
+
+ // Default smtFetchPolicy to "RoundRobin", if necessary.
+ std::string round_robin_policy = "RoundRobin";
+ std::string single_thread = "SingleThread";
+
+ if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0)
+ params->smtFetchPolicy = round_robin_policy;
+ else
+ params->smtFetchPolicy = smtFetchPolicy;
+
+ params->smtIQPolicy = smtIQPolicy;
+ params->smtLSQPolicy = smtLSQPolicy;
+ params->smtLSQThreshold = smtLSQThreshold;
+ params->smtROBPolicy = smtROBPolicy;
+ params->smtROBThreshold = smtROBThreshold;
+ params->smtCommitPolicy = smtCommitPolicy;
+
+ params->instShiftAmt = 2;
+
+ params->deferRegistration = defer_registration;
+
+ params->functionTrace = function_trace;
+ params->functionTraceStart = function_trace_start;
+
+ cpu = new DerivO3CPU(params);
+
+ return cpu;
+}
+
+REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)
+
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ * Korey Sewell
+ */
+
+#include "config/use_checker.hh"
+
+#include "arch/mips/faults.hh"
+#include "base/cprintf.hh"
+#include "base/statistics.hh"
+#include "base/timebuf.hh"
+#include "cpu/checker/thread_context.hh"
+#include "sim/sim_events.hh"
+#include "sim/stats.hh"
+
+#include "cpu/o3/mips/cpu.hh"
+#include "cpu/o3/mips/params.hh"
+#include "cpu/o3/mips/thread_context.hh"
+#include "cpu/o3/comm.hh"
+#include "cpu/o3/thread_state.hh"
+
+template <class Impl>
+MipsO3CPU<Impl>::MipsO3CPU(Params *params)
+ : FullO3CPU<Impl>(params)
+{
+ DPRINTF(O3CPU, "Creating MipsO3CPU object.\n");
+
+ // Setup any thread state.
+ this->thread.resize(this->numThreads);
+
+ for (int i = 0; i < this->numThreads; ++i) {
+ if (i < params->workload.size()) {
+ DPRINTF(O3CPU, "Workload[%i] process is %#x",
+ i, this->thread[i]);
+ this->thread[i] = new Thread(this, i, params->workload[i],
+ i, params->mem);
+
+ this->thread[i]->setStatus(ThreadContext::Suspended);
+
+
+ /* Use this port to for syscall emulation writes to memory. */
+ Port *mem_port;
+ TranslatingPort *trans_port;
+ trans_port = new TranslatingPort(csprintf("%s-%d-funcport",
+ name(), i),
+ params->workload[i]->pTable,
+ false);
+ mem_port = params->mem->getPort("functional");
+ mem_port->setPeer(trans_port);
+ trans_port->setPeer(mem_port);
+ this->thread[i]->setMemPort(trans_port);
+
+ //usedTids[i] = true;
+ //threadMap[i] = i;
+ } else {
+ //Allocate Empty thread so M5 can use later
+ //when scheduling threads to CPU
+ Process* dummy_proc = NULL;
+
+ this->thread[i] = new Thread(this, i, dummy_proc, i, params->mem);
+ //usedTids[i] = false;
+ }
+
+ ThreadContext *tc;
+
+ // Setup the TC that will serve as the interface to the threads/CPU.
+ MipsTC<Impl> *mips_tc =
+ new MipsTC<Impl>;
+
+ tc = mips_tc;
+
+ // If we're using a checker, then the TC should be the
+ // CheckerThreadContext.
+#if USE_CHECKER
+ if (params->checker) {
+ tc = new CheckerThreadContext<MipsTC<Impl> >(
+ mips_tc, this->checker);
+ }
+#endif
+
+ mips_tc->cpu = this;
+ mips_tc->thread = this->thread[i];
+
+ // Give the thread the TC.
+ this->thread[i]->tc = tc;
+
+ // Add the TC to the CPU's list of TC's.
+ this->threadContexts.push_back(tc);
+ }
+
+ for (int i=0; i < this->numThreads; i++) {
+ this->thread[i]->setFuncExeInst(0);
+ }
+
+ // Sets CPU pointers. These must be set at this level because the CPU
+ // pointers are defined to be the highest level of CPU class.
+ this->fetch.setCPU(this);
+ this->decode.setCPU(this);
+ this->rename.setCPU(this);
+ this->iew.setCPU(this);
+ this->commit.setCPU(this);
+
+ this->rob.setCPU(this);
+ this->regFile.setCPU(this);
+
+ lockAddr = 0;
+ lockFlag = false;
+}
+
+template <class Impl>
+void
+MipsO3CPU<Impl>::regStats()
+{
+ // Register stats for everything that has stats.
+ this->fullCPURegStats();
+ this->fetch.regStats();
+ this->decode.regStats();
+ this->rename.regStats();
+ this->iew.regStats();
+ this->commit.regStats();
+}
+
+
+template <class Impl>
+MiscReg
+MipsO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
+{
+ return this->regFile.readMiscReg(misc_reg, tid);
+}
+
+template <class Impl>
+MiscReg
+MipsO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault,
+ unsigned tid)
+{
+ return this->regFile.readMiscRegWithEffect(misc_reg, fault, tid);
+}
+
+template <class Impl>
+Fault
+MipsO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
+{
+ return this->regFile.setMiscReg(misc_reg, val, tid);
+}
+
+template <class Impl>
+Fault
+MipsO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
+ unsigned tid)
+{
+ return this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
+}
+
+template <class Impl>
+void
+MipsO3CPU<Impl>::squashFromTC(unsigned tid)
+{
+ this->thread[tid]->inSyscall = true;
+ this->commit.generateTCEvent(tid);
+}
+
+template <class Impl>
+void
+MipsO3CPU<Impl>::trap(Fault fault, unsigned tid)
+{
+ // Pass the thread's TC into the invoke method.
+ fault->invoke(this->threadContexts[tid]);
+}
+
+#if !FULL_SYSTEM
+
+template <class Impl>
+void
+MipsO3CPU<Impl>::syscall(int64_t callnum, int tid)
+{
+ DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
+
+ DPRINTF(Activity,"Activity: syscall() called.\n");
+
+ // Temporarily increase this by one to account for the syscall
+ // instruction.
+ ++(this->thread[tid]->funcExeInst);
+
+ // Execute the actual syscall.
+ this->thread[tid]->syscall(callnum);
+
+ // Decrease funcExeInst by one as the normal commit will handle
+ // incrementing it.
+ --(this->thread[tid]->funcExeInst);
+
+ DPRINTF(O3CPU, "[tid:%i] Register 2 is %i ", tid, this->readIntReg(2));
+}
+
+template <class Impl>
+TheISA::IntReg
+MipsO3CPU<Impl>::getSyscallArg(int i, int tid)
+{
+ return this->readArchIntReg(MipsISA::ArgumentReg0 + i, tid);
+}
+
+template <class Impl>
+void
+MipsO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid)
+{
+ this->setArchIntReg(MipsISA::ArgumentReg0 + i, val, tid);
+}
+
+template <class Impl>
+void
+MipsO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
+{
+ // check for error condition.
+ if (return_value.successful()) {
+ // no error
+ this->setArchIntReg(TheISA::SyscallSuccessReg, 0, tid);
+ this->setArchIntReg(TheISA::ReturnValueReg, return_value.value(), tid);
+ } else {
+ // got an error, return details
+ this->setArchIntReg(TheISA::SyscallSuccessReg,
+ (TheISA::IntReg) -1, tid);
+ this->setArchIntReg(TheISA::ReturnValueReg, -return_value.value(), tid);
+ }
+}
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ * Korey Sewell
+ */
+
+#include "cpu/o3/mips/dyn_inst_impl.hh"
+#include "cpu/o3/mips/impl.hh"
+
+// Force instantiation of MipsDynInst for all the implementations that
+// are needed.
+template class MipsDynInst<MipsSimpleImpl>;
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ * Korey Sewell
+ */
+
+#ifndef __CPU_O3_MIPS_DYN_INST_HH__
+#define __CPU_O3_MIPS_DYN_INST_HH__
+
+#include "arch/isa_traits.hh"
+#include "cpu/base_dyn_inst.hh"
+#include "cpu/inst_seq.hh"
+#include "cpu/o3/mips/cpu.hh"
+#include "cpu/o3/mips/impl.hh"
+
+class Packet;
+
+/**
+ * Mostly implementation & ISA specific MipsDynInst. As with most
+ * other classes in the new CPU model, it is templated on the Impl to
+ * allow for passing in of all types, such as the CPU type and the ISA
+ * type. The MipsDynInst serves as the primary interface to the CPU
+ * for instructions that are executing.
+ */
+template <class Impl>
+class MipsDynInst : public BaseDynInst<Impl>
+{
+ public:
+ /** Typedef for the CPU. */
+ typedef typename Impl::O3CPU O3CPU;
+
+ /** Binary machine instruction type. */
+ typedef TheISA::MachInst MachInst;
+ /** Extended machine instruction type. */
+ typedef TheISA::ExtMachInst ExtMachInst;
+ /** Logical register index type. */
+ typedef TheISA::RegIndex RegIndex;
+ /** Integer register index type. */
+ typedef TheISA::IntReg IntReg;
+ typedef TheISA::FloatReg FloatReg;
+ typedef TheISA::FloatRegBits FloatRegBits;
+ /** Misc register index type. */
+ typedef TheISA::MiscReg MiscReg;
+
+ enum {
+ MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
+ MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
+ };
+
+ public:
+ /** BaseDynInst constructor given a binary instruction. */
+ MipsDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
+ O3CPU *cpu);
+
+ /** BaseDynInst constructor given a static inst pointer. */
+ MipsDynInst(StaticInstPtr &_staticInst);
+
+ /** Executes the instruction.*/
+ Fault execute();
+
+ /** Initiates the access. Only valid for memory operations. */
+ Fault initiateAcc();
+
+ /** Completes the access. Only valid for memory operations. */
+ Fault completeAcc(Packet *pkt);
+
+ private:
+ /** Initializes variables. */
+ void initVars();
+
+ public:
+ /** Reads a miscellaneous register. */
+ MiscReg readMiscReg(int misc_reg)
+ {
+ return this->cpu->readMiscReg(misc_reg, this->threadNumber);
+ }
+
+ /** Reads a misc. register, including any side-effects the read
+ * might have as defined by the architecture.
+ */
+ MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+ {
+ return this->cpu->readMiscRegWithEffect(misc_reg, fault,
+ this->threadNumber);
+ }
+
+ /** Sets a misc. register. */
+ Fault setMiscReg(int misc_reg, const MiscReg &val)
+ {
+ this->instResult.integer = val;
+ return this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
+ }
+
+ /** Sets a misc. register, including any side-effects the write
+ * might have as defined by the architecture.
+ */
+ Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+ {
+ return this->cpu->setMiscRegWithEffect(misc_reg, val,
+ this->threadNumber);
+ }
+
+ /** Calls a syscall. */
+ void syscall(int64_t callnum);
+
+ private:
+ /** Physical register index of the destination registers of this
+ * instruction.
+ */
+ PhysRegIndex _destRegIdx[MaxInstDestRegs];
+
+ /** Physical register index of the source registers of this
+ * instruction.
+ */
+ PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
+
+ /** Physical register index of the previous producers of the
+ * architected destinations.
+ */
+ PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
+
+ public:
+
+ // The register accessor methods provide the index of the
+ // instruction's operand (e.g., 0 or 1), not the architectural
+ // register index, to simplify the implementation of register
+ // renaming. We find the architectural register index by indexing
+ // into the instruction's own operand index table. Note that a
+ // raw pointer to the StaticInst is provided instead of a
+ // ref-counted StaticInstPtr to redice overhead. This is fine as
+ // long as these methods don't copy the pointer into any long-term
+ // storage (which is pretty hard to imagine they would have reason
+ // to do).
+
+ uint64_t readIntReg(const StaticInst *si, int idx)
+ {
+ return this->cpu->readIntReg(_srcRegIdx[idx]);
+ }
+
+ FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+ {
+ return this->cpu->readFloatReg(_srcRegIdx[idx], width);
+ }
+
+ FloatReg readFloatReg(const StaticInst *si, int idx)
+ {
+ return this->cpu->readFloatReg(_srcRegIdx[idx]);
+ }
+
+ FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ {
+ return this->cpu->readFloatRegBits(_srcRegIdx[idx], width);
+ }
+
+ FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ {
+ return this->cpu->readFloatRegBits(_srcRegIdx[idx]);
+ }
+
+ /** @todo: Make results into arrays so they can handle multiple dest
+ * registers.
+ */
+ void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ {
+ this->cpu->setIntReg(_destRegIdx[idx], val);
+ BaseDynInst<Impl>::setIntReg(si, idx, val);
+ }
+
+ void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ {
+ this->cpu->setFloatReg(_destRegIdx[idx], val, width);
+ BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
+ }
+
+ void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ {
+ this->cpu->setFloatReg(_destRegIdx[idx], val);
+ BaseDynInst<Impl>::setFloatReg(si, idx, val);
+ }
+
+ void setFloatRegBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
+ {
+ this->cpu->setFloatRegBits(_destRegIdx[idx], val, width);
+ BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+ }
+
+ void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ {
+ this->cpu->setFloatRegBits(_destRegIdx[idx], val);
+ BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+ }
+
+ /** Returns the physical register index of the i'th destination
+ * register.
+ */
+ PhysRegIndex renamedDestRegIdx(int idx) const
+ {
+ return _destRegIdx[idx];
+ }
+
+ /** Returns the physical register index of the i'th source register. */
+ PhysRegIndex renamedSrcRegIdx(int idx) const
+ {
+ return _srcRegIdx[idx];
+ }
+
+ /** Returns the physical register index of the previous physical register
+ * that remapped to the same logical register index.
+ */
+ PhysRegIndex prevDestRegIdx(int idx) const
+ {
+ return _prevDestRegIdx[idx];
+ }
+
+ /** Renames a destination register to a physical register. Also records
+ * the previous physical register that the logical register mapped to.
+ */
+ void renameDestReg(int idx,
+ PhysRegIndex renamed_dest,
+ PhysRegIndex previous_rename)
+ {
+ _destRegIdx[idx] = renamed_dest;
+ _prevDestRegIdx[idx] = previous_rename;
+ }
+
+ /** Renames a source logical register to the physical register which
+ * has/will produce that logical register's result.
+ * @todo: add in whether or not the source register is ready.
+ */
+ void renameSrcReg(int idx, PhysRegIndex renamed_src)
+ {
+ _srcRegIdx[idx] = renamed_src;
+ }
+
+ public:
+ /** Calculates EA part of a memory instruction. Currently unused,
+ * though it may be useful in the future if we want to split
+ * memory operations into EA calculation and memory access parts.
+ */
+ Fault calcEA()
+ {
+ return this->staticInst->eaCompInst()->execute(this, this->traceData);
+ }
+
+ /** Does the memory access part of a memory instruction. Currently unused,
+ * though it may be useful in the future if we want to split
+ * memory operations into EA calculation and memory access parts.
+ */
+ Fault memAccess()
+ {
+ return this->staticInst->memAccInst()->execute(this, this->traceData);
+ }
+};
+
+#endif // __CPU_O3_MIPS_DYN_INST_HH__
+
--- /dev/null
+/*
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ */
+
+#include "cpu/o3/mips/dyn_inst.hh"
+
+template <class Impl>
+MipsDynInst<Impl>::MipsDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
+ InstSeqNum seq_num, O3CPU *cpu)
+ : BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
+{
+ initVars();
+}
+
+template <class Impl>
+MipsDynInst<Impl>::MipsDynInst(StaticInstPtr &_staticInst)
+ : BaseDynInst<Impl>(_staticInst)
+{
+ initVars();
+}
+
+template <class Impl>
+void
+MipsDynInst<Impl>::initVars()
+{
+ // Make sure to have the renamed register entries set to the same
+ // as the normal register entries. It will allow the IQ to work
+ // without any modifications.
+ for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
+ _destRegIdx[i] = this->staticInst->destRegIdx(i);
+ }
+
+ for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
+ _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
+ this->_readySrcRegIdx[i] = 0;
+ }
+}
+
+template <class Impl>
+Fault
+MipsDynInst<Impl>::execute()
+{
+ // @todo: Pretty convoluted way to avoid squashing from happening
+ // when using the TC during an instruction's execution
+ // (specifically for instructions that have side-effects that use
+ // the TC). Fix this.
+ bool in_syscall = this->thread->inSyscall;
+ this->thread->inSyscall = true;
+
+ this->fault = this->staticInst->execute(this, this->traceData);
+
+ this->thread->inSyscall = in_syscall;
+
+ return this->fault;
+}
+
+template <class Impl>
+Fault
+MipsDynInst<Impl>::initiateAcc()
+{
+ // @todo: Pretty convoluted way to avoid squashing from happening
+ // when using the TC during an instruction's execution
+ // (specifically for instructions that have side-effects that use
+ // the TC). Fix this.
+ bool in_syscall = this->thread->inSyscall;
+ this->thread->inSyscall = true;
+
+ this->fault = this->staticInst->initiateAcc(this, this->traceData);
+
+ this->thread->inSyscall = in_syscall;
+
+ return this->fault;
+}
+
+template <class Impl>
+Fault
+MipsDynInst<Impl>::completeAcc(Packet *pkt)
+{
+ this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
+
+ return this->fault;
+}
+
+template <class Impl>
+void
+MipsDynInst<Impl>::syscall(int64_t callnum)
+{
+ this->cpu->syscall(callnum, this->threadNumber);
+}
+
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ * Korey Sewell
+ */
+
+#ifndef __CPU_O3_MIPS_IMPL_HH__
+#define __CPU_O3_MIPS_IMPL_HH__
+
+#include "arch/mips/isa_traits.hh"
+
+#include "cpu/o3/mips/params.hh"
+#include "cpu/o3/cpu_policy.hh"
+
+
+// Forward declarations.
+template <class Impl>
+class MipsDynInst;
+
+template <class Impl>
+class MipsO3CPU;
+
+/** Implementation specific struct that defines several key types to the
+ * CPU, the stages within the CPU, the time buffers, and the DynInst.
+ * The struct defines the ISA, the CPU policy, the specific DynInst, the
+ * specific O3CPU, and all of the structs from the time buffers to do
+ * communication.
+ * This is one of the key things that must be defined for each hardware
+ * specific CPU implementation.
+ */
+struct MipsSimpleImpl
+{
+ /** The type of MachInst. */
+ typedef TheISA::MachInst MachInst;
+
+ /** The CPU policy to be used, which defines all of the CPU stages. */
+ typedef SimpleCPUPolicy<MipsSimpleImpl> CPUPol;
+
+ /** The DynInst type to be used. */
+ typedef MipsDynInst<MipsSimpleImpl> DynInst;
+
+ /** The refcounted DynInst pointer to be used. In most cases this is
+ * what should be used, and not DynInst *.
+ */
+ typedef RefCountingPtr<DynInst> DynInstPtr;
+
+ /** The O3CPU type to be used. */
+ typedef MipsO3CPU<MipsSimpleImpl> O3CPU;
+
+ /** Same typedef, but for CPUType. BaseDynInst may not always use
+ * an O3 CPU, so it's clearer to call it CPUType instead in that
+ * case.
+ */
+ typedef O3CPU CPUType;
+
+ /** The Params to be passed to each stage. */
+ typedef MipsSimpleParams Params;
+
+ enum {
+ MaxWidth = 8,
+ MaxThreads = 4
+ };
+};
+
+/** The O3Impl to be used. */
+typedef MipsSimpleImpl O3CPUImpl;
+
+#endif // __CPU_O3_MIPS_IMPL_HH__
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ * Korey Sewell
+ */
+
+#ifndef __CPU_O3_MIPS_PARAMS_HH__
+#define __CPU_O3_MIPS_PARAMS_HH__
+
+#include "cpu/o3/cpu.hh"
+#include "cpu/o3/params.hh"
+
+//Forward declarations
+//class MipsDTB;
+//class MipsITB;
+class MemObject;
+class Process;
+class System;
+
+/**
+ * This file defines the parameters that will be used for the MipsO3CPU.
+ * This must be defined externally so that the Impl can have a params class
+ * defined that it can pass to all of the individual stages.
+ */
+
+class MipsSimpleParams : public O3Params
+{
+ public:
+ MipsSimpleParams() {}
+
+#if FULL_SYSTEM
+ //Full System Paramater Objects place here
+ MipsITB *itb;
+ MipsDTB *dtb;
+#endif
+};
+
+#endif // __CPU_O3_MIPS_PARAMS_HH__
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ * Korey Sewell
+ */
+
+#include "cpu/o3/thread_context.hh"
+#include "cpu/o3/thread_context_impl.hh"
+
+template class O3ThreadContext<MipsSimpleImpl>;
+
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ * Korey Sewell
+ */
+
+#include "arch/mips/types.hh"
+#include "cpu/o3/thread_context.hh"
+
+template <class Impl>
+class MipsTC : public O3ThreadContext<Impl>
+{
+ public:
+ virtual uint64_t readNextNPC()
+ {
+ return this->cpu->readNextNPC(this->thread->readTid());
+ }
+
+ virtual void setNextNPC(uint64_t val)
+ {
+ this->cpu->setNextNPC(val, this->thread->readTid());
+ }
+
+ virtual void changeRegFileContext(TheISA::RegContextParam param,
+ TheISA::RegContextVal val)
+ { panic("Not supported on Mips!"); }
+
+ /** This function exits the thread context in the CPU and returns
+ * 1 if the CPU has no more active threads (meaning it's OK to exit);
+ * Used in syscall-emulation mode when a thread executes the 'exit'
+ * syscall.
+ */
+ virtual int exit()
+ {
+ this->deallocate();
+
+ // If there are still threads executing in the system
+ if (this->cpu->numActiveThreads())
+ return 0; // don't exit simulation
+ else
+ return 1; // exit simulation
+ }
+};
#ifndef __CPU_O3_RAS_HH__
#define __CPU_O3_RAS_HH__
-// For Addr type.
-#include "arch/isa_traits.hh"
+#include "sim/host.hh"
#include <vector>
/** Return address stack class, implements a simple RAS. */
#define __CPU_O3_REGFILE_HH__
#include "arch/isa_traits.hh"
-#include "arch/faults.hh"
#include "arch/types.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/o3/comm.hh"
+#include "sim/faults.hh"
#if FULL_SYSTEM
#include "kern/kernel_stats.hh"
// using a list instead of a queue. (Most other stages use a
// queue)
typedef std::list<DynInstPtr> InstQueue;
+ typedef typename std::list<DynInstPtr>::iterator ListIt;
public:
/** Overall rename status. Used to determine if the CPU can
void takeOverFrom();
/** Squashes all instructions in a thread. */
- void squash(unsigned tid);
+ void squash(const InstSeqNum &squash_seq_num, unsigned tid);
/** Ticks rename, which processes all input signals and attempts to rename
* as many instructions as possible.
bool unblock(unsigned tid);
/** Executes actual squash, removing squashed instructions. */
- void doSquash(unsigned tid);
+ void doSquash(const InstSeqNum &squash_seq_num, unsigned tid);
/** Removes a committed instruction's rename history. */
void removeFromHistory(InstSeqNum inst_seq_num, unsigned tid);
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
+ * Korey Sewell
*/
#include <list>
#include "config/full_system.hh"
#include "cpu/o3/rename.hh"
-using namespace std;
-
template <class Impl>
DefaultRename<Impl>::DefaultRename(Params *params)
: iewToRenameDelay(params->iewToRenameDelay),
template<class Impl>
void
-DefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+DefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
{
DPRINTF(Rename, "Setting active threads list pointer.\n");
activeThreads = at_ptr;
{
// Clear any state, fix up the rename map.
for (int i = 0; i < numThreads; i++) {
- typename list<RenameHistory>::iterator hb_it = historyBuffer[i].begin();
+ typename std::list<RenameHistory>::iterator hb_it =
+ historyBuffer[i].begin();
while (!historyBuffer[i].empty()) {
assert(hb_it != historyBuffer[i].end());
template <class Impl>
void
-DefaultRename<Impl>::squash(unsigned tid)
+DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
{
DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
unsigned squashCount = 0;
for (int i=0; i<fromDecode->size; i++) {
- if (fromDecode->insts[i]->threadNumber == tid) {
+ if (fromDecode->insts[i]->threadNumber == tid &&
+ fromDecode->insts[i]->seqNum > squash_seq_num) {
fromDecode->insts[i]->setSquashed();
wroteToTimeBuffer = true;
squashCount++;
}
+
}
+ // Clear the instruction list and skid buffer in case they have any
+ // insts in them. Since we support multiple ISAs, we cant just:
+ // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is
+ // a possible delay slot inst for different architectures
+ // insts[tid].clear();
+#if THE_ISA == ALPHA_ISA
insts[tid].clear();
+#else
+ DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until "
+ "[sn:%i].\n",tid, squash_seq_num);
+ ListIt ilist_it = insts[tid].begin();
+ while (ilist_it != insts[tid].end()) {
+ if ((*ilist_it)->seqNum > squash_seq_num) {
+ (*ilist_it)->setSquashed();
+ DPRINTF(Rename, "Squashing incoming decode instruction, "
+ "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC);
+ }
+ ilist_it++;
+ }
+#endif
// Clear the skid buffer in case it has any data in it.
+ // See comments above.
+ // skidBuffer[tid].clear();
+#if THE_ISA == ALPHA_ISA
skidBuffer[tid].clear();
-
- doSquash(tid);
+#else
+ DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions "
+ "until [sn:%i].\n", tid, squash_seq_num);
+ ListIt slist_it = skidBuffer[tid].begin();
+ while (slist_it != skidBuffer[tid].end()) {
+ if ((*slist_it)->seqNum > squash_seq_num) {
+ (*slist_it)->setSquashed();
+ DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]"
+ "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC);
+ }
+ slist_it++;
+ }
+#endif
+ doSquash(squash_seq_num, tid);
}
template <class Impl>
sortInsts();
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
// Check stall and squash signals.
while (threads != (*activeThreads).end()) {
if (inst->isSquashed()) {
DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
"squashed, skipping.\n",
- tid, inst->seqNum, inst->threadNumber,inst->readPC());
+ tid, inst->seqNum, inst->readPC());
++renameSquashedInsts;
{
int insts_from_decode = fromDecode->size;
#ifdef DEBUG
+#if THE_ISA == ALPHA_ISA
for (int i=0; i < numThreads; i++)
assert(insts[i].empty());
+#endif
#endif
for (int i = 0; i < insts_from_decode; ++i) {
DynInstPtr inst = fromDecode->insts[i];
bool
DefaultRename<Impl>::skidsEmpty()
{
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
if (!skidBuffer[*threads++].empty())
{
bool any_unblocking = false;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
threads = (*activeThreads).begin();
template <class Impl>
void
-DefaultRename<Impl>::doSquash(unsigned tid)
+DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid)
{
- typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin();
-
- InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
+ typename std::list<RenameHistory>::iterator hb_it =
+ historyBuffer[tid].begin();
// After a syscall squashes everything, the history buffer may be empty
// but the ROB may still be squashing instructions.
"history buffer %u (size=%i), until [sn:%lli].\n",
tid, tid, historyBuffer[tid].size(), inst_seq_num);
- typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end();
+ typename std::list<RenameHistory>::iterator hb_it =
+ historyBuffer[tid].end();
--hb_it;
historyBuffer[tid].push_front(hb_entry);
- DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer, "
- "[sn:%lli].\n",tid,
+ DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
+ "(size=%i), [sn:%lli].\n",tid,
+ historyBuffer[tid].size(),
(*historyBuffer[tid].begin()).instSeqNum);
// Tell the instruction to rename the appropriate destination
DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
"commit.\n", tid);
- squash(tid);
+#if THE_ISA == ALPHA_ISA
+ InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
+#else
+ InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
+#endif
+
+ squash(squashed_seq_num, tid);
return true;
}
void
DefaultRename<Impl>::dumpHistory()
{
- typename list<RenameHistory>::iterator buf_it;
+ typename std::list<RenameHistory>::iterator buf_it;
for (int i = 0; i < numThreads; i++) {
#include <vector>
#include "cpu/o3/free_list.hh"
-//For RegIndex
-#include "arch/isa_traits.hh"
+#include "arch/types.hh"
class SimpleRenameMap
{
#include "config/full_system.hh"
#include "cpu/o3/rob.hh"
-using namespace std;
+#include <list>
template <class Impl>
ROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth,
- string _smtROBPolicy, unsigned _smtROBThreshold,
+ std::string _smtROBPolicy, unsigned _smtROBThreshold,
unsigned _numThreads)
: numEntries(_numEntries),
squashWidth(_squashWidth),
threadEntries[tid] = 0;
}
- string policy = _smtROBPolicy;
+ std::string policy = _smtROBPolicy;
//Convert string to lowercase
std::transform(policy.begin(), policy.end(), policy.begin(),
template <class Impl>
void
-ROB<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+ROB<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
{
DPRINTF(ROB, "Setting active threads list pointer.\n");
activeThreads = at_ptr;
if (robPolicy != Dynamic || numThreads > 1) {
int active_threads = (*activeThreads).size();
- list<unsigned>::iterator threads = (*activeThreads).begin();
- list<unsigned>::iterator list_end = (*activeThreads).end();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator list_end = (*activeThreads).end();
while (threads != list_end) {
if (robPolicy == Partitioned) {
ROB<Impl>::canCommit()
{
//@todo: set ActiveThreads through ROB or CPU
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
bool first_valid = true;
// @todo: set ActiveThreads through ROB or CPU
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned thread_num = *threads++;
tail = instList[0].end();
bool first_valid = true;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
#include <iostream>
#include <utility>
#include <vector>
-#include "arch/alpha/isa_traits.hh"
#include "base/trace.hh"
#include "base/traceflags.hh"
#include "cpu/o3/comm.hh"
#include <utility>
#include <vector>
-#include "arch/isa_traits.hh"
#include "cpu/inst_seq.hh"
+#include "sim/host.hh"
struct ltseqnum {
bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
- * Korey Sewell
*/
#ifndef __CPU_O3_THREAD_CONTEXT_HH__
#define __CPU_O3_THREAD_CONTEXT_HH__
+#include "cpu/thread_context.hh"
#include "cpu/o3/isa_specific.hh"
class EndQuiesceEvent;
#include "cpu/o3/thread_context.hh"
#include "cpu/quiesce_event.hh"
-using namespace TheISA;
-
#if FULL_SYSTEM
template <class Impl>
VirtualPort *
}
// Copy the misc regs.
- copyMiscRegs(tc, this);
+ TheISA::copyMiscRegs(tc, this);
// Then finally set the PC and the next PC.
cpu->setPC(tc->readPC(), tid);
}
template <class Impl>
-FloatReg
+TheISA::FloatReg
O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
{
switch(width) {
}
template <class Impl>
-FloatReg
+TheISA::FloatReg
O3ThreadContext<Impl>::readFloatReg(int reg_idx)
{
return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
}
template <class Impl>
-FloatRegBits
+TheISA::FloatRegBits
O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
{
DPRINTF(Fault, "Reading floatint register through the TC!\n");
}
template <class Impl>
-FloatRegBits
+TheISA::FloatRegBits
O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
{
return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
#ifndef __CPU_O3_THREAD_STATE_HH__
#define __CPU_O3_THREAD_STATE_HH__
-#include "arch/faults.hh"
-#include "arch/isa_traits.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
#ifndef __CPU_O3_TOURNAMENT_PRED_HH__
#define __CPU_O3_TOURNAMENT_PRED_HH__
-// For Addr type.
-#include "arch/isa_traits.hh"
#include "cpu/o3/sat_counter.hh"
+#include "sim/host.hh"
#include <vector>
/**
#include "arch/faults.hh"
#include "arch/alpha/osfpal.hh"
#include "arch/alpha/tlb.hh"
+#include "arch/alpha/types.hh"
#include "arch/vtophys.hh"
#include "base/callback.hh"
//#include "base/remote_gdb.hh"
#define __CPU_OZONE_DYN_INST_HH__
#include "arch/isa_traits.hh"
+#include "arch/types.hh"
#include "config/full_system.hh"
#include "cpu/base_dyn_inst.hh"
#include "cpu/inst_seq.hh"
*/
#include "arch/faults.hh"
-#include "arch/isa_traits.hh"
#include "config/full_system.hh"
#include "cpu/ozone/dyn_inst.hh"
#include "kern/kernel_stats.hh"
-using namespace TheISA;
-
template <class Impl>
OzoneDynInst<Impl>::OzoneDynInst(OzoneCPU *cpu)
: BaseDynInst<Impl>(0, 0, 0, 0, cpu)
#include <list>
#include <utility>
-#include "arch/isa_traits.hh"
#include "cpu/inst_seq.hh"
+#include "sim/host.hh"
/**
* Simple class to hold onto a list of pairs, each pair having a memory
#include "arch/faults.hh"
#include "arch/isa_traits.hh"
+#include "arch/utility.hh"
#include "base/statistics.hh"
#include "cpu/thread_context.hh"
#include "cpu/exetrace.hh"
*/
#include "arch/faults.hh"
-#include "arch/isa_traits.hh"
+#include "arch/types.hh"
#include "cpu/ozone/inorder_back_end.hh"
#include "cpu/ozone/thread_state.hh"
-using namespace TheISA;
-
template <class Impl>
InorderBackEnd<Impl>::InorderBackEnd(Params *params)
: squashPending(false),
#include <algorithm>
#include "arch/faults.hh"
-#include "arch/isa_traits.hh"
+#include "arch/types.hh"
#include "config/full_system.hh"
#include "base/hashmap.hh"
#include "cpu/inst_seq.hh"
* Authors: Kevin Lim
*/
-#include "arch/isa_traits.hh"
+#include "arch/faults.hh"
#include "base/str.hh"
#include "cpu/ozone/lsq_unit.hh"
#include <algorithm>
#include "arch/faults.hh"
-#include "arch/isa_traits.hh"
+#include "arch/types.hh"
#include "config/full_system.hh"
#include "base/hashmap.hh"
#include "cpu/inst_seq.hh"
#include "config/use_checker.hh"
-#include "arch/isa_traits.hh"
+#include "arch/faults.hh"
#include "base/str.hh"
#include "cpu/ozone/lw_lsq.hh"
#include "cpu/checker/cpu.hh"
#ifndef __CPU_OZONE_NULL_PREDICTOR_HH__
#define __CPU_OZONE_NULL_PREDICTOR_HH__
-#include "arch/isa_traits.hh"
#include "cpu/inst_seq.hh"
+#include "sim/host.hh"
template <class Impl>
class NullPredictor
#ifndef __CPU_OZONE_OZONE_IMPL_HH__
#define __CPU_OZONE_OZONE_IMPL_HH__
-#include "arch/alpha/isa_traits.hh"
#include "cpu/o3/bpred_unit.hh"
#include "cpu/ozone/front_end.hh"
#include "cpu/ozone/inst_queue.hh"
#ifndef __CPU_OZONE_SIMPLE_IMPL_HH__
#define __CPU_OZONE_SIMPLE_IMPL_HH__
-#include "arch/isa_traits.hh"
#include "cpu/o3/bpred_unit.hh"
#include "cpu/ozone/cpu.hh"
#include "cpu/ozone/front_end.hh"
#define __CPU_OZONE_THREAD_STATE_HH__
#include "arch/faults.hh"
-#include "arch/isa_traits.hh"
+#include "arch/types.hh"
+#include "arch/regfile.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
#include "sim/process.hh"
#include "cpu/simple/atomic.hh"
#include "mem/packet_impl.hh"
#include "sim/builder.hh"
+#include "sim/system.hh"
using namespace std;
using namespace TheISA;
void
AtomicSimpleCPU::serialize(ostream &os)
{
- SERIALIZE_ENUM(_status);
- BaseSimpleCPU::serialize(os);
+ SimObject::State so_state = SimObject::getState();
+ SERIALIZE_ENUM(so_state);
nameOut(os, csprintf("%s.tickEvent", name()));
tickEvent.serialize(os);
+ BaseSimpleCPU::serialize(os);
}
void
AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
{
- UNSERIALIZE_ENUM(_status);
- BaseSimpleCPU::unserialize(cp, section);
+ SimObject::State so_state;
+ UNSERIALIZE_ENUM(so_state);
tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
+ BaseSimpleCPU::unserialize(cp, section);
+}
+
+void
+AtomicSimpleCPU::resume()
+{
+ assert(system->getMemoryMode() == System::Atomic);
+ changeState(SimObject::Running);
+ if (thread->status() == ThreadContext::Active) {
+ if (!tickEvent.scheduled())
+ tickEvent.schedule(curTick);
+ }
}
void
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
SimObjectParam<MemObject *> mem;
+ SimObjectParam<System *> system;
#if FULL_SYSTEM
SimObjectParam<AlphaITB *> itb;
SimObjectParam<AlphaDTB *> dtb;
- SimObjectParam<System *> system;
Param<int> cpu_id;
Param<Tick> profile;
#else
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
INIT_PARAM(mem, "memory"),
+ INIT_PARAM(system, "system object"),
#if FULL_SYSTEM
INIT_PARAM(itb, "Instruction TLB"),
INIT_PARAM(dtb, "Data TLB"),
- INIT_PARAM(system, "system object"),
INIT_PARAM(cpu_id, "processor ID"),
INIT_PARAM(profile, ""),
#else
params->width = width;
params->simulate_stalls = simulate_stalls;
params->mem = mem;
+ params->system = system;
#if FULL_SYSTEM
params->itb = itb;
params->dtb = dtb;
- params->system = system;
params->cpu_id = cpu_id;
params->profile = profile;
#else
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string §ion);
+ virtual void resume();
void switchOut();
void takeOverFrom(BaseCPU *oldCPU);
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Reinhardt
- * Korey Sewell
*/
#include "arch/utility.hh"
+#include "arch/faults.hh"
#include "base/cprintf.hh"
#include "base/inifile.hh"
#include "base/loader/symtab.hh"
#include "sim/sim_events.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
+#include "sim/system.hh"
#if FULL_SYSTEM
#include "base/remote_gdb.hh"
-#include "sim/system.hh"
#include "arch/tlb.hh"
#include "arch/stacktrace.hh"
#include "arch/vtophys.hh"
BaseSimpleCPU::serialize(ostream &os)
{
BaseCPU::serialize(os);
- SERIALIZE_SCALAR(inst);
- nameOut(os, csprintf("%s.xc", name()));
+// SERIALIZE_SCALAR(inst);
+ nameOut(os, csprintf("%s.xc.0", name()));
thread->serialize(os);
}
BaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
{
BaseCPU::unserialize(cp, section);
- UNSERIALIZE_SCALAR(inst);
- thread->unserialize(cp, csprintf("%s.xc", section));
+// UNSERIALIZE_SCALAR(inst);
+ thread->unserialize(cp, csprintf("%s.xc.0", section));
}
void
#else
thread->setNextPC(thread->readNextNPC());
thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
+ assert(thread->readNextPC() != thread->readNextNPC());
#endif
}
#include "cpu/simple/timing.hh"
#include "mem/packet_impl.hh"
#include "sim/builder.hh"
+#include "sim/system.hh"
using namespace std;
using namespace TheISA;
panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
}
+
+void
+TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t)
+{
+ pkt = _pkt;
+ Event::schedule(t);
+}
+
TimingSimpleCPU::TimingSimpleCPU(Params *p)
- : BaseSimpleCPU(p), icachePort(this), dcachePort(this)
+ : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
{
_status = Idle;
ifetch_pkt = dcache_pkt = NULL;
drainEvent = NULL;
fetchEvent = NULL;
- state = SimObject::Timing;
+ changeState(SimObject::Running);
}
void
TimingSimpleCPU::serialize(ostream &os)
{
- SERIALIZE_ENUM(_status);
+ SimObject::State so_state = SimObject::getState();
+ SERIALIZE_ENUM(so_state);
BaseSimpleCPU::serialize(os);
}
void
TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
{
- UNSERIALIZE_ENUM(_status);
+ SimObject::State so_state;
+ UNSERIALIZE_ENUM(so_state);
BaseSimpleCPU::unserialize(cp, section);
}
-bool
+unsigned int
TimingSimpleCPU::drain(Event *drain_event)
{
// TimingSimpleCPU is ready to drain if it's not waiting for
// an access to complete.
if (status() == Idle || status() == Running || status() == SwitchedOut) {
- changeState(SimObject::DrainedTiming);
- return true;
+ changeState(SimObject::Drained);
+ return 0;
} else {
changeState(SimObject::Draining);
drainEvent = drain_event;
- return false;
+ return 1;
}
}
if (_status != SwitchedOut && _status != Idle) {
// Delete the old event if it existed.
if (fetchEvent) {
- assert(!fetchEvent->scheduled());
+ if (fetchEvent->scheduled())
+ fetchEvent->deschedule();
+
delete fetchEvent;
}
new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
fetchEvent->schedule(curTick);
}
-}
-void
-TimingSimpleCPU::setMemoryMode(State new_mode)
-{
- assert(new_mode == SimObject::Timing);
+ assert(system->getMemoryMode() == System::Timing);
+ changeState(SimObject::Running);
}
void
}
}
+void
+TimingSimpleCPU::IcachePort::ITickEvent::process()
+{
+ cpu->completeIfetch(pkt);
+}
bool
TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
{
- cpu->completeIfetch(pkt);
+ // These next few lines could be replaced with something faster
+ // who knows what though
+ Tick time = pkt->req->getTime();
+ while (time < curTick)
+ time += lat;
+
+ if (time == curTick)
+ cpu->completeIfetch(pkt);
+ else
+ tickEvent.schedule(pkt, time);
+
return true;
}
TimingSimpleCPU::completeDrain()
{
DPRINTF(Config, "Done draining\n");
- changeState(SimObject::DrainedTiming);
+ changeState(SimObject::Drained);
drainEvent->process();
}
bool
TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
{
- cpu->completeDataAccess(pkt);
+ Tick time = pkt->req->getTime();
+ while (time < curTick)
+ time += lat;
+
+ if (time == curTick)
+ cpu->completeDataAccess(pkt);
+ else
+ tickEvent.schedule(pkt, time);
+
return true;
}
+void
+TimingSimpleCPU::DcachePort::DTickEvent::process()
+{
+ cpu->completeDataAccess(pkt);
+}
+
void
TimingSimpleCPU::DcachePort::recvRetry()
{
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
SimObjectParam<MemObject *> mem;
+ SimObjectParam<System *> system;
#if FULL_SYSTEM
SimObjectParam<AlphaITB *> itb;
SimObjectParam<AlphaDTB *> dtb;
- SimObjectParam<System *> system;
Param<int> cpu_id;
Param<Tick> profile;
#else
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
INIT_PARAM(mem, "memory"),
+ INIT_PARAM(system, "system object"),
#if FULL_SYSTEM
INIT_PARAM(itb, "Instruction TLB"),
INIT_PARAM(dtb, "Data TLB"),
- INIT_PARAM(system, "system object"),
INIT_PARAM(cpu_id, "processor ID"),
INIT_PARAM(profile, ""),
#else
params->functionTrace = function_trace;
params->functionTraceStart = function_trace_start;
params->mem = mem;
+ params->system = system;
#if FULL_SYSTEM
params->itb = itb;
params->dtb = dtb;
- params->system = system;
params->cpu_id = cpu_id;
params->profile = profile;
#else
{
protected:
TimingSimpleCPU *cpu;
+ Tick lat;
public:
- CpuPort(const std::string &_name, TimingSimpleCPU *_cpu)
- : Port(_name), cpu(_cpu)
+ CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
+ : Port(_name), cpu(_cpu), lat(_lat)
{ }
protected:
virtual void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop)
{ resp.clear(); snoop.clear(); }
+
+ struct TickEvent : public Event
+ {
+ Packet *pkt;
+ TimingSimpleCPU *cpu;
+
+ TickEvent(TimingSimpleCPU *_cpu)
+ :Event(&mainEventQueue), cpu(_cpu) {}
+ const char *description() { return "Timing CPU clock event"; }
+ void schedule(Packet *_pkt, Tick t);
+ };
+
};
class IcachePort : public CpuPort
{
public:
- IcachePort(TimingSimpleCPU *_cpu)
- : CpuPort(_cpu->name() + "-iport", _cpu)
+ IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
+ : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
{ }
protected:
virtual bool recvTiming(Packet *pkt);
virtual void recvRetry();
+
+ struct ITickEvent : public TickEvent
+ {
+
+ ITickEvent(TimingSimpleCPU *_cpu)
+ : TickEvent(_cpu) {}
+ void process();
+ const char *description() { return "Timing CPU clock event"; }
+ };
+
+ ITickEvent tickEvent;
+
};
class DcachePort : public CpuPort
{
public:
- DcachePort(TimingSimpleCPU *_cpu)
- : CpuPort(_cpu->name() + "-dport", _cpu)
+ DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
+ : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
{ }
protected:
virtual bool recvTiming(Packet *pkt);
virtual void recvRetry();
+
+ struct DTickEvent : public TickEvent
+ {
+ DTickEvent(TimingSimpleCPU *_cpu)
+ : TickEvent(_cpu) {}
+ void process();
+ const char *description() { return "Timing CPU clock event"; }
+ };
+
+ DTickEvent tickEvent;
+
};
IcachePort icachePort;
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string §ion);
- virtual bool drain(Event *drain_event);
+ virtual unsigned int drain(Event *drain_event);
virtual void resume();
- virtual void setMemoryMode(State new_mode);
void switchOut();
void takeOverFrom(BaseCPU *oldCPU);
#if !FULL_SYSTEM
funcExeInst = oldContext->readFuncExeInst();
#endif
+ inst = oldContext->getInst();
}
void
}
#endif
- void changeRegFileContext(RegFile::ContextParam param,
- RegFile::ContextVal val)
+ void changeRegFileContext(TheISA::RegContextParam param,
+ TheISA::RegContextVal val)
{
regs.changeContext(param, val);
}
#include <bitset>
#include <string>
+#include "arch/isa_traits.hh"
+#include "sim/faults.hh"
#include "base/bitfield.hh"
#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/refcnt.hh"
#include "cpu/op_class.hh"
#include "cpu/o3/dyn_inst.hh"
+#include "sim/faults.hh"
#include "sim/host.hh"
-#include "arch/isa_traits.hh"
// forward declarations
struct AlphaSimpleImpl;
bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
bool isCondCtrl() const { return flags[IsCondControl]; }
bool isUncondCtrl() const { return flags[IsUncondControl]; }
+ bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
bool isThreadSync() const { return flags[IsThreadSync]; }
bool isSerializing() const { return flags[IsSerializing] ||
#ifndef __CPU_THREAD_CONTEXT_HH__
#define __CPU_THREAD_CONTEXT_HH__
+#include "arch/types.hh"
+#include "arch/regfile.hh"
+#include "arch/syscallreturn.hh"
#include "config/full_system.hh"
#include "mem/request.hh"
#include "sim/faults.hh"
virtual int exit() { return 1; };
#endif
- virtual void changeRegFileContext(RegFile::ContextParam param,
- RegFile::ContextVal val) = 0;
+ virtual void changeRegFileContext(TheISA::RegContextParam param,
+ TheISA::RegContextVal val) = 0;
};
/**
Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
#endif
- void changeRegFileContext(RegFile::ContextParam param,
- RegFile::ContextVal val)
+ void changeRegFileContext(TheISA::RegContextParam param,
+ TheISA::RegContextVal val)
{
actualTC->changeRegFileContext(param, val);
}
#ifndef __CPU_THREAD_STATE_HH__
#define __CPU_THREAD_STATE_HH__
-#include "arch/isa_traits.hh"
+#include "arch/types.hh"
#include "cpu/thread_context.hh"
#if !FULL_SYSTEM
Param<uint32_t> pci_dev;
Param<uint32_t> pci_func;
Param<Tick> pio_latency;
+ Param<Tick> config_latency;
SimObjectVectorParam<IdeDisk *> disks;
END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
INIT_PARAM(pci_dev, "PCI device number"),
INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
+ INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
INIT_PARAM(disks, "IDE disks attached to this controller")
END_INIT_SIM_OBJECT_PARAMS(IdeController)
params->deviceNum = pci_dev;
params->functionNum = pci_func;
params->pio_delay = pio_latency;
+ params->config_delay = config_latency;
params->disks = disks;
return new IdeController(params);
}
panic("Inconsistent DMA transfer state: dmaState = %d devState = %d\n",
dmaState, devState);
- if (ctrl->dmaPending()) {
+ if (ctrl->dmaPending() || ctrl->getState() != SimObject::Running) {
dmaTransferEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
return;
} else
curPrd.getByteCount(), TheISA::PageBytes);
}
- if (ctrl->dmaPending()) {
- panic("shouldn't be reentant??");
+ if (ctrl->dmaPending() || ctrl->getState() != SimObject::Running) {
dmaReadWaitEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
return;
} else if (!dmaReadCG->done()) {
dmaWriteCG = new ChunkGenerator(curPrd.getBaseAddr(),
curPrd.getByteCount(), TheISA::PageBytes);
}
- if (ctrl->dmaPending()) {
- panic("shouldn't be reentant??");
+ if (ctrl->dmaPending() || ctrl->getState() != SimObject::Running) {
dmaWriteWaitEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
return;
} else if (!dmaWriteCG->done()) {
#include "base/trace.hh"
#include "dev/io_device.hh"
#include "sim/builder.hh"
+#include "sim/system.hh"
-PioPort::PioPort(PioDevice *dev, Platform *p, std::string pname)
- : Port(dev->name() + pname), device(dev), platform(p)
+PioPort::PioPort(PioDevice *dev, System *s, std::string pname)
+ : SimpleTimingPort(dev->name() + pname), device(dev), sys(s)
{ }
}
-void
-PioPort::recvRetry()
-{
- bool result = true;
- while (result && transmitList.size()) {
- result = Port::sendTiming(transmitList.front());
- if (result)
- transmitList.pop_front();
- }
-}
-
-void
-PioPort::SendEvent::process()
-{
- if (port->Port::sendTiming(packet))
- return;
-
- port->transmitList.push_back(packet);
-}
-
-void
-PioPort::resendNacked(Packet *pkt) {
- pkt->reinitNacked();
- if (transmitList.size()) {
- transmitList.push_front(pkt);
- } else {
- if (!Port::sendTiming(pkt))
- transmitList.push_front(pkt);
- }
-};
-
-
bool
PioPort::recvTiming(Packet *pkt)
{
pioPort->sendStatusChange(Port::RangeChange);
}
+
+unsigned int
+PioDevice::drain(Event *de)
+{
+ unsigned int count;
+ count = pioPort->drain(de);
+ if (count)
+ changeState(Draining);
+ else
+ changeState(Drained);
+ return count;
+}
+
void
BasicPioDevice::addressRanges(AddrRangeList &range_list)
{
}
-DmaPort::DmaPort(DmaDevice *dev, Platform *p)
- : Port(dev->name() + "-dmaport"), device(dev), platform(p), pendingCount(0)
+DmaPort::DmaPort(DmaDevice *dev, System *s)
+ : Port(dev->name() + "-dmaport"), device(dev), sys(s), pendingCount(0),
+ actionInProgress(0), drainEvent(NULL)
{ }
bool
}
delete pkt->req;
delete pkt;
+
+ if (pendingCount == 0 && drainEvent) {
+ drainEvent->process();
+ drainEvent = NULL;
+ }
} else {
panic("Got packet without sender state... huh?\n");
}
: PioDevice(p), dmaPort(NULL)
{ }
+
+unsigned int
+DmaDevice::drain(Event *de)
+{
+ unsigned int count;
+ count = pioPort->drain(de) + dmaPort->drain(de);
+ if (count)
+ changeState(Draining);
+ else
+ changeState(Drained);
+ return count;
+}
+
+unsigned int
+DmaPort::drain(Event *de)
+{
+ if (pendingCount == 0)
+ return 0;
+ drainEvent = de;
+ return 1;
+}
+
+
void
DmaPort::recvRetry()
{
{
assert(event);
+ assert(device->getState() == SimObject::Running);
+
DmaReqState *reqState = new DmaReqState(event, this, size);
for (ChunkGenerator gen(addr, size, peerBlockSize());
pendingCount++;
sendDma(pkt);
}
+
}
void
DmaPort::sendDma(Packet *pkt, bool front)
{
- // some kind of selction between access methods
- // more work is going to have to be done to make
- // switching actually work
- /* MemState state = device->platform->system->memState;
-
- if (state == Timing) { */
- DPRINTF(DMA, "Attempting to send Packet %#x with addr: %#x\n",
- pkt, pkt->getAddr());
- if (transmitList.size() || !sendTiming(pkt)) {
- if (front)
- transmitList.push_front(pkt);
- else
- transmitList.push_back(pkt);
- DPRINTF(DMA, "-- Failed: queued\n");
- } else {
- DPRINTF(DMA, "-- Done\n");
- }
- /* } else if (state == Atomic) {
- sendAtomic(pkt);
- if (pkt->senderState) {
- DmaReqState *state = dynamic_cast<DmaReqState*>(pkt->senderState);
- assert(state);
- state->completionEvent->schedule(curTick + (pkt->time -
- pkt->req->getTime()) +1);
- delete state;
- }
- pendingCount--;
- assert(pendingCount >= 0);
- delete pkt->req;
- delete pkt;
-
- } else if (state == Functional) {
- sendFunctional(pkt);
- // Is this correct???
- completionEvent->schedule(pkt->req->responseTime - pkt->req->requestTime);
- completionEvent == NULL;
+ // some kind of selction between access methods
+ // more work is going to have to be done to make
+ // switching actually work
+
+ System::MemoryMode state = sys->getMemoryMode();
+ if (state == System::Timing) {
+ DPRINTF(DMA, "Attempting to send Packet %#x with addr: %#x\n",
+ pkt, pkt->getAddr());
+ if (transmitList.size() || !sendTiming(pkt)) {
+ if (front)
+ transmitList.push_front(pkt);
+ else
+ transmitList.push_back(pkt);
+ DPRINTF(DMA, "-- Failed: queued\n");
+ } else {
+ DPRINTF(DMA, "-- Done\n");
+ }
+ } else if (state == System::Atomic) {
+ Tick lat;
+ lat = sendAtomic(pkt);
+ assert(pkt->senderState);
+ DmaReqState *state = dynamic_cast<DmaReqState*>(pkt->senderState);
+ assert(state);
+
+ state->numBytes += pkt->req->getSize();
+ if (state->totBytes == state->numBytes) {
+ state->completionEvent->schedule(curTick + lat);
+ delete state;
+ delete pkt->req;
+ }
+ pendingCount--;
+ assert(pendingCount >= 0);
+ delete pkt;
+
+ if (pendingCount == 0 && drainEvent) {
+ drainEvent->process();
+ drainEvent = NULL;
+ }
+
} else
panic("Unknown memory command state.");
- */
}
DmaDevice::~DmaDevice()
#include "mem/packet_impl.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
+#include "mem/tport.hh"
class Platform;
class PioDevice;
* sensitive to an address range use. The port takes all the memory
* access types and roles them into one read() and write() call that the device
* must respond to. The device must also provide the addressRanges() function
- * with which it returns the address ranges it is interested in. An extra
- * sendTiming() function is implemented which takes an delay. In this way the
- * device can immediatly call sendTiming(pkt, time) after processing a request
- * and the request will be handled by the port even if the port bus the device
- * connects to is blocked.
- */
-class PioPort : public Port
+ * with which it returns the address ranges it is interested in. */
+
+class PioPort : public SimpleTimingPort
{
protected:
/** The device that this port serves. */
PioDevice *device;
- /** The platform that device/port are in. This is used to select which mode
+ /** The system that device/port are in. This is used to select which mode
* we are currently operating in. */
- Platform *platform;
-
- /** A list of outgoing timing response packets that haven't been serviced
- * yet. */
- std::list<Packet*> transmitList;
+ System *sys;
/** The current status of the peer(bus) that we are connected to. */
Status peerStatus;
virtual void getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop);
- void resendNacked(Packet *pkt);
-
- /**
- * This class is used to implemented sendTiming() with a delay. When a delay
- * is requested a new event is created. When the event time expires it
- * attempts to send the packet. If it cannot, the packet is pushed onto the
- * transmit list to be sent when recvRetry() is called. */
- class SendEvent : public Event
- {
- PioPort *port;
- Packet *packet;
-
- SendEvent(PioPort *p, Packet *pkt, Tick t)
- : Event(&mainEventQueue), port(p), packet(pkt)
- { schedule(curTick + t); }
-
- virtual void process();
-
- virtual const char *description()
- { return "Future scheduled sendTiming event"; }
-
- friend class PioPort;
- };
-
- /** Schedule a sendTiming() event to be called in the future. */
- void sendTiming(Packet *pkt, Tick time)
- { new PioPort::SendEvent(this, pkt, time); }
-
- /** This function is notification that the device should attempt to send a
- * packet again. */
- virtual void recvRetry();
-
public:
- PioPort(PioDevice *dev, Platform *p, std::string pname = "-pioport");
+ PioPort(PioDevice *dev, System *s, std::string pname = "-pioport");
- friend class PioPort::SendEvent;
};
DmaDevice *device;
std::list<Packet*> transmitList;
- /** The platform that device/port are in. This is used to select which mode
+ /** The system that device/port are in. This is used to select which mode
* we are currently operating in. */
- Platform *platform;
+ System *sys;
/** Number of outstanding packets the dma port has. */
int pendingCount;
+ /** If a dmaAction is in progress. */
+ int actionInProgress;
+
+ /** If we need to drain, keep the drain event around until we're done
+ * here.*/
+ Event *drainEvent;
+
virtual bool recvTiming(Packet *pkt);
virtual Tick recvAtomic(Packet *pkt)
{ panic("dma port shouldn't be used for pio access."); }
void sendDma(Packet *pkt, bool front = false);
public:
- DmaPort(DmaDevice *dev, Platform *p);
+ DmaPort(DmaDevice *dev, System *s);
void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
uint8_t *data = NULL);
bool dmaPending() { return pendingCount > 0; }
+ unsigned int drain(Event *de);
};
/**
* transaction we should perform. */
Platform *platform;
+ System *sys;
+
/** The pioPort that handles the requests for us and provides us requests
* that it sees. */
PioPort *pioPort;
const Params *params() const { return _params; }
PioDevice(Params *p)
- : MemObject(p->name), platform(p->platform), pioPort(NULL),
- _params(p)
+ : MemObject(p->name), platform(p->platform), sys(p->system),
+ pioPort(NULL), _params(p)
{}
virtual ~PioDevice();
virtual void init();
+ virtual unsigned int drain(Event *de);
+
virtual Port *getPort(const std::string &if_name, int idx = -1)
{
if (if_name == "pio") {
if (pioPort != NULL)
panic("pio port already connected to.");
- pioPort = new PioPort(this, params()->platform);
+ pioPort = new PioPort(this, sys);
return pioPort;
} else
return NULL;
{}
/** return the address ranges that this device responds to.
- * @params range_list range list to populate with ranges
+ * @param range_list range list to populate with ranges
*/
void addressRanges(AddrRangeList &range_list);
bool dmaPending() { return dmaPort->dmaPending(); }
+ virtual unsigned int drain(Event *de);
+
virtual Port *getPort(const std::string &if_name, int idx = -1)
{
if (if_name == "pio") {
if (pioPort != NULL)
panic("pio port already connected to.");
- pioPort = new PioPort(this, params()->platform);
+ pioPort = new PioPort(this, sys);
return pioPort;
} else if (if_name == "dma") {
if (dmaPort != NULL)
panic("dma port already connected to.");
- dmaPort = new DmaPort(this, params()->platform);
+ dmaPort = new DmaPort(this, sys);
return dmaPort;
} else
return NULL;
/**
* This read always returns -1.
- * @param req The memory request.
+ * @param pkt The memory request.
* @param data Where to put the data.
*/
virtual Tick read(Packet *pkt);
/**
* All writes are simply ignored.
- * @param req The memory request.
+ * @param pkt The memory request.
* @param data the data to not write.
*/
virtual Tick write(Packet *pkt);
assert(rxDmaState == dmaIdle || rxDmaState == dmaReadWaiting);
rxDmaState = dmaReading;
- if (dmaPending())
+ if (dmaPending() || getState() != Running)
rxDmaState = dmaReadWaiting;
else
dmaRead(rxDmaAddr, rxDmaLen, &rxDmaReadEvent, (uint8_t*)rxDmaData);
assert(rxDmaState == dmaIdle || rxDmaState == dmaWriteWaiting);
rxDmaState = dmaWriting;
- if (dmaPending())
+ if (dmaPending() || getState() != Running)
rxDmaState = dmaWriteWaiting;
else
dmaWrite(rxDmaAddr, rxDmaLen, &rxDmaWriteEvent, (uint8_t*)rxDmaData);
assert(txDmaState == dmaIdle || txDmaState == dmaReadWaiting);
txDmaState = dmaReading;
- if (dmaPending())
+ if (dmaPending() || getState() != Running)
txDmaState = dmaReadWaiting;
else
dmaRead(txDmaAddr, txDmaLen, &txDmaReadEvent, (uint8_t*)txDmaData);
assert(txDmaState == dmaIdle || txDmaState == dmaWriteWaiting);
txDmaState = dmaWriting;
- if (dmaPending())
+ if (dmaPending() || getState() != Running)
txDmaState = dmaWriteWaiting;
else
dmaWrite(txDmaAddr, txDmaLen, &txDmaWriteEvent, (uint8_t*)txDmaData);
return true;
}
+
+void
+NSGigE::resume()
+{
+ SimObject::resume();
+
+ // During drain we could have left the state machines in a waiting state and
+ // they wouldn't get out until some other event occured to kick them.
+ // This way they'll get out immediately
+ txKick();
+ rxKick();
+}
+
+
//=====================================================================
//
//
Param<uint32_t> pci_dev;
Param<uint32_t> pci_func;
Param<Tick> pio_latency;
+ Param<Tick> config_latency;
Param<Tick> clock;
Param<bool> dma_desc_free;
INIT_PARAM(pci_dev, "PCI device number"),
INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
+ INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
INIT_PARAM(clock, "State machine cycle time"),
INIT_PARAM(dma_desc_free, "DMA of Descriptors is free"),
params->deviceNum = pci_dev;
params->functionNum = pci_func;
params->pio_delay = pio_latency;
+ params->config_delay = config_latency;
params->clock = clock;
params->dma_desc_free = dma_desc_free;
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string §ion);
+ virtual void resume();
+
public:
void regStats();
PciDev::PciConfigPort::PciConfigPort(PciDev *dev, int busid, int devid,
int funcid, Platform *p)
- : PioPort(dev,p,"-pciconf"), device(dev), busId(busid), deviceId(devid),
- functionId(funcid)
+ : PioPort(dev,p->system,"-pciconf"), device(dev), platform(p),
+ busId(busid), deviceId(devid), functionId(funcid)
{
configAddr = platform->calcConfigAddr(busId, deviceId, functionId);
}
PioDevice::init();
}
+unsigned int
+PciDev::drain(Event *de)
+{
+ unsigned int count;
+ count = pioPort->drain(de) + dmaPort->drain(de) + configPort->drain(de);
+ if (count)
+ changeState(Draining);
+ else
+ changeState(Drained);
+ return count;
+}
+
Tick
PciDev::readConfig(Packet *pkt)
{
virtual void getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop);
+ Platform *platform;
+
int busId;
int deviceId;
int functionId;
*/
virtual void unserialize(Checkpoint *cp, const std::string §ion);
+
+ virtual unsigned int drain(Event *de);
+
virtual Port *getPort(const std::string &if_name, int idx = -1)
{
if (if_name == "config") {
* Nathan Binkert
*/
+#include "base/misc.hh"
#include "dev/platform.hh"
#include "sim/builder.hh"
#include "sim/sim_exit.hh"
break;
case rxBeginCopy:
- if (dmaPending())
+ if (dmaPending() || getState() != Running)
goto exit;
rxDmaAddr = params()->platform->pciToDma(
break;
case txBeginCopy:
- if (dmaPending())
+ if (dmaPending() || getState() != Running)
goto exit;
txDmaAddr = params()->platform->pciToDma(
return true;
}
+void
+Device::resume()
+{
+ SimObject::resume();
+
+ // During drain we could have left the state machines in a waiting state and
+ // they wouldn't get out until some other event occured to kick them.
+ // This way they'll get out immediately
+ txKick();
+ rxKick();
+}
+
//=====================================================================
//
//
Param<uint32_t> pci_dev;
Param<uint32_t> pci_func;
Param<Tick> pio_latency;
+ Param<Tick> config_latency;
Param<Tick> intr_delay;
Param<Tick> clock;
INIT_PARAM(pci_dev, "PCI device number"),
INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
+ INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
INIT_PARAM(intr_delay, "Interrupt Delay"),
INIT_PARAM(clock, "State machine cycle time"),
params->deviceNum = pci_dev;
params->functionNum = pci_func;
params->pio_delay = pio_latency;
+ params->config_delay = config_latency;
params->intr_delay = intr_delay;
params->clock = clock;
public:
virtual Tick read(Packet *pkt);
virtual Tick write(Packet *pkt);
+ virtual void resume();
void prepareIO(int cpu, int index);
void prepareRead(int cpu, int index);
/**
* Constructor for the Tsunami Class.
* @param name name of the object
- * @param intrctrl pointer to the interrupt controller
+ * @param s system the object belongs to
+ * @param intctrl pointer to the interrupt controller
*/
Tsunami(const std::string &name, System *s, IntrControl *intctrl);
/**
* Serialize this object to the given output stream.
+ * @param base The base name of the counter object.
* @param os The stream to serialize to.
*/
void serialize(const std::string &base, std::ostream &os);
/**
* Reconstruct the state of this object from a checkpoint.
+ * @param base The base name of the counter object.
* @param cp The checkpoint use.
* @param section The section name of this object
*/
/**
* Serialize this object to the given output stream.
- * @param os The stream to serialize to.
+ * @param base The base name of the counter object.
+ * @param os The stream to serialize to.
*/
void serialize(const std::string &base, std::ostream &os);
/**
* Reconstruct the state of this object from a checkpoint.
+ * @param base The base name of the counter object.
* @param cp The checkpoint use.
* @param section The section name of this object
*/
/**
* Serialize this object to the given output stream.
+ * @param base The base name of the counter object.
* @param os The stream to serialize to.
*/
void serialize(const std::string &base, std::ostream &os);
/**
* Reconstruct the state of this object from a checkpoint.
+ * @param base The base name of the counter object.
* @param cp The checkpoint use.
* @param section The section name of this object
*/
--- /dev/null
+<hr size="1"><address style="align: right;"><small>
+Generated on $datetime for $projectname by <a href="http://www.doxygen.org/index.html"> doxygen</a> $doxygenversion</small></address>
+
+</body>
+</html>
--- /dev/null
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Erik Hallnor
+ * Nathan Binkert
+ */
+
+/**
+ * @file
+ * Dummy definitions of STL classes to pick up relationships in doxygen.
+ */
+
+namespace std {
+
+/** STL vector class*/
+template <class T> class vector {
+ public:
+ /** Dummy Item */
+ T item;
+};
+
+/** STL deque class */
+template <class T> class deque {
+ public:
+ /** Dummy Item */
+ T item;
+};
+
+/** STL list class */
+template <class T> class list {
+ public:
+ /** Dummy Item */
+ T item;
+};
+
+/** STL pair class */
+template <class X, class Y> class pair {
+ public:
+ /** Dummy Item */
+ X item1;
+ /** Dummy Item */
+ Y item2;
+};
+
+}
*/
/**
- * @file Definition of a simple bus bridge without buffering.
+ * @file
+ * Definition of a simple bus bridge without buffering.
*/
#include <algorithm>
*/
/**
- * @file Decleration of a simple bus bridge object with no buffering
+ * @file
+ * Declaration of a simple bus bridge object with no buffering
*/
#ifndef __MEM_BRIDGE_HH__
class Bridge : public MemObject
{
protected:
- /** Decleration of the buses port type, one will be instantiated for each
+ /** Declaration of the buses port type, one will be instantiated for each
of the interfaces connecting to the bus. */
class BridgePort : public Port
{
*/
/**
- * @file Definition of a bus object.
+ * @file
+ * Definition of a bus object.
*/
*/
/**
- * @file Decleration of a bus object.
+ * @file
+ * Declaration of a bus object.
*/
#ifndef __MEM_BUS_HH__
void addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id);
- /** Decleration of the buses port type, one will be instantiated for each
+ /** Declaration of the buses port type, one will be instantiated for each
of the interfaces connecting to the bus. */
class BusPort : public Port
{
/**
* Send a response to the slave interface.
- * @param req The request being responded to.
+ * @param pkt The request being responded to.
* @param time The time the response is ready.
*/
void respond(Packet *pkt, Tick time)
/**
* Send a reponse to the slave interface and calculate miss latency.
- * @param req The request to respond to.
+ * @param pkt The request to respond to.
* @param time The time the response is ready.
*/
void respondToMiss(Packet *pkt, Tick time)
/**
* Suppliess the data if cache to cache transfers are enabled.
- * @param req The bus transaction to fulfill.
+ * @param pkt The bus transaction to fulfill.
*/
void respondToSnoop(Packet *pkt)
{
/**
* Performs the access specified by the request.
- * @param req The request to perform.
+ * @param pkt The request to perform.
* @return The result of the access.
*/
bool access(Packet * &pkt);
/**
* Was the request was sent successfully?
- * @param req The request.
+ * @param pkt The request.
* @param success True if the request was sent successfully.
*/
virtual void sendResult(Packet * &pkt, bool success);
/**
* Handles a response (cache line fill/write ack) from the bus.
- * @param req The request being responded to.
+ * @param pkt The request being responded to.
*/
void handleResponse(Packet * &pkt);
/**
* Start handling a copy transaction.
- * @param req The copy request to perform.
+ * @param pkt The copy request to perform.
*/
void startCopy(Packet * &pkt);
/**
* Handle a delayed copy transaction.
- * @param req The delayed copy request to continue.
+ * @param pkt The delayed copy request to continue.
* @param addr The address being responded to.
* @param blk The block of the current response.
* @param mshr The mshr being handled.
/**
* Snoops bus transactions to maintain coherence.
- * @param req The current bus transaction.
+ * @param pkt The current bus transaction.
*/
void snoop(Packet * &pkt);
void invalidateBlk(Addr addr, int asid);
/**
- * Aquash all requests associated with specified thread.
+ * Squash all requests associated with specified thread.
* intended for use by I-cache.
- * @param req->getThreadNum()ber The thread to squash.
+ * @param threadNum The thread to squash.
*/
void squash(int threadNum)
{
* time of completion. This function can either update the hierarchy state
* or just perform the access wherever the data is found depending on the
* state of the update flag.
- * @param req The memory request to satisfy
+ * @param pkt The memory request to satisfy
* @param update If true, update the hierarchy, otherwise just perform the
* request.
* @return The estimated completion time.
* Snoop for the provided request in the cache and return the estimated
* time of completion.
* @todo Can a snoop probe not change state?
- * @param req The memory request to satisfy
+ * @param pkt The memory request to satisfy
* @param update If true, update the hierarchy, otherwise just perform the
* request.
* @return The estimated completion time.
#include "sim/root.hh" // for Tick
#include "arch/isa_traits.hh" // for Addr
+#include <iostream>
+
/**
* Cache block status bit assignments
*/
#include "sim/sim_events.hh" // for SimExitEvent
-using namespace std;
-
template<class TagStore, class Buffering, class Coherence>
bool
Cache<TagStore,Buffering,Coherence>::
MSHR* mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid());
// There can be many matching outstanding writes.
- vector<MSHR*> writes;
+ std::vector<MSHR*> writes;
missQueue->findWrites(blk_addr, pkt->req->getAsid(), writes);
if (!update) {
/**
* Return the proper state given the current state and the bus response.
- * @param req The bus response.
+ * @param pkt The bus response.
* @param oldState The current block state.
* @return The new state.
*/
/**
* Handle snooped bus requests.
* @param cache The cache that snooped the request.
- * @param req The snooped bus request.
+ * @param pkt The snooped bus request.
* @param blk The cache block corresponding to the request, if any.
* @param mshr The MSHR corresponding to the request, if any.
* @param new_state The new coherence state of the block.
/**
* Return the proper state given the current state and the bus response.
- * @param req The bus response.
+ * @param pkt The bus response.
* @param current The current block state.
* @return The new state.
*/
/**
* Handle snooped bus requests.
- * @param req The snooped bus request.
+ * @param pkt The snooped bus request.
* @param blk The cache block corresponding to the request, if any.
* @param mshr The MSHR corresponding to the request, if any.
* @param new_state Return the new state for the block.
/**
* Just return readable and writeable.
- * @param req The bus response.
+ * @param pkt The bus response.
* @param current The current block state.
* @return The new state.
*/
/**
* Handle snooped bus requests.
- * @param req The snooped bus request.
+ * @param pkt The snooped bus request.
* @param blk The cache block corresponding to the request, if any.
* @param mshr The MSHR corresponding to the request, if any.
* @param new_state The new coherence state of the block.
#include "sim/eventq.hh" // for Event declaration.
#include "mem/request.hh"
-using namespace TheISA;
-
/**
* @todo Move writebacks into shared BaseBuffer class.
*/
/**
* Handle a cache miss properly. Requests the bus and marks the cache as
* blocked.
- * @param req The request that missed in the cache.
+ * @param pkt The request that missed in the cache.
* @param blk_size The block size of the cache.
* @param time The time the miss is detected.
*/
}
/**
- * Selects a outstanding request to service.
- * @return The request to service, NULL if none found.
+ * Selects a outstanding pktuest to service.
+ * @return The pktuest to service, NULL if none found.
*/
Packet * getPacket();
/**
* Set the command to the given bus command.
- * @param req The request to update.
+ * @param pkt The request to update.
* @param cmd The bus command to use.
*/
void setBusCmd(Packet * &pkt, Packet::Command cmd);
/**
* Restore the original command in case of a bus transmission error.
- * @param req The request to reset.
+ * @param pkt The request to reset.
*/
void restoreOrigCmd(Packet * &pkt);
/**
- * Marks a request as in service (sent on the bus). This can have side
+ * Marks a pktuest as in service (sent on the bus). This can have side
* effect since storage for no response commands is deallocated once they
* are successfully sent.
- * @param req The request that was sent on the bus.
+ * @param pkt The request that was sent on the bus.
*/
void markInService(Packet * &pkt);
/**
- * Frees the resources of the request and unblock the cache.
- * @param req The request that has been satisfied.
- * @param time The time when the request is satisfied.
+ * Frees the resources of the pktuest and unblock the cache.
+ * @param pkt The request that has been satisfied.
+ * @param time The time when the pktuest is satisfied.
*/
void handleResponse(Packet * &pkt, Tick time);
/**
- * Removes all outstanding requests for a given thread number. If a request
+ * Removes all outstanding pktuests for a given thread number. If a request
* has been sent to the bus, this function removes all of its targets.
- * @param req->getThreadNum()ber The thread number of the requests to squash.
+ * @param threadNum The thread number of the requests to squash.
*/
void squash(int threadNum);
int size, uint8_t *data, bool compressed);
/**
- * Perform a writeback request.
- * @param req The writeback request.
+ * Perform a writeback pktuest.
+ * @param pkt The writeback request.
*/
void doWriteback(Packet * &pkt);
/**
- * Returns true if there are outstanding requests.
- * @return True if there are outstanding requests.
+ * Returns true if there are outstanding pktuests.
+ * @return True if there are outstanding pktuests.
*/
bool havePending()
{
/**
* Add a target to the given MSHR. This assumes it is in the miss queue.
* @param mshr The mshr to add a target to.
- * @param req The target to add.
+ * @param pkt The target to add.
*/
void addTarget(MSHR *mshr, Packet * &pkt)
{
/** The block size of the parent cache. */
int blkSize;
- /** Increasing order number assigned to each incoming request. */
+ /** Increasing order number assigned to each incoming pktuest. */
uint64_t order;
bool prefetchMiss;
/**
* Allocate a new MSHR to handle the provided miss.
- * @param req The miss to buffer.
+ * @param pkt The miss to buffer.
* @param size The number of bytes to fetch.
* @param time The time the miss occurs.
* @return A pointer to the new MSHR.
/**
* Allocate a new WriteBuffer to handle the provided write.
- * @param req The write to handle.
+ * @param pkt The write to handle.
* @param size The number of bytes to write.
* @param time The time the write occurs.
* @return A pointer to the new write buffer.
void setPrefetcher(BasePrefetcher *_prefetcher);
/**
- * Handle a cache miss properly. Either allocate an MSHR for the request,
+ * Handle a cache miss properly. Either allocate an MSHR for the pktuest,
* or forward it through the write buffer.
- * @param req The request that missed in the cache.
+ * @param pkt The request that missed in the cache.
* @param blk_size The block size of the cache.
* @param time The time the miss is detected.
*/
Packet * &target);
/**
- * Selects a outstanding request to service.
- * @return The request to service, NULL if none found.
+ * Selects a outstanding pktuest to service.
+ * @return The pktuest to service, NULL if none found.
*/
Packet * getPacket();
/**
* Set the command to the given bus command.
- * @param req The request to update.
+ * @param pkt The request to update.
* @param cmd The bus command to use.
*/
void setBusCmd(Packet * &pkt, Packet::Command cmd);
/**
* Restore the original command in case of a bus transmission error.
- * @param req The request to reset.
+ * @param pkt The request to reset.
*/
void restoreOrigCmd(Packet * &pkt);
/**
- * Marks a request as in service (sent on the bus). This can have side
+ * Marks a pktuest as in service (sent on the bus). This can have side
* effect since storage for no response commands is deallocated once they
* are successfully sent.
- * @param req The request that was sent on the bus.
+ * @param pkt The request that was sent on the bus.
*/
void markInService(Packet * &pkt);
/**
- * Collect statistics and free resources of a satisfied request.
- * @param req The request that has been satisfied.
- * @param time The time when the request is satisfied.
+ * Collect statistics and free resources of a satisfied pktuest.
+ * @param pkt The request that has been satisfied.
+ * @param time The time when the pktuest is satisfied.
*/
void handleResponse(Packet * &pkt, Tick time);
/**
- * Removes all outstanding requests for a given thread number. If a request
+ * Removes all outstanding pktuests for a given thread number. If a request
* has been sent to the bus, this function removes all of its targets.
- * @param req->getThreadNum()ber The thread number of the requests to squash.
+ * @param threadNum The thread number of the requests to squash.
*/
void squash(int threadNum);
int size, uint8_t *data, bool compressed);
/**
- * Perform the given writeback request.
- * @param req The writeback request.
+ * Perform the given writeback pktuest.
+ * @param pkt The writeback request.
*/
void doWriteback(Packet * &pkt);
/**
- * Returns true if there are outstanding requests.
- * @return True if there are outstanding requests.
+ * Returns true if there are outstanding pktuests.
+ * @return True if there are outstanding pktuests.
*/
bool havePending();
/**
* Add a target to the given MSHR. This assumes it is in the miss queue.
* @param mshr The mshr to add a target to.
- * @param req The target to add.
+ * @param pkt The target to add.
*/
void addTarget(MSHR *mshr, Packet * &pkt)
{
/**
* Miss Status and handling Register. This class keeps all the information
- * needed to handle a cache miss including a list of target requests.
+ * needed to handle a cache miss including a list of target pktuests.
*/
class MSHR {
public:
Addr addr;
/** Adress space id of the miss. */
short asid;
- /** True if the request has been sent to the bus. */
+ /** True if the pktuest has been sent to the bus. */
bool inService;
/** Thread number of the miss. */
int threadNum;
- /** The request that is forwarded to the next level of the hierarchy. */
+ /** The pktuest that is forwarded to the next level of the hierarchy. */
Packet * pkt;
/** The number of currently allocated targets. */
short ntargets;
- /** The original requesting command. */
+ /** The original pktuesting command. */
Packet::Command originalCmd;
/** Order number of assigned by the miss queue. */
uint64_t order;
Iterator allocIter;
private:
- /** List of all requests that match the address */
+ /** List of all pktuests that match the address */
TargetList targets;
public:
/**
* Allocate a miss to this MSHR.
- * @param cmd The requesting command.
+ * @param cmd The pktuesting command.
* @param addr The address of the miss.
* @param asid The address space id of the miss.
- * @param size The number of bytes to request.
- * @param req The original miss.
+ * @param size The number of bytes to pktuest.
+ * @param pkt The original miss.
*/
void allocate(Packet::Command cmd, Addr addr, int asid, int size,
Packet * &pkt);
/**
- * Allocate this MSHR as a buffer for the given request.
- * @param target The memory request to buffer.
+ * Allocate this MSHR as a buffer for the given pktuest.
+ * @param target The memory pktuest to buffer.
*/
void allocateAsBuffer(Packet * &target);
void deallocate();
/**
- * Add a request to the list of targets.
+ * Add a pktuest to the list of targets.
* @param target The target.
*/
void allocateTarget(Packet * &target);
#include "mem/cache/miss/mshr.hh"
/**
- * A Class for maintaining a list of pending and allocated memory requests.
+ * A Class for maintaining a list of pending and allocated memory pktuests.
*/
class MSHRQueue {
private:
// Parameters
/**
* The total number of MSHRs in this queue. This number is set as the
- * number of MSHRs requested plus (numReserve - 1). This allows for
+ * number of MSHRs pktuested plus (numReserve - 1). This allows for
* the same number of effective MSHRs while still maintaining the reserve.
*/
const int numMSHRs;
bool findMatches(Addr addr, int asid, std::vector<MSHR*>& matches) const;
/**
- * Find any pending requests that overlap the given request.
- * @param req The request to find.
+ * Find any pending pktuests that overlap the given request.
+ * @param pkt The request to find.
* @return A pointer to the earliest matching MSHR.
*/
MSHR* findPending(Packet * &pkt) const;
/**
- * Allocates a new MSHR for the request and size. This places the request
+ * Allocates a new MSHR for the pktuest and size. This places the request
* as the first target in the MSHR.
- * @param req The request to handle.
+ * @param pkt The request to handle.
* @param size The number in bytes to fetch from memory.
* @return The a pointer to the MSHR allocated.
*
MSHR* allocate(Packet * &pkt, int size = 0);
/**
- * Allocate a read request for the given address, and places the given
+ * Allocate a read pktuest for the given address, and places the given
* target on the target list.
* @param addr The address to fetch.
* @param asid The address space for the fetch.
- * @param size The number of bytes to request.
- * @param target The first target for the request.
+ * @param size The number of bytes to pktuest.
+ * @param target The first target for the pktuest.
* @return Pointer to the new MSHR.
*/
MSHR* allocateFetch(Addr addr, int asid, int size, Packet * &target);
* Allocate a target list for the given address.
* @param addr The address to fetch.
* @param asid The address space for the fetch.
- * @param size The number of bytes to request.
+ * @param size The number of bytes to pktuest.
* @return Pointer to the new MSHR.
*/
MSHR* allocateTargetList(Addr addr, int asid, int size);
* Allocates a target to the given MSHR. Used to keep track of the number
* of outstanding targets.
* @param mshr The MSHR to allocate the target to.
- * @param req The target request.
+ * @param pkt The target request.
*/
void allocateTarget(MSHR* mshr, Packet * &pkt)
{
void markInService(MSHR* mshr);
/**
- * Mark an in service mshr as pending, used to resend a request.
+ * Mark an in service mshr as pending, used to resend a pktuest.
* @param mshr The MSHR to resend.
* @param cmd The command to resend.
*/
void markPending(MSHR* mshr, Packet::Command cmd);
/**
- * Squash outstanding requests with the given thread number. If a request
+ * Squash outstanding pktuests with the given thread number. If a request
* is in service, just squashes the targets.
- * @param req->getThreadNum()ber The thread to squash.
+ * @param threadNum The thread to squash.
*/
void squash(int threadNum);
/**
* Returns true if the pending list is not empty.
- * @return True if there are outstanding requests.
+ * @return True if there are outstanding pktuests.
*/
bool havePending() const
{
}
/**
- * Returns the request at the head of the pendingList.
- * @return The next request to service.
+ * Returns the pktuest at the head of the pendingList.
+ * @return The next pktuest to service.
*/
Packet * getReq() const
{
* Describes a tagged prefetcher based on template policies.
*/
+#include "arch/isa_traits.hh"
#include "mem/cache/prefetch/tagged_prefetcher.hh"
template <class TagStore, class Buffering>
/**
* Find the block in the cache and update the replacement data. Returns
* the access latency and the in cache flags as a side effect
- * @param req The req whose block to find
+ * @param pkt The req whose block to find
* @param lat The latency of the access.
* @param inCache The FALRUBlk::inCache flags.
* @return Pointer to the cache block.
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
* @param source The block aligned source address.
* @param dest The block aligned destination adddress.
* @param asid The address space ID.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks)
{
/**
* Find the block and update the replacement data. This call also returns
* the access latency as a side effect.
- * @param req The req whose block to find
+ * @param pkt The req whose block to find
* @param lat The access latency.
* @return A pointer to the block found, if any.
*/
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
/**
* If a block is currently marked copy on write, copy it before writing.
- * @param req The write request.
- * @param writebacks List for any generated writeback requests.
+ * @param pkt The write request.
+ * @param writebacks List for any generated writeback pktuests.
*/
void fixCopy(Packet * &pkt, PacketList &writebacks);
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
- * @param req The request whose block to find.
+ * @param pkt The request whose block to find.
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
Addr blkMask;
- /** Number of NIC requests that hit in the NIC partition */
+ /** Number of NIC pktuests that hit in the NIC partition */
Stats::Scalar<> NR_NP_hits;
- /** Number of NIC requests that hit in the CPU partition */
+ /** Number of NIC pktuests that hit in the CPU partition */
Stats::Scalar<> NR_CP_hits;
- /** Number of CPU requests that hit in the NIC partition */
+ /** Number of CPU pktuests that hit in the NIC partition */
Stats::Scalar<> CR_NP_hits;
- /** Number of CPU requests that hit in the CPU partition */
+ /** Number of CPU pktuests that hit in the CPU partition */
Stats::Scalar<> CR_CP_hits;
/** The number of nic replacements (i.e. misses) */
Stats::Scalar<> nic_repl;
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
- * @param req The memory request whose block to find
+ * @param pkt The memory request whose block to find
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
bool isTouched;
/** Has this block been used after being brought in? (for LIFO partition) */
bool isUsed;
- /** is this blk a NIC block? (i.e. requested by the NIC) */
+ /** is this blk a NIC block? (i.e. pktuested by the NIC) */
bool isNIC;
/** timestamp of the arrival of this block into the cache */
Tick ts;
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
- * @param req The req whose block to find
+ * @param pkt The req whose block to find
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
- * @param req The req whose block to find.
+ * @param pkt The req whose block to find.
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
/**
* @file
- * Base Memory Object decleration.
+ * Base Memory Object declaration.
*/
#ifndef __MEM_MEM_OBJECT_HH__
#define __MEM_PACKET_HH__
#include "mem/request.hh"
-#include "arch/isa_traits.hh"
+#include "sim/host.hh"
#include "sim/root.hh"
#include <list>
}
Fault
-PageTable::page_check(Addr addr, int size) const
+PageTable::page_check(Addr addr, int64_t size) const
{
if (size < sizeof(uint64_t)) {
if (!isPowerOf2(size)) {
void
-PageTable::allocate(Addr vaddr, int size)
+PageTable::allocate(Addr vaddr, int64_t size)
{
// starting address must be page aligned
assert(pageOffset(vaddr) == 0);
#include <string>
+#include "sim/faults.hh"
#include "arch/isa_traits.hh"
#include "base/hashmap.hh"
#include "base/trace.hh"
class System;
/**
- * Page Table Decleration.
+ * Page Table Declaration.
*/
class PageTable
{
Addr pageAlign(Addr a) { return (a & ~offsetMask); }
Addr pageOffset(Addr a) { return (a & offsetMask); }
- Fault page_check(Addr addr, int size) const;
+ Fault page_check(Addr addr, int64_t size) const;
- void allocate(Addr vaddr, int size);
+ void allocate(Addr vaddr, int64_t size);
/**
* Translate function
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Ron Dreslinski
+ * Ali Saidi
*/
#include <sys/types.h>
using namespace std;
using namespace TheISA;
-PhysicalMemory::MemResponseEvent::MemResponseEvent(Packet *pkt, MemoryPort* _m)
- : Event(&mainEventQueue, CPU_Tick_Pri), pkt(pkt), memoryPort(_m)
-{
-
- this->setFlags(AutoDelete);
-}
-
-void
-PhysicalMemory::MemResponseEvent::process()
-{
- memoryPort->sendTiming(pkt);
-}
-
-const char *
-PhysicalMemory::MemResponseEvent::description()
-{
- return "Physical Memory Timing Access respnse event";
-}
PhysicalMemory::PhysicalMemory(const string &n, Tick latency)
: MemObject(n),base_addr(0), pmem_addr(NULL), port(NULL), lat(latency)
return 0;
}
-bool
-PhysicalMemory::doTimingAccess (Packet *pkt, MemoryPort* memoryPort)
-{
- doFunctionalAccess(pkt);
-
- // turn packet around to go back to requester
- pkt->makeTimingResponse();
- MemResponseEvent* response = new MemResponseEvent(pkt, memoryPort);
- response->schedule(curTick + lat);
-
- return true;
-}
Tick
-PhysicalMemory::doAtomicAccess(Packet *pkt)
-{
- doFunctionalAccess(pkt);
- return lat;
-}
-
-void
PhysicalMemory::doFunctionalAccess(Packet *pkt)
{
assert(pkt->getAddr() + pkt->getSize() < pmem_size);
}
pkt->result = Packet::Success;
+ return lat;
}
Port *
PhysicalMemory::MemoryPort::MemoryPort(const std::string &_name,
PhysicalMemory *_memory)
- : Port(_name), memory(_memory)
+ : SimpleTimingPort(_name), memory(_memory)
{ }
void
bool
PhysicalMemory::MemoryPort::recvTiming(Packet *pkt)
{
- return memory->doTimingAccess(pkt, this);
+ assert(pkt->result != Packet::Nacked);
+
+ Tick latency = memory->doFunctionalAccess(pkt);
+
+ pkt->makeTimingResponse();
+ sendTiming(pkt, latency);
+
+ return true;
}
Tick
PhysicalMemory::MemoryPort::recvAtomic(Packet *pkt)
{
- return memory->doAtomicAccess(pkt);
+ return memory->doFunctionalAccess(pkt);
}
void
memory->doFunctionalAccess(pkt);
}
-
+unsigned int
+PhysicalMemory::drain(Event *de)
+{
+ int count = port->drain(de);
+ if (count)
+ changeState(Draining);
+ else
+ changeState(Drained);
+ return count;
+}
void
PhysicalMemory::serialize(ostream &os)
#include "base/range.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
-#include "mem/port.hh"
+#include "mem/tport.hh"
#include "sim/eventq.hh"
#include <map>
#include <string>
//
class PhysicalMemory : public MemObject
{
- class MemoryPort : public Port
+ class MemoryPort : public SimpleTimingPort
{
PhysicalMemory *memory;
int numPorts;
- struct MemResponseEvent : public Event
- {
- Packet *pkt;
- MemoryPort *memoryPort;
-
- MemResponseEvent(Packet *pkt, MemoryPort *memoryPort);
- void process();
- const char *description();
- };
-
private:
// prevent copying of a MainMemory object
PhysicalMemory(const PhysicalMemory &specmem);
void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop);
virtual Port *getPort(const std::string &if_name, int idx = -1);
void virtual init();
+ unsigned int drain(Event *de);
- // fast back-door memory access for vtophys(), remote gdb, etc.
- // uint64_t phys_read_qword(Addr addr) const;
private:
- bool doTimingAccess(Packet *pkt, MemoryPort *memoryPort);
- Tick doAtomicAccess(Packet *pkt);
- void doFunctionalAccess(Packet *pkt);
+ Tick doFunctionalAccess(Packet *pkt);
void recvStatusChange(Port::Status status);
*/
/**
- * @file Port object definitions.
+ * @file
+ * Port object definitions.
*/
#include "base/chunk_generator.hh"
/**
* @file
- * Port Object Decleration. Ports are used to interface memory objects to
+ * Port Object Declaration. Ports are used to interface memory objects to
* each other. They will always come in pairs, and we refer to the other
* port object as the peer. These are used to make the design more
* modular so that a specific interface between every type of objcet doesn't
* Authors: Ali Saidi
*/
-#include "arch/isa_specific.hh"
-#include "arch/isa_traits.hh"
#include "mem/port.hh"
#include "sim/byteswap.hh"
void
FunctionalPort::writeHtoG(Addr addr, T d)
{
- d = TheISA::htog(d);
+ d = htog(d);
writeBlob(addr, (uint8_t*)&d, sizeof(T));
}
{
T d;
readBlob(addr, (uint8_t*)&d, sizeof(T));
- return TheISA::gtoh(d);
+ return gtoh(d);
}
*/
/**
- * @file Decleration of a request, the overall memory request consisting of
+ * @file
+ * Declaration of a request, the overall memory request consisting of
the parts of the request that are persistent throughout the transaction.
*/
#ifndef __MEM_REQUEST_HH__
#define __MEM_REQUEST_HH__
-#include "arch/isa_traits.hh"
+#include "sim/host.hh"
+#include "sim/root.hh"
class Request;
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#include "mem/tport.hh"
+
+void
+SimpleTimingPort::recvRetry()
+{
+ bool result = true;
+ while (result && transmitList.size()) {
+ result = Port::sendTiming(transmitList.front());
+ if (result)
+ transmitList.pop_front();
+ }
+ if (transmitList.size() == 0 && drainEvent) {
+ drainEvent->process();
+ drainEvent = NULL;
+ }
+}
+
+void
+SimpleTimingPort::SendEvent::process()
+{
+ port->outTiming--;
+ assert(port->outTiming >= 0);
+ if (port->Port::sendTiming(packet))
+ if (port->transmitList.size() == 0 && port->drainEvent) {
+ port->drainEvent->process();
+ port->drainEvent = NULL;
+ }
+ return;
+
+ port->transmitList.push_back(packet);
+}
+
+void
+SimpleTimingPort::resendNacked(Packet *pkt) {
+ pkt->reinitNacked();
+ if (transmitList.size()) {
+ transmitList.push_front(pkt);
+ } else {
+ if (!Port::sendTiming(pkt))
+ transmitList.push_front(pkt);
+ }
+};
+
+
+unsigned int
+SimpleTimingPort::drain(Event *de)
+{
+ if (outTiming == 0 && transmitList.size() == 0)
+ return 0;
+ drainEvent = de;
+ return 1;
+}
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/**
+ * @file
+ * Implement a port which adds simple support of a sendTiming() function that
+ * takes a delay. In this way the * device can immediatly call
+ * sendTiming(pkt, time) after processing a request and the request will be
+ * handled by the port even if the port bus the device connects to is blocked.
+ */
+
+/** recvTiming and drain should be implemented something like this when this
+ * class is used.
+
+bool
+PioPort::recvTiming(Packet *pkt)
+{
+ if (pkt->result == Packet::Nacked) {
+ resendNacked(pkt);
+ } else {
+ Tick latency = device->recvAtomic(pkt);
+ // turn packet around to go back to requester
+ pkt->makeTimingResponse();
+ sendTiming(pkt, latency);
+ }
+ return true;
+}
+
+PioDevice::drain(Event *de)
+{
+ unsigned int count;
+ count = SimpleTimingPort->drain(de);
+ if (count)
+ changeState(Draining);
+ else
+ changeState(Drained);
+ return count;
+}
+*/
+
+#ifndef __MEM_TPORT_HH__
+#define __MEM_TPORT_HH__
+
+#include "mem/port.hh"
+#include "sim/eventq.hh"
+#include <list>
+#include <string>
+
+class SimpleTimingPort : public Port
+{
+ protected:
+ /** A list of outgoing timing response packets that haven't been serviced
+ * yet. */
+ std::list<Packet*> transmitList;
+ /**
+ * This class is used to implemented sendTiming() with a delay. When a delay
+ * is requested a new event is created. When the event time expires it
+ * attempts to send the packet. If it cannot, the packet is pushed onto the
+ * transmit list to be sent when recvRetry() is called. */
+ class SendEvent : public Event
+ {
+ SimpleTimingPort *port;
+ Packet *packet;
+
+ SendEvent(SimpleTimingPort *p, Packet *pkt, Tick t)
+ : Event(&mainEventQueue), port(p), packet(pkt)
+ { setFlags(AutoDelete); schedule(curTick + t); }
+
+ virtual void process();
+
+ virtual const char *description()
+ { return "Future scheduled sendTiming event"; }
+
+ friend class SimpleTimingPort;
+ };
+
+
+ /** Number of timing requests that are emulating the device timing before
+ * attempting to end up on the bus.
+ */
+ int outTiming;
+
+ /** If we need to drain, keep the drain event around until we're done
+ * here.*/
+ Event *drainEvent;
+
+ /** Schedule a sendTiming() event to be called in the future. */
+ void sendTiming(Packet *pkt, Tick time)
+ { outTiming++; new SimpleTimingPort::SendEvent(this, pkt, time); }
+
+ /** This function is notification that the device should attempt to send a
+ * packet again. */
+ virtual void recvRetry();
+
+ void resendNacked(Packet *pkt);
+ public:
+
+ SimpleTimingPort(std::string pname)
+ : Port(pname), outTiming(0), drainEvent(NULL)
+ {}
+
+ unsigned int drain(Event *de);
+
+ friend class SimpleTimingPort::SendEvent;
+};
+
+#endif // __MEM_TPORT_HH__
*/
/**
- * @file Port object definitions.
+ * @file
+ * Port object definitions.
*/
#include "base/chunk_generator.hh"
/**
* @file
- * Virtual Port Object Decleration. These ports incorporate some translation
+ * Virtual Port Object Declaration. These ports incorporate some translation
* into their access methods. Thus you can use one to read and write data
* to/from virtual addresses.
*/
print >>sys.stderr, 'panic:', string
sys.exit(1)
+def makeList(objOrList):
+ if isinstance(objOrList, list):
+ return objOrList
+ return [objOrList]
+
# Prepend given directory to system module search path. We may not
# need this anymore if we can structure our config library more like a
# Python package.
count = 0
# ParamContexts don't serialize
if isinstance(self, SimObject) and not isinstance(self, ParamContext):
- if not self._ccObject.drain(drain_event):
- count = 1
+ count += self._ccObject.drain(drain_event)
if recursive:
for child in self._children.itervalues():
count += child.startDrain(drain_event, True)
child.resume()
def changeTiming(self, mode):
- if isinstance(self, SimObject) and not isinstance(self, ParamContext):
+ if isinstance(self, System):
self._ccObject.setMemoryMode(mode)
for child in self._children.itervalues():
child.changeTiming(mode)
result, done = self.find(obj)
if not done:
- raise AttributeError, "Can't resolve proxy '%s' from '%s'" % \
+ raise AttributeError, \
+ "Can't resolve proxy '%s' from '%s'" % \
(self.path(), base.path())
if isinstance(result, BaseProxy):
help="Set the output directory to DIR [Default: %default]")
add_option('-i', "--interactive", action="store_true", default=False,
help="Invoke the interactive interpreter after running the script")
+add_option("--pdb", action="store_true", default=False,
+ help="Invoke the python debugger before running the script")
add_option('-p', "--path", metavar="PATH[:PATH]", action='append', split=':',
help="Prepend PATH to the system path when invoking the script")
add_option('-q', "--quiet", action="count", default=0,
help="Print fetch sequence numbers in trace output")
bool_option("print-cpseq", default=False,
help="Print correct path sequence numbers in trace output")
+#bool_option("print-reg-delta", default=False,
+# help="Print which registers changed to what in trace output")
options = attrdict()
arguments = []
def usage(exitcode=None):
- print parser.help
+ parser.print_help()
if exitcode is not None:
sys.exit(exitcode)
print "M5 compiled %s" % cc_main.cvar.compileDate;
print "M5 started %s" % datetime.now().ctime()
print "M5 executing on %s" % socket.gethostname()
+ print "command line:",
+ for argv in sys.argv:
+ print argv,
+ print
# check to make sure we can find the listed script
if not arguments or not os.path.isfile(arguments[0]):
+ if arguments and not os.path.isfile(arguments[0]):
+ print "Script %s not found" % arguments[0]
usage(2)
# tell C++ about output directory
objects.ExecutionTrace.print_iregs = options.print_iregs
objects.ExecutionTrace.print_fetchseq = options.print_fetch_seq
objects.ExecutionTrace.print_cpseq = options.print_cpseq
+ #objects.ExecutionTrace.print_reg_delta = options.print_reg_delta
- scope = { '__file__' : sys.argv[0] }
sys.argv = arguments
sys.path = [ os.path.dirname(sys.argv[0]) ] + sys.path
- exec("import readline", scope)
- execfile(sys.argv[0], scope)
+
+ scope = { '__file__' : sys.argv[0] }
+
+ # we want readline if we're doing anything interactive
+ if options.interactive or options.pdb:
+ exec("import readline", scope)
+
+ # if pdb was requested, execfile the thing under pdb, otherwise,
+ # just do the execfile normally
+ if options.pdb:
+ from pdb import Pdb
+ debugger = Pdb()
+ debugger.run('execfile("%s")' % sys.argv[0], scope)
+ else:
+ execfile(sys.argv[0], scope)
# once the script is done
if options.interactive:
abstract = True
mem = Param.MemObject("memory")
+ system = Param.System(Parent.any, "system object")
if build_env['FULL_SYSTEM']:
dtb = Param.AlphaDTB("Data TLB")
itb = Param.AlphaITB("Instruction TLB")
- system = Param.System(Parent.any, "system object")
cpu_id = Param.Int(-1, "CPU identifier")
else:
workload = VectorParam.Process("processes to run")
type = 'BasicPioDevice'
abstract = True
pio_addr = Param.Addr("Device Address")
- pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
+ pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
class DmaDevice(PioDevice):
type = 'DmaDevice'
class CowDiskImage(DiskImage):
type = 'CowDiskImage'
- child = Param.DiskImage("child image")
+ child = Param.DiskImage(RawDiskImage(read_only=True),
+ "child image")
table_size = Param.Int(65536, "initial table size")
- image_file = ''
from m5 import build_env
from m5.config import *
from Device import DmaDevice
-from Pci import PciDevice
+from Pci import PciDevice, PciConfigData
class EtherInt(SimObject):
type = 'EtherInt'
clock = Param.Clock('0ns', "State machine processor frequency")
+ config_latency = Param.Latency('20ns', "Config read or write latency")
+
dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
rss = Param.Bool(False, "Receive Side Scaling")
+class NSGigEPciData(PciConfigData):
+ VendorID = 0x100B
+ DeviceID = 0x0022
+ Status = 0x0290
+ SubClassCode = 0x00
+ ClassCode = 0x02
+ ProgIF = 0x00
+ BAR0 = 0x00000001
+ BAR1 = 0x00000000
+ BAR2 = 0x00000000
+ BAR3 = 0x00000000
+ BAR4 = 0x00000000
+ BAR5 = 0x00000000
+ MaximumLatency = 0x34
+ MinimumGrant = 0xb0
+ InterruptLine = 0x1e
+ InterruptPin = 0x01
+ BAR0Size = '256B'
+ BAR1Size = '4kB'
+
class NSGigE(EtherDevBase):
type = 'NSGigE'
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
+ configdata = NSGigEPciData()
+
class NSGigEInt(EtherInt):
type = 'NSGigEInt'
device = Param.NSGigE("Ethernet device of this interface")
+class SinicPciData(PciConfigData):
+ VendorID = 0x1291
+ DeviceID = 0x1293
+ Status = 0x0290
+ SubClassCode = 0x00
+ ClassCode = 0x02
+ ProgIF = 0x00
+ BAR0 = 0x00000000
+ BAR1 = 0x00000000
+ BAR2 = 0x00000000
+ BAR3 = 0x00000000
+ BAR4 = 0x00000000
+ BAR5 = 0x00000000
+ MaximumLatency = 0x34
+ MinimumGrant = 0xb0
+ InterruptLine = 0x1e
+ InterruptPin = 0x01
+ BAR0Size = '64kB'
+
class Sinic(EtherDevBase):
type = 'Sinic'
delay_copy = Param.Bool(False, "Delayed copy transmit")
virtual_addr = Param.Bool(False, "Virtual addressing")
+ configdata = SinicPciData()
+
class SinicInt(EtherInt):
type = 'SinicInt'
device = Param.Sinic("Ethernet device of this interface")
from m5.config import *
-from Pci import PciDevice
+from Pci import PciDevice, PciConfigData
class IdeID(Enum): vals = ['master', 'slave']
+class IdeControllerPciData(PciConfigData):
+ VendorID = 0x8086
+ DeviceID = 0x7111
+ Command = 0x0
+ Status = 0x280
+ Revision = 0x0
+ ClassCode = 0x01
+ SubClassCode = 0x01
+ ProgIF = 0x85
+ BAR0 = 0x00000001
+ BAR1 = 0x00000001
+ BAR2 = 0x00000001
+ BAR3 = 0x00000001
+ BAR4 = 0x00000001
+ BAR5 = 0x00000001
+ InterruptLine = 0x1f
+ InterruptPin = 0x01
+ BAR0Size = '8B'
+ BAR1Size = '4B'
+ BAR2Size = '8B'
+ BAR3Size = '4B'
+ BAR4Size = '16B'
+
class IdeDisk(SimObject):
type = 'IdeDisk'
delay = Param.Latency('1us', "Fixed disk delay in microseconds")
class IdeController(PciDevice):
type = 'IdeController'
disks = VectorParam.IdeDisk("IDE disks attached to this controller")
+
+ config_latency = Param.Latency('20ns', "Config read or write latency")
+
+ configdata =IdeControllerPciData()
from m5 import build_env
from m5.config import *
from BaseCPU import BaseCPU
+from Checker import O3Checker
class DerivO3CPU(BaseCPU):
type = 'DerivO3CPU'
- activity = Param.Unsigned("Initial count")
- numThreads = Param.Unsigned("number of HW thread contexts")
-
- checker = Param.BaseCPU(NULL, "checker")
+ activity = Param.Unsigned(0, "Initial count")
+ numThreads = Param.Unsigned(1, "number of HW thread contexts")
+
+ if build_env['USE_CHECKER']:
+ if not build_env['FULL_SYSTEM']:
+ checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
+ exitOnError=True,
+ warnOnlyOnLoadError=False),
+ "checker")
+ else:
+ checker = Param.BaseCPU(O3Checker(exitOnError=True, warnOnlyOnLoadError=False), "checker")
+ checker.itb = Parent.itb
+ checker.dtb = Parent.dtb
cachePorts = Param.Unsigned("Cache Ports")
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
- decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
- renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
- iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
- "delay")
- commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
- fetchWidth = Param.Unsigned("Fetch width")
+ decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
+ renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")
+ iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch "
+ "delay")
+ commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay")
+ fetchWidth = Param.Unsigned(8, "Fetch width")
- renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
- iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
+ renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay")
+ iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode "
"delay")
- commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
- fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
- decodeWidth = Param.Unsigned("Decode width")
+ commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay")
+ fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay")
+ decodeWidth = Param.Unsigned(8, "Decode width")
- iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
+ iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename "
"delay")
- commitToRenameDelay = Param.Unsigned("Commit to rename delay")
- decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
- renameWidth = Param.Unsigned("Rename width")
+ commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay")
+ decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay")
+ renameWidth = Param.Unsigned(8, "Rename width")
- commitToIEWDelay = Param.Unsigned("Commit to "
+ commitToIEWDelay = Param.Unsigned(1, "Commit to "
"Issue/Execute/Writeback delay")
- renameToIEWDelay = Param.Unsigned("Rename to "
+ renameToIEWDelay = Param.Unsigned(2, "Rename to "
"Issue/Execute/Writeback delay")
- issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
+ issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal "
"to the IEW stage)")
- dispatchWidth = Param.Unsigned("Dispatch width")
- issueWidth = Param.Unsigned("Issue width")
- wbWidth = Param.Unsigned("Writeback width")
- wbDepth = Param.Unsigned("Writeback depth")
- fuPool = Param.FUPool(NULL, "Functional Unit pool")
+ dispatchWidth = Param.Unsigned(8, "Dispatch width")
+ issueWidth = Param.Unsigned(8, "Issue width")
+ wbWidth = Param.Unsigned(8, "Writeback width")
+ wbDepth = Param.Unsigned(1, "Writeback depth")
+ fuPool = Param.FUPool("Functional Unit pool")
- iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
+ iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit "
"delay")
- renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
- commitWidth = Param.Unsigned("Commit width")
- squashWidth = Param.Unsigned("Squash width")
- trapLatency = Param.Tick("Trap latency")
- fetchTrapLatency = Param.Tick("Fetch trap latency")
-
- backComSize = Param.Unsigned("Time buffer size for backwards communication")
- forwardComSize = Param.Unsigned("Time buffer size for forward communication")
-
- predType = Param.String("Branch predictor type ('local', 'tournament')")
- localPredictorSize = Param.Unsigned("Size of local predictor")
- localCtrBits = Param.Unsigned("Bits per counter")
- localHistoryTableSize = Param.Unsigned("Size of local history table")
- localHistoryBits = Param.Unsigned("Bits for the local history")
- globalPredictorSize = Param.Unsigned("Size of global predictor")
- globalCtrBits = Param.Unsigned("Bits per counter")
- globalHistoryBits = Param.Unsigned("Bits of history")
- choicePredictorSize = Param.Unsigned("Size of choice predictor")
- choiceCtrBits = Param.Unsigned("Bits of choice counters")
-
- BTBEntries = Param.Unsigned("Number of BTB entries")
- BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
-
- RASSize = Param.Unsigned("RAS size")
-
- LQEntries = Param.Unsigned("Number of load queue entries")
- SQEntries = Param.Unsigned("Number of store queue entries")
- LFSTSize = Param.Unsigned("Last fetched store table size")
- SSITSize = Param.Unsigned("Store set ID table size")
-
- numRobs = Param.Unsigned("Number of Reorder Buffers");
-
- numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
- numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
- "registers")
- numIQEntries = Param.Unsigned("Number of instruction queue entries")
- numROBEntries = Param.Unsigned("Number of reorder buffer entries")
-
- instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
+ renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay")
+ commitWidth = Param.Unsigned(8, "Commit width")
+ squashWidth = Param.Unsigned(8, "Squash width")
+ trapLatency = Param.Tick(13, "Trap latency")
+ fetchTrapLatency = Param.Tick(1, "Fetch trap latency")
+
+ backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
+ forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
+
+ predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')")
+ localPredictorSize = Param.Unsigned(2048, "Size of local predictor")
+ localCtrBits = Param.Unsigned(2, "Bits per counter")
+ localHistoryTableSize = Param.Unsigned(2048, "Size of local history table")
+ localHistoryBits = Param.Unsigned(11, "Bits for the local history")
+ globalPredictorSize = Param.Unsigned(8192, "Size of global predictor")
+ globalCtrBits = Param.Unsigned(2, "Bits per counter")
+ globalHistoryBits = Param.Unsigned(4096, "Bits of history")
+ choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor")
+ choiceCtrBits = Param.Unsigned(2, "Bits of choice counters")
+
+ BTBEntries = Param.Unsigned(4096, "Number of BTB entries")
+ BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits")
+
+ RASSize = Param.Unsigned(16, "RAS size")
+
+ LQEntries = Param.Unsigned(32, "Number of load queue entries")
+ SQEntries = Param.Unsigned(32, "Number of store queue entries")
+ LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
+ SSITSize = Param.Unsigned(1024, "Store set ID table size")
+
+ numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
+
+ numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
+ numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
+ "registers")
+ numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
+ numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
+
+ instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by")
function_trace = Param.Bool(False, "Enable function trace")
function_trace_start = Param.Tick(0, "Cycle to start function trace")
pci_bus = Param.Int("PCI bus")
pci_dev = Param.Int("PCI device number")
pci_func = Param.Int("PCI function code")
- pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
+ pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
configdata = Param.PciConfigData(Parent.any, "PCI Config data")
class PciFake(PciDevice):
class Root(SimObject):
type = 'Root'
- clock = Param.RootClock('200MHz', "tick frequency")
+ clock = Param.RootClock('1THz', "tick frequency")
max_tick = Param.Tick('0', "maximum simulation ticks (0 = infinite)")
progress_interval = Param.Tick('0',
"print a progress message every n ticks (0 = never)")
from m5 import build_env
from m5.config import *
+class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
+
class System(SimObject):
type = 'System'
physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
+ mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
if build_env['FULL_SYSTEM']:
boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
"boot processor frequency")
from m5.config import *
from Device import BasicPioDevice
from Platform import Platform
-
-class Tsunami(Platform):
- type = 'Tsunami'
-# pciconfig = Param.PciConfigAll("PCI configuration")
- system = Param.System(Parent.any, "system")
+from AlphaConsole import AlphaConsole
+from Uart import Uart8250
+from Pci import PciConfigAll
+from BadDevice import BadDevice
class TsunamiCChip(BasicPioDevice):
type = 'TsunamiCChip'
class TsunamiPChip(BasicPioDevice):
type = 'TsunamiPChip'
tsunami = Param.Tsunami(Parent.any, "Tsunami")
+
+class Tsunami(Platform):
+ type = 'Tsunami'
+ system = Param.System(Parent.any, "system")
+
+ cchip = TsunamiCChip(pio_addr=0x801a0000000)
+ pchip = TsunamiPChip(pio_addr=0x80180000000)
+ pciconfig = PciConfigAll()
+ fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
+
+ fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
+ fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
+ fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
+ fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
+
+ fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
+
+ fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
+
+ fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
+ fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
+ fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
+ fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
+ fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
+ fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
+ fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
+ fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
+ fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
+ fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
+
+ fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
+ fake_ata1 = IsaFake(pio_addr=0x801fc000170)
+
+ fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
+ io = TsunamiIO(pio_addr=0x801fc000000)
+ uart = Uart8250(pio_addr=0x801fc0003f8)
+ console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
+
+ # Attach I/O devices to specified bus object. Can't do this
+ # earlier, since the bus object itself is typically defined at the
+ # System level.
+ def attachIO(self, bus):
+ self.cchip.pio = bus.port
+ self.pchip.pio = bus.port
+ self.pciconfig.pio = bus.default
+ self.fake_sm_chip.pio = bus.port
+ self.fake_uart1.pio = bus.port
+ self.fake_uart2.pio = bus.port
+ self.fake_uart3.pio = bus.port
+ self.fake_uart4.pio = bus.port
+ self.fake_ppc.pio = bus.port
+ self.fake_OROM.pio = bus.port
+ self.fake_pnp_addr.pio = bus.port
+ self.fake_pnp_write.pio = bus.port
+ self.fake_pnp_read0.pio = bus.port
+ self.fake_pnp_read1.pio = bus.port
+ self.fake_pnp_read2.pio = bus.port
+ self.fake_pnp_read3.pio = bus.port
+ self.fake_pnp_read4.pio = bus.port
+ self.fake_pnp_read5.pio = bus.port
+ self.fake_pnp_read6.pio = bus.port
+ self.fake_pnp_read7.pio = bus.port
+ self.fake_ata0.pio = bus.port
+ self.fake_ata1.pio = bus.port
+ self.fb.pio = bus.port
+ self.io.pio = bus.port
+ self.uart.pio = bus.port
+ self.console.pio = bus.port
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Ali Saidi
+ * Authors: Gabe Black
+ * Ali Saidi
* Nathan Binkert
*/
configStream = simout.find("config.out");
// The configuration database is now complete; start processing it.
- inifile.load("config.ini");
+ inifile.load(simout.resolve("config.ini"));
// Initialize statistics database
Stats::InitSimStats();
class ThreadContext;
-//We need the "Tick" data type from here
+//We need the "Tick" and "Addr" data types from here
#include "sim/host.hh"
-//We need the "Addr" data type from here
-#include "arch/isa_traits.hh"
namespace AlphaPseudo
{
doRecordEvent = !Stats::event_ignore.match(name());
simObjectList.push_back(this);
- state = Atomic;
+ state = Running;
}
//
doRecordEvent = !Stats::event_ignore.match(name());
simObjectList.push_back(this);
- state = Atomic;
+ state = Running;
}
void
Stats::recordEvent(stat);
}
-bool
+unsigned int
SimObject::drain(Event *drain_event)
{
- if (state != DrainedAtomic && state != Atomic) {
- panic("Must implement your own drain function if it is to be used "
- "in timing mode!");
- }
- state = DrainedAtomic;
- return true;
+ state = Drained;
+ return 0;
}
void
SimObject::resume()
{
- if (state == DrainedAtomic) {
- state = Atomic;
- } else if (state == DrainedTiming) {
- state = Timing;
- }
+ state = Running;
}
void
SimObject::setMemoryMode(State new_mode)
{
- assert(new_mode == Timing || new_mode == Atomic);
- if (state == DrainedAtomic && new_mode == Timing) {
- state = DrainedTiming;
- } else if (state == DrainedTiming && new_mode == Atomic) {
- state = DrainedAtomic;
- } else {
- state = new_mode;
- }
+ panic("setMemoryMode() should only be called on systems");
}
void
};
enum State {
- Atomic,
- Timing,
+ Running,
Draining,
- DrainedAtomic,
- DrainedTiming
+ Drained
};
+ private:
+ State state;
protected:
Params *_params;
- State state;
void changeState(State new_state) { state = new_state; }
// Methods to drain objects in order to take checkpoints
// Or switch from timing -> atomic memory model
- // Drain returns false if the SimObject cannot drain immediately.
- virtual bool drain(Event *drain_event);
+ // Drain returns 0 if the simobject can drain immediately or
+ // the number of times the drain_event's process function will be called
+ // before the object will be done draining. Normally this should be 1
+ virtual unsigned int drain(Event *drain_event);
virtual void resume();
virtual void setMemoryMode(State new_mode);
virtual void switchOut();
#else
page_ptr(0),
#endif
- _params(p)
+ memoryMode(p->mem_mode), _params(p)
{
// add self to global system list
systemList.push_back(this);
#endif // FULL_SYSTEM
+
+void
+System::setMemoryMode(MemoryMode mode)
+{
+ assert(getState() == Drained);
+ memoryMode = mode;
+}
+
int
System::registerThreadContext(ThreadContext *tc, int id)
{
System::printSystems();
}
+const char *System::MemoryModeStrings[3] = {"invalid", "atomic",
+ "timing"};
+
#if FULL_SYSTEM
// In full system mode, only derived classes (e.g. AlphaLinuxSystem)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(System)
SimObjectParam<PhysicalMemory *> physmem;
+ SimpleEnumParam<System::MemoryMode> mem_mode;
END_DECLARE_SIM_OBJECT_PARAMS(System)
BEGIN_INIT_SIM_OBJECT_PARAMS(System)
- INIT_PARAM(physmem, "physical memory")
+ INIT_PARAM(physmem, "physical memory"),
+ INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
+ System::MemoryModeStrings)
END_INIT_SIM_OBJECT_PARAMS(System)
System::Params *p = new System::Params;
p->name = getInstanceName();
p->physmem = physmem;
+ p->mem_mode = mem_mode;
return new System(p);
}
#include "base/loader/symtab.hh"
#include "base/misc.hh"
#include "base/statistics.hh"
+#include "config/full_system.hh"
#include "cpu/pc_event.hh"
#include "mem/port.hh"
#include "sim/sim_object.hh"
class System : public SimObject
{
public:
+ enum MemoryMode {
+ Invalid=0,
+ Atomic,
+ Timing
+ };
+
+ static const char *MemoryModeStrings[3];
+
+
+ MemoryMode getMemoryMode() { assert(memoryMode); return memoryMode; }
+
+ /** Change the memory mode of the system. This should only be called by the
+ * python!!
+ * @param mode Mode to change to (atomic/timing)
+ */
+ void setMemoryMode(MemoryMode mode);
+
PhysicalMemory *physmem;
PCEventQueue pcEventQueue;
protected:
+ MemoryMode memoryMode;
+
#if FULL_SYSTEM
/**
* Fix up an address used to match PCs for hooking simulator
{
std::string name;
PhysicalMemory *physmem;
+ MemoryMode mem_mode;
#if FULL_SYSTEM
Tick boot_cpu_frequency;
--- /dev/null
+# -*- mode:python -*-
+
+# Copyright (c) 2004-2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+# Kevin Lim
+
+import os
+import sys
+import glob
+from SCons.Script.SConscript import SConsEnvironment
+
+Import('env')
+
+env['DIFFOUT'] = File('diff-out')
+
+# Dict that accumulates lists of tests by category (quick, medium, long)
+env.Tests = {}
+
+def contents(node):
+ return file(str(node)).read()
+
+def check_test(target, source, env):
+ """Check output from running test.
+
+ Targets are as follows:
+ target[0] : outdiff
+ target[1] : statsdiff
+ target[2] : status
+
+ """
+ # make sure target files are all gone
+ for t in target:
+ if os.path.exists(t.abspath):
+ Execute(Delete(t.abspath))
+ # Run diff on output & ref directories to find differences.
+ # Exclude m5stats.txt since we will use diff-out on that.
+ Execute(env.subst('diff -ubr ${SOURCES[0].dir} ${SOURCES[1].dir} ' +
+ '-I "^command line:" ' + # for stdout file
+ '-I "^M5 compiled on" ' + # for stderr file
+ '-I "^M5 simulation started" ' + # for stderr file
+ '-I "^Simulation complete at" ' + # for stderr file
+ '-I "^Listening for" ' + # for stderr file
+ '--exclude=m5stats.txt --exclude=SCCS ' +
+ '--exclude=${TARGETS[0].file} ' +
+ '> ${TARGETS[0]}', target=target, source=source), None)
+ print "===== Output differences ====="
+ print contents(target[0])
+ # Run diff-out on m5stats.txt file
+ status = Execute(env.subst('$DIFFOUT $SOURCES > ${TARGETS[1]}',
+ target=target, source=source),
+ strfunction=None)
+ print "===== Statistics differences ====="
+ print contents(target[1])
+ # Generate status file contents based on exit status of diff-out
+ if status == 0:
+ status_str = "passed."
+ else:
+ status_str = "FAILED!"
+ f = file(str(target[2]), 'w')
+ print >>f, env.subst('${TARGETS[2].dir}', target=target, source=source), \
+ status_str
+ f.close()
+ # done
+ return 0
+
+def check_test_string(target, source, env):
+ return env.subst("Comparing outputs in ${TARGETS[0].dir}.",
+ target=target, source=source)
+
+testAction = env.Action(check_test, check_test_string)
+
+def print_test(target, source, env):
+ print '***** ' + contents(source[0])
+ return 0
+
+printAction = env.Action(print_test, strfunction = None)
+
+def update_test(target, source, env):
+ """Update reference test outputs.
+
+ Target is phony. First two sources are the ref & new m5stats.txt
+ files, respectively. We actually copy everything in the
+ respective directories except the status & diff output files.
+
+ """
+ dest_dir = str(source[0].get_dir())
+ src_dir = str(source[1].get_dir())
+ dest_files = os.listdir(dest_dir)
+ src_files = os.listdir(src_dir)
+ # Exclude status & diff outputs
+ for f in ('outdiff', 'statsdiff', 'status'):
+ if f in src_files:
+ src_files.remove(f)
+ for f in src_files:
+ if f in dest_files:
+ print " Replacing file", f
+ dest_files.remove(f)
+ else:
+ print " Creating new file", f
+ copyAction = Copy(os.path.join(dest_dir, f), os.path.join(src_dir, f))
+ copyAction.strfunction = None
+ Execute(copyAction)
+ # warn about any files in dest not overwritten (other than SCCS dir)
+ if 'SCCS' in dest_files:
+ dest_files.remove('SCCS')
+ if dest_files:
+ print "Warning: file(s) in", dest_dir, "not updated:",
+ print ', '.join(dest_files)
+ return 0
+
+def update_test_string(target, source, env):
+ return env.subst("Updating ${SOURCES[0].dir} from ${SOURCES[1].dir}",
+ target=target, source=source)
+
+updateAction = env.Action(update_test, update_test_string)
+
+def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref',
+ timeout=15):
+ """Define a test.
+
+ Args:
+ category -- string describing test category (e.g., 'quick')
+ cpu_list -- list of CPUs to runs this test on (blank means all compiled CPUs)
+ os_list -- list of OSs to run this test on
+ refdir -- subdirectory containing reference output (default 'ref')
+ timeout -- test timeout in minutes (only enforced on pool)
+
+ """
+
+ default_refdir = False
+ if refdir == 'ref':
+ default_refdir = True
+ valid_cpu_list = []
+ if len(cpu_list) == 0:
+ valid_cpu_list = env['CPU_MODELS']
+ else:
+ for i in cpu_list:
+ if i in env['CPU_MODELS']:
+ valid_cpu_list.append(i)
+ cpu_list = valid_cpu_list
+ if env['TEST_CPU_MODELS']:
+ valid_cpu_list = []
+ for i in env['TEST_CPU_MODELS']:
+ if i in cpu_list:
+ valid_cpu_list.append(i)
+ cpu_list = valid_cpu_list
+# Code commented out that shows the general structure if we want to test
+# different OS's as well.
+# if len(os_list) == 0:
+# for test_cpu in cpu_list:
+# build_cpu_test(env, category, '', test_cpu, refdir, timeout)
+# else:
+# for test_os in os_list:
+# for test_cpu in cpu_list:
+# build_cpu_test(env, category, test_os, test_cpu, refdir,
+# timeout)
+ # Loop through CPU models and generate proper options, ref directories
+ for cpu in cpu_list:
+ test_os = ''
+ if cpu == "AtomicSimpleCPU":
+ cpu_option = ('','atomic/')
+ elif cpu == "TimingSimpleCPU":
+ cpu_option = ('--timing','timing/')
+ elif cpu == "O3CPU":
+ cpu_option = ('--detailed','detailed/')
+ else:
+ raise TypeError, "Unknown CPU model specified"
+
+ if default_refdir:
+ # Reference stats located in ref/arch/os/cpu or ref/arch/cpu
+ # if no OS specified
+ test_refdir = os.path.join(refdir, env['TARGET_ISA'])
+ if test_os != '':
+ test_refdir = os.path.join(test_refdir, test_os)
+ cpu_refdir = os.path.join(test_refdir, cpu_option[1])
+
+ ref_stats = os.path.join(cpu_refdir, 'm5stats.txt')
+
+ # base command for running test
+ base_cmd = '${SOURCES[0]} -d $TARGET.dir ${SOURCES[1]}'
+ base_cmd = base_cmd + ' ' + cpu_option[0]
+ # stdout and stderr files
+ cmd_stdout = '${TARGETS[0]}'
+ cmd_stderr = '${TARGETS[1]}'
+
+ stdout_string = cpu_option[1] + 'stdout'
+ stderr_string = cpu_option[1] + 'stderr'
+ m5stats_string = cpu_option[1] + 'm5stats.txt'
+ outdiff_string = cpu_option[1] + 'outdiff'
+ statsdiff_string = cpu_option[1] + 'statsdiff'
+ status_string = cpu_option[1] + 'status'
+
+ # Prefix test run with batch job submission command if appropriate.
+ # Output redirection is also different for batch runs.
+ # Batch command also supports timeout arg (in seconds, not minutes).
+ if env['BATCH']:
+ cmd = [env['BATCH_CMD'], '-t', str(timeout * 60),
+ '-o', cmd_stdout, '-e', cmd_stderr, base_cmd]
+ else:
+ cmd = [base_cmd, '>', cmd_stdout, '2>', cmd_stderr]
+
+ env.Command([stdout_string, stderr_string, m5stats_string],
+ [env.M5Binary, 'run.py'], ' '.join(cmd))
+
+ # order of targets is important... see check_test
+ env.Command([outdiff_string, statsdiff_string, status_string],
+ [ref_stats, m5stats_string],
+ testAction)
+
+ # phony target to echo status
+ if env['update_ref']:
+ p = env.Command(cpu_option[1] + '_update',
+ [ref_stats, m5stats_string, status_string],
+ updateAction)
+ else:
+ p = env.Command(cpu_option[1] + '_print', [status_string],
+ printAction)
+ env.AlwaysBuild(p)
+
+ env.Tests.setdefault(category, [])
+ env.Tests[category] += p
+
+# Make test_builder a "wrapper" function. See SCons wiki page at
+# http://www.scons.org/cgi-bin/wiki/WrapperFunctions.
+SConsEnvironment.Test = test_builder
+
+cwd = os.getcwd()
+os.chdir(str(Dir('.').srcdir))
+scripts = glob.glob('*/SConscript')
+os.chdir(cwd)
+
+for s in scripts:
+ SConscript(s, exports = 'env', duplicate = False)
+
+# Set up phony commands for various test categories
+allTests = []
+for (key, val) in env.Tests.iteritems():
+ env.Command(key, val, env.NoAction)
+ allTests += val
+
+# The 'all' target is redundant since just specifying the test
+# directory name (e.g., ALPHA_SE/test/opt) has the same effect.
+env.Command('all', allTests, env.NoAction)
--- /dev/null
+#!/usr/bin/perl
+# Copyright (c) 2001-2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+#
+# This script diffs two SimpleScalar statistics output files.
+#
+
+use Getopt::Std;
+
+#
+# -t thresh sets threshold for ignoring differences (in %)
+# -p sorts differences by % chg (default is alphabetic)
+# -f ignores fetch-loss statistics
+# -d ignores all distributions
+#
+
+getopts('dfn:pt:h');
+
+if ($#ARGV < 1)
+{
+ print "\nError: need two file arguments (<reference> <new>).\n";
+ print " Options: -d = Ignore distributions\n";
+ print " -f = Ignore fetch-loss stats\n";
+ print " -p = Sort errors by percentage\n";
+ print " -h = Diff header info separately from stats\n";
+ print " -n <num> = Print top <num> errors (default 20)\n";
+ print " -t <num> = Error threshold in percent (default 1)\n\n";
+ die -1;
+}
+
+open(REF, "<$ARGV[0]") or die "Error: can't open $ARGV[0].\n";
+open(NEW, "<$ARGV[1]") or die "Error: can't open $ARGV[1].\n";
+
+
+#
+# Things that really should be adjustable via the command line
+#
+
+# Ignorable error (in percent)
+$err_thresh = ($opt_t) ? $opt_t : 0;
+
+# Number of stats to print before omitting
+$omit_count = ($opt_n) ? $opt_n : 20;
+
+
+#
+# First copy everything up to the simulation statistics to a pair of
+# temporary files, stripping out date-related items, and do a plain
+# diff. Any differences in the arguments are not necessarily an issue;
+# any differences in the program output should be caught by the EIO
+# mechanism if an EIO file is used.
+#
+
+# copy_header takes input filehandle and output filename
+
+sub copy_header
+{
+ my ($inhandle, $outname) = @_;
+
+ open(OUTPUT, ">$outname") or die "Error: can't open $outname.\n";
+
+ while (<$inhandle>)
+ {
+ # strip out lines that can vary
+ next if /^(command line:|M5 compiled on |M5 simulation started |M5 executing on )/;
+ last if /Begin Simulation Statistics/;
+ print OUTPUT;
+ }
+ close OUTPUT;
+}
+
+if ($opt_h) {
+
+ # Diff header separately from stats
+
+ $refheader = "/tmp/smt-test.refheader.$$";
+ $newheader = "/tmp/smt-test.newheader.$$";
+
+ copy_header(\*REF, $refheader);
+ copy_header(\*NEW, $newheader);
+
+ print "\n===== Header and program output differences =====\n\n";
+
+ print `diff $refheader $newheader`;
+
+ print "\n===== Statistics differences =====\n\n";
+}
+
+#
+# Now parse statistics
+#
+
+#
+# This function takes an open filehandle and returns a reference to
+# a hash containing all the statistics variables and their values.
+#
+sub parse_file
+{
+ $stathandle = shift;
+
+ $in_dist = undef;
+ $hashref = { }; # initialize hash for values
+
+ while (<$stathandle>)
+ {
+ next if /^\s*$/; # skip blank lines
+ next if /^\*\*Ignore/; # temporary, to make totaling scripts easy for ISCA 03
+ last if /End Simulation Statistics/;
+
+ s/ *#.*//; # strip comments
+
+ if (/^Memory usage: (\d+) KBytes/) {
+ $stat = 'memory usage';
+ $value = $1;
+ }
+ elsif ($in_dist) {
+ if ($in_dist =~ /^fetch_loss_counters/) {
+ if (/^fetch_loss_counters_\d+\.end/) {
+ # end line of distribution: clear $in_dist flag
+ $in_dist = undef;
+ next;
+ }
+ else {
+ next if $opt_f;
+
+ ($stat, $value) = /^(\S+)\s+(.*)/;
+ }
+ }
+ else {
+ if (/(.*)\.end_dist/) {
+ # end line of distribution: clear $in_dist flag
+ $in_dist = undef;
+ next;
+ }
+ if ($opt_d) {
+ next; # bail out if we are ignoring dists...
+ }
+ elsif (/(.*)\.(min|max)_value/) {
+ # treat these like normal stats
+ ($stat, $value) = /^(\S+)\s+(.*)/;
+ }
+ else {
+ # this is ugly because labels in the distribution
+ # buckets don't start in column 0 and may include
+ # embedded spaces
+ ($stat, $value) =
+ /^\s*(\S+(?:.*\S)?)\s+(\d+)\s+\d+\.\d+%/;
+ $stat = $in_dist . '::' . $stat;
+ }
+ }
+ }
+ else {
+ if (/(.*)\.start_dist/) {
+ # start line of distribution: set $in_dist flag
+ # and save distribution name for future reference
+ $in_dist = $1;
+ $stat = $1;
+ $value = 0;
+ }
+ elsif (/^(fetch_loss_counters_\d+)\.start/) {
+ # treat fetch loss counters like distribution, sort of
+ $in_dist = $1;
+ $stat = $1;
+ $value = 0;
+ }
+ else {
+ ($stat, $value) = /^(\S+)\s+(.*)/;
+ }
+ }
+
+ $$hashref{$stat} = $value;
+ }
+
+ close($stathandle);
+ return $hashref;
+}
+
+
+#
+# pct_diff($old, $new) returns percent difference from $old to $new.
+#
+sub pct_diff
+{
+ my ($old, $new) = @_;
+ return ($old == 0) ? (($new == 0) ? 0 : 9999) : 100 * ($new - $old) / $old;
+}
+
+
+#
+# Statistics to ignore: these relate to simulator performance, not
+# correctness, so don't fail on changes here.
+#
+%ignore = (
+ 'host_seconds' => 1,
+ 'host_tick_rate' => 1,
+ 'host_inst_rate' => 1,
+ 'host_mem_usage' => 1
+);
+
+#
+# List of key statistics (always displayed)
+# ==> list stats here WITHOUT trailing thread ID
+#
+@key_stat_list = (
+ 'COM:IPC',
+ 'ISSUE:MSIPC',
+ 'COM:count',
+ 'host_inst_rate',
+ 'sim_insts',
+ 'sim_ticks',
+ 'host_mem_usage'
+);
+
+$key_stat_pattern = join('|', @key_stat_list);
+
+# initialize first statistics from each file
+
+$max_err_mag = 0;
+
+$refhash = parse_file(\*REF);
+$newhash = parse_file(\*NEW);
+
+# The string sim-smt prints on a divide by zero
+$divbyzero = '<err: divide by zero>';
+
+foreach $stat (sort keys %$refhash)
+{
+ $refvalue = $$refhash{$stat};
+ $newvalue = $$newhash{$stat};
+
+ if (!defined($newvalue)) {
+ # stat missing from new file
+ push @missing_stats, $stat;
+ next;
+ }
+
+ if ($stat =~ /($key_stat_pattern)/o) {
+ # key statistics: always record & display changes in these
+ push @key_stats, [$stat, $refvalue, $newvalue];
+ }
+
+ if ($ignore{$stat} or $refvalue eq $newvalue) {
+ # stat is in "ignore" list, or hasn't changed
+ }
+ else {
+ if ($refvalue eq $divbyzero || $newvalue eq $divbyzero) {
+ # one or the other was a divide by zero:
+ # no point in trying to quantify error
+ print "$stat: $refvalue --> $newvalue\n";
+ }
+ else {
+ $reldiff = pct_diff($refvalue, $newvalue);
+ $diffmag = abs($reldiff);
+
+ if ($diffmag > $err_thresh) {
+ push @errs,
+ [$stat, $refvalue, $newvalue, $reldiff];
+ }
+
+ if ($diffmag > $max_err_mag) {
+ $max_err_mag = $diffmag;
+ }
+ }
+ }
+
+ # remove from new hash so we can detect added stats
+ delete $$newhash{$stat};
+}
+
+
+#
+# All done. Print comparison summary.
+#
+
+printf("Maximum error magnitude: %+f%%\n\n", $max_err_mag);
+
+printf(" %-30s %10s %10s %10s %7s\n", ' ', 'Reference', 'New Value', 'Abs Diff', 'Pct Chg');
+
+printf("Key statistics:\n\n");
+
+foreach $key_stat (@key_stats)
+{
+ ($statname, $refvalue, $newvalue, $reldiff) = @$key_stat;
+
+ # deduce format from reference value
+ $pointpos = rindex($refvalue, '.');
+ $digits = ($pointpos < 0) ? 0 :(length($refvalue) - $pointpos - 1);
+ $fmt = "%10.${digits}f";
+
+ # print differing values with absolute and relative error
+ printf(" %-30s $fmt $fmt $fmt %+7.2f%%\n",
+ $statname, $refvalue, $newvalue,
+ $newvalue - $refvalue, pct_diff($refvalue, $newvalue));
+}
+
+printf("\nLargest $omit_count relative errors (> %d%%):\n\n", $err_thresh);
+
+$num_errs = 0;
+
+if ($opt_p)
+{
+ # sort differences by percent change
+ @errs = sort { abs($$b[3]) <=> abs($$a[3]) } @errs;
+}
+
+foreach $err (@errs)
+{
+ ($statname, $refvalue, $newvalue, $reldiff) = @$err;
+
+ # deduce format from reference value
+ $pointpos1 = rindex($refvalue, '.');
+ $digits1 = ($pointpos1 < 0) ? 0 :(length($refvalue) - $pointpos1 - 1);
+ $pointpos2 = rindex($newvalue, '.');
+ $digits2 = ($pointpos2 < 0) ? 0 :(length($newvalue) - $pointpos2 - 1);
+ $digits = ($digits1 > $digits2) ? $digits1 : $digits2;
+ $fmt = "%10.${digits}f";
+
+ # print differing values with absolute and relative error
+ printf(" %-30s $fmt $fmt $fmt %+7.2f%%\n",
+ $statname, $refvalue, $newvalue, $newvalue - $refvalue, $reldiff);
+
+ # only print top N errors
+ if (++$num_errs >= $omit_count)
+ {
+ print "[... additional errors omitted ...]\n";
+ last;
+ }
+}
+
+#
+# Report missing stats, but first filter out distribution buckets:
+# these are mostly noise
+
+@missing_stats = grep { !/::(\d+|overflows)?$/ } @missing_stats;
+
+# get count
+$missing_stats = scalar(@missing_stats);
+
+if ($missing_stats)
+{
+ print "\nMissing $missing_stats reference statistics:\n\n";
+ foreach $stat (@missing_stats)
+ {
+# print "\t$stat\n";
+ printf " %-50s ", $stat;
+ print "$$refhash{$stat}\n";
+ }
+}
+
+#
+# Any stats left in newhash are added since the reference file
+#
+
+@added_stats = keys %$newhash;
+
+# first filter out distribution buckets: mostly noise
+
+@added_stats = grep { !/::(\d+|overflows)?$/ } @added_stats;
+
+# get count
+$added_stats = scalar(@added_stats);
+
+if ($added_stats)
+{
+ print "\nFound $added_stats new statistics:\n\n";
+ foreach $stat (sort @added_stats)
+ {
+# print "\t$stat\n";
+ printf " %-50s ", $stat;
+ print "$$newhash{$stat}\n";
+ }
+}
+
+cleanup();
+# Exit code is 0 if no stats error, 1 otherwise
+$status = ($max_err_mag == 0.0) ? 0 : 1;
+exit $status;
+
+sub cleanup
+{
+ unlink($refheader) if ($refheader);
+ unlink($newheader) if ($newheader);
+}
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=2000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[debug]
+break_cycles=
+
+[exetrace]
+intel_format=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=LinuxAlphaSystem
+children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami
+boot_cpu_frequency=1
+boot_osflags=root=/dev/hda1 console=ttyS0
+console=/dist/m5/system/binaries/console
+init_param=0
+kernel=/dist/m5/system/binaries/vmlinux
+mem_mode=atomic
+pal=/dist/m5/system/binaries/ts_osfpal
+physmem=system.physmem
+readfile=/z/ktlim2/clean/newmem-merge/tests/halt.sh
+system_rev=1024
+system_type=34
+
+[system.bridge]
+type=Bridge
+delay=0
+queue_size_a=16
+queue_size_b=16
+write_ack=false
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb
+clock=1
+cpu_id=-1
+defer_registration=false
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.membus
+profile=0
+simulate_stalls=false
+system=system
+width=1
+
+[system.cpu.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu.itb]
+type=AlphaITB
+size=48
+
+[system.disk0]
+type=IdeDisk
+children=image
+delay=2000
+driveID=master
+image=system.disk0.image
+
+[system.disk0.image]
+type=CowDiskImage
+children=child
+child=system.disk0.image.child
+read_only=false
+table_size=65536
+
+[system.disk0.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.disk2]
+type=IdeDisk
+children=image
+delay=2000
+driveID=master
+image=system.disk2.image
+
+[system.disk2.image]
+type=CowDiskImage
+children=child
+child=system.disk2.image.child
+read_only=false
+table_size=65536
+
+[system.disk2.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-bigswap2.img
+read_only=true
+
+[system.intrctrl]
+type=IntrControl
+cpu=system.cpu
+
+[system.iobus]
+type=Bus
+bus_id=0
+
+[system.membus]
+type=Bus
+bus_id=1
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+
+[system.sim_console]
+type=SimConsole
+children=listener
+append_name=true
+intr_control=system.intrctrl
+listener=system.sim_console.listener
+number=0
+output=console
+
+[system.sim_console.listener]
+type=ConsoleListener
+port=3456
+
+[system.simple_disk]
+type=SimpleDisk
+children=disk
+disk=system.simple_disk.disk
+system=system
+
+[system.simple_disk.disk]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.tsunami]
+type=Tsunami
+children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+intrctrl=system.intrctrl
+system=system
+
+[system.tsunami.cchip]
+type=TsunamiCChip
+pio_addr=8803072344064
+pio_latency=2
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+
+[system.tsunami.console]
+type=AlphaConsole
+cpu=system.cpu
+disk=system.simple_disk
+pio_addr=8804682956800
+pio_latency=2
+platform=system.tsunami
+sim_console=system.sim_console
+system=system
+
+[system.tsunami.etherint]
+type=NSGigEInt
+device=system.tsunami.ethernet
+peer=Null
+
+[system.tsunami.ethernet]
+type=NSGigE
+children=configdata
+clock=0
+config_latency=40
+configdata=system.tsunami.ethernet.configdata
+dma_data_free=false
+dma_desc_free=false
+dma_no_allocate=true
+dma_read_delay=0
+dma_read_factor=0
+dma_write_delay=0
+dma_write_factor=0
+hardware_address=00:90:00:00:00:01
+intr_delay=20000
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=2
+platform=system.tsunami
+rss=false
+rx_delay=2000
+rx_fifo_size=524288
+rx_filter=true
+rx_thread=false
+system=system
+tx_delay=2000
+tx_fifo_size=524288
+tx_thread=false
+
+[system.tsunami.ethernet.configdata]
+type=PciConfigData
+BAR0=1
+BAR0Size=256
+BAR1=0
+BAR1Size=4096
+BAR2=0
+BAR2Size=0
+BAR3=0
+BAR3Size=0
+BAR4=0
+BAR4Size=0
+BAR5=0
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=34
+ExpansionROM=0
+HeaderType=0
+InterruptLine=30
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=52
+MinimumGrant=176
+ProgIF=0
+Revision=0
+Status=656
+SubClassCode=0
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=4107
+
+[system.tsunami.fake_OROM]
+type=IsaFake
+pio_addr=8796093677568
+pio_latency=2
+pio_size=393216
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_ata0]
+type=IsaFake
+pio_addr=8804615848432
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_ata1]
+type=IsaFake
+pio_addr=8804615848304
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_addr]
+type=IsaFake
+pio_addr=8804615848569
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read0]
+type=IsaFake
+pio_addr=8804615848451
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read1]
+type=IsaFake
+pio_addr=8804615848515
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read2]
+type=IsaFake
+pio_addr=8804615848579
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read3]
+type=IsaFake
+pio_addr=8804615848643
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read4]
+type=IsaFake
+pio_addr=8804615848707
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read5]
+type=IsaFake
+pio_addr=8804615848771
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read6]
+type=IsaFake
+pio_addr=8804615848835
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read7]
+type=IsaFake
+pio_addr=8804615848899
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_write]
+type=IsaFake
+pio_addr=8804615850617
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_ppc]
+type=IsaFake
+pio_addr=8804615848892
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_sm_chip]
+type=IsaFake
+pio_addr=8804615848816
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart1]
+type=IsaFake
+pio_addr=8804615848696
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart2]
+type=IsaFake
+pio_addr=8804615848936
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart3]
+type=IsaFake
+pio_addr=8804615848680
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart4]
+type=IsaFake
+pio_addr=8804615848944
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fb]
+type=BadDevice
+devicename=FrameBuffer
+pio_addr=8804615848912
+pio_latency=2
+platform=system.tsunami
+system=system
+
+[system.tsunami.ide]
+type=IdeController
+children=configdata
+config_latency=40
+configdata=system.tsunami.ide.configdata
+disks=system.disk0 system.disk2
+pci_bus=0
+pci_dev=0
+pci_func=0
+pio_latency=2
+platform=system.tsunami
+system=system
+
+[system.tsunami.ide.configdata]
+type=PciConfigData
+BAR0=1
+BAR0Size=8
+BAR1=1
+BAR1Size=4
+BAR2=1
+BAR2Size=8
+BAR3=1
+BAR3Size=4
+BAR4=1
+BAR4Size=16
+BAR5=1
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+
+[system.tsunami.io]
+type=TsunamiIO
+frequency=1953125
+pio_addr=8804615847936
+pio_latency=2
+platform=system.tsunami
+system=system
+time=1136073600
+tsunami=system.tsunami
+
+[system.tsunami.pchip]
+type=TsunamiPChip
+pio_addr=8802535473152
+pio_latency=2
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+
+[system.tsunami.pciconfig]
+type=PciConfigAll
+bus=0
+pio_latency=1
+platform=system.tsunami
+size=16777216
+system=system
+
+[system.tsunami.uart]
+type=Uart8250
+pio_addr=8804615848952
+pio_latency=2
+platform=system.tsunami
+sim_console=system.sim_console
+system=system
+
+[trace]
+bufsize=0
+cycle=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
--- /dev/null
+[root]
+type=Root
+clock=2000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+
+[system]
+type=LinuxAlphaSystem
+boot_cpu_frequency=1
+physmem=system.physmem
+mem_mode=atomic
+kernel=/dist/m5/system/binaries/vmlinux
+console=/dist/m5/system/binaries/console
+pal=/dist/m5/system/binaries/ts_osfpal
+boot_osflags=root=/dev/hda1 console=ttyS0
+readfile=/z/ktlim2/clean/newmem-merge/tests/halt.sh
+init_param=0
+system_type=34
+system_rev=1024
+
+[system.membus]
+type=Bus
+bus_id=1
+
+[system.bridge]
+type=Bridge
+queue_size_a=16
+queue_size_b=16
+delay=0
+write_ack=false
+
+[system.disk0.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.disk0.image]
+type=CowDiskImage
+child=system.disk0.image.child
+image_file=
+table_size=65536
+read_only=false
+
+[system.disk0]
+type=IdeDisk
+image=system.disk0.image
+driveID=master
+delay=2000
+
+[system.disk2.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-bigswap2.img
+read_only=true
+
+[system.disk2.image]
+type=CowDiskImage
+child=system.disk2.image.child
+image_file=
+table_size=65536
+read_only=false
+
+[system.disk2]
+type=IdeDisk
+image=system.disk2.image
+driveID=master
+delay=2000
+
+[system.cpu.itb]
+type=AlphaITB
+size=48
+
+[system.cpu.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu]
+type=AtomicSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+mem=system.membus
+system=system
+itb=system.cpu.itb
+dtb=system.cpu.dtb
+cpu_id=-1
+profile=0
+clock=1
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
+[system.intrctrl]
+type=IntrControl
+cpu=system.cpu
+
+[system.simple_disk.disk]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.simple_disk]
+type=SimpleDisk
+system=system
+disk=system.simple_disk.disk
+
+[system.tsunami]
+type=Tsunami
+system=system
+intrctrl=system.intrctrl
+
+[system.tsunami.fake_uart1]
+type=IsaFake
+pio_addr=8804615848696
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart2]
+type=IsaFake
+pio_addr=8804615848936
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart3]
+type=IsaFake
+pio_addr=8804615848680
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart4]
+type=IsaFake
+pio_addr=8804615848944
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_ppc]
+type=IsaFake
+pio_addr=8804615848892
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.cchip]
+type=TsunamiCChip
+pio_addr=8803072344064
+pio_latency=2
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+
+[system.tsunami.io]
+type=TsunamiIO
+pio_addr=8804615847936
+pio_latency=2
+frequency=1953125
+platform=system.tsunami
+system=system
+time=1136073600
+tsunami=system.tsunami
+
+[]
+type=PciConfigAll
+pio_latency=1
+bus=0
+size=16777216
+platform=system.tsunami
+system=system
+
+[system.sim_console.listener]
+type=ConsoleListener
+port=3456
+
+[system.sim_console]
+type=SimConsole
+listener=system.sim_console.listener
+intr_control=system.intrctrl
+output=console
+append_name=true
+number=0
+
+[system.tsunami.console]
+type=AlphaConsole
+sim_console=system.sim_console
+disk=system.simple_disk
+pio_addr=8804682956800
+system=system
+cpu=system.cpu
+platform=system.tsunami
+pio_latency=2
+
+[system.tsunami.fake_ata1]
+type=IsaFake
+pio_addr=8804615848304
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_ata0]
+type=IsaFake
+pio_addr=8804615848432
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.pchip]
+type=TsunamiPChip
+pio_addr=8802535473152
+pio_latency=2
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+
+[system.tsunami.fake_pnp_read3]
+type=IsaFake
+pio_addr=8804615848643
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read2]
+type=IsaFake
+pio_addr=8804615848579
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read1]
+type=IsaFake
+pio_addr=8804615848515
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read0]
+type=IsaFake
+pio_addr=8804615848451
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read7]
+type=IsaFake
+pio_addr=8804615848899
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read6]
+type=IsaFake
+pio_addr=8804615848835
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read5]
+type=IsaFake
+pio_addr=8804615848771
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read4]
+type=IsaFake
+pio_addr=8804615848707
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_write]
+type=IsaFake
+pio_addr=8804615850617
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fb]
+type=BadDevice
+devicename=FrameBuffer
+pio_addr=8804615848912
+system=system
+platform=system.tsunami
+pio_latency=2
+
+[system.tsunami.ethernet.configdata]
+type=PciConfigData
+VendorID=4107
+DeviceID=34
+Command=0
+Status=656
+Revision=0
+ProgIF=0
+SubClassCode=0
+ClassCode=2
+CacheLineSize=0
+LatencyTimer=0
+HeaderType=0
+BIST=0
+BAR0=1
+BAR1=0
+BAR2=0
+BAR3=0
+BAR4=0
+BAR5=0
+CardbusCIS=0
+SubsystemVendorID=0
+SubsystemID=0
+ExpansionROM=0
+InterruptLine=30
+InterruptPin=1
+MinimumGrant=176
+MaximumLatency=52
+BAR0Size=256
+BAR1Size=4096
+BAR2Size=0
+BAR3Size=0
+BAR4Size=0
+BAR5Size=0
+
+[system.tsunami.ethernet]
+type=NSGigE
+system=system
+platform=system.tsunami
+configdata=system.tsunami.ethernet.configdata
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=2
+config_latency=40
+clock=0
+dma_desc_free=false
+dma_data_free=false
+dma_read_delay=0
+dma_write_delay=0
+dma_read_factor=0
+dma_write_factor=0
+dma_no_allocate=true
+intr_delay=20000
+rx_delay=2000
+tx_delay=2000
+rx_fifo_size=524288
+tx_fifo_size=524288
+rx_filter=true
+hardware_address=00:90:00:00:00:01
+rx_thread=false
+tx_thread=false
+rss=false
+
+[system.tsunami.etherint]
+type=NSGigEInt
+peer=null
+device=system.tsunami.ethernet
+
+[system.tsunami.fake_OROM]
+type=IsaFake
+pio_addr=8796093677568
+pio_latency=2
+pio_size=393216
+platform=system.tsunami
+system=system
+
+[system.tsunami.uart]
+type=Uart8250
+pio_addr=8804615848952
+pio_latency=2
+platform=system.tsunami
+sim_console=system.sim_console
+system=system
+
+[system.tsunami.fake_sm_chip]
+type=IsaFake
+pio_addr=8804615848816
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_addr]
+type=IsaFake
+pio_addr=8804615848569
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.ide.configdata]
+type=PciConfigData
+VendorID=32902
+DeviceID=28945
+Command=0
+Status=640
+Revision=0
+ProgIF=133
+SubClassCode=1
+ClassCode=1
+CacheLineSize=0
+LatencyTimer=0
+HeaderType=0
+BIST=0
+BAR0=1
+BAR1=1
+BAR2=1
+BAR3=1
+BAR4=1
+BAR5=1
+CardbusCIS=0
+SubsystemVendorID=0
+SubsystemID=0
+ExpansionROM=0
+InterruptLine=31
+InterruptPin=1
+MinimumGrant=0
+MaximumLatency=0
+BAR0Size=8
+BAR1Size=4
+BAR2Size=8
+BAR3Size=4
+BAR4Size=16
+BAR5Size=0
+
+[system.tsunami.ide]
+type=IdeController
+system=system
+platform=system.tsunami
+configdata=system.tsunami.ide.configdata
+pci_bus=0
+pci_dev=0
+pci_func=0
+pio_latency=2
+config_latency=40
+disks=system.disk0 system.disk2
+
+[system.iobus]
+type=Bus
+bus_id=0
+
+[trace]
+flags=
+start=0
+cycle=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+pc_symbol=true
+intel_format=false
+trace_system=client
+
+[debug]
+break_cycles=
+
+[pseudo_inst]
+quiesce=true
+statistics=true
+checkpoint=true
+
--- /dev/null
+M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
+\rGot Configuration 623
+\rmemsize 8000000 pages 4000
+\rFirst free page after ROM 0xFFFFFC0000018000
+\rHWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
+\rkstart = 0xFFFFFC0000310000, kend = 0xFFFFFC00008064E8, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
+\rCPU Clock at 2000 MHz IntrClockFrequency=1024
+\rBooting with 1 processor(s)
+\rKSP: 0x20043FE8 PTBR 0x20
+\rConsole Callback at 0x0, fixup at 0x0, crb offset: 0x510
+\rMemory cluster 0 [0 - 392]
+\rMemory cluster 1 [392 - 15992]
+\rInitalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
+\rConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
+\runix_boot_mem ends at FFFFFC0000076000
+\rk_argc = 0
+\rjumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1028)
+\rCallbackFixup 0 18000, t7=FFFFFC0000700000
+\rLinux version 2.6.8.1 (binkertn@ziff.eecs.umich.edu) (gcc version 3.4.3) #36 SMP Mon May 2 19:50:53 EDT 2005
+\rBooting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
+\rMajor Options: SMP LEGACY_START VERBOSE_MCHECK
+\rCommand line: root=/dev/hda1 console=ttyS0
+\rmemcluster 0, usage 1, start 0, end 392
+\rmemcluster 1, usage 0, start 392, end 16384
+\rfreeing pages 1030:16384
+\rreserving pages 1030:1031
+\rSMP: 1 CPUs probed -- cpu_present_mask = 1
+\rBuilt 1 zonelists
+\rKernel command line: root=/dev/hda1 console=ttyS0
+\rPID hash table entries: 1024 (order 10: 16384 bytes)
+\rUsing epoch = 1900
+\rConsole: colour dummy device 80x25
+\rDentry cache hash table entries: 32768 (order: 5, 262144 bytes)
+\rInode-cache hash table entries: 16384 (order: 4, 131072 bytes)
+\rMemory: 119072k/131072k available (3058k kernel code, 8680k reserved, 695k data, 480k init)
+\rMount-cache hash table entries: 512 (order: 0, 8192 bytes)
+\rper-CPU timeslice cutoff: 374.49 usecs.
+\rtask migration cache decay timeout: 0 msecs.
+\rSMP mode deactivated.
+\rBrought up 1 CPUs
+\rSMP: Total of 1 processors activated (4002.20 BogoMIPS).
+\rNET: Registered protocol family 16
+\rEISA bus registered
+\rpci: enabling save/restore of SRM state
+\rSCSI subsystem initialized
+\rsrm_env: version 0.0.5 loaded successfully
+\rInstalling knfsd (copyright (C) 1996 okir@monad.swb.de).
+\rInitializing Cryptographic API
+\rrtc: Standard PC (1900) epoch (1900) detected
+\rReal Time Clock Driver v1.12
+\rSerial: 8250/16550 driver $Revision: 1.90 $ 5 ports, IRQ sharing disabled
+\rttyS0 at I/O 0x3f8 (irq = 4) is a 8250
+\rloop: loaded (max 8 devices)
+\rUsing anticipatory io scheduler
+\rnbd: registered device at major 43
+\rsinic.c: M5 Simple Integrated NIC driver
+\rns83820.c: National Semiconductor DP83820 10/100/1000 driver.
+\reth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
+\reth0: enabling optical transceiver
+\reth0: ns83820 v0.20: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=sg
+\rUniform Multi-Platform E-IDE driver Revision: 7.00alpha2
+\ride: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
+\rPIIX4: IDE controller at PCI slot 0000:00:00.0
+\rPIIX4: chipset revision 0
+\rPIIX4: 100% native mode on irq 31
+\r ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
+\r ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
+\rhda: M5 IDE Disk, ATA DISK drive
+\rhdb: M5 IDE Disk, ATA DISK drive
+\ride0 at 0x8410-0x8417,0x8422 on irq 31
+\rhda: max request size: 128KiB
+\rhda: 163296 sectors (83 MB), CHS=162/16/63, UDMA(33)
+\r hda: hda1
+\rhdb: max request size: 128KiB
+\rhdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
+\r hdb: unknown partition table
+\rscsi0 : scsi_m5, version 1.73 [20040518], dev_size_mb=8, opts=0x0
+\r Vendor: Linux Model: scsi_m5 Li Rev: 0004
+\r Type: Direct-Access ANSI SCSI revision: 03
+\rSCSI device sda: 16384 512-byte hdwr sectors (8 MB)
+\rSCSI device sda: drive cache: write back
+\r sda: unknown partition table
+\rAttached scsi disk sda at scsi0, channel 0, id 0, lun 0
+\rmice: PS/2 mouse device common for all mice
+\rNET: Registered protocol family 2
+\rIP: routing cache hash table of 1024 buckets, 16Kbytes
+\rTCP: Hash tables configured (established 8192 bind 8192)
+\rip_conntrack version 2.1 (512 buckets, 4096 max) - 440 bytes per conntrack
+\rip_tables: (C) 2000-2002 Netfilter core team
+\rarp_tables: (C) 2002 David S. Miller
+\rInitializing IPsec netlink socket
+\rNET: Registered protocol family 1
+\rNET: Registered protocol family 17
+\rNET: Registered protocol family 15
+\rBridge firewalling registered
+\r802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
+\rAll bugs added by David S. Miller <davem@redhat.com>
+\rVFS: Mounted root (ext2 filesystem) readonly.
+\rFreeing unused kernel memory: 480k freed
+\r\rinit started: BusyBox v1.00-rc2 (2004.11.18-16:22+0000) multi-call binary
+
+PTXdist-0.7.0 (2004-11-18T11:23:40-0500)
+
+mounting filesystems...
+EXT2-fs warning: checktime reached, running e2fsck is recommended
+\rloading script...
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 505604 # Simulator instruction rate (inst/s)
+host_mem_usage 195484 # Number of bytes of host memory used
+host_seconds 118.53 # Real time elapsed on the host
+host_tick_rate 29473706 # Simulator tick rate (ticks/s)
+sim_freq 2000000000 # Frequency of simulated ticks
+sim_insts 59929520 # Number of instructions simulated
+sim_seconds 1.746773 # Number of seconds simulated
+sim_ticks 3493545624 # Number of ticks simulated
+system.cpu.dtb.accesses 2354955 # DTB accesses
+system.cpu.dtb.acv 413 # DTB access violations
+system.cpu.dtb.hits 13929995 # DTB hits
+system.cpu.dtb.misses 16187 # DTB misses
+system.cpu.dtb.read_accesses 832415 # DTB read accesses
+system.cpu.dtb.read_acv 242 # DTB read access violations
+system.cpu.dtb.read_hits 7718636 # DTB read hits
+system.cpu.dtb.read_misses 13695 # DTB read misses
+system.cpu.dtb.write_accesses 1522540 # DTB write accesses
+system.cpu.dtb.write_acv 171 # DTB write access violations
+system.cpu.dtb.write_hits 6211359 # DTB write hits
+system.cpu.dtb.write_misses 2492 # DTB write misses
+system.cpu.idle_fraction 0.982844 # Percentage of idle cycles
+system.cpu.itb.accesses 4037380 # ITB accesses
+system.cpu.itb.acv 239 # ITB acv
+system.cpu.itb.hits 4030656 # ITB hits
+system.cpu.itb.misses 6724 # ITB misses
+system.cpu.kern.callpal 184022 # number of callpals executed
+system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_swpctx 1864 1.01% 1.02% # number of callpals executed
+system.cpu.kern.callpal_tbi 28 0.02% 1.03% # number of callpals executed
+system.cpu.kern.callpal_wrent 7 0.00% 1.03% # number of callpals executed
+system.cpu.kern.callpal_swpipl 172016 93.48% 94.51% # number of callpals executed
+system.cpu.kern.callpal_rdps 4808 2.61% 97.12% # number of callpals executed
+system.cpu.kern.callpal_wrkgp 1 0.00% 97.12% # number of callpals executed
+system.cpu.kern.callpal_wrusp 8 0.00% 97.13% # number of callpals executed
+system.cpu.kern.callpal_rdusp 12 0.01% 97.13% # number of callpals executed
+system.cpu.kern.callpal_whami 2 0.00% 97.14% # number of callpals executed
+system.cpu.kern.callpal_rti 4291 2.33% 99.47% # number of callpals executed
+system.cpu.kern.callpal_callsys 667 0.36% 99.83% # number of callpals executed
+system.cpu.kern.callpal_imb 314 0.17% 100.00% # number of callpals executed
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.hwrei 209657 # number of hwrei instructions executed
+system.cpu.kern.inst.ivlb 0 # number of ivlb instructions executed
+system.cpu.kern.inst.ivle 0 # number of ivle instructions executed
+system.cpu.kern.inst.quiesce 1868 # number of quiesce instructions executed
+system.cpu.kern.ipl_count 178378 # number of times we switched to this ipl
+system.cpu.kern.ipl_count_0 75463 42.31% 42.31% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_21 286 0.16% 42.47% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_22 5446 3.05% 45.52% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_31 97183 54.48% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_good 160188 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_0 75397 47.07% 47.07% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_21 286 0.18% 47.25% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_22 5446 3.40% 50.65% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_31 79059 49.35% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks 3493545167 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0 3471576124 99.37% 99.37% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_21 45785 0.00% 99.37% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_22 934362 0.03% 99.40% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_31 20988896 0.60% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used 0.898026 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_0 0.999125 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_31 0.813506 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good_kernel 2342
+system.cpu.kern.mode_good_user 2171
+system.cpu.kern.mode_good_idle 171
+system.cpu.kern.mode_switch_kernel 4092 # number of protection mode switches
+system.cpu.kern.mode_switch_user 2171 # number of protection mode switches
+system.cpu.kern.mode_switch_idle 2041 # number of protection mode switches
+system.cpu.kern.mode_switch_good 0.564066 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_kernel 0.572336 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_idle 0.083782 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks_kernel 33028385 0.95% 0.95% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_user 4450361 0.13% 1.07% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle 3456066419 98.93% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context 1865 # number of times the context was actually changed
+system.cpu.kern.syscall 475 # number of syscalls executed
+system.cpu.kern.syscall_fork 10 2.11% 2.11% # number of syscalls executed
+system.cpu.kern.syscall_read 33 6.95% 9.05% # number of syscalls executed
+system.cpu.kern.syscall_write 7 1.47% 10.53% # number of syscalls executed
+system.cpu.kern.syscall_close 49 10.32% 20.84% # number of syscalls executed
+system.cpu.kern.syscall_chdir 1 0.21% 21.05% # number of syscalls executed
+system.cpu.kern.syscall_chmod 1 0.21% 21.26% # number of syscalls executed
+system.cpu.kern.syscall_obreak 44 9.26% 30.53% # number of syscalls executed
+system.cpu.kern.syscall_lseek 13 2.74% 33.26% # number of syscalls executed
+system.cpu.kern.syscall_getpid 10 2.11% 35.37% # number of syscalls executed
+system.cpu.kern.syscall_setuid 4 0.84% 36.21% # number of syscalls executed
+system.cpu.kern.syscall_getuid 8 1.68% 37.89% # number of syscalls executed
+system.cpu.kern.syscall_access 4 0.84% 38.74% # number of syscalls executed
+system.cpu.kern.syscall_dup 4 0.84% 39.58% # number of syscalls executed
+system.cpu.kern.syscall_open 68 14.32% 53.89% # number of syscalls executed
+system.cpu.kern.syscall_getgid 8 1.68% 55.58% # number of syscalls executed
+system.cpu.kern.syscall_sigprocmask 14 2.95% 58.53% # number of syscalls executed
+system.cpu.kern.syscall_ioctl 16 3.37% 61.89% # number of syscalls executed
+system.cpu.kern.syscall_readlink 2 0.42% 62.32% # number of syscalls executed
+system.cpu.kern.syscall_execve 8 1.68% 64.00% # number of syscalls executed
+system.cpu.kern.syscall_pre_F64_stat 31 6.53% 70.53% # number of syscalls executed
+system.cpu.kern.syscall_pre_F64_lstat 1 0.21% 70.74% # number of syscalls executed
+system.cpu.kern.syscall_mmap 55 11.58% 82.32% # number of syscalls executed
+system.cpu.kern.syscall_munmap 6 1.26% 83.58% # number of syscalls executed
+system.cpu.kern.syscall_mprotect 14 2.95% 86.53% # number of syscalls executed
+system.cpu.kern.syscall_gethostname 2 0.42% 86.95% # number of syscalls executed
+system.cpu.kern.syscall_dup2 4 0.84% 87.79% # number of syscalls executed
+system.cpu.kern.syscall_pre_F64_fstat 28 5.89% 93.68% # number of syscalls executed
+system.cpu.kern.syscall_fcntl 14 2.95% 96.63% # number of syscalls executed
+system.cpu.kern.syscall_socket 3 0.63% 97.26% # number of syscalls executed
+system.cpu.kern.syscall_connect 3 0.63% 97.89% # number of syscalls executed
+system.cpu.kern.syscall_setgid 4 0.84% 98.74% # number of syscalls executed
+system.cpu.kern.syscall_getrlimit 3 0.63% 99.37% # number of syscalls executed
+system.cpu.kern.syscall_setsid 3 0.63% 100.00% # number of syscalls executed
+system.cpu.not_idle_fraction 0.017156 # Percentage of non-idle cycles
+system.cpu.numCycles 59936483 # number of cpu cycles simulated
+system.cpu.num_insts 59929520 # Number of instructions executed
+system.cpu.num_refs 13982880 # Number of memory references
+system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_bytes 2521088 # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_full_pages 285 # Number of full page size DMA writes.
+system.disk0.dma_write_txs 375 # Number of DMA write transactions.
+system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
+system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
+system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
+system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+
+---------- End Simulation Statistics ----------
--- /dev/null
+ 0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006
+Listening for console connection on port 3457
+0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001
+warn: Entering event queue @ 0. Starting simulation...
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 27 2006 16:54:00
+M5 started Thu Jul 27 17:10:13 2006
+M5 executing on zamp.eecs.umich.edu
+command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/test/opt/linux-boot/atomic tests/linux-boot/run.py
+Exiting @ cycle 3493545624 because m5_exit instruction encountered
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=2000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[debug]
+break_cycles=
+
+[exetrace]
+intel_format=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=LinuxAlphaSystem
+children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami
+boot_cpu_frequency=1
+boot_osflags=root=/dev/hda1 console=ttyS0
+console=/dist/m5/system/binaries/console
+init_param=0
+kernel=/dist/m5/system/binaries/vmlinux
+mem_mode=atomic
+pal=/dist/m5/system/binaries/ts_osfpal
+physmem=system.physmem
+readfile=/z/ktlim2/clean/newmem-merge/tests/halt.sh
+system_rev=1024
+system_type=34
+
+[system.bridge]
+type=Bridge
+delay=0
+queue_size_a=16
+queue_size_b=16
+write_ack=false
+
+[system.cpu0]
+type=AtomicSimpleCPU
+children=dtb itb
+clock=1
+cpu_id=-1
+defer_registration=false
+dtb=system.cpu0.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.membus
+profile=0
+simulate_stalls=false
+system=system
+width=1
+
+[system.cpu0.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu0.itb]
+type=AlphaITB
+size=48
+
+[system.cpu1]
+type=AtomicSimpleCPU
+children=dtb itb
+clock=1
+cpu_id=-1
+defer_registration=false
+dtb=system.cpu1.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.membus
+profile=0
+simulate_stalls=false
+system=system
+width=1
+
+[system.cpu1.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu1.itb]
+type=AlphaITB
+size=48
+
+[system.disk0]
+type=IdeDisk
+children=image
+delay=2000
+driveID=master
+image=system.disk0.image
+
+[system.disk0.image]
+type=CowDiskImage
+children=child
+child=system.disk0.image.child
+read_only=false
+table_size=65536
+
+[system.disk0.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.disk2]
+type=IdeDisk
+children=image
+delay=2000
+driveID=master
+image=system.disk2.image
+
+[system.disk2.image]
+type=CowDiskImage
+children=child
+child=system.disk2.image.child
+read_only=false
+table_size=65536
+
+[system.disk2.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-bigswap2.img
+read_only=true
+
+[system.intrctrl]
+type=IntrControl
+cpu=system.cpu0
+
+[system.iobus]
+type=Bus
+bus_id=0
+
+[system.membus]
+type=Bus
+bus_id=1
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+
+[system.sim_console]
+type=SimConsole
+children=listener
+append_name=true
+intr_control=system.intrctrl
+listener=system.sim_console.listener
+number=0
+output=console
+
+[system.sim_console.listener]
+type=ConsoleListener
+port=3456
+
+[system.simple_disk]
+type=SimpleDisk
+children=disk
+disk=system.simple_disk.disk
+system=system
+
+[system.simple_disk.disk]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.tsunami]
+type=Tsunami
+children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+intrctrl=system.intrctrl
+system=system
+
+[system.tsunami.cchip]
+type=TsunamiCChip
+pio_addr=8803072344064
+pio_latency=2
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+
+[system.tsunami.console]
+type=AlphaConsole
+cpu=system.cpu0
+disk=system.simple_disk
+pio_addr=8804682956800
+pio_latency=2
+platform=system.tsunami
+sim_console=system.sim_console
+system=system
+
+[system.tsunami.etherint]
+type=NSGigEInt
+device=system.tsunami.ethernet
+peer=Null
+
+[system.tsunami.ethernet]
+type=NSGigE
+children=configdata
+clock=0
+config_latency=40
+configdata=system.tsunami.ethernet.configdata
+dma_data_free=false
+dma_desc_free=false
+dma_no_allocate=true
+dma_read_delay=0
+dma_read_factor=0
+dma_write_delay=0
+dma_write_factor=0
+hardware_address=00:90:00:00:00:01
+intr_delay=20000
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=2
+platform=system.tsunami
+rss=false
+rx_delay=2000
+rx_fifo_size=524288
+rx_filter=true
+rx_thread=false
+system=system
+tx_delay=2000
+tx_fifo_size=524288
+tx_thread=false
+
+[system.tsunami.ethernet.configdata]
+type=PciConfigData
+BAR0=1
+BAR0Size=256
+BAR1=0
+BAR1Size=4096
+BAR2=0
+BAR2Size=0
+BAR3=0
+BAR3Size=0
+BAR4=0
+BAR4Size=0
+BAR5=0
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=34
+ExpansionROM=0
+HeaderType=0
+InterruptLine=30
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=52
+MinimumGrant=176
+ProgIF=0
+Revision=0
+Status=656
+SubClassCode=0
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=4107
+
+[system.tsunami.fake_OROM]
+type=IsaFake
+pio_addr=8796093677568
+pio_latency=2
+pio_size=393216
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_ata0]
+type=IsaFake
+pio_addr=8804615848432
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_ata1]
+type=IsaFake
+pio_addr=8804615848304
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_addr]
+type=IsaFake
+pio_addr=8804615848569
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read0]
+type=IsaFake
+pio_addr=8804615848451
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read1]
+type=IsaFake
+pio_addr=8804615848515
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read2]
+type=IsaFake
+pio_addr=8804615848579
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read3]
+type=IsaFake
+pio_addr=8804615848643
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read4]
+type=IsaFake
+pio_addr=8804615848707
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read5]
+type=IsaFake
+pio_addr=8804615848771
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read6]
+type=IsaFake
+pio_addr=8804615848835
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read7]
+type=IsaFake
+pio_addr=8804615848899
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_write]
+type=IsaFake
+pio_addr=8804615850617
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_ppc]
+type=IsaFake
+pio_addr=8804615848892
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_sm_chip]
+type=IsaFake
+pio_addr=8804615848816
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart1]
+type=IsaFake
+pio_addr=8804615848696
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart2]
+type=IsaFake
+pio_addr=8804615848936
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart3]
+type=IsaFake
+pio_addr=8804615848680
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart4]
+type=IsaFake
+pio_addr=8804615848944
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fb]
+type=BadDevice
+devicename=FrameBuffer
+pio_addr=8804615848912
+pio_latency=2
+platform=system.tsunami
+system=system
+
+[system.tsunami.ide]
+type=IdeController
+children=configdata
+config_latency=40
+configdata=system.tsunami.ide.configdata
+disks=system.disk0 system.disk2
+pci_bus=0
+pci_dev=0
+pci_func=0
+pio_latency=2
+platform=system.tsunami
+system=system
+
+[system.tsunami.ide.configdata]
+type=PciConfigData
+BAR0=1
+BAR0Size=8
+BAR1=1
+BAR1Size=4
+BAR2=1
+BAR2Size=8
+BAR3=1
+BAR3Size=4
+BAR4=1
+BAR4Size=16
+BAR5=1
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+
+[system.tsunami.io]
+type=TsunamiIO
+frequency=1953125
+pio_addr=8804615847936
+pio_latency=2
+platform=system.tsunami
+system=system
+time=1136073600
+tsunami=system.tsunami
+
+[system.tsunami.pchip]
+type=TsunamiPChip
+pio_addr=8802535473152
+pio_latency=2
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+
+[system.tsunami.pciconfig]
+type=PciConfigAll
+bus=0
+pio_latency=1
+platform=system.tsunami
+size=16777216
+system=system
+
+[system.tsunami.uart]
+type=Uart8250
+pio_addr=8804615848952
+pio_latency=2
+platform=system.tsunami
+sim_console=system.sim_console
+system=system
+
+[trace]
+bufsize=0
+cycle=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
--- /dev/null
+[root]
+type=Root
+clock=2000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+
+[system]
+type=LinuxAlphaSystem
+boot_cpu_frequency=1
+physmem=system.physmem
+mem_mode=atomic
+kernel=/dist/m5/system/binaries/vmlinux
+console=/dist/m5/system/binaries/console
+pal=/dist/m5/system/binaries/ts_osfpal
+boot_osflags=root=/dev/hda1 console=ttyS0
+readfile=/z/ktlim2/clean/newmem-merge/tests/halt.sh
+init_param=0
+system_type=34
+system_rev=1024
+
+[system.membus]
+type=Bus
+bus_id=1
+
+[system.bridge]
+type=Bridge
+queue_size_a=16
+queue_size_b=16
+delay=0
+write_ack=false
+
+[system.disk0.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.disk0.image]
+type=CowDiskImage
+child=system.disk0.image.child
+image_file=
+table_size=65536
+read_only=false
+
+[system.disk0]
+type=IdeDisk
+image=system.disk0.image
+driveID=master
+delay=2000
+
+[system.disk2.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-bigswap2.img
+read_only=true
+
+[system.disk2.image]
+type=CowDiskImage
+child=system.disk2.image.child
+image_file=
+table_size=65536
+read_only=false
+
+[system.disk2]
+type=IdeDisk
+image=system.disk2.image
+driveID=master
+delay=2000
+
+[system.cpu0.itb]
+type=AlphaITB
+size=48
+
+[system.cpu0.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu0]
+type=AtomicSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+mem=system.membus
+system=system
+itb=system.cpu0.itb
+dtb=system.cpu0.dtb
+cpu_id=-1
+profile=0
+clock=1
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
+[system.cpu1.itb]
+type=AlphaITB
+size=48
+
+[system.cpu1.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu1]
+type=AtomicSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+mem=system.membus
+system=system
+itb=system.cpu1.itb
+dtb=system.cpu1.dtb
+cpu_id=-1
+profile=0
+clock=1
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
+[system.intrctrl]
+type=IntrControl
+cpu=system.cpu0
+
+[system.simple_disk.disk]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.simple_disk]
+type=SimpleDisk
+system=system
+disk=system.simple_disk.disk
+
+[system.tsunami]
+type=Tsunami
+system=system
+intrctrl=system.intrctrl
+
+[system.tsunami.fake_uart1]
+type=IsaFake
+pio_addr=8804615848696
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart2]
+type=IsaFake
+pio_addr=8804615848936
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart3]
+type=IsaFake
+pio_addr=8804615848680
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart4]
+type=IsaFake
+pio_addr=8804615848944
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_ppc]
+type=IsaFake
+pio_addr=8804615848892
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.cchip]
+type=TsunamiCChip
+pio_addr=8803072344064
+pio_latency=2
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+
+[system.tsunami.io]
+type=TsunamiIO
+pio_addr=8804615847936
+pio_latency=2
+frequency=1953125
+platform=system.tsunami
+system=system
+time=1136073600
+tsunami=system.tsunami
+
+[]
+type=PciConfigAll
+pio_latency=1
+bus=0
+size=16777216
+platform=system.tsunami
+system=system
+
+[system.sim_console.listener]
+type=ConsoleListener
+port=3456
+
+[system.sim_console]
+type=SimConsole
+listener=system.sim_console.listener
+intr_control=system.intrctrl
+output=console
+append_name=true
+number=0
+
+[system.tsunami.console]
+type=AlphaConsole
+sim_console=system.sim_console
+disk=system.simple_disk
+pio_addr=8804682956800
+system=system
+cpu=system.cpu0
+platform=system.tsunami
+pio_latency=2
+
+[system.tsunami.fake_ata1]
+type=IsaFake
+pio_addr=8804615848304
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_ata0]
+type=IsaFake
+pio_addr=8804615848432
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.pchip]
+type=TsunamiPChip
+pio_addr=8802535473152
+pio_latency=2
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+
+[system.tsunami.fake_pnp_read3]
+type=IsaFake
+pio_addr=8804615848643
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read2]
+type=IsaFake
+pio_addr=8804615848579
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read1]
+type=IsaFake
+pio_addr=8804615848515
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read0]
+type=IsaFake
+pio_addr=8804615848451
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read7]
+type=IsaFake
+pio_addr=8804615848899
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read6]
+type=IsaFake
+pio_addr=8804615848835
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read5]
+type=IsaFake
+pio_addr=8804615848771
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read4]
+type=IsaFake
+pio_addr=8804615848707
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_write]
+type=IsaFake
+pio_addr=8804615850617
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fb]
+type=BadDevice
+devicename=FrameBuffer
+pio_addr=8804615848912
+system=system
+platform=system.tsunami
+pio_latency=2
+
+[system.tsunami.ethernet.configdata]
+type=PciConfigData
+VendorID=4107
+DeviceID=34
+Command=0
+Status=656
+Revision=0
+ProgIF=0
+SubClassCode=0
+ClassCode=2
+CacheLineSize=0
+LatencyTimer=0
+HeaderType=0
+BIST=0
+BAR0=1
+BAR1=0
+BAR2=0
+BAR3=0
+BAR4=0
+BAR5=0
+CardbusCIS=0
+SubsystemVendorID=0
+SubsystemID=0
+ExpansionROM=0
+InterruptLine=30
+InterruptPin=1
+MinimumGrant=176
+MaximumLatency=52
+BAR0Size=256
+BAR1Size=4096
+BAR2Size=0
+BAR3Size=0
+BAR4Size=0
+BAR5Size=0
+
+[system.tsunami.ethernet]
+type=NSGigE
+system=system
+platform=system.tsunami
+configdata=system.tsunami.ethernet.configdata
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=2
+config_latency=40
+clock=0
+dma_desc_free=false
+dma_data_free=false
+dma_read_delay=0
+dma_write_delay=0
+dma_read_factor=0
+dma_write_factor=0
+dma_no_allocate=true
+intr_delay=20000
+rx_delay=2000
+tx_delay=2000
+rx_fifo_size=524288
+tx_fifo_size=524288
+rx_filter=true
+hardware_address=00:90:00:00:00:01
+rx_thread=false
+tx_thread=false
+rss=false
+
+[system.tsunami.etherint]
+type=NSGigEInt
+peer=null
+device=system.tsunami.ethernet
+
+[system.tsunami.fake_OROM]
+type=IsaFake
+pio_addr=8796093677568
+pio_latency=2
+pio_size=393216
+platform=system.tsunami
+system=system
+
+[system.tsunami.uart]
+type=Uart8250
+pio_addr=8804615848952
+pio_latency=2
+platform=system.tsunami
+sim_console=system.sim_console
+system=system
+
+[system.tsunami.fake_sm_chip]
+type=IsaFake
+pio_addr=8804615848816
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_addr]
+type=IsaFake
+pio_addr=8804615848569
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.ide.configdata]
+type=PciConfigData
+VendorID=32902
+DeviceID=28945
+Command=0
+Status=640
+Revision=0
+ProgIF=133
+SubClassCode=1
+ClassCode=1
+CacheLineSize=0
+LatencyTimer=0
+HeaderType=0
+BIST=0
+BAR0=1
+BAR1=1
+BAR2=1
+BAR3=1
+BAR4=1
+BAR5=1
+CardbusCIS=0
+SubsystemVendorID=0
+SubsystemID=0
+ExpansionROM=0
+InterruptLine=31
+InterruptPin=1
+MinimumGrant=0
+MaximumLatency=0
+BAR0Size=8
+BAR1Size=4
+BAR2Size=8
+BAR3Size=4
+BAR4Size=16
+BAR5Size=0
+
+[system.tsunami.ide]
+type=IdeController
+system=system
+platform=system.tsunami
+configdata=system.tsunami.ide.configdata
+pci_bus=0
+pci_dev=0
+pci_func=0
+pio_latency=2
+config_latency=40
+disks=system.disk0 system.disk2
+
+[system.iobus]
+type=Bus
+bus_id=0
+
+[trace]
+flags=
+start=0
+cycle=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+pc_symbol=true
+intel_format=false
+trace_system=client
+
+[debug]
+break_cycles=
+
+[pseudo_inst]
+quiesce=true
+statistics=true
+checkpoint=true
+
--- /dev/null
+M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
+\rGot Configuration 623
+\rmemsize 8000000 pages 4000
+\rFirst free page after ROM 0xFFFFFC0000018000
+\rHWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
+\rkstart = 0xFFFFFC0000310000, kend = 0xFFFFFC00008064E8, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
+\rCPU Clock at 2000 MHz IntrClockFrequency=1024
+\rBooting with 2 processor(s)
+\rKSP: 0x20043FE8 PTBR 0x20
+\rKSP: 0x20043FE8 PTBR 0x20
+\rConsole Callback at 0x0, fixup at 0x0, crb offset: 0x790
+\rMemory cluster 0 [0 - 392]
+\rMemory cluster 1 [392 - 15992]
+\rInitalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
+\rConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8
+\rBootstraping CPU 1 with sp=0xFFFFFC0000076000
+\runix_boot_mem ends at FFFFFC0000078000
+\rk_argc = 0
+\rjumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1028)
+\rCallbackFixup 0 18000, t7=FFFFFC0000700000
+\rEntering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
+\rLinux version 2.6.8.1 (binkertn@ziff.eecs.umich.edu) (gcc version 3.4.3) #36 SMP Mon May 2 19:50:53 EDT 2005
+\rBooting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
+\rMajor Options: SMP LEGACY_START VERBOSE_MCHECK
+\rCommand line: root=/dev/hda1 console=ttyS0
+\rmemcluster 0, usage 1, start 0, end 392
+\rmemcluster 1, usage 0, start 392, end 16384
+\rfreeing pages 1030:16384
+\rreserving pages 1030:1031
+\rSMP: 2 CPUs probed -- cpu_present_mask = 3
+\rBuilt 1 zonelists
+\rKernel command line: root=/dev/hda1 console=ttyS0
+\rPID hash table entries: 1024 (order 10: 16384 bytes)
+\rUsing epoch = 1900
+\rConsole: colour dummy device 80x25
+\rDentry cache hash table entries: 32768 (order: 5, 262144 bytes)
+\rInode-cache hash table entries: 16384 (order: 4, 131072 bytes)
+\rMemory: 119072k/131072k available (3058k kernel code, 8680k reserved, 695k data, 480k init)
+\rMount-cache hash table entries: 512 (order: 0, 8192 bytes)
+\rper-CPU timeslice cutoff: 374.49 usecs.
+\rtask migration cache decay timeout: 0 msecs.
+\rSMP starting up secondaries.
+\rSlave CPU 1 console command START
+SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400
+\rBrought up 2 CPUs
+\rSMP: Total of 2 processors activated (8000.15 BogoMIPS).
+\rNET: Registered protocol family 16
+\rEISA bus registered
+\rpci: enabling save/restore of SRM state
+\rSCSI subsystem initialized
+\rsrm_env: version 0.0.5 loaded successfully
+\rInstalling knfsd (copyright (C) 1996 okir@monad.swb.de).
+\rInitializing Cryptographic API
+\rrtc: Standard PC (1900) epoch (1900) detected
+\rReal Time Clock Driver v1.12
+\rSerial: 8250/16550 driver $Revision: 1.90 $ 5 ports, IRQ sharing disabled
+\rttyS0 at I/O 0x3f8 (irq = 4) is a 8250
+\rloop: loaded (max 8 devices)
+\rUsing anticipatory io scheduler
+\rnbd: registered device at major 43
+\rsinic.c: M5 Simple Integrated NIC driver
+\rns83820.c: National Semiconductor DP83820 10/100/1000 driver.
+\reth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
+\reth0: enabling optical transceiver
+\reth0: ns83820 v0.20: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=sg
+\rUniform Multi-Platform E-IDE driver Revision: 7.00alpha2
+\ride: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
+\rPIIX4: IDE controller at PCI slot 0000:00:00.0
+\rPIIX4: chipset revision 0
+\rPIIX4: 100% native mode on irq 31
+\r ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
+\r ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
+\rhda: M5 IDE Disk, ATA DISK drive
+\rhdb: M5 IDE Disk, ATA DISK drive
+\ride0 at 0x8410-0x8417,0x8422 on irq 31
+\rhda: max request size: 128KiB
+\rhda: 163296 sectors (83 MB), CHS=162/16/63, UDMA(33)
+\r hda: hda1
+\rhdb: max request size: 128KiB
+\rhdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
+\r hdb: unknown partition table
+\rscsi0 : scsi_m5, version 1.73 [20040518], dev_size_mb=8, opts=0x0
+\r Vendor: Linux Model: scsi_m5 Li Rev: 0004
+\r Type: Direct-Access ANSI SCSI revision: 03
+\rSCSI device sda: 16384 512-byte hdwr sectors (8 MB)
+\rSCSI device sda: drive cache: write back
+\r sda: unknown partition table
+\rAttached scsi disk sda at scsi0, channel 0, id 0, lun 0
+\rmice: PS/2 mouse device common for all mice
+\rNET: Registered protocol family 2
+\rIP: routing cache hash table of 1024 buckets, 16Kbytes
+\rTCP: Hash tables configured (established 8192 bind 8192)
+\rip_conntrack version 2.1 (512 buckets, 4096 max) - 440 bytes per conntrack
+\rip_tables: (C) 2000-2002 Netfilter core team
+\rarp_tables: (C) 2002 David S. Miller
+\rInitializing IPsec netlink socket
+\rNET: Registered protocol family 1
+\rNET: Registered protocol family 17
+\rNET: Registered protocol family 15
+\rBridge firewalling registered
+\r802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
+\rAll bugs added by David S. Miller <davem@redhat.com>
+\rVFS: Mounted root (ext2 filesystem) readonly.
+\rFreeing unused kernel memory: 480k freed
+\r\rinit started: BusyBox v1.00-rc2 (2004.11.18-16:22+0000) multi-call binary
+
+PTXdist-0.7.0 (2004-11-18T11:23:40-0500)
+
+mounting filesystems...
+EXT2-fs warning: checktime reached, running e2fsck is recommended
+\rloading script...
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 677052 # Simulator instruction rate (inst/s)
+host_mem_usage 195656 # Number of bytes of host memory used
+host_seconds 93.44 # Real time elapsed on the host
+host_tick_rate 38056235 # Simulator tick rate (ticks/s)
+sim_freq 2000000000 # Frequency of simulated ticks
+sim_insts 63264995 # Number of instructions simulated
+sim_seconds 1.778030 # Number of seconds simulated
+sim_ticks 3556060806 # Number of ticks simulated
+system.cpu0.dtb.accesses 1831687 # DTB accesses
+system.cpu0.dtb.acv 360 # DTB access violations
+system.cpu0.dtb.hits 12876975 # DTB hits
+system.cpu0.dtb.misses 11050 # DTB misses
+system.cpu0.dtb.read_accesses 495437 # DTB read accesses
+system.cpu0.dtb.read_acv 219 # DTB read access violations
+system.cpu0.dtb.read_hits 7121424 # DTB read hits
+system.cpu0.dtb.read_misses 9036 # DTB read misses
+system.cpu0.dtb.write_accesses 1336250 # DTB write accesses
+system.cpu0.dtb.write_acv 141 # DTB write access violations
+system.cpu0.dtb.write_hits 5755551 # DTB write hits
+system.cpu0.dtb.write_misses 2014 # DTB write misses
+system.cpu0.idle_fraction 0.984569 # Percentage of idle cycles
+system.cpu0.itb.accesses 2328068 # ITB accesses
+system.cpu0.itb.acv 216 # ITB acv
+system.cpu0.itb.hits 2323500 # ITB hits
+system.cpu0.itb.misses 4568 # ITB misses
+system.cpu0.kern.callpal 179206 # number of callpals executed
+system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
+system.cpu0.kern.callpal_wripir 91 0.05% 0.05% # number of callpals executed
+system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed
+system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed
+system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed
+system.cpu0.kern.callpal_swpctx 1375 0.77% 0.82% # number of callpals executed
+system.cpu0.kern.callpal_tbi 20 0.01% 0.83% # number of callpals executed
+system.cpu0.kern.callpal_wrent 7 0.00% 0.84% # number of callpals executed
+system.cpu0.kern.callpal_swpipl 168681 94.13% 94.96% # number of callpals executed
+system.cpu0.kern.callpal_rdps 4713 2.63% 97.59% # number of callpals executed
+system.cpu0.kern.callpal_wrkgp 1 0.00% 97.59% # number of callpals executed
+system.cpu0.kern.callpal_wrusp 4 0.00% 97.59% # number of callpals executed
+system.cpu0.kern.callpal_rdusp 11 0.01% 97.60% # number of callpals executed
+system.cpu0.kern.callpal_whami 2 0.00% 97.60% # number of callpals executed
+system.cpu0.kern.callpal_rti 3639 2.03% 99.63% # number of callpals executed
+system.cpu0.kern.callpal_callsys 461 0.26% 99.89% # number of callpals executed
+system.cpu0.kern.callpal_imb 197 0.11% 100.00% # number of callpals executed
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.hwrei 197512 # number of hwrei instructions executed
+system.cpu0.kern.inst.ivlb 0 # number of ivlb instructions executed
+system.cpu0.kern.inst.ivle 0 # number of ivle instructions executed
+system.cpu0.kern.inst.quiesce 1917 # number of quiesce instructions executed
+system.cpu0.kern.ipl_count 174431 # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_0 73383 42.07% 42.07% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_21 286 0.16% 42.23% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_22 5540 3.18% 45.41% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_30 8 0.00% 45.41% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_31 95214 54.59% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_good 156222 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_0 73336 46.94% 46.94% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_21 286 0.18% 47.13% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_22 5540 3.55% 50.67% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_30 8 0.01% 50.68% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_31 77052 49.32% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks 3555570558 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_0 3533670973 99.38% 99.38% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_21 45785 0.00% 99.39% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_22 1008642 0.03% 99.41% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_30 1988 0.00% 99.41% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_31 20843170 0.59% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used 0.895609 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_0 0.999360 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_31 0.809251 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good_kernel 1633
+system.cpu0.kern.mode_good_user 1486
+system.cpu0.kern.mode_good_idle 147
+system.cpu0.kern.mode_switch_kernel 2898 # number of protection mode switches
+system.cpu0.kern.mode_switch_user 1486 # number of protection mode switches
+system.cpu0.kern.mode_switch_idle 2090 # number of protection mode switches
+system.cpu0.kern.mode_switch_good 0.504479 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_kernel 0.563492 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_idle 0.070335 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks_kernel 29671488 0.83% 0.83% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_user 2605758 0.07% 0.91% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_idle 3523245106 99.09% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context 1376 # number of times the context was actually changed
+system.cpu0.kern.syscall 312 # number of syscalls executed
+system.cpu0.kern.syscall_fork 9 2.88% 2.88% # number of syscalls executed
+system.cpu0.kern.syscall_read 20 6.41% 9.29% # number of syscalls executed
+system.cpu0.kern.syscall_write 6 1.92% 11.22% # number of syscalls executed
+system.cpu0.kern.syscall_close 36 11.54% 22.76% # number of syscalls executed
+system.cpu0.kern.syscall_chdir 1 0.32% 23.08% # number of syscalls executed
+system.cpu0.kern.syscall_chmod 1 0.32% 23.40% # number of syscalls executed
+system.cpu0.kern.syscall_obreak 26 8.33% 31.73% # number of syscalls executed
+system.cpu0.kern.syscall_lseek 9 2.88% 34.62% # number of syscalls executed
+system.cpu0.kern.syscall_getpid 8 2.56% 37.18% # number of syscalls executed
+system.cpu0.kern.syscall_setuid 2 0.64% 37.82% # number of syscalls executed
+system.cpu0.kern.syscall_getuid 4 1.28% 39.10% # number of syscalls executed
+system.cpu0.kern.syscall_access 4 1.28% 40.38% # number of syscalls executed
+system.cpu0.kern.syscall_dup 4 1.28% 41.67% # number of syscalls executed
+system.cpu0.kern.syscall_open 40 12.82% 54.49% # number of syscalls executed
+system.cpu0.kern.syscall_getgid 4 1.28% 55.77% # number of syscalls executed
+system.cpu0.kern.syscall_sigprocmask 12 3.85% 59.62% # number of syscalls executed
+system.cpu0.kern.syscall_ioctl 13 4.17% 63.78% # number of syscalls executed
+system.cpu0.kern.syscall_readlink 1 0.32% 64.10% # number of syscalls executed
+system.cpu0.kern.syscall_execve 7 2.24% 66.35% # number of syscalls executed
+system.cpu0.kern.syscall_pre_F64_stat 22 7.05% 73.40% # number of syscalls executed
+system.cpu0.kern.syscall_pre_F64_lstat 1 0.32% 73.72% # number of syscalls executed
+system.cpu0.kern.syscall_mmap 28 8.97% 82.69% # number of syscalls executed
+system.cpu0.kern.syscall_munmap 4 1.28% 83.97% # number of syscalls executed
+system.cpu0.kern.syscall_mprotect 7 2.24% 86.22% # number of syscalls executed
+system.cpu0.kern.syscall_gethostname 1 0.32% 86.54% # number of syscalls executed
+system.cpu0.kern.syscall_dup2 3 0.96% 87.50% # number of syscalls executed
+system.cpu0.kern.syscall_pre_F64_fstat 15 4.81% 92.31% # number of syscalls executed
+system.cpu0.kern.syscall_fcntl 11 3.53% 95.83% # number of syscalls executed
+system.cpu0.kern.syscall_socket 3 0.96% 96.79% # number of syscalls executed
+system.cpu0.kern.syscall_connect 3 0.96% 97.76% # number of syscalls executed
+system.cpu0.kern.syscall_setgid 2 0.64% 98.40% # number of syscalls executed
+system.cpu0.kern.syscall_getrlimit 2 0.64% 99.04% # number of syscalls executed
+system.cpu0.kern.syscall_setsid 3 0.96% 100.00% # number of syscalls executed
+system.cpu0.not_idle_fraction 0.015431 # Percentage of non-idle cycles
+system.cpu0.numCycles 54873632 # number of cpu cycles simulated
+system.cpu0.num_insts 54868848 # Number of instructions executed
+system.cpu0.num_refs 12918621 # Number of memory references
+system.cpu1.dtb.accesses 524398 # DTB accesses
+system.cpu1.dtb.acv 60 # DTB access violations
+system.cpu1.dtb.hits 2058922 # DTB hits
+system.cpu1.dtb.misses 5263 # DTB misses
+system.cpu1.dtb.read_accesses 337746 # DTB read accesses
+system.cpu1.dtb.read_acv 23 # DTB read access violations
+system.cpu1.dtb.read_hits 1301369 # DTB read hits
+system.cpu1.dtb.read_misses 4766 # DTB read misses
+system.cpu1.dtb.write_accesses 186652 # DTB write accesses
+system.cpu1.dtb.write_acv 37 # DTB write access violations
+system.cpu1.dtb.write_hits 757553 # DTB write hits
+system.cpu1.dtb.write_misses 497 # DTB write misses
+system.cpu1.idle_fraction 0.997638 # Percentage of idle cycles
+system.cpu1.itb.accesses 1711917 # ITB accesses
+system.cpu1.itb.acv 23 # ITB acv
+system.cpu1.itb.hits 1709682 # ITB hits
+system.cpu1.itb.misses 2235 # ITB misses
+system.cpu1.kern.callpal 25990 # number of callpals executed
+system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
+system.cpu1.kern.callpal_wripir 8 0.03% 0.03% # number of callpals executed
+system.cpu1.kern.callpal_wrmces 1 0.00% 0.04% # number of callpals executed
+system.cpu1.kern.callpal_wrfen 1 0.00% 0.04% # number of callpals executed
+system.cpu1.kern.callpal_swpctx 554 2.13% 2.17% # number of callpals executed
+system.cpu1.kern.callpal_tbi 7 0.03% 2.20% # number of callpals executed
+system.cpu1.kern.callpal_wrent 7 0.03% 2.23% # number of callpals executed
+system.cpu1.kern.callpal_swpipl 22366 86.06% 88.28% # number of callpals executed
+system.cpu1.kern.callpal_rdps 98 0.38% 88.66% # number of callpals executed
+system.cpu1.kern.callpal_wrkgp 1 0.00% 88.66% # number of callpals executed
+system.cpu1.kern.callpal_wrusp 4 0.02% 88.68% # number of callpals executed
+system.cpu1.kern.callpal_rdusp 1 0.00% 88.68% # number of callpals executed
+system.cpu1.kern.callpal_whami 3 0.01% 88.70% # number of callpals executed
+system.cpu1.kern.callpal_rti 2613 10.05% 98.75% # number of callpals executed
+system.cpu1.kern.callpal_callsys 208 0.80% 99.55% # number of callpals executed
+system.cpu1.kern.callpal_imb 116 0.45% 100.00% # number of callpals executed
+system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.hwrei 35475 # number of hwrei instructions executed
+system.cpu1.kern.inst.ivlb 0 # number of ivlb instructions executed
+system.cpu1.kern.inst.ivle 0 # number of ivle instructions executed
+system.cpu1.kern.inst.quiesce 1946 # number of quiesce instructions executed
+system.cpu1.kern.ipl_count 26882 # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_0 9636 35.85% 35.85% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_22 5504 20.47% 56.32% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_30 91 0.34% 56.66% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_31 11651 43.34% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_good 26602 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_0 9607 36.11% 36.11% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_22 5504 20.69% 56.80% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_30 91 0.34% 57.15% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_31 11400 42.85% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks 3556060349 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_0 3533823708 99.37% 99.37% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_22 1040434 0.03% 99.40% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_30 23860 0.00% 99.40% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_31 21172347 0.60% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used 0.989584 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_0 0.996990 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_31 0.978457 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.mode_good_kernel 691
+system.cpu1.kern.mode_good_user 692
+system.cpu1.kern.mode_good_idle 0
+system.cpu1.kern.mode_switch_kernel 3163 # number of protection mode switches
+system.cpu1.kern.mode_switch_user 692 # number of protection mode switches
+system.cpu1.kern.mode_switch_idle 0 # number of protection mode switches
+system.cpu1.kern.mode_switch_good 0.358755 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_kernel 0.218463 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks_kernel 3554209770 99.95% 99.95% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_user 1850577 0.05% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 555 # number of times the context was actually changed
+system.cpu1.kern.syscall 163 # number of syscalls executed
+system.cpu1.kern.syscall_fork 1 0.61% 0.61% # number of syscalls executed
+system.cpu1.kern.syscall_read 13 7.98% 8.59% # number of syscalls executed
+system.cpu1.kern.syscall_write 1 0.61% 9.20% # number of syscalls executed
+system.cpu1.kern.syscall_close 13 7.98% 17.18% # number of syscalls executed
+system.cpu1.kern.syscall_obreak 18 11.04% 28.22% # number of syscalls executed
+system.cpu1.kern.syscall_lseek 4 2.45% 30.67% # number of syscalls executed
+system.cpu1.kern.syscall_getpid 2 1.23% 31.90% # number of syscalls executed
+system.cpu1.kern.syscall_setuid 2 1.23% 33.13% # number of syscalls executed
+system.cpu1.kern.syscall_getuid 4 2.45% 35.58% # number of syscalls executed
+system.cpu1.kern.syscall_open 28 17.18% 52.76% # number of syscalls executed
+system.cpu1.kern.syscall_getgid 4 2.45% 55.21% # number of syscalls executed
+system.cpu1.kern.syscall_sigprocmask 2 1.23% 56.44% # number of syscalls executed
+system.cpu1.kern.syscall_ioctl 3 1.84% 58.28% # number of syscalls executed
+system.cpu1.kern.syscall_readlink 1 0.61% 58.90% # number of syscalls executed
+system.cpu1.kern.syscall_execve 1 0.61% 59.51% # number of syscalls executed
+system.cpu1.kern.syscall_pre_F64_stat 9 5.52% 65.03% # number of syscalls executed
+system.cpu1.kern.syscall_mmap 27 16.56% 81.60% # number of syscalls executed
+system.cpu1.kern.syscall_munmap 2 1.23% 82.82% # number of syscalls executed
+system.cpu1.kern.syscall_mprotect 7 4.29% 87.12% # number of syscalls executed
+system.cpu1.kern.syscall_gethostname 1 0.61% 87.73% # number of syscalls executed
+system.cpu1.kern.syscall_dup2 1 0.61% 88.34% # number of syscalls executed
+system.cpu1.kern.syscall_pre_F64_fstat 13 7.98% 96.32% # number of syscalls executed
+system.cpu1.kern.syscall_fcntl 3 1.84% 98.16% # number of syscalls executed
+system.cpu1.kern.syscall_setgid 2 1.23% 99.39% # number of syscalls executed
+system.cpu1.kern.syscall_getrlimit 1 0.61% 100.00% # number of syscalls executed
+system.cpu1.not_idle_fraction 0.002362 # Percentage of non-idle cycles
+system.cpu1.numCycles 8398405 # number of cpu cycles simulated
+system.cpu1.num_insts 8396147 # Number of instructions executed
+system.cpu1.num_refs 2073144 # Number of memory references
+system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_bytes 2521088 # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_full_pages 285 # Number of full page size DMA writes.
+system.disk0.dma_write_txs 375 # Number of DMA write transactions.
+system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
+system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
+system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
+system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+
+---------- End Simulation Statistics ----------
--- /dev/null
+ 0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006
+Listening for console connection on port 3457
+0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001
+0: system.remote_gdb.listener: listening for remote gdb #1 on port 7002
+warn: Entering event queue @ 0. Starting simulation...
+warn: 195722: Trying to launch CPU number 1!
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 27 2006 16:54:00
+M5 started Thu Jul 27 17:12:14 2006
+M5 executing on zamp.eecs.umich.edu
+command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/test/opt/linux-mpboot/atomic tests/linux-mpboot/run.py
+Exiting @ cycle 3556060806 because m5_exit instruction encountered
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=2000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[debug]
+break_cycles=
+
+[exetrace]
+intel_format=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=LinuxAlphaSystem
+children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami
+boot_cpu_frequency=1
+boot_osflags=root=/dev/hda1 console=ttyS0
+console=/dist/m5/system/binaries/console
+init_param=0
+kernel=/dist/m5/system/binaries/vmlinux
+mem_mode=timing
+pal=/dist/m5/system/binaries/ts_osfpal
+physmem=system.physmem
+readfile=/z/ktlim2/clean/newmem-merge/tests/halt.sh
+system_rev=1024
+system_type=34
+
+[system.bridge]
+type=Bridge
+delay=0
+queue_size_a=16
+queue_size_b=16
+write_ack=false
+
+[system.cpu0]
+type=TimingSimpleCPU
+children=dtb itb
+clock=1
+cpu_id=-1
+defer_registration=false
+dtb=system.cpu0.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.membus
+profile=0
+system=system
+
+[system.cpu0.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu0.itb]
+type=AlphaITB
+size=48
+
+[system.cpu1]
+type=TimingSimpleCPU
+children=dtb itb
+clock=1
+cpu_id=-1
+defer_registration=false
+dtb=system.cpu1.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.membus
+profile=0
+system=system
+
+[system.cpu1.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu1.itb]
+type=AlphaITB
+size=48
+
+[system.disk0]
+type=IdeDisk
+children=image
+delay=2000
+driveID=master
+image=system.disk0.image
+
+[system.disk0.image]
+type=CowDiskImage
+children=child
+child=system.disk0.image.child
+read_only=false
+table_size=65536
+
+[system.disk0.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.disk2]
+type=IdeDisk
+children=image
+delay=2000
+driveID=master
+image=system.disk2.image
+
+[system.disk2.image]
+type=CowDiskImage
+children=child
+child=system.disk2.image.child
+read_only=false
+table_size=65536
+
+[system.disk2.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-bigswap2.img
+read_only=true
+
+[system.intrctrl]
+type=IntrControl
+cpu=system.cpu0
+
+[system.iobus]
+type=Bus
+bus_id=0
+
+[system.membus]
+type=Bus
+bus_id=1
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+
+[system.sim_console]
+type=SimConsole
+children=listener
+append_name=true
+intr_control=system.intrctrl
+listener=system.sim_console.listener
+number=0
+output=console
+
+[system.sim_console.listener]
+type=ConsoleListener
+port=3456
+
+[system.simple_disk]
+type=SimpleDisk
+children=disk
+disk=system.simple_disk.disk
+system=system
+
+[system.simple_disk.disk]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.tsunami]
+type=Tsunami
+children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+intrctrl=system.intrctrl
+system=system
+
+[system.tsunami.cchip]
+type=TsunamiCChip
+pio_addr=8803072344064
+pio_latency=2
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+
+[system.tsunami.console]
+type=AlphaConsole
+cpu=system.cpu0
+disk=system.simple_disk
+pio_addr=8804682956800
+pio_latency=2
+platform=system.tsunami
+sim_console=system.sim_console
+system=system
+
+[system.tsunami.etherint]
+type=NSGigEInt
+device=system.tsunami.ethernet
+peer=Null
+
+[system.tsunami.ethernet]
+type=NSGigE
+children=configdata
+clock=0
+config_latency=40
+configdata=system.tsunami.ethernet.configdata
+dma_data_free=false
+dma_desc_free=false
+dma_no_allocate=true
+dma_read_delay=0
+dma_read_factor=0
+dma_write_delay=0
+dma_write_factor=0
+hardware_address=00:90:00:00:00:01
+intr_delay=20000
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=2
+platform=system.tsunami
+rss=false
+rx_delay=2000
+rx_fifo_size=524288
+rx_filter=true
+rx_thread=false
+system=system
+tx_delay=2000
+tx_fifo_size=524288
+tx_thread=false
+
+[system.tsunami.ethernet.configdata]
+type=PciConfigData
+BAR0=1
+BAR0Size=256
+BAR1=0
+BAR1Size=4096
+BAR2=0
+BAR2Size=0
+BAR3=0
+BAR3Size=0
+BAR4=0
+BAR4Size=0
+BAR5=0
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=34
+ExpansionROM=0
+HeaderType=0
+InterruptLine=30
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=52
+MinimumGrant=176
+ProgIF=0
+Revision=0
+Status=656
+SubClassCode=0
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=4107
+
+[system.tsunami.fake_OROM]
+type=IsaFake
+pio_addr=8796093677568
+pio_latency=2
+pio_size=393216
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_ata0]
+type=IsaFake
+pio_addr=8804615848432
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_ata1]
+type=IsaFake
+pio_addr=8804615848304
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_addr]
+type=IsaFake
+pio_addr=8804615848569
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read0]
+type=IsaFake
+pio_addr=8804615848451
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read1]
+type=IsaFake
+pio_addr=8804615848515
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read2]
+type=IsaFake
+pio_addr=8804615848579
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read3]
+type=IsaFake
+pio_addr=8804615848643
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read4]
+type=IsaFake
+pio_addr=8804615848707
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read5]
+type=IsaFake
+pio_addr=8804615848771
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read6]
+type=IsaFake
+pio_addr=8804615848835
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read7]
+type=IsaFake
+pio_addr=8804615848899
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_write]
+type=IsaFake
+pio_addr=8804615850617
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_ppc]
+type=IsaFake
+pio_addr=8804615848892
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_sm_chip]
+type=IsaFake
+pio_addr=8804615848816
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart1]
+type=IsaFake
+pio_addr=8804615848696
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart2]
+type=IsaFake
+pio_addr=8804615848936
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart3]
+type=IsaFake
+pio_addr=8804615848680
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart4]
+type=IsaFake
+pio_addr=8804615848944
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fb]
+type=BadDevice
+devicename=FrameBuffer
+pio_addr=8804615848912
+pio_latency=2
+platform=system.tsunami
+system=system
+
+[system.tsunami.ide]
+type=IdeController
+children=configdata
+config_latency=40
+configdata=system.tsunami.ide.configdata
+disks=system.disk0 system.disk2
+pci_bus=0
+pci_dev=0
+pci_func=0
+pio_latency=2
+platform=system.tsunami
+system=system
+
+[system.tsunami.ide.configdata]
+type=PciConfigData
+BAR0=1
+BAR0Size=8
+BAR1=1
+BAR1Size=4
+BAR2=1
+BAR2Size=8
+BAR3=1
+BAR3Size=4
+BAR4=1
+BAR4Size=16
+BAR5=1
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+
+[system.tsunami.io]
+type=TsunamiIO
+frequency=1953125
+pio_addr=8804615847936
+pio_latency=2
+platform=system.tsunami
+system=system
+time=1136073600
+tsunami=system.tsunami
+
+[system.tsunami.pchip]
+type=TsunamiPChip
+pio_addr=8802535473152
+pio_latency=2
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+
+[system.tsunami.pciconfig]
+type=PciConfigAll
+bus=0
+pio_latency=1
+platform=system.tsunami
+size=16777216
+system=system
+
+[system.tsunami.uart]
+type=Uart8250
+pio_addr=8804615848952
+pio_latency=2
+platform=system.tsunami
+sim_console=system.sim_console
+system=system
+
+[trace]
+bufsize=0
+cycle=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
--- /dev/null
+[root]
+type=Root
+clock=2000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+
+[system]
+type=LinuxAlphaSystem
+boot_cpu_frequency=1
+physmem=system.physmem
+mem_mode=timing
+kernel=/dist/m5/system/binaries/vmlinux
+console=/dist/m5/system/binaries/console
+pal=/dist/m5/system/binaries/ts_osfpal
+boot_osflags=root=/dev/hda1 console=ttyS0
+readfile=/z/ktlim2/clean/newmem-merge/tests/halt.sh
+init_param=0
+system_type=34
+system_rev=1024
+
+[system.membus]
+type=Bus
+bus_id=1
+
+[system.bridge]
+type=Bridge
+queue_size_a=16
+queue_size_b=16
+delay=0
+write_ack=false
+
+[system.disk0.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.disk0.image]
+type=CowDiskImage
+child=system.disk0.image.child
+image_file=
+table_size=65536
+read_only=false
+
+[system.disk0]
+type=IdeDisk
+image=system.disk0.image
+driveID=master
+delay=2000
+
+[system.disk2.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-bigswap2.img
+read_only=true
+
+[system.disk2.image]
+type=CowDiskImage
+child=system.disk2.image.child
+image_file=
+table_size=65536
+read_only=false
+
+[system.disk2]
+type=IdeDisk
+image=system.disk2.image
+driveID=master
+delay=2000
+
+[system.cpu0.itb]
+type=AlphaITB
+size=48
+
+[system.cpu0.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu0]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+mem=system.membus
+system=system
+itb=system.cpu0.itb
+dtb=system.cpu0.dtb
+cpu_id=-1
+profile=0
+clock=1
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu1.itb]
+type=AlphaITB
+size=48
+
+[system.cpu1.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu1]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+mem=system.membus
+system=system
+itb=system.cpu1.itb
+dtb=system.cpu1.dtb
+cpu_id=-1
+profile=0
+clock=1
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.intrctrl]
+type=IntrControl
+cpu=system.cpu0
+
+[system.simple_disk.disk]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.simple_disk]
+type=SimpleDisk
+system=system
+disk=system.simple_disk.disk
+
+[system.tsunami]
+type=Tsunami
+system=system
+intrctrl=system.intrctrl
+
+[system.tsunami.fake_uart1]
+type=IsaFake
+pio_addr=8804615848696
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart2]
+type=IsaFake
+pio_addr=8804615848936
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart3]
+type=IsaFake
+pio_addr=8804615848680
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_uart4]
+type=IsaFake
+pio_addr=8804615848944
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_ppc]
+type=IsaFake
+pio_addr=8804615848892
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.cchip]
+type=TsunamiCChip
+pio_addr=8803072344064
+pio_latency=2
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+
+[system.tsunami.io]
+type=TsunamiIO
+pio_addr=8804615847936
+pio_latency=2
+frequency=1953125
+platform=system.tsunami
+system=system
+time=1136073600
+tsunami=system.tsunami
+
+[]
+type=PciConfigAll
+pio_latency=1
+bus=0
+size=16777216
+platform=system.tsunami
+system=system
+
+[system.sim_console.listener]
+type=ConsoleListener
+port=3456
+
+[system.sim_console]
+type=SimConsole
+listener=system.sim_console.listener
+intr_control=system.intrctrl
+output=console
+append_name=true
+number=0
+
+[system.tsunami.console]
+type=AlphaConsole
+sim_console=system.sim_console
+disk=system.simple_disk
+pio_addr=8804682956800
+system=system
+cpu=system.cpu0
+platform=system.tsunami
+pio_latency=2
+
+[system.tsunami.fake_ata1]
+type=IsaFake
+pio_addr=8804615848304
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_ata0]
+type=IsaFake
+pio_addr=8804615848432
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.pchip]
+type=TsunamiPChip
+pio_addr=8802535473152
+pio_latency=2
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+
+[system.tsunami.fake_pnp_read3]
+type=IsaFake
+pio_addr=8804615848643
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read2]
+type=IsaFake
+pio_addr=8804615848579
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read1]
+type=IsaFake
+pio_addr=8804615848515
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read0]
+type=IsaFake
+pio_addr=8804615848451
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read7]
+type=IsaFake
+pio_addr=8804615848899
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read6]
+type=IsaFake
+pio_addr=8804615848835
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read5]
+type=IsaFake
+pio_addr=8804615848771
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_read4]
+type=IsaFake
+pio_addr=8804615848707
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_write]
+type=IsaFake
+pio_addr=8804615850617
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fb]
+type=BadDevice
+devicename=FrameBuffer
+pio_addr=8804615848912
+system=system
+platform=system.tsunami
+pio_latency=2
+
+[system.tsunami.ethernet.configdata]
+type=PciConfigData
+VendorID=4107
+DeviceID=34
+Command=0
+Status=656
+Revision=0
+ProgIF=0
+SubClassCode=0
+ClassCode=2
+CacheLineSize=0
+LatencyTimer=0
+HeaderType=0
+BIST=0
+BAR0=1
+BAR1=0
+BAR2=0
+BAR3=0
+BAR4=0
+BAR5=0
+CardbusCIS=0
+SubsystemVendorID=0
+SubsystemID=0
+ExpansionROM=0
+InterruptLine=30
+InterruptPin=1
+MinimumGrant=176
+MaximumLatency=52
+BAR0Size=256
+BAR1Size=4096
+BAR2Size=0
+BAR3Size=0
+BAR4Size=0
+BAR5Size=0
+
+[system.tsunami.ethernet]
+type=NSGigE
+system=system
+platform=system.tsunami
+configdata=system.tsunami.ethernet.configdata
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=2
+config_latency=40
+clock=0
+dma_desc_free=false
+dma_data_free=false
+dma_read_delay=0
+dma_write_delay=0
+dma_read_factor=0
+dma_write_factor=0
+dma_no_allocate=true
+intr_delay=20000
+rx_delay=2000
+tx_delay=2000
+rx_fifo_size=524288
+tx_fifo_size=524288
+rx_filter=true
+hardware_address=00:90:00:00:00:01
+rx_thread=false
+tx_thread=false
+rss=false
+
+[system.tsunami.etherint]
+type=NSGigEInt
+peer=null
+device=system.tsunami.ethernet
+
+[system.tsunami.fake_OROM]
+type=IsaFake
+pio_addr=8796093677568
+pio_latency=2
+pio_size=393216
+platform=system.tsunami
+system=system
+
+[system.tsunami.uart]
+type=Uart8250
+pio_addr=8804615848952
+pio_latency=2
+platform=system.tsunami
+sim_console=system.sim_console
+system=system
+
+[system.tsunami.fake_sm_chip]
+type=IsaFake
+pio_addr=8804615848816
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.fake_pnp_addr]
+type=IsaFake
+pio_addr=8804615848569
+pio_latency=2
+pio_size=8
+platform=system.tsunami
+system=system
+
+[system.tsunami.ide.configdata]
+type=PciConfigData
+VendorID=32902
+DeviceID=28945
+Command=0
+Status=640
+Revision=0
+ProgIF=133
+SubClassCode=1
+ClassCode=1
+CacheLineSize=0
+LatencyTimer=0
+HeaderType=0
+BIST=0
+BAR0=1
+BAR1=1
+BAR2=1
+BAR3=1
+BAR4=1
+BAR5=1
+CardbusCIS=0
+SubsystemVendorID=0
+SubsystemID=0
+ExpansionROM=0
+InterruptLine=31
+InterruptPin=1
+MinimumGrant=0
+MaximumLatency=0
+BAR0Size=8
+BAR1Size=4
+BAR2Size=8
+BAR3Size=4
+BAR4Size=16
+BAR5Size=0
+
+[system.tsunami.ide]
+type=IdeController
+system=system
+platform=system.tsunami
+configdata=system.tsunami.ide.configdata
+pci_bus=0
+pci_dev=0
+pci_func=0
+pio_latency=2
+config_latency=40
+disks=system.disk0 system.disk2
+
+[system.iobus]
+type=Bus
+bus_id=0
+
+[trace]
+flags=
+start=0
+cycle=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+pc_symbol=true
+intel_format=false
+trace_system=client
+
+[debug]
+break_cycles=
+
+[pseudo_inst]
+quiesce=true
+statistics=true
+checkpoint=true
+
--- /dev/null
+M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
+\rGot Configuration 623
+\rmemsize 8000000 pages 4000
+\rFirst free page after ROM 0xFFFFFC0000018000
+\rHWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
+\rkstart = 0xFFFFFC0000310000, kend = 0xFFFFFC00008064E8, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
+\rCPU Clock at 2000 MHz IntrClockFrequency=1024
+\rBooting with 2 processor(s)
+\rKSP: 0x20043FE8 PTBR 0x20
+\rKSP: 0x20043FE8 PTBR 0x20
+\rConsole Callback at 0x0, fixup at 0x0, crb offset: 0x790
+\rMemory cluster 0 [0 - 392]
+\rMemory cluster 1 [392 - 15992]
+\rInitalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
+\rConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8
+\rBootstraping CPU 1 with sp=0xFFFFFC0000076000
+\runix_boot_mem ends at FFFFFC0000078000
+\rk_argc = 0
+\rjumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1028)
+\rCallbackFixup 0 18000, t7=FFFFFC0000700000
+\rEntering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
+\rLinux version 2.6.8.1 (binkertn@ziff.eecs.umich.edu) (gcc version 3.4.3) #36 SMP Mon May 2 19:50:53 EDT 2005
+\rBooting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
+\rMajor Options: SMP LEGACY_START VERBOSE_MCHECK
+\rCommand line: root=/dev/hda1 console=ttyS0
+\rmemcluster 0, usage 1, start 0, end 392
+\rmemcluster 1, usage 0, start 392, end 16384
+\rfreeing pages 1030:16384
+\rreserving pages 1030:1031
+\rSMP: 2 CPUs probed -- cpu_present_mask = 3
+\rBuilt 1 zonelists
+\rKernel command line: root=/dev/hda1 console=ttyS0
+\rPID hash table entries: 1024 (order 10: 16384 bytes)
+\rUsing epoch = 1900
+\rConsole: colour dummy device 80x25
+\rDentry cache hash table entries: 32768 (order: 5, 262144 bytes)
+\rInode-cache hash table entries: 16384 (order: 4, 131072 bytes)
+\rMemory: 119072k/131072k available (3058k kernel code, 8680k reserved, 695k data, 480k init)
+\rMount-cache hash table entries: 512 (order: 0, 8192 bytes)
+\rper-CPU timeslice cutoff: 374.49 usecs.
+\rtask migration cache decay timeout: 0 msecs.
+\rSMP starting up secondaries.
+\rSlave CPU 1 console command START
+SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400
+\rBrought up 2 CPUs
+\rSMP: Total of 2 processors activated (8000.15 BogoMIPS).
+\rNET: Registered protocol family 16
+\rEISA bus registered
+\rpci: enabling save/restore of SRM state
+\rSCSI subsystem initialized
+\rsrm_env: version 0.0.5 loaded successfully
+\rInstalling knfsd (copyright (C) 1996 okir@monad.swb.de).
+\rInitializing Cryptographic API
+\rrtc: Standard PC (1900) epoch (1900) detected
+\rReal Time Clock Driver v1.12
+\rSerial: 8250/16550 driver $Revision: 1.90 $ 5 ports, IRQ sharing disabled
+\rttyS0 at I/O 0x3f8 (irq = 4) is a 8250
+\rloop: loaded (max 8 devices)
+\rUsing anticipatory io scheduler
+\rnbd: registered device at major 43
+\rsinic.c: M5 Simple Integrated NIC driver
+\rns83820.c: National Semiconductor DP83820 10/100/1000 driver.
+\reth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
+\reth0: enabling optical transceiver
+\reth0: ns83820 v0.20: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=sg
+\rUniform Multi-Platform E-IDE driver Revision: 7.00alpha2
+\ride: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
+\rPIIX4: IDE controller at PCI slot 0000:00:00.0
+\rPIIX4: chipset revision 0
+\rPIIX4: 100% native mode on irq 31
+\r ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
+\r ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
+\rhda: M5 IDE Disk, ATA DISK drive
+\rhdb: M5 IDE Disk, ATA DISK drive
+\ride0 at 0x8410-0x8417,0x8422 on irq 31
+\rhda: max request size: 128KiB
+\rhda: 163296 sectors (83 MB), CHS=162/16/63, UDMA(33)
+\r hda: hda1
+\rhdb: max request size: 128KiB
+\rhdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
+\r hdb: unknown partition table
+\rscsi0 : scsi_m5, version 1.73 [20040518], dev_size_mb=8, opts=0x0
+\r Vendor: Linux Model: scsi_m5 Li Rev: 0004
+\r Type: Direct-Access ANSI SCSI revision: 03
+\rSCSI device sda: 16384 512-byte hdwr sectors (8 MB)
+\rSCSI device sda: drive cache: write back
+\r sda: unknown partition table
+\rAttached scsi disk sda at scsi0, channel 0, id 0, lun 0
+\rmice: PS/2 mouse device common for all mice
+\rNET: Registered protocol family 2
+\rIP: routing cache hash table of 1024 buckets, 16Kbytes
+\rTCP: Hash tables configured (established 8192 bind 8192)
+\rip_conntrack version 2.1 (512 buckets, 4096 max) - 440 bytes per conntrack
+\rip_tables: (C) 2000-2002 Netfilter core team
+\rarp_tables: (C) 2002 David S. Miller
+\rInitializing IPsec netlink socket
+\rNET: Registered protocol family 1
+\rNET: Registered protocol family 17
+\rNET: Registered protocol family 15
+\rBridge firewalling registered
+\r802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
+\rAll bugs added by David S. Miller <davem@redhat.com>
+\rVFS: Mounted root (ext2 filesystem) readonly.
+\rFreeing unused kernel memory: 480k freed
+\r\rinit started: BusyBox v1.00-rc2 (2004.11.18-16:22+0000) multi-call binary
+
+PTXdist-0.7.0 (2004-11-18T11:23:40-0500)
+
+mounting filesystems...
+EXT2-fs warning: checktime reached, running e2fsck is recommended
+\rloading script...
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 502011 # Simulator instruction rate (inst/s)
+host_mem_usage 195696 # Number of bytes of host memory used
+host_seconds 125.67 # Real time elapsed on the host
+host_tick_rate 28164267 # Simulator tick rate (ticks/s)
+sim_freq 2000000000 # Frequency of simulated ticks
+sim_insts 63088076 # Number of instructions simulated
+sim_seconds 1.769718 # Number of seconds simulated
+sim_ticks 3539435029 # Number of ticks simulated
+system.cpu0.dtb.accesses 1831687 # DTB accesses
+system.cpu0.dtb.acv 360 # DTB access violations
+system.cpu0.dtb.hits 10286150 # DTB hits
+system.cpu0.dtb.misses 11050 # DTB misses
+system.cpu0.dtb.read_accesses 495437 # DTB read accesses
+system.cpu0.dtb.read_acv 219 # DTB read access violations
+system.cpu0.dtb.read_hits 5741423 # DTB read hits
+system.cpu0.dtb.read_misses 9036 # DTB read misses
+system.cpu0.dtb.write_accesses 1336250 # DTB write accesses
+system.cpu0.dtb.write_acv 141 # DTB write access violations
+system.cpu0.dtb.write_hits 4544727 # DTB write hits
+system.cpu0.dtb.write_misses 2014 # DTB write misses
+system.cpu0.idle_fraction 0.984526 # Percentage of idle cycles
+system.cpu0.itb.accesses 2328068 # ITB accesses
+system.cpu0.itb.acv 216 # ITB acv
+system.cpu0.itb.hits 2323500 # ITB hits
+system.cpu0.itb.misses 4568 # ITB misses
+system.cpu0.kern.callpal 145575 # number of callpals executed
+system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
+system.cpu0.kern.callpal_wripir 45 0.03% 0.03% # number of callpals executed
+system.cpu0.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed
+system.cpu0.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed
+system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.03% # number of callpals executed
+system.cpu0.kern.callpal_swpctx 1334 0.92% 0.95% # number of callpals executed
+system.cpu0.kern.callpal_tbi 20 0.01% 0.96% # number of callpals executed
+system.cpu0.kern.callpal_wrent 7 0.00% 0.97% # number of callpals executed
+system.cpu0.kern.callpal_swpipl 135235 92.90% 93.87% # number of callpals executed
+system.cpu0.kern.callpal_rdps 4594 3.16% 97.02% # number of callpals executed
+system.cpu0.kern.callpal_wrkgp 1 0.00% 97.02% # number of callpals executed
+system.cpu0.kern.callpal_wrusp 4 0.00% 97.02% # number of callpals executed
+system.cpu0.kern.callpal_rdusp 11 0.01% 97.03% # number of callpals executed
+system.cpu0.kern.callpal_whami 2 0.00% 97.03% # number of callpals executed
+system.cpu0.kern.callpal_rti 3660 2.51% 99.55% # number of callpals executed
+system.cpu0.kern.callpal_callsys 461 0.32% 99.86% # number of callpals executed
+system.cpu0.kern.callpal_imb 197 0.14% 100.00% # number of callpals executed
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.hwrei 163916 # number of hwrei instructions executed
+system.cpu0.kern.inst.ivlb 0 # number of ivlb instructions executed
+system.cpu0.kern.inst.ivle 0 # number of ivle instructions executed
+system.cpu0.kern.inst.quiesce 1952 # number of quiesce instructions executed
+system.cpu0.kern.ipl_count 141041 # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_0 56950 40.38% 40.38% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_21 286 0.20% 40.58% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_22 5513 3.91% 44.49% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_30 52 0.04% 44.53% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_31 78240 55.47% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_good 123339 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_0 56917 46.15% 46.15% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_21 286 0.23% 46.38% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_22 5513 4.47% 50.85% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_30 52 0.04% 50.89% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_31 60571 49.11% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks 3539063979 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_0 3513499166 99.28% 99.28% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_21 60705 0.00% 99.28% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_22 1354114 0.04% 99.32% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_30 18748 0.00% 99.32% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_31 24131246 0.68% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used 0.874490 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_0 0.999421 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_31 0.774169 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good_kernel 1632
+system.cpu0.kern.mode_good_user 1487
+system.cpu0.kern.mode_good_idle 145
+system.cpu0.kern.mode_switch_kernel 2857 # number of protection mode switches
+system.cpu0.kern.mode_switch_user 1487 # number of protection mode switches
+system.cpu0.kern.mode_switch_idle 2125 # number of protection mode switches
+system.cpu0.kern.mode_switch_good 0.504560 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_kernel 0.571229 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_idle 0.068235 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks_kernel 23634401 0.67% 0.67% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_user 3241731 0.09% 0.76% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_idle 3511854943 99.24% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context 1335 # number of times the context was actually changed
+system.cpu0.kern.syscall 312 # number of syscalls executed
+system.cpu0.kern.syscall_fork 9 2.88% 2.88% # number of syscalls executed
+system.cpu0.kern.syscall_read 20 6.41% 9.29% # number of syscalls executed
+system.cpu0.kern.syscall_write 6 1.92% 11.22% # number of syscalls executed
+system.cpu0.kern.syscall_close 36 11.54% 22.76% # number of syscalls executed
+system.cpu0.kern.syscall_chdir 1 0.32% 23.08% # number of syscalls executed
+system.cpu0.kern.syscall_chmod 1 0.32% 23.40% # number of syscalls executed
+system.cpu0.kern.syscall_obreak 26 8.33% 31.73% # number of syscalls executed
+system.cpu0.kern.syscall_lseek 9 2.88% 34.62% # number of syscalls executed
+system.cpu0.kern.syscall_getpid 8 2.56% 37.18% # number of syscalls executed
+system.cpu0.kern.syscall_setuid 2 0.64% 37.82% # number of syscalls executed
+system.cpu0.kern.syscall_getuid 4 1.28% 39.10% # number of syscalls executed
+system.cpu0.kern.syscall_access 4 1.28% 40.38% # number of syscalls executed
+system.cpu0.kern.syscall_dup 4 1.28% 41.67% # number of syscalls executed
+system.cpu0.kern.syscall_open 40 12.82% 54.49% # number of syscalls executed
+system.cpu0.kern.syscall_getgid 4 1.28% 55.77% # number of syscalls executed
+system.cpu0.kern.syscall_sigprocmask 12 3.85% 59.62% # number of syscalls executed
+system.cpu0.kern.syscall_ioctl 13 4.17% 63.78% # number of syscalls executed
+system.cpu0.kern.syscall_readlink 1 0.32% 64.10% # number of syscalls executed
+system.cpu0.kern.syscall_execve 7 2.24% 66.35% # number of syscalls executed
+system.cpu0.kern.syscall_pre_F64_stat 22 7.05% 73.40% # number of syscalls executed
+system.cpu0.kern.syscall_pre_F64_lstat 1 0.32% 73.72% # number of syscalls executed
+system.cpu0.kern.syscall_mmap 28 8.97% 82.69% # number of syscalls executed
+system.cpu0.kern.syscall_munmap 4 1.28% 83.97% # number of syscalls executed
+system.cpu0.kern.syscall_mprotect 7 2.24% 86.22% # number of syscalls executed
+system.cpu0.kern.syscall_gethostname 1 0.32% 86.54% # number of syscalls executed
+system.cpu0.kern.syscall_dup2 3 0.96% 87.50% # number of syscalls executed
+system.cpu0.kern.syscall_pre_F64_fstat 15 4.81% 92.31% # number of syscalls executed
+system.cpu0.kern.syscall_fcntl 11 3.53% 95.83% # number of syscalls executed
+system.cpu0.kern.syscall_socket 3 0.96% 96.79% # number of syscalls executed
+system.cpu0.kern.syscall_connect 3 0.96% 97.76% # number of syscalls executed
+system.cpu0.kern.syscall_setgid 2 0.64% 98.40% # number of syscalls executed
+system.cpu0.kern.syscall_getrlimit 2 0.64% 99.04% # number of syscalls executed
+system.cpu0.kern.syscall_setsid 3 0.96% 100.00% # number of syscalls executed
+system.cpu0.not_idle_fraction 0.015474 # Percentage of non-idle cycles
+system.cpu0.numCycles 0 # number of cpu cycles simulated
+system.cpu0.num_insts 44447414 # Number of instructions executed
+system.cpu0.num_refs 10321518 # Number of memory references
+system.cpu1.dtb.accesses 524398 # DTB accesses
+system.cpu1.dtb.acv 60 # DTB access violations
+system.cpu1.dtb.hits 4612716 # DTB hits
+system.cpu1.dtb.misses 5263 # DTB misses
+system.cpu1.dtb.read_accesses 337746 # DTB read accesses
+system.cpu1.dtb.read_acv 23 # DTB read access violations
+system.cpu1.dtb.read_hits 2649302 # DTB read hits
+system.cpu1.dtb.read_misses 4766 # DTB read misses
+system.cpu1.dtb.write_accesses 186652 # DTB write accesses
+system.cpu1.dtb.write_acv 37 # DTB write access violations
+system.cpu1.dtb.write_hits 1963414 # DTB write hits
+system.cpu1.dtb.write_misses 497 # DTB write misses
+system.cpu1.idle_fraction 0.993423 # Percentage of idle cycles
+system.cpu1.itb.accesses 1711918 # ITB accesses
+system.cpu1.itb.acv 23 # ITB acv
+system.cpu1.itb.hits 1709683 # ITB hits
+system.cpu1.itb.misses 2235 # ITB misses
+system.cpu1.kern.callpal 58341 # number of callpals executed
+system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
+system.cpu1.kern.callpal_wripir 52 0.09% 0.09% # number of callpals executed
+system.cpu1.kern.callpal_wrmces 1 0.00% 0.09% # number of callpals executed
+system.cpu1.kern.callpal_wrfen 1 0.00% 0.09% # number of callpals executed
+system.cpu1.kern.callpal_swpctx 588 1.01% 1.10% # number of callpals executed
+system.cpu1.kern.callpal_tbi 7 0.01% 1.11% # number of callpals executed
+system.cpu1.kern.callpal_wrent 7 0.01% 1.13% # number of callpals executed
+system.cpu1.kern.callpal_swpipl 54562 93.52% 94.65% # number of callpals executed
+system.cpu1.kern.callpal_rdps 217 0.37% 95.02% # number of callpals executed
+system.cpu1.kern.callpal_wrkgp 1 0.00% 95.02% # number of callpals executed
+system.cpu1.kern.callpal_wrusp 4 0.01% 95.03% # number of callpals executed
+system.cpu1.kern.callpal_rdusp 1 0.00% 95.03% # number of callpals executed
+system.cpu1.kern.callpal_whami 3 0.01% 95.04% # number of callpals executed
+system.cpu1.kern.callpal_rti 2571 4.41% 99.44% # number of callpals executed
+system.cpu1.kern.callpal_callsys 208 0.36% 99.80% # number of callpals executed
+system.cpu1.kern.callpal_imb 116 0.20% 100.00% # number of callpals executed
+system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.hwrei 67770 # number of hwrei instructions executed
+system.cpu1.kern.inst.ivlb 0 # number of ivlb instructions executed
+system.cpu1.kern.inst.ivle 0 # number of ivle instructions executed
+system.cpu1.kern.inst.quiesce 1892 # number of quiesce instructions executed
+system.cpu1.kern.ipl_count 58980 # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_0 25467 43.18% 43.18% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_22 5476 9.28% 52.46% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_30 45 0.08% 52.54% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_31 27992 47.46% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_good 58199 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_0 25424 43.68% 43.68% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_22 5476 9.41% 53.09% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_30 45 0.08% 53.17% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_31 27254 46.83% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks 3539434499 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_0 3510645847 99.19% 99.19% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_22 1415637 0.04% 99.23% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_30 16792 0.00% 99.23% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_31 27356223 0.77% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used 0.986758 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_0 0.998312 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_31 0.973635 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.mode_good_kernel 690
+system.cpu1.kern.mode_good_user 691
+system.cpu1.kern.mode_good_idle 0
+system.cpu1.kern.mode_switch_kernel 3141 # number of protection mode switches
+system.cpu1.kern.mode_switch_user 691 # number of protection mode switches
+system.cpu1.kern.mode_switch_idle 0 # number of protection mode switches
+system.cpu1.kern.mode_switch_good 0.360386 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_kernel 0.219675 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks_kernel 3537141786 99.94% 99.94% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_user 2292711 0.06% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 589 # number of times the context was actually changed
+system.cpu1.kern.syscall 163 # number of syscalls executed
+system.cpu1.kern.syscall_fork 1 0.61% 0.61% # number of syscalls executed
+system.cpu1.kern.syscall_read 13 7.98% 8.59% # number of syscalls executed
+system.cpu1.kern.syscall_write 1 0.61% 9.20% # number of syscalls executed
+system.cpu1.kern.syscall_close 13 7.98% 17.18% # number of syscalls executed
+system.cpu1.kern.syscall_obreak 18 11.04% 28.22% # number of syscalls executed
+system.cpu1.kern.syscall_lseek 4 2.45% 30.67% # number of syscalls executed
+system.cpu1.kern.syscall_getpid 2 1.23% 31.90% # number of syscalls executed
+system.cpu1.kern.syscall_setuid 2 1.23% 33.13% # number of syscalls executed
+system.cpu1.kern.syscall_getuid 4 2.45% 35.58% # number of syscalls executed
+system.cpu1.kern.syscall_open 28 17.18% 52.76% # number of syscalls executed
+system.cpu1.kern.syscall_getgid 4 2.45% 55.21% # number of syscalls executed
+system.cpu1.kern.syscall_sigprocmask 2 1.23% 56.44% # number of syscalls executed
+system.cpu1.kern.syscall_ioctl 3 1.84% 58.28% # number of syscalls executed
+system.cpu1.kern.syscall_readlink 1 0.61% 58.90% # number of syscalls executed
+system.cpu1.kern.syscall_execve 1 0.61% 59.51% # number of syscalls executed
+system.cpu1.kern.syscall_pre_F64_stat 9 5.52% 65.03% # number of syscalls executed
+system.cpu1.kern.syscall_mmap 27 16.56% 81.60% # number of syscalls executed
+system.cpu1.kern.syscall_munmap 2 1.23% 82.82% # number of syscalls executed
+system.cpu1.kern.syscall_mprotect 7 4.29% 87.12% # number of syscalls executed
+system.cpu1.kern.syscall_gethostname 1 0.61% 87.73% # number of syscalls executed
+system.cpu1.kern.syscall_dup2 1 0.61% 88.34% # number of syscalls executed
+system.cpu1.kern.syscall_pre_F64_fstat 13 7.98% 96.32% # number of syscalls executed
+system.cpu1.kern.syscall_fcntl 3 1.84% 98.16% # number of syscalls executed
+system.cpu1.kern.syscall_setgid 2 1.23% 99.39% # number of syscalls executed
+system.cpu1.kern.syscall_getrlimit 1 0.61% 100.00% # number of syscalls executed
+system.cpu1.not_idle_fraction 0.006577 # Percentage of non-idle cycles
+system.cpu1.numCycles 0 # number of cpu cycles simulated
+system.cpu1.num_insts 18640662 # Number of instructions executed
+system.cpu1.num_refs 4633112 # Number of memory references
+system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_bytes 2521088 # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_full_pages 285 # Number of full page size DMA writes.
+system.disk0.dma_write_txs 375 # Number of DMA write transactions.
+system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
+system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
+system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
+system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+
+---------- End Simulation Statistics ----------
--- /dev/null
+ 0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006
+Listening for console connection on port 3456
+0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
+0: system.remote_gdb.listener: listening for remote gdb #1 on port 7003
+warn: Entering event queue @ 0. Starting simulation...
+warn: 271342: Trying to launch CPU number 1!
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 27 2006 16:54:00
+M5 started Thu Jul 27 17:12:18 2006
+M5 executing on zamp.eecs.umich.edu
+command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/test/opt/linux-mpboot/timing tests/linux-mpboot/run.py --timing
+Exiting @ cycle 3539435029 because m5_exit instruction encountered
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[debug]
+break_cycles=
+
+[exetrace]
+intel_format=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu physmem workload
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=mem
+clock=1
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=500000
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.cpu.mem
+simulate_stalls=false
+system=system
+width=1
+workload=system.workload
+
+[system.cpu.mem]
+type=Bus
+bus_id=0
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+
+[system.workload]
+type=EioProcess
+chkpt=
+file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
+output=cout
+system=system
+
+[trace]
+bufsize=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+// range not specified
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.workload]
+type=EioProcess
+file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
+chkpt=
+output=cout
+system=system
+
+[system.cpu.mem]
+type=Bus
+bus_id=0
+
+[system.cpu]
+type=AtomicSimpleCPU
+max_insts_any_thread=500000
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+mem=system.cpu.mem
+system=system
+workload=system.workload
+clock=1
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
+[trace]
+flags=
+start=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+pc_symbol=true
+intel_format=false
+trace_system=client
+
+[debug]
+break_cycles=
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1310554 # Simulator instruction rate (inst/s)
+host_mem_usage 147620 # Number of bytes of host memory used
+host_seconds 0.38 # Real time elapsed on the host
+host_tick_rate 1308843 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 500000 # Number of instructions simulated
+sim_seconds 0.000000 # Number of seconds simulated
+sim_ticks 499999 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 500000 # number of cpu cycles simulated
+system.cpu.num_insts 500000 # Number of instructions executed
+system.cpu.num_refs 182204 # Number of memory references
+system.workload.PROG:num_syscalls 18 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+warn: Entering event queue @ 0. Starting simulation...
+
+gzip: stdout: Broken pipe
--- /dev/null
+main dictionary has 1245 entries
+49508 bytes wasted
+>M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 27 2006 17:25:03
+M5 started Thu Jul 27 17:25:11 2006
+M5 executing on zamp.eecs.umich.edu
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/test1/atomic tests/test1/run.py
+Exiting @ tick 499999 because a thread reached the max instruction count
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[debug]
+break_cycles=
+
+[exetrace]
+intel_format=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu physmem workload
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=fuPool mem
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=1
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=500000
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.cpu.mem
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+predType=tournament
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+squashWidth=8
+system=system
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.workload
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList0
+count=6
+opList=system.cpu.fuPool.FUList0.opList0
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList4.opList0
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList5.opList0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0
+count=1
+opList=system.cpu.fuPool.FUList7.opList0
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.mem]
+type=Bus
+bus_id=0
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+
+[system.workload]
+type=EioProcess
+chkpt=
+file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
+output=cout
+system=system
+
+[trace]
+bufsize=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+// range not specified
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.workload]
+type=EioProcess
+file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
+chkpt=
+output=cout
+system=system
+
+[system.cpu.mem]
+type=Bus
+bus_id=0
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+opClass=IntAlu
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+opList=system.cpu.fuPool.FUList0.opList0
+count=6
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+opClass=IntMult
+opLat=3
+issueLat=1
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+opClass=IntDiv
+opLat=20
+issueLat=19
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+count=2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+opClass=FloatAdd
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+opClass=FloatCmp
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+opClass=FloatCvt
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+count=4
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+opClass=FloatMult
+opLat=4
+issueLat=1
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+opClass=FloatDiv
+opLat=12
+issueLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+opClass=FloatSqrt
+opLat=24
+issueLat=24
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+count=2
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+opList=system.cpu.fuPool.FUList4.opList0
+count=0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+opList=system.cpu.fuPool.FUList5.opList0
+count=0
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+count=4
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+opClass=IprAccess
+opLat=3
+issueLat=3
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+opList=system.cpu.fuPool.FUList7.opList0
+count=1
+
+[system.cpu.fuPool]
+type=FUPool
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu]
+type=DerivO3CPU
+clock=1
+numThreads=1
+activity=0
+workload=system.workload
+mem=system.cpu.mem
+checker=null
+max_insts_any_thread=500000
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+cachePorts=200
+decodeToFetchDelay=1
+renameToFetchDelay=1
+iewToFetchDelay=1
+commitToFetchDelay=1
+fetchWidth=8
+renameToDecodeDelay=1
+iewToDecodeDelay=1
+commitToDecodeDelay=1
+fetchToDecodeDelay=1
+decodeWidth=8
+iewToRenameDelay=1
+commitToRenameDelay=1
+decodeToRenameDelay=1
+renameWidth=8
+commitToIEWDelay=1
+renameToIEWDelay=2
+issueToExecuteDelay=1
+dispatchWidth=8
+issueWidth=8
+wbWidth=8
+wbDepth=1
+fuPool=system.cpu.fuPool
+iewToCommitDelay=1
+renameToROBDelay=1
+commitWidth=8
+squashWidth=8
+trapLatency=13
+backComSize=5
+forwardComSize=5
+predType=tournament
+localPredictorSize=2048
+localCtrBits=2
+localHistoryTableSize=2048
+localHistoryBits=11
+globalPredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+choicePredictorSize=8192
+choiceCtrBits=2
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+LQEntries=32
+SQEntries=32
+LFSTSize=1024
+SSITSize=1024
+numPhysIntRegs=256
+numPhysFloatRegs=256
+numIQEntries=64
+numROBEntries=192
+smtNumFetchingThreads=1
+smtFetchPolicy=SingleThread
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+smtCommitPolicy=RoundRobin
+instShiftAmt=2
+defer_registration=false
+function_trace=false
+function_trace_start=0
+
+[trace]
+flags=
+start=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+pc_symbol=true
+intel_format=false
+trace_system=client
+
+[debug]
+break_cycles=
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 47245 # Number of BTB hits
+global.BPredUnit.BTBLookups 62226 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 88 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 3133 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 48198 # Number of conditional branches predicted
+global.BPredUnit.lookups 72853 # Number of BP lookups
+global.BPredUnit.usedRAS 7892 # Number of times the RAS was used to get a target.
+host_inst_rate 90438 # Simulator instruction rate (inst/s)
+host_mem_usage 148172 # Number of bytes of host memory used
+host_seconds 5.53 # Real time elapsed on the host
+host_tick_rate 35958 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 15372 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 1808 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 147140 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 63225 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 500002 # Number of instructions simulated
+sim_seconds 0.000000 # Number of seconds simulated
+sim_ticks 198813 # Number of ticks simulated
+system.cpu.commit.COM:branches 61160 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 24524 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 189916
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 37455 1972.19%
+ 1 50343 2650.80%
+ 2 29014 1527.73%
+ 3 12786 673.25%
+ 4 19808 1042.99%
+ 5 2516 132.48%
+ 6 10075 530.50%
+ 7 3395 178.76%
+ 8 24524 1291.31%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 518948 # Number of instructions committed
+system.cpu.commit.COM:loads 131376 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 189772 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 2863 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 518948 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 18 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 59006 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 500002 # Number of Instructions Simulated
+system.cpu.committedInsts_total 500002 # Number of Instructions Simulated
+system.cpu.cpi 0.397624 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.397624 # CPI: Total CPI of All Threads
+system.cpu.decode.DECODE:BlockedCycles 2191 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 297 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 16283 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 604200 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 76141 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 110735 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 8898 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 1017 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 849 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 72853 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 72795 # Number of cache lines fetched
+system.cpu.fetch.Cycles 186280 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Insts 616104 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 3180 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.366438 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 72795 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 55137 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 3.098896 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 198814
+system.cpu.fetch.rateDist.min_value 0
+ 0 85330 4291.95%
+ 1 3737 187.96%
+ 2 9626 484.17%
+ 3 11018 554.19%
+ 4 8626 433.87%
+ 5 19021 956.72%
+ 6 27490 1382.70%
+ 7 6216 312.65%
+ 8 27750 1395.78%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.iew.EXEC:branches 65998 # Number of branches executed
+system.cpu.iew.EXEC:insts 534582 # Number of executed instructions
+system.cpu.iew.EXEC:loads 141825 # Number of load instructions executed
+system.cpu.iew.EXEC:nop 21827 # number of nop insts executed
+system.cpu.iew.EXEC:rate 2.688855 # Inst execution rate
+system.cpu.iew.EXEC:refs 202010 # number of memory reference insts executed
+system.cpu.iew.EXEC:squashedInsts 7038 # Number of squashed instructions skipped in execute
+system.cpu.iew.EXEC:stores 60185 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 413743 # num instructions consuming a value
+system.cpu.iew.WB:count 532886 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.745847 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 308589 # num instructions producing a value
+system.cpu.iew.WB:rate 2.680324 # insts written-back per cycle
+system.cpu.iew.WB:sent 533753 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 3004 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 147140 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 1292 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 63225 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 578006 # Number of instructions dispatched to IQ
+system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 8898 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 22061 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 15747 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 4825 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 48 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 1801 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 1203 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 2.514936 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 2.514936 # IPC: Total IPC of All Threads
+system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
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+
+system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
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+
+system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
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+
+system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
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+
+system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatAdd.samples 0
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+
+system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatCmp.samples 0
+system.cpu.iq.IQ:residence:FloatCmp.min_value 0
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+
+system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
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+
+system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
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+
+system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatDiv.samples 0
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+system.cpu.iq.IQ:residence:FloatDiv.max_value 0
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+
+system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatSqrt.samples 0
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+system.cpu.iq.IQ:residence:FloatSqrt.end_dist
+
+system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:MemRead.samples 0
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+system.cpu.iq.IQ:residence:MemRead.max_value 0
+system.cpu.iq.IQ:residence:MemRead.end_dist
+
+system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:MemWrite.samples 0
+system.cpu.iq.IQ:residence:MemWrite.min_value 0
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+system.cpu.iq.IQ:residence:MemWrite.max_value 0
+system.cpu.iq.IQ:residence:MemWrite.end_dist
+
+system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:IprAccess.samples 0
+system.cpu.iq.IQ:residence:IprAccess.min_value 0
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+system.cpu.iq.IQ:residence:IprAccess.max_value 0
+system.cpu.iq.IQ:residence:IprAccess.end_dist
+
+system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:InstPrefetch.samples 0
+system.cpu.iq.IQ:residence:InstPrefetch.min_value 0
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+system.cpu.iq.IQ:residence:InstPrefetch.max_value 0
+system.cpu.iq.IQ:residence:InstPrefetch.end_dist
+
+system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:(null)_delay.samples 0
+system.cpu.iq.ISSUE:(null)_delay.min_value 0
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+system.cpu.iq.ISSUE:(null)_delay.max_value 0
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+
+system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntAlu_delay.samples 0
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+system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
+system.cpu.iq.ISSUE:IntAlu_delay.end_dist
+
+system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntMult_delay.samples 0
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+system.cpu.iq.ISSUE:IntMult_delay.max_value 0
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+
+system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntDiv_delay.samples 0
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+system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
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+
+system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
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+system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
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+
+system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
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+system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
+system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
+system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
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+system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
+system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatMult_delay.samples 0
+system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
+system.cpu.iq.ISSUE:FloatMult_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
+system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
+system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
+
+system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:MemRead_delay.samples 0
+system.cpu.iq.ISSUE:MemRead_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:MemRead_delay.max_value 0
+system.cpu.iq.ISSUE:MemRead_delay.end_dist
+
+system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:MemWrite_delay.samples 0
+system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
+system.cpu.iq.ISSUE:MemWrite_delay.end_dist
+
+system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IprAccess_delay.samples 0
+system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
+system.cpu.iq.ISSUE:IprAccess_delay.end_dist
+
+system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
+
+system.cpu.iq.ISSUE:FU_type_0 541621 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ (null) 0 0.00% # Type of FU issued
+ IntAlu 336144 62.06% # Type of FU issued
+ IntMult 10 0.00% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 13 0.00% # Type of FU issued
+ FloatCmp 3 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 2 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 144008 26.59% # Type of FU issued
+ MemWrite 61441 11.34% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 10389 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.019181 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ (null) 0 0.00% # attempts to use FU when none available
+ IntAlu 6229 59.96% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 2497 24.04% # attempts to use FU when none available
+ MemWrite 1663 16.01% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 198814
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 27333 1374.80%
+ 1 36906 1856.31%
+ 2 35716 1796.45%
+ 3 28916 1454.42%
+ 4 31868 1602.91%
+ 5 13027 655.24%
+ 6 21677 1090.32%
+ 7 3102 156.03%
+ 8 269 13.53%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 2.724260 # Inst issue rate
+system.cpu.iq.iqInstsAdded 556152 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 541621 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 55198 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 404 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 27398 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.numCycles 198814 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 266 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 386063 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IdleCycles 78342 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 1401 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 775201 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 594947 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 443127 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 109388 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 8898 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 1662 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 57015 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 258 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 41 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 4872 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 39 # count of temporary serializing insts renamed
+system.workload.PROG:num_syscalls 18 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+warn: Entering event queue @ 0. Starting simulation...
+warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
+
+gzip: stdout: Broken pipe
--- /dev/null
+main dictionary has 1245 entries
+49508 bytes wasted
+>M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 27 2006 17:25:03
+M5 started Thu Jul 27 17:25:11 2006
+M5 executing on zamp.eecs.umich.edu
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/test1/detailed tests/test1/run.py --detailed
+Exiting @ tick 198813 because a thread reached the max instruction count
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[debug]
+break_cycles=
+
+[exetrace]
+intel_format=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu physmem workload
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=mem
+clock=1
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=500000
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.cpu.mem
+system=system
+workload=system.workload
+
+[system.cpu.mem]
+type=Bus
+bus_id=0
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+
+[system.workload]
+type=EioProcess
+chkpt=
+file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
+output=cout
+system=system
+
+[trace]
+bufsize=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+// range not specified
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.workload]
+type=EioProcess
+file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
+chkpt=
+output=cout
+system=system
+
+[system.cpu.mem]
+type=Bus
+bus_id=0
+
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=500000
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+mem=system.cpu.mem
+system=system
+workload=system.workload
+clock=1
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[trace]
+flags=
+start=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+pc_symbol=true
+intel_format=false
+trace_system=client
+
+[debug]
+break_cycles=
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 781730 # Simulator instruction rate (inst/s)
+host_mem_usage 147616 # Number of bytes of host memory used
+host_seconds 0.64 # Real time elapsed on the host
+host_tick_rate 1063244 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 500000 # Number of instructions simulated
+sim_seconds 0.000001 # Number of seconds simulated
+sim_ticks 680774 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 0 # number of cpu cycles simulated
+system.cpu.num_insts 500000 # Number of instructions executed
+system.cpu.num_refs 182203 # Number of memory references
+system.workload.PROG:num_syscalls 18 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+warn: Entering event queue @ 0. Starting simulation...
+
+gzip: stdout: Broken pipe
--- /dev/null
+main dictionary has 1245 entries
+49508 bytes wasted
+>M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 27 2006 17:25:03
+M5 started Thu Jul 27 17:25:14 2006
+M5 executing on zamp.eecs.umich.edu
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/test1/timing tests/test1/run.py --timing
+Exiting @ tick 680774 because a thread reached the max instruction count
projects / gem5.git / commitdiff