sparc.c (sparc_expand_vec_perm_bmask): Use a scratch register as destination of bmask.

	* config/sparc/sparc.c (sparc_expand_vec_perm_bmask): Use a scratch
	register as destination of bmask.
	(vector_init_bshuffle): Likewise.
	* config/sparc/sparc.md (vec_perm_constv8qi): Likewise.
	(bmaskdi_vis): Enable only in 64-bit mode.

From-SVN: r241205

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 54fba44562d3547d8035594e5b0e720a24fc176f..e616910bb0077c94658def78f5f5b44a3749de63 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2016-10-15  Eric Botcazou  <ebotcazou@adacore.com>
+
+       * config/sparc/sparc.c (sparc_expand_vec_perm_bmask): Use a scratch
+       register as destination of bmask.
+       (vector_init_bshuffle): Likewise.
+       * config/sparc/sparc.md (vec_perm_constv8qi): Likewise.
+       (bmaskdi_vis): Enable only in 64-bit mode.
+
 2016-10-15  Segher Boessenkool  <segher@kernel.crashing.org>
 
        * config/rs6000/rs6000.c (rs6000_get_separate_components): Do not

diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 8633b8d34f9f51f5bf981327c0bee49a33d5d9ad..f737061b92cb3dff062fce12af254547c1083c7f 100644 (file)
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -12044,7 +12044,7 @@ sparc_expand_vec_perm_bmask (machine_mode vmode, rtx sel)
     }
 
   /* Always perform the final addition/merge within the bmask insn.  */
-  emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, t_1));
+  emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, t_1));
 }
 
 /* Implement TARGET_FRAME_POINTER_REQUIRED.  */
@@ -12310,7 +12310,7 @@ vector_init_bshuffle (rtx target, rtx elt, machine_mode mode,
     }
 
   sel = force_reg (SImode, GEN_INT (bmask));
-  emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, const0_rtx));
+  emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, const0_rtx));
   emit_insn (final_insn);
 }
 

diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 5a89872824869d331c2208fe23ef41c76f786808..64376c7cad361076d469cb5c17e95ba711cba99c 100644 (file)
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -8548,7 +8548,7 @@
                  (match_operand:DI 2 "register_or_zero_operand" "rJ")))
    (set (zero_extract:DI (reg:DI GSR_REG) (const_int 32) (const_int 32))
         (plus:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_VIS2"
+  "TARGET_VIS2 && TARGET_ARCH64"
   "bmask\t%r1, %r2, %0"
   [(set_attr "type" "array")
    (set_attr "v3pipe" "true")])
@@ -8593,7 +8593,7 @@
     mask |= (INTVAL (XVECEXP (sel, 0, i)) & 0xf) << (28 - i*4);
   sel = force_reg (SImode, gen_int_mode (mask, SImode));
 
-  emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, const0_rtx));
+  emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, const0_rtx));
   emit_insn (gen_bshufflev8qi_vis (operands[0], operands[1], operands[2]));
   DONE;
 })

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d3183332a4bb1f35722969113bdc05459c2d0084..e55d653284c256afdf260b60cc0103378fe5a330 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2016-10-15  Eric Botcazou  <ebotcazou@adacore.com>
+
+       * gcc.target/sparc/bmaskbshuf.c: Rename to...
+       * gcc.target/sparc/bmaskbshuf-1.c: ...this.
+       * gcc.target/sparc/bmaskbshuf-2.c: New test.
+
 2016-10-15  Eric Botcazou  <ebotcazou@adacore.com>
 
        * gcc.target/sparc/popc.c: Rename to...

diff --git a/gcc/testsuite/gcc.target/sparc/bmaskbshuf-1.c b/gcc/testsuite/gcc.target/sparc/bmaskbshuf-1.c
new file mode 100644 (file)
index 0000000..22809b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/bmaskbshuf-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mvis2" } */
+
+typedef long long int64_t;
+typedef int vec32 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+long test_bmask (long x, long y)
+{
+  return __builtin_vis_bmask (x, y);
+}
+
+vec16 test_bshufv4hi (vec16 x, vec16 y)
+{
+  return __builtin_vis_bshufflev4hi (x, y);
+}
+
+vec32 test_bshufv2si (vec32 x, vec32 y)
+{
+  return __builtin_vis_bshufflev2si (x, y);
+}
+
+vec8 test_bshufv8qi (vec8 x, vec8 y)
+{
+  return __builtin_vis_bshufflev8qi (x, y);
+}
+
+int64_t test_bshufdi (int64_t x, int64_t y)
+{
+  return __builtin_vis_bshuffledi (x, y);
+}
+
+/* { dg-final { scan-assembler "bmask\t%" } } */
+/* { dg-final { scan-assembler "bshuffle\t%" } } */

diff --git a/gcc/testsuite/gcc.target/sparc/bmaskbshuf-2.c b/gcc/testsuite/gcc.target/sparc/bmaskbshuf-2.c
new file mode 100644 (file)
index 0000000..874e3db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/bmaskbshuf-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_vis2_hw } */
+/* { dg-options "-mcpu=ultrasparc3 -O" } */
+
+typedef unsigned int Vect __attribute__((vector_size(8)));
+
+extern void abort (void);
+
+Vect a, b, c, d;
+
+__attribute__((noinline, noclone)) void test (void)
+{
+  Vect mask = { 2, 2 };
+  int i;
+
+  c = __builtin_shuffle (a, mask);
+  d = __builtin_shuffle (a, b, mask);
+
+  __asm__ ("" : : "r" (&c), "r" (&d) : "memory");
+
+  for (i = 0; i < 2; ++i)
+    if (c[i] != a[mask[i] & 1])
+      abort ();
+    else if (mask[i] & 2)
+      {
+       if (d[i] != b[mask[i] & 1])
+         abort ();
+      }
+}
+
+int main (void)
+{
+  int i;
+  for (i = 0; i < 2; ++i)
+    {
+      a[i] = i + 2;
+      b[i] = 2 + i + 2;
+    }
+
+  test ();
+  return 0;
+}

diff --git a/gcc/testsuite/gcc.target/sparc/bmaskbshuf.c b/gcc/testsuite/gcc.target/sparc/bmaskbshuf.c
deleted file mode 100644 (file)
index 22809b5..0000000
--- a/gcc/testsuite/gcc.target/sparc/bmaskbshuf.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O -mvis2" } */
-
-typedef long long int64_t;
-typedef int vec32 __attribute__((vector_size(8)));
-typedef short vec16 __attribute__((vector_size(8)));
-typedef unsigned char vec8 __attribute__((vector_size(8)));
-
-long test_bmask (long x, long y)
-{
-  return __builtin_vis_bmask (x, y);
-}
-
-vec16 test_bshufv4hi (vec16 x, vec16 y)
-{
-  return __builtin_vis_bshufflev4hi (x, y);
-}
-
-vec32 test_bshufv2si (vec32 x, vec32 y)
-{
-  return __builtin_vis_bshufflev2si (x, y);
-}
-
-vec8 test_bshufv8qi (vec8 x, vec8 y)
-{
-  return __builtin_vis_bshufflev8qi (x, y);
-}
-
-int64_t test_bshufdi (int64_t x, int64_t y)
-{
-  return __builtin_vis_bshuffledi (x, y);
-}
-
-/* { dg-final { scan-assembler "bmask\t%" } } */
-/* { dg-final { scan-assembler "bshuffle\t%" } } */