arch: Make readMiscRegNoEffect const throughout

Finally took the plunge and made this apply to all ISAs, not just ARM.

diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
index 95dfdedd65416a9be72d4e659aad79cc43e88e89..20f03916628161830a6dc8a18a6135402a8359f6 100644 (file)
--- a/src/arch/alpha/isa.cc
+++ b/src/arch/alpha/isa.cc
@@ -74,7 +74,7 @@ ISA::unserialize(Checkpoint *cp, const std::string &section)
 
 
 MiscReg
-ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
+ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
 {
     switch (misc_reg) {
       case MISCREG_FPCR:

diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index 36515b520e1029fecfb88965ea46dba9e617229a..52e4e98beb7cac67efddbe305c5287d3058917c9 100644 (file)
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -73,7 +73,7 @@ namespace AlphaISA
 
       public:
 
-        MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
+        MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
         MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
 
         void setMiscRegNoEffect(int misc_reg, const MiscReg &val,

diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 164f10d5d03896312cee045ca5eee7dbba307cb2..a37f523d984682c1ef0cf9542b256f9306a02e56 100644 (file)
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -410,14 +410,14 @@ ISA::configCP()
 }
 
 inline unsigned
-ISA::getVPENum(ThreadID tid)
+ISA::getVPENum(ThreadID tid) const
 {
     TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
     return tcBind.curVPE;
 }
 
 MiscReg
-ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
+ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
 {
     unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
         ? tid : getVPENum(tid);

diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index fea3f00ca8bd7f68554a7cd7b0fdc518ee30f191..feb55e473996dfeac988c62617ab7b884a805f78 100644 (file)
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -76,7 +76,7 @@ namespace MipsISA
 
         void configCP();
 
-        unsigned getVPENum(ThreadID tid);
+        unsigned getVPENum(ThreadID tid) const;
 
         //////////////////////////////////////////////////////////
         //
@@ -87,7 +87,7 @@ namespace MipsISA
         //@TODO: MIPS MT's register view automatically connects
         //       Status to TCStatus depending on current thread
         void updateCP0ReadView(int misc_reg, ThreadID tid) { }
-        MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
+        MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
 
         //template <class TC>
         MiscReg readMiscReg(int misc_reg,

diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index d19410037d28b5efdf10bb0093f937d09b4fa2b6..aaf5bd92a3be06ff65fd59b5727a76e932108357 100644 (file)
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -61,7 +61,7 @@ class ISA : public SimObject
     }
 
     MiscReg
-    readMiscRegNoEffect(int misc_reg)
+    readMiscRegNoEffect(int misc_reg) const
     {
         fatal("Power does not currently have any misc regs defined\n");
         return dummy;

diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index 4daf8775b83ef464aac2889c489487b99aba8330..c9a3a33b4cc2e0d90e4607f69a850447cb7d0b20 100644 (file)
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -173,7 +173,7 @@ ISA::clear()
 }
 
 MiscReg
-ISA::readMiscRegNoEffect(int miscReg)
+ISA::readMiscRegNoEffect(int miscReg) const
 {
 
   // The three miscRegs are moved up from the switch statement

diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 536deb69c1b56d3393ccffeeace91c42c8d2f5d4..4551cf3c151fae5470f0d00f2d4473604b1a2645 100644 (file)
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -183,7 +183,7 @@ class ISA : public SimObject
 
   public:
 
-    MiscReg readMiscRegNoEffect(int miscReg);
+    MiscReg readMiscRegNoEffect(int miscReg) const;
     MiscReg readMiscReg(int miscReg, ThreadContext *tc);
 
     void setMiscRegNoEffect(int miscReg, const MiscReg val);

diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index f65bc2392c5a261ce9331abc1050372fbf4f85c7..f2d3ce42abdc9ce8ad5edc918c5ecd71a5cb068f 100644 (file)
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -124,7 +124,7 @@ ISA::params() const
 }
 
 MiscReg
-ISA::readMiscRegNoEffect(int miscReg)
+ISA::readMiscRegNoEffect(int miscReg) const
 {
     // Make sure we're not dealing with an illegal control register.
     // Instructions should filter out these indexes, and nothing else should

diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 3ca771c61cdfda1771b2565ba1b7c0a42f308ca8..a82b4ae2f4ccb2c286c808b676cffe11b9b3abf9 100644 (file)
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -63,7 +63,7 @@ namespace X86ISA
         ISA(Params *p);
         const Params *params() const;
 
-        MiscReg readMiscRegNoEffect(int miscReg);
+        MiscReg readMiscRegNoEffect(int miscReg) const;
         MiscReg readMiscReg(int miscReg, ThreadContext *tc);
 
         void setMiscRegNoEffect(int miscReg, MiscReg val);

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 49f44ff001d2a5839781b2fc191208d51aea33f9..bed3b9e3239a42bf44d36e930b38af674c26e241 100644 (file)
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -285,7 +285,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
     MicroPC microPC() { return thread->microPC(); }
     //////////////////////////////////////////
 
-    MiscReg readMiscRegNoEffect(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg) const
     {
         return thread->readMiscRegNoEffect(misc_reg);
     }

diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index ccf0d3c1d1bc5215135b38aac8d10a291a1dfd82..26d0dfa8b5d0cd1a20e8bac7ca169659adbadb84 100644 (file)
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -275,7 +275,7 @@ class CheckerThreadContext : public ThreadContext
     MicroPC microPC()
     { return actualTC->microPC(); }
 
-    MiscReg readMiscRegNoEffect(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg) const
     { return actualTC->readMiscRegNoEffect(misc_reg); }
 
     MiscReg readMiscReg(int misc_reg)

diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 41345d3bddf4dbe7b180bcbac1211a51cf7e249f..80d5d98720b624b26d90945b33dfb42c0cbd5793 100644 (file)
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -187,7 +187,7 @@ class ExecContext : public ::ExecContext
     }
 
     TheISA::MiscReg
-    readMiscRegNoEffect(int misc_reg)
+    readMiscRegNoEffect(int misc_reg) const
     {
         return thread.readMiscRegNoEffect(misc_reg);
     }

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index b48c66c371b7e962128157f8e88be0708220c63b..434bfd7da020b7b3e1b5f892a2a3871f85a25f04 100644 (file)
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1205,7 +1205,7 @@ FullO3CPU<Impl>::verifyMemoryMode() const
 
 template <class Impl>
 TheISA::MiscReg
-FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
+FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
 {
     return this->isa[tid]->readMiscRegNoEffect(misc_reg);
 }

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 09b7db867f75e3ac776b10e05ff725d1417a85d5..5b33285c43b03398c9317eec74910026b95063be 100644 (file)
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -403,7 +403,7 @@ class FullO3CPU : public BaseO3CPU
     /** Register accessors.  Index refers to the physical register index. */
 
     /** Reads a miscellaneous register. */
-    TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
+    TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
 
     /** Reads a misc. register, including any side effects the read
      * might have as defined by the architecture.

diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 952d365bf9c6e152e2394a6f80b06efea5ae2ede..87d87900c1e3bd49b58656acbf026577723b2ab4 100755 (executable)
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -228,7 +228,7 @@ class O3ThreadContext : public ThreadContext
     { return cpu->microPC(thread->threadId()); }
 
     /** Reads a miscellaneous register. */
-    virtual MiscReg readMiscRegNoEffect(int misc_reg)
+    virtual MiscReg readMiscRegNoEffect(int misc_reg) const
     { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
 
     /** Reads a misc. register, including any side-effects the

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 7ace2204a9b9a793a01dc808e36bf75b002573f0..6e8b4a8c8876faeffee8cc72e55d853165c00a6d 100644 (file)
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -367,7 +367,7 @@ class BaseSimpleCPU : public BaseCPU, public ExecContext
     Addr nextInstAddr() { return thread->nextInstAddr(); }
     MicroPC microPC() { return thread->microPC(); }
 
-    MiscReg readMiscRegNoEffect(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg) const
     {
         return thread->readMiscRegNoEffect(misc_reg);
     }

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 1f9e58ad94fc0fc97a475472e31194dd30edbd71..e862385c57833cefe29dc993dcf0d3709061b490 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -372,7 +372,7 @@ class SimpleThread : public ThreadState
     }
 
     MiscReg
-    readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
+    readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const
     {
         return isa->readMiscRegNoEffect(misc_reg);
     }

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 850ff9468becdac6f86c8afc902d981406087db3..966924c50f23389defbf9895648599e4b3461ec8 100644 (file)
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -225,7 +225,7 @@ class ThreadContext
 
     virtual MicroPC microPC() = 0;
 
-    virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
+    virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0;
 
     virtual MiscReg readMiscReg(int misc_reg) = 0;
 
@@ -429,7 +429,7 @@ class ProxyThreadContext : public ThreadContext
     void setPredicate(bool val)
     { actualTC->setPredicate(val); }
 
-    MiscReg readMiscRegNoEffect(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg) const
     { return actualTC->readMiscRegNoEffect(misc_reg); }
 
     MiscReg readMiscReg(int misc_reg)