cpu: Add a memory access predicate

This changeset introduces a new predicate to guard memory accesses.
The most immediate use for this is to allow proper handling of
predicated-false vector contiguous loads and predicated-false
micro-ops of vector gather loads (added in separate changesets).

Change-Id: Ice6894fe150faec2f2f7ab796a00c99ac843810a
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17991
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bradley Wang <radwang@ucdavis.edu>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index f1c78295638cd7a7d2297b633e96036ed2afe896..4084241bd3edc16c252979b2b5aa835c1b16a76c 100644 (file)
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -135,6 +135,7 @@ class BaseDynInst : public ExecContext, public RefCounted
         EffAddrValid,
         RecordResult,
         Predicate,
+        MemAccPredicate,
         PredTaken,
         IsStrictlyOrdered,
         ReqMade,
@@ -851,6 +852,18 @@ class BaseDynInst : public ExecContext, public RefCounted
         }
     }
 
+    bool
+    readMemAccPredicate() const
+    {
+        return instFlags[MemAccPredicate];
+    }
+
+    void
+    setMemAccPredicate(bool val)
+    {
+        instFlags[MemAccPredicate] = val;
+    }
+
     /** Sets the ASID. */
     void setASID(short addr_space_id) { asid = addr_space_id; }
     short getASID() { return asid; }

diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh
index d8473f7d51ab0e6ec1c658c3603eca54b99ef7c5..6d3a3ac4e01c4a1d22ee876a2945c3e039675493 100644 (file)
--- a/src/cpu/base_dyn_inst_impl.hh
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011, 2018 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -103,6 +103,7 @@ BaseDynInst<Impl>::initVars()
     instFlags.reset();
     instFlags[RecordResult] = true;
     instFlags[Predicate] = true;
+    instFlags[MemAccPredicate] = true;
 
     lqIdx = -1;
     sqIdx = -1;

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 7582e5e59f9393da99878f4e9e11cbc78d924c03..8c3000005cb96464e1564e684b48e24cb0ae7951 100644 (file)
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011, 2016-2017 ARM Limited
+ * Copyright (c) 2011, 2016-2018 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -424,6 +424,18 @@ class CheckerCPU : public BaseCPU, public ExecContext
         thread->setPredicate(val);
     }
 
+    bool
+    readMemAccPredicate() const override
+    {
+        return thread->readMemAccPredicate();
+    }
+
+    void
+    setMemAccPredicate(bool val) override
+    {
+        thread->setMemAccPredicate(val);
+    }
+
     TheISA::PCState pcState() const override { return thread->pcState(); }
     void
     pcState(const TheISA::PCState &val) override

diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 5909af646a1f714f789386647f253f9745f06f60..4cad9e3e1434b611437fbf62692dd16e5d4332e3 100644 (file)
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, 2016-2017 ARM Limited
+ * Copyright (c) 2014, 2016-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -316,6 +316,8 @@ class ExecContext {
 
     virtual bool readPredicate() const = 0;
     virtual void setPredicate(bool val) = 0;
+    virtual bool readMemAccPredicate() const = 0;
+    virtual void setMemAccPredicate(bool val) = 0;
 
     /** @} */
 

diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 55391c3fad21a0aae9332c6ead09dd88fa128a50..b39bbac3fa2f2de1b45fa566c9ab38331c817932 100644 (file)
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2014, 2016-2017 ARM Limited
+ * Copyright (c) 2011-2014, 2016-2018 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -319,6 +319,18 @@ class ExecContext : public ::ExecContext
         thread.setPredicate(val);
     }
 
+    bool
+    readMemAccPredicate() const override
+    {
+        return thread.readMemAccPredicate();
+    }
+
+    void
+    setMemAccPredicate(bool val) override
+    {
+        thread.setMemAccPredicate(val);
+    }
+
     TheISA::PCState
     pcState() const override
     {

diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 62402bf4f6712d4f42c588f119fb4bfc58c49781..9323e863466f9ff36040bb3b887a5b5ea83a4c0c 100644 (file)
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -542,6 +542,16 @@ LSQUnit<Impl>::executeLoad(const DynInstPtr &inst)
 
     load_fault = inst->initiateAcc();
 
+    if (!inst->readMemAccPredicate()) {
+        assert(load_fault == NoFault);
+        assert(inst->readPredicate());
+        inst->setExecuted();
+        inst->completeAcc(nullptr);
+        iewStage->instToCommit(inst);
+        iewStage->activityThisCycle();
+        return NoFault;
+    }
+
     if (inst->isTranslationDelayed() && load_fault == NoFault)
         return load_fault;
 

diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index fb4ced381fe1b8335864228a3eb959ceab1c71b6..be7a863c5fcfeee09a967aea91326f8466a33b6d 100644 (file)
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017 ARM Limited
+ * Copyright (c) 2014-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -518,6 +518,18 @@ class SimpleExecContext : public ExecContext {
         }
     }
 
+    bool
+    readMemAccPredicate() const override
+    {
+        return thread->readMemAccPredicate();
+    }
+
+    void
+    setMemAccPredicate(bool val) override
+    {
+        thread->setMemAccPredicate(val);
+    }
+
     /**
      * Invalidate a page in the DTLB <i>and</i> ITLB.
      */

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 733047f7105c424dff370716771d475f290f4403..8b5e49a3e7d3f6ba7071b83261948ed7895ca531 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -117,6 +117,9 @@ class SimpleThread : public ThreadState, public ThreadContext
     /** Did this instruction execute or is it predicated false */
     bool predicate;
 
+    /** True if the memory access should be skipped for this instruction */
+    bool memAccPredicate;
+
   public:
     std::string name() const
     {
@@ -576,6 +579,18 @@ class SimpleThread : public ThreadState, public ThreadContext
 
     unsigned readStCondFailures() const override { return storeCondFailures; }
 
+    bool
+    readMemAccPredicate()
+    {
+        return memAccPredicate;
+    }
+
+    void
+    setMemAccPredicate(bool val)
+    {
+        memAccPredicate = val;
+    }
+
     void
     setStCondFailures(unsigned sc_failures) override
     {