add words to describe first few instructions, bug #672 popspopcount

diff --git a/openpower/sv/cookbook/pospopcnt.mdwn b/openpower/sv/cookbook/pospopcnt.mdwn
index f8b46d378698663a7556146a0a088f248c1c338e..9a2d619f6babd5cb18964f1038ca6d2cd27e178a 100644 (file)
--- a/openpower/sv/cookbook/pospopcnt.mdwn
+++ b/openpower/sv/cookbook/pospopcnt.mdwn
@@ -57,12 +57,30 @@ bit-position, of an array of input values.
 
 # Walkthrough of the assembler
 
+Firstly the CTR (Counter) SPR is set up, and is key to looping
+as outlined further, below
+
 ```
 mtspr 9, 3"                # move r3 to CTR
 ```
 
+The Vector Length, which is limited to 8 (MVL - Maximum
+Vector Length) is set up. A special "CTR" Mode is used
+which automatically uses the CTR SPR rather than register
+RA. (*Note that RA is set to zero to indicate this, because there is
+limited encoding space. See [[openpower/sv/setvl]] instruction
+specification for details)*.
+
+The result of this instruction is that if CTR is greater than
+8, VL is set to 8. If however CTR is less than or equal to 8,
+then VL is set to CTR.  Additionally, a copy of VL is placed
+into RT (r3 in this case), which again is necessary as part
+of the limited encoding space but in some cases (not here)
+this is desirable, and avoids a `mfspr` instruction to take
+a copy of VL into a GPR.
+
 ```
-# VL = MIN(CTR,MAXVL=8), Rc=1 (CR0 set if CTR ends)
+# VL = MIN(CTR,MAXVL=8)
 setvl 3,0,8,0,1,1"         # set MVL=8, VL=MIN(MVL,CTR)
 ```