fhdl.ir: fix port threading code.

diff --git a/examples/alu_hier.py b/examples/alu_hier.py
index 81640b2691f787536fa80a86292d4f6526eac0f8..6f862ca452fc8f3dacaea1ce07c3636546d47ef6 100644 (file)
--- a/examples/alu_hier.py
+++ b/examples/alu_hier.py
@@ -56,4 +56,4 @@ class ALU:
 alu  = ALU(width=16)
 frag = alu.get_fragment(platform=None)
 # print(rtlil.convert(frag, ports=[alu.op, alu.a, alu.b, alu.o]))
-print(verilog.convert(frag, ports=[alu.op, alu.a, alu.b, alu.o, alu.add.o, alu.sub.o]))
+print(verilog.convert(frag, ports=[alu.op, alu.a, alu.b, alu.o]))

diff --git a/nmigen/fhdl/ir.py b/nmigen/fhdl/ir.py
index eeeace15e4e879a550b485c0c5d21305c0ae92f9..2af5a525b0f21dbe4b7d390245b8f9546764dcdc 100644 (file)
--- a/nmigen/fhdl/ir.py
+++ b/nmigen/fhdl/ir.py
@@ -66,7 +66,7 @@ class Fragment:
             subfrag, sub_ins, sub_outs = subfrag.prepare(ports=self_used | ports,
                                                          clock_domains=clock_domains)
             frag.subfragments[n] = (subfrag, name)
-            ins  |= sub_ins - self_driven
+            ins  -= sub_outs
             outs |= ports & sub_outs
 
         frag.add_ports(ins, outs)