dvisampler: reset PLL at startup

diff --git a/milkymist/dvisampler/clocking.py b/milkymist/dvisampler/clocking.py
index bf6f01e85acb7a4c81de7ed72b5e4f1e499d8e37..9e261d05c114bec8dce1a3ecf155d522a942f0a3 100644 (file)
--- a/milkymist/dvisampler/clocking.py
+++ b/milkymist/dvisampler/clocking.py
@@ -4,7 +4,7 @@ from migen.bank.description import *
 
 class Clocking(Module, AutoCSR):
        def __init__(self, pads):
-               self._r_pll_reset = CSRStorage()
+               self._r_pll_reset = CSRStorage(reset=1)
                self._r_locked = CSRStatus()
 
                self.locked = Signal()